diff --git a/.typos.toml b/.typos.toml
index 56f0ad44e0..70eeb7f618 100644
--- a/.typos.toml
+++ b/.typos.toml
@@ -1,7 +1,7 @@
# For information about the config format, see https://github.com/crate-ci/typos
[files]
-extend-exclude = ["imported/"]
+extend-exclude = ["imported/", "*.pipe"]
[default.extend-identifiers]
# Needs to be fixed in xgl first
@@ -24,4 +24,5 @@ USCALED = "USCALED"
Datas = "Datas"
HSA = "HSA"
VALU = "VALU"
+offen = "offen"
Derivate = "Derivate"
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 483dbccfc9..54f9769ad8 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
@@ -35,6 +35,10 @@ endif()
### Version info ###
include(cmake/llpc_version.cmake)
+if(NOT ICD_BUILD_LLPC)
+ set(DISABLE_LLPC_VERSION_USES_LLVM ON)
+endif()
+
add_llpc_version_projects()
### Top-level VKGC Interface ###
diff --git a/cmake/CompilerStandalone.cmake b/cmake/CompilerStandalone.cmake
index a2f335f676..d7f42eea16 100644
--- a/cmake/CompilerStandalone.cmake
+++ b/cmake/CompilerStandalone.cmake
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/cmake/compilerutils.cmake b/cmake/compilerutils.cmake
index 440e63d741..7db7bb6eaf 100644
--- a/cmake/compilerutils.cmake
+++ b/cmake/compilerutils.cmake
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/cmake/continuations.cmake b/cmake/continuations.cmake
index cf7b96ed80..e6716ad654 100644
--- a/cmake/continuations.cmake
+++ b/cmake/continuations.cmake
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/cmake/lgc.cmake b/cmake/lgc.cmake
index 87aae4a8bb..baab57084b 100644
--- a/cmake/lgc.cmake
+++ b/cmake/lgc.cmake
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/cmake/llpc_version.cmake b/cmake/llpc_version.cmake
index 881eb464a6..c318af06d1 100644
--- a/cmake/llpc_version.cmake
+++ b/cmake/llpc_version.cmake
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/compilerutils/include/compilerutils/CompilerUtils.h b/compilerutils/include/compilerutils/CompilerUtils.h
index 0ca8d72b81..b324938d89 100644
--- a/compilerutils/include/compilerutils/CompilerUtils.h
+++ b/compilerutils/include/compilerutils/CompilerUtils.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/compilerutils/include/compilerutils/LoweringPointerTupleMap.h b/compilerutils/include/compilerutils/LoweringPointerTupleMap.h
index 8111ac7157..60c3c84327 100644
--- a/compilerutils/include/compilerutils/LoweringPointerTupleMap.h
+++ b/compilerutils/include/compilerutils/LoweringPointerTupleMap.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -116,6 +116,20 @@ template <typename KeyT, typename ValueT, bool TrackReverse> class LoweringPoint
return decode(&it->second);
}
+ KeyT lookupUniqueKey(ValueT value) const {
+ static_assert(TrackReverse);
+
+ auto it = m_reverseMap.find(value);
+ if (it == m_reverseMap.end())
+ return nullptr;
+
+ uintptr_t keyValue = it->second[0];
+ if (keyValue & 1u) // 1-N mapping, keyValue is N number but not key ptr
+ return nullptr;
+
+ return reinterpret_cast<KeyT>(it->second[0]);
+ }
+
llvm::ArrayRef<ValueT> set(KeyT key, llvm::ArrayRef<ValueT> value) {
if (value.empty()) {
auto it = m_map.find(key);
diff --git a/compilerutils/include/compilerutils/TypeLowering.h b/compilerutils/include/compilerutils/TypeLowering.h
index fb57d825da..f697681db0 100644
--- a/compilerutils/include/compilerutils/TypeLowering.h
+++ b/compilerutils/include/compilerutils/TypeLowering.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/compilerutils/lib/CompilerUtils.cpp b/compilerutils/lib/CompilerUtils.cpp
index 3fa8892098..81f8ae571d 100644
--- a/compilerutils/lib/CompilerUtils.cpp
+++ b/compilerutils/lib/CompilerUtils.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -135,6 +135,12 @@ namespace {
// Get the name of a global that is copied to a different module for inlining.
std::string getCrossModuleName(GlobalValue &gv) {
+ if (auto *fn = dyn_cast<Function>(&gv)) {
+ // Intrinsics should not be renamed since the IR verifier insists on a "correct" name mangling based on any
+ // overloaded types.
+ if (fn->isIntrinsic())
+ return fn->getName().str();
+ }
return (Twine(gv.getName()) + ".cloned." + gv.getParent()->getName()).str();
}
@@ -314,8 +320,7 @@ GlobalValue *CompilerUtils::CrossModuleInliner::findCopiedGlobal(GlobalValue &so
return found->second;
}
- auto *gv =
- targetModule.getNamedValue((Twine(sourceGv.getName()) + ".cloned." + sourceGv.getParent()->getName()).str());
+ GlobalValue *gv = targetModule.getNamedValue(getCrossModuleName(sourceGv));
if (gv)
assert(gv->getValueType() == sourceGv.getValueType());
return gv;
diff --git a/compilerutils/lib/TypeLowering.cpp b/compilerutils/lib/TypeLowering.cpp
index c864391f8d..36f2db1cad 100644
--- a/compilerutils/lib/TypeLowering.cpp
+++ b/compilerutils/lib/TypeLowering.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/compilerutils/tool/cross-module-inline/CMakeLists.txt b/compilerutils/tool/cross-module-inline/CMakeLists.txt
index d77a1cbcc9..ac29184704 100644
--- a/compilerutils/tool/cross-module-inline/CMakeLists.txt
+++ b/compilerutils/tool/cross-module-inline/CMakeLists.txt
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/compilerutils/tool/cross-module-inline/cross-module-inline.cpp b/compilerutils/tool/cross-module-inline/cross-module-inline.cpp
index a90c3ac83d..fbc1484816 100644
--- a/compilerutils/tool/cross-module-inline/cross-module-inline.cpp
+++ b/compilerutils/tool/cross-module-inline/cross-module-inline.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/imported/llvm-dialects b/imported/llvm-dialects
index 16a0e93317..69e114f9d8 160000
--- a/imported/llvm-dialects
+++ b/imported/llvm-dialects
@@ -1 +1 @@
-Subproject commit 16a0e93317979f0b281458a5f3b830e0426983b1
+Subproject commit 69e114f9d8863ab056cf0e2392d82daadd4b0b95
diff --git a/include/gpurt-compiler.h b/include/gpurt-compiler.h
index ad6d3259a5..eeaa71b26a 100644
--- a/include/gpurt-compiler.h
+++ b/include/gpurt-compiler.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/include/khronos/GLSL.std.450.h b/include/khronos/GLSL.std.450.h
index 93f05c9936..7c6ef64370 100644
--- a/include/khronos/GLSL.std.450.h
+++ b/include/khronos/GLSL.std.450.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2015-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2015-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/include/khronos/spirv.hpp b/include/khronos/spirv.hpp
index f6e7f87d2f..85c1549fd2 100644
--- a/include/khronos/spirv.hpp
+++ b/include/khronos/spirv.hpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2015-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2015-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/include/vkgcBase.h b/include/vkgcBase.h
index ee57be0e91..7c5561f143 100644
--- a/include/vkgcBase.h
+++ b/include/vkgcBase.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/include/vkgcDefs.h b/include/vkgcDefs.h
index 30eb24ae31..3ffb6a2080 100644
--- a/include/vkgcDefs.h
+++ b/include/vkgcDefs.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -78,6 +78,7 @@ namespace Vkgc {
static const unsigned Version = LLPC_INTERFACE_MAJOR_VERSION;
static const unsigned InternalDescriptorSetId = static_cast<unsigned>(-1);
static const unsigned MaxVertexAttribs = 64;
+static const unsigned MaxVertexBindings = 64;
static const unsigned MaxColorTargets = 8;
static const unsigned MaxFetchShaderInternalBufferSize = 16 * MaxVertexAttribs;
@@ -473,6 +474,7 @@ struct PipelineOptions {
/// loading it from userdata
unsigned reserved20;
bool enablePrimGeneratedQuery; ///< If set, primitive generated query is enabled
+ bool disablePerCompFetch; ///< Disable per component fetch in uber fetch shader.
};
/// Prototype of allocator for output data buffer, used in shader-specific operations.
@@ -498,6 +500,7 @@ struct ResourceNodeData {
bool mergedLocationBinding; ///< TRUE if location and binding are merged in spirv binary
unsigned isTexelBuffer; ///< TRUE if it is ImageBuffer or TextureBuffer
unsigned isDefaultUniformSampler; ///< TRUE if it's sampler image in default uniform struct
+ unsigned columnCount; ///< Column count if this is a matrix variable.
BasicType basicType; ///< Type of the variable or element
};
@@ -548,7 +551,11 @@ struct ShaderModuleUsage {
bool usePointSize; ///< Whether gl_PointSize is used in output
bool useShadingRate; ///< Whether shading rate is used
bool useSampleInfo; ///< Whether gl_SamplePosition or InterpolateAtSample are used
- bool useClipVertex; ///< Whether gl_useClipVertex is used
+ bool useClipVertex; ///< Whether gl_ClipVertex is used
+ bool useFrontColor; ///< Whether gl_FrontColor is used
+ bool useBackColor; ///< Whether gl_BackColor is used
+ bool useFrontSecondaryColor; ///< Whether gl_FrontSecondaryColor is used
+ bool useBackSecondaryColor; ///< Whether gl_BackSecondaryColor is used
ResourcesNodes *pResources; ///< Resource node for buffers and opaque types
bool useFragCoord; ///< Whether gl_FragCoord is used
bool originUpperLeft; ///< Whether pixel origin is upper-left
@@ -1063,6 +1070,12 @@ enum CpsFlag : unsigned {
CpsFlagStackInGlobalMem = 1 << 0, // Put stack in global memory instead of scratch.
};
+enum class LibraryMode : unsigned {
+ Any, //< Compiler output can be used as both a pipeline and a library
+ Pipeline, //< Compiler output can be used only as a completed pipeline
+ Library, //< Compiler output can only be used as a library
+};
+
/// RayTracing state
struct RtState {
unsigned nodeStrideShift; ///< Ray tracing BVH node stride
@@ -1242,6 +1255,8 @@ struct GraphicsPipelineBuildInfo {
unsigned numUniformConstantMaps; ///< Number of uniform constant maps
UniformConstantMap **ppUniformMaps; ///< Pointers to array of pointers for the uniform constant map.
ApiXfbOutData apiXfbOutData; ///< Transform feedback data specified by API interface.
+ bool vbAddressLowBitsKnown; ///< Whether vbAddressLowBits is valid
+ uint8_t vbAddressLowBits[MaxVertexBindings]; ///< Lowest two bits of vertex buffer addresses
};
/// Represents info to build a compute pipeline.
@@ -1283,18 +1298,25 @@ struct RayTracingPipelineBuildInfo {
uint64_t pipelineLayoutApiHash; ///< Pipeline Layout Api Hash
unsigned shaderGroupCount; ///< Count of shader group
const VkRayTracingShaderGroupCreateInfoKHR *pShaderGroups; ///< An array of shader group
+ LibraryMode libraryMode; ///< Whether to compile as pipeline or library or both
+ unsigned libraryCount; ///< Count of libraries linked into this build
+ const BinaryData *pLibrarySummaries; ///< MsgPack summaries of libraries linked into this build
#if LLPC_CLIENT_INTERFACE_MAJOR_VERSION < 62
BinaryData shaderTraceRay; ///< Trace-ray SPIR-V binary data
#endif
- PipelineOptions options; ///< Per pipeline tuning options
- unsigned maxRecursionDepth; ///< Ray tracing max recursion depth
- unsigned indirectStageMask; ///< Ray tracing indirect stage mask
- LlpcRaytracingMode mode; ///< Ray tracing compiling mode
- RtState rtState; ///< Ray tracing state
+ PipelineOptions options; ///< Per pipeline tuning options
+ unsigned maxRecursionDepth; ///< Ray tracing max recursion depth
+ unsigned indirectStageMask; ///< Ray tracing indirect stage mask
+ LlpcRaytracingMode mode; ///< Ray tracing compiling mode
+ RtState rtState; ///< Ray tracing state
+ // These pipeline library fields are superseded by the pLibrarySummaries when available.
+ //@{
+ bool hasPipelineLibrary; ///< Whether include pipeline library
+ unsigned pipelineLibStageMask; ///< Pipeline library stage mask
+ //@}
+
unsigned payloadSizeMaxInLib; ///< Pipeline library maxPayloadSize
unsigned attributeSizeMaxInLib; ///< Pipeline library maxAttributeSize
- bool hasPipelineLibrary; ///< Whether include pipeline library
- unsigned pipelineLibStageMask; ///< Pipeline library stage mask
bool isReplay; ///< Pipeline is created for replaying
const void *pClientMetadata; ///< Pointer to (optional) client-defined data to be
/// stored inside the ELF
@@ -1501,6 +1523,12 @@ class IPipelineDumper {
/// @param [in] dumpFile The handle of pipeline dump file
/// @param [in] pipelineMeta Ray tracing pipeline metadata binary
static void VKAPI_CALL DumpRayTracingPipelineMetadata(void *dumpFile, BinaryData *pipelineMeta);
+
+ /// Dumps ray tracing library summary.
+ ///
+ /// @param [in] dumpFile The handle of pipeline dump file
+ /// @param [in] librarySummary Ray tracing library summary binary
+ static void VKAPI_CALL DumpRayTracingLibrarySummary(void *dumpFile, BinaryData *librarySummary);
};
// =====================================================================================================================
diff --git a/include/vkgcGpurtShim.h b/include/vkgcGpurtShim.h
index 0c4ac1a663..2246b36702 100644
--- a/include/vkgcGpurtShim.h
+++ b/include/vkgcGpurtShim.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/CMakeLists.txt b/lgc/CMakeLists.txt
index 8cde640507..088e1a342a 100644
--- a/lgc/CMakeLists.txt
+++ b/lgc/CMakeLists.txt
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
@@ -141,6 +141,7 @@ target_sources(LLVMlgc PRIVATE
patch/Gfx9Chip.cpp
patch/Gfx9ConfigBuilder.cpp
patch/LowerDebugPrintf.cpp
+ patch/LowerDesc.cpp
patch/MeshTaskShader.cpp
patch/NggPrimShader.cpp
patch/Patch.cpp
@@ -183,6 +184,7 @@ target_sources(LLVMlgc PRIVATE
state/PassManagerCache.cpp
state/PipelineShaders.cpp
state/PipelineState.cpp
+ state/RayTracingLibrarySummary.cpp
state/ResourceUsage.cpp
state/ShaderModes.cpp
state/ShaderStage.cpp
diff --git a/lgc/builder/ArithBuilder.cpp b/lgc/builder/ArithBuilder.cpp
index 8671bb1ce1..186f2c1e63 100644
--- a/lgc/builder/ArithBuilder.cpp
+++ b/lgc/builder/ArithBuilder.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -1296,7 +1296,7 @@ Value *BuilderImpl::createFMix(Value *x, Value *y, Value *a, const Twine &instNa
//
// @param value : Value to canonicalize
Value *BuilderImpl::canonicalize(Value *value) {
- const auto &shaderMode = getShaderModes()->getCommonShaderMode(m_shaderStage);
+ const auto &shaderMode = getShaderModes()->getCommonShaderMode(m_shaderStage.value());
auto destTy = value->getType();
FpDenormMode denormMode = destTy->getScalarType()->isHalfTy() ? shaderMode.fp16DenormMode
: destTy->getScalarType()->isFloatTy() ? shaderMode.fp32DenormMode
diff --git a/lgc/builder/Builder.cpp b/lgc/builder/Builder.cpp
index a491889446..5094aae178 100644
--- a/lgc/builder/Builder.cpp
+++ b/lgc/builder/Builder.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -30,6 +30,7 @@
*/
#include "BuilderRecorder.h"
#include "lgc/LgcContext.h"
+#include "lgc/LgcDialect.h"
#include "lgc/builder/BuilderImpl.h"
#include "lgc/state/PipelineState.h"
#include "lgc/state/ShaderModes.h"
diff --git a/lgc/builder/BuilderBase.cpp b/lgc/builder/BuilderBase.cpp
index 21d4caf638..92a993b347 100644
--- a/lgc/builder/BuilderBase.cpp
+++ b/lgc/builder/BuilderBase.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -31,6 +31,7 @@
#include "lgc/util/BuilderBase.h"
#include "compilerutils/CompilerUtils.h"
+#include "lgc/CommonDefs.h"
#include "lgc/LgcDialect.h"
#include "lgc/state/IntrinsDefs.h"
#include "llvm/IR/IntrinsicInst.h"
diff --git a/lgc/builder/BuilderImpl.cpp b/lgc/builder/BuilderImpl.cpp
index ec99c51e21..1ee82a9d57 100644
--- a/lgc/builder/BuilderImpl.cpp
+++ b/lgc/builder/BuilderImpl.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -256,7 +256,8 @@ bool BuilderImpl::supportDppRowXmask() const {
bool BuilderImpl::supportWaveWideBPermute() const {
auto gfxIp = getPipelineState()->getTargetInfo().getGfxIpVersion().major;
auto supportBPermute = gfxIp == 8 || gfxIp == 9;
- auto waveSize = getPipelineState()->getShaderWaveSize(getShaderStage(GetInsertBlock()->getParent()));
+ auto shaderStage = getShaderStage(GetInsertBlock()->getParent());
+ auto waveSize = getPipelineState()->getShaderWaveSize(shaderStage.value());
supportBPermute = supportBPermute || (gfxIp >= 10 && waveSize == 32);
return supportBPermute;
}
@@ -271,7 +272,8 @@ bool BuilderImpl::supportPermLaneDpp() const {
// Get whether the context we are building in supports permute lane 64 DPP operations.
bool BuilderImpl::supportPermLane64Dpp() const {
auto gfxip = getPipelineState()->getTargetInfo().getGfxIpVersion().major;
- auto waveSize = getPipelineState()->getShaderWaveSize(getShaderStage(GetInsertBlock()->getParent()));
+ auto shaderStage = getShaderStage(GetInsertBlock()->getParent());
+ auto waveSize = getPipelineState()->getShaderWaveSize(shaderStage.value());
return gfxip >= 11 && waveSize == 64;
}
@@ -793,7 +795,7 @@ Value *BuilderImpl::scalarize(Value *value0, Value *value1, Value *value2,
// and thus on the shader stage it is used from.
Value *BuilderImpl::CreateGetLaneNumber() {
Value *result = CreateIntrinsic(Intrinsic::amdgcn_mbcnt_lo, {}, {getInt32(-1), getInt32(0)});
- if (getPipelineState()->getShaderWaveSize(m_shaderStage) == 64)
+ if (getPipelineState()->getShaderWaveSize(m_shaderStage.value()) == 64)
result = CreateIntrinsic(Intrinsic::amdgcn_mbcnt_hi, {}, {getInt32(-1), result});
return result;
}
diff --git a/lgc/builder/BuilderRecorder.cpp b/lgc/builder/BuilderRecorder.cpp
index 179d9690fe..b039121209 100644
--- a/lgc/builder/BuilderRecorder.cpp
+++ b/lgc/builder/BuilderRecorder.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -172,8 +172,6 @@ StringRef BuilderRecorder::getCallName(BuilderOpcode opcode) {
return "msad4";
case BuilderOpcode::FDot2:
return "fdot2";
- case BuilderOpcode::LoadBufferDesc:
- return "load.buffer.desc";
case BuilderOpcode::GetDescStride:
return "get.desc.stride";
case BuilderOpcode::GetDescPtr:
@@ -328,6 +326,10 @@ StringRef BuilderRecorder::getCallName(BuilderOpcode opcode) {
return "subgroup.mbcnt";
case BuilderOpcode::SubgroupPartition:
return "subgroup.partition";
+ case BuilderOpcode::QuadAll:
+ return "quad.all";
+ case BuilderOpcode::QuadAny:
+ return "quad.any";
case BuilderOpcode::Count:
break;
}
@@ -1056,26 +1058,6 @@ Value *Builder::CreateFDot2(Value *a, Value *b, Value *scalar, Value *clamp, con
return record(BuilderOpcode::FDot2, scalar->getType(), {a, b, scalar, clamp}, instName);
}
-// =====================================================================================================================
-// Create a load of a buffer descriptor.
-//
-// @param descSet : Descriptor set
-// @param binding : Descriptor binding
-// @param descIndex : Descriptor index
-// @param flags : BufferFlag* bit settings
-// @param instName : Name to give instruction(s)
-Value *Builder::CreateLoadBufferDesc(uint64_t descSet, unsigned binding, Value *descIndex, unsigned flags,
- const Twine &instName) {
- return record(BuilderOpcode::LoadBufferDesc, getBufferDescTy(),
- {
- getInt64(descSet),
- getInt32(binding),
- descIndex,
- getInt32(flags),
- },
- instName);
-}
-
// =====================================================================================================================
// Create a get of the stride (in bytes) of a descriptor. Returns an i32 value.
//
@@ -1978,6 +1960,26 @@ Value *Builder::CreateSubgroupPartition(Value *const value, const Twine &instNam
return record(BuilderOpcode::SubgroupPartition, FixedVectorType::get(getInt32Ty(), 4), value, instName);
}
+// =====================================================================================================================
+// Create a Quad all.
+//
+// @param value : The value to contribute
+// @param requireFullQuads: whether it requires full quads.
+// @param instName : Name to give instruction(s)
+Value *Builder::CreateQuadAll(Value *const value, bool requireFullQuads, const Twine &instName) {
+ return record(BuilderOpcode::QuadAll, getInt1Ty(), {value, getInt1(requireFullQuads)}, instName);
+}
+
+// =====================================================================================================================
+// Create a Quad any.
+//
+// @param value : The value to contribute
+// @param requireFullQuads: whether it requires full quads.
+// @param instName : Name to give instruction(s)
+Value *Builder::CreateQuadAny(Value *const value, bool requireFullQuads, const llvm::Twine &instName) {
+ return record(BuilderOpcode::QuadAny, getInt1Ty(), {value, getInt1(requireFullQuads)}, instName);
+}
+
// =====================================================================================================================
// Record one Builder call
//
@@ -2100,7 +2102,6 @@ Instruction *Builder::record(BuilderOpcode opcode, Type *resultTy, ArrayRef<Valu
case BuilderOpcode::ImageLoadWithFmask:
case BuilderOpcode::ImageSample:
case BuilderOpcode::ImageSampleConvert:
- case BuilderOpcode::LoadBufferDesc:
case BuilderOpcode::LoadPushConstantsPtr:
case BuilderOpcode::ReadBaryCoord:
case BuilderOpcode::ReadBuiltInInput:
@@ -2149,6 +2150,8 @@ Instruction *Builder::record(BuilderOpcode opcode, Type *resultTy, ArrayRef<Valu
case BuilderOpcode::SubgroupSwizzleMask:
case BuilderOpcode::SubgroupSwizzleQuad:
case BuilderOpcode::Barrier:
+ case BuilderOpcode::QuadAll:
+ case BuilderOpcode::QuadAny:
// TODO: we should mark these functions 'ReadNone' in theory, but that need to wait until we fix all convergent
// issues in LLVM optimizations.
func->addFnAttr(Attribute::Convergent);
@@ -2189,13 +2192,13 @@ Instruction *Builder::record(BuilderOpcode opcode, Type *resultTy, ArrayRef<Valu
// @param name : Name of function declaration
// @returns : Opcode
BuilderOpcode BuilderRecorder::getOpcodeFromName(StringRef name) {
- assert(name.startswith(BuilderCallPrefix));
+ assert(name.starts_with(BuilderCallPrefix));
name = name.drop_front(strlen(BuilderCallPrefix));
unsigned bestOpcode = 0;
unsigned bestLength = 0;
for (unsigned opcode = 0; opcode != BuilderOpcode::Count; ++opcode) {
StringRef opcodeName = getCallName(static_cast<BuilderOpcode>(opcode));
- if (name.startswith(opcodeName)) {
+ if (name.starts_with(opcodeName)) {
if (opcodeName.size() > bestLength) {
bestLength = opcodeName.size();
bestOpcode = opcode;
diff --git a/lgc/builder/BuilderRecorder.h b/lgc/builder/BuilderRecorder.h
index da4860e946..a0e91a7cfb 100644
--- a/lgc/builder/BuilderRecorder.h
+++ b/lgc/builder/BuilderRecorder.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -106,7 +106,6 @@ enum BuilderOpcode : unsigned {
FDot2,
// Descriptor
- LoadBufferDesc,
GetDescStride,
GetDescPtr,
LoadPushConstantsPtr,
@@ -194,6 +193,8 @@ enum BuilderOpcode : unsigned {
SubgroupWriteInvocation,
SubgroupMbcnt,
SubgroupPartition,
+ QuadAll,
+ QuadAny,
// Total count of opcodes
Count
};
diff --git a/lgc/builder/BuilderReplayer.cpp b/lgc/builder/BuilderReplayer.cpp
index b0c2b15524..eb095b109f 100644
--- a/lgc/builder/BuilderReplayer.cpp
+++ b/lgc/builder/BuilderReplayer.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -78,9 +78,9 @@ bool BuilderReplayer::runImpl(Module &module, PipelineState *pipelineState) {
if (pipelineState->getTargetInfo().getGfxIpVersion().major >= 10) {
// NOTE: The sub-attribute 'wavefrontsize' of 'target-features' is set in advance to let optimization
// pass know we are in which wavesize mode.
- ShaderStage shaderStage = lgc::getShaderStage(&func);
- if (shaderStage != ShaderStageInvalid) {
- unsigned waveSize = pipelineState->getShaderWaveSize(shaderStage);
+ auto shaderStage = lgc::getShaderStage(&func);
+ if (shaderStage) {
+ unsigned waveSize = pipelineState->getShaderWaveSize(shaderStage.value());
func.addFnAttr("target-features", ",+wavefrontsize" + std::to_string(waveSize));
}
}
@@ -95,13 +95,13 @@ bool BuilderReplayer::runImpl(Module &module, PipelineState *pipelineState) {
if (const MDNode *funcMeta = func.getMetadata(opcodeMetaKindId)) {
const ConstantAsMetadata *metaConst = cast<ConstantAsMetadata>(funcMeta->getOperand(0));
opcode = cast<ConstantInt>(metaConst->getValue())->getZExtValue();
- assert(func.getName().startswith(BuilderCallPrefix));
+ assert(func.getName().starts_with(BuilderCallPrefix));
assert(func.getName()
.slice(strlen(BuilderCallPrefix), StringRef::npos)
- .startswith(BuilderRecorder::getCallName(static_cast<BuilderOpcode>(opcode))) &&
+ .starts_with(BuilderRecorder::getCallName(static_cast<BuilderOpcode>(opcode))) &&
"lgc.create.* mismatch!");
} else {
- if (!func.getName().startswith(BuilderCallPrefix))
+ if (!func.getName().starts_with(BuilderCallPrefix))
continue; // Not lgc.create.* call
opcode = BuilderRecorder::getOpcodeFromName(func.getName());
}
@@ -136,12 +136,13 @@ void BuilderReplayer::replayCall(unsigned opcode, CallInst *call) {
m_enclosingFunc = enclosingFunc;
auto mapIt = m_shaderStageMap.find(enclosingFunc);
- ShaderStage stage = ShaderStageInvalid;
+ std::optional<ShaderStageEnum> stage;
if (mapIt == m_shaderStageMap.end()) {
stage = getShaderStage(enclosingFunc);
- m_shaderStageMap[enclosingFunc] = stage;
- } else
+ m_shaderStageMap[enclosingFunc] = stage.value();
+ } else {
stage = mapIt->second;
+ }
m_builder->setShaderStage(stage);
}
@@ -400,14 +401,6 @@ Value *BuilderReplayer::processCall(unsigned opcode, CallInst *call) {
return m_builder->CreateFDot2(args[0], args[1], args[2], args[3]);
}
- // Replayer implementations of DescBuilder methods
- case BuilderOpcode::LoadBufferDesc: {
- return m_builder->CreateLoadBufferDesc(cast<ConstantInt>(args[0])->getZExtValue(), // descSet
- cast<ConstantInt>(args[1])->getZExtValue(), // binding
- args[2], // descIndex
- cast<ConstantInt>(args[3])->getZExtValue()); // flags
- }
-
case BuilderOpcode::GetDescStride:
return m_builder->CreateGetDescStride(static_cast<ResourceNodeType>(cast<ConstantInt>(args[0])->getZExtValue()),
static_cast<ResourceNodeType>(cast<ConstantInt>(args[1])->getZExtValue()),
@@ -838,5 +831,11 @@ Value *BuilderReplayer::processCall(unsigned opcode, CallInst *call) {
case BuilderOpcode::SubgroupPartition: {
return m_builder->CreateSubgroupPartition(args[0]);
}
+ case BuilderOpcode::QuadAll: {
+ return m_builder->CreateQuadAll(args[0], cast<ConstantInt>(args[1])->getZExtValue());
+ }
+ case BuilderOpcode::QuadAny: {
+ return m_builder->CreateQuadAny(args[0], cast<ConstantInt>(args[1])->getZExtValue());
+ }
}
}
diff --git a/lgc/builder/DescBuilder.cpp b/lgc/builder/DescBuilder.cpp
index 6e96c12817..5c9609b7b1 100644
--- a/lgc/builder/DescBuilder.cpp
+++ b/lgc/builder/DescBuilder.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -44,32 +44,6 @@
using namespace lgc;
using namespace llvm;
-// =====================================================================================================================
-// Create a load of a buffer descriptor.
-//
-// If descSet = InternalDescriptorSetId (0xFFFFFFFF), this is an internal user data, which is a plain 64-bit pointer,
-// flags must be 'BufferFlagAddress' i64 address is returned.
-//
-// @param descSet : Descriptor set
-// @param binding : Descriptor binding
-// @param descIndex : Descriptor index
-// @param flags : BufferFlag* bit settings
-// @param instName : Name to give instruction(s)
-Value *BuilderImpl::CreateLoadBufferDesc(uint64_t descSet, unsigned binding, Value *descIndex, unsigned flags,
- const Twine &instName) {
- Value *desc = nullptr;
- bool return64Address = false;
- if (flags & BufferFlagAddress)
- return64Address = true;
-
- desc = CreateBufferDesc(descSet, binding, descIndex, flags, instName);
- if (return64Address || isa<PoisonValue>(desc))
- return desc;
-
- // Convert to fat pointer.
- return create<BufferDescToPtrOp>(desc);
-}
-
// =====================================================================================================================
// Create a buffer descriptor, not convert to a fat pointer
//
@@ -87,12 +61,7 @@ Value *BuilderImpl::CreateBufferDesc(uint64_t descSet, unsigned binding, Value *
bool return64Address = false;
descIndex = scalarizeIfUniform(descIndex, flags & BufferFlagNonUniform);
- // Mark the shader as reading and writing (if applicable) a resource.
- auto resUsage = getPipelineState()->getShaderResourceUsage(m_shaderStage);
- resUsage->resourceRead = true;
- if (flags & BufferFlagWritten)
- resUsage->resourceWrite = true;
- else if (flags & BufferFlagAddress)
+ if (flags & BufferFlagAddress)
return64Address = true;
// Find the descriptor node.
@@ -133,14 +102,10 @@ Value *BuilderImpl::CreateBufferDesc(uint64_t descSet, unsigned binding, Value *
unsigned dwordSize = descTy->getPrimitiveSizeInBits() / 32;
unsigned dwordOffset = cast<ConstantInt>(descIndex)->getZExtValue() * dwordSize;
- if (dwordOffset + dwordSize > node->sizeInDwords) {
- // Index out of range
- desc = PoisonValue::get(descTy);
- } else {
- dwordOffset += node->offsetInDwords;
- dwordOffset += (binding - node->binding) * node->stride;
- desc = create<LoadUserDataOp>(descTy, dwordOffset * 4);
- }
+ assert((dwordOffset + dwordSize <= node->sizeInDwords) && "Resource index out of range");
+ dwordOffset += node->offsetInDwords;
+ dwordOffset += (binding - node->binding) * node->stride;
+ desc = create<LoadUserDataOp>(descTy, dwordOffset * 4);
if (return64Address)
return desc;
} else if (node->concreteType == ResourceNodeType::InlineBuffer) {
diff --git a/lgc/builder/ImageBuilder.cpp b/lgc/builder/ImageBuilder.cpp
index 08043b337b..a44d8f31f2 100644
--- a/lgc/builder/ImageBuilder.cpp
+++ b/lgc/builder/ImageBuilder.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -424,8 +424,8 @@ Value *BuilderImpl::CreateImageLoad(Type *resultTy, unsigned dim, unsigned flags
Value *mipLevel, const Twine &instName) {
imageDesc = fixImageDescForRead(imageDesc);
// Mark usage of images, to allow the compute workgroup reconfiguration optimization.
- getPipelineState()->getShaderResourceUsage(m_shaderStage)->useImages = true;
- getPipelineState()->getShaderResourceUsage(m_shaderStage)->resourceRead = true;
+ getPipelineState()->getShaderResourceUsage(m_shaderStage.value())->useImages = true;
+ getPipelineState()->getShaderResourceUsage(m_shaderStage.value())->resourceRead = true;
assert(coord->getType()->getScalarType()->isIntegerTy(32));
imageDesc = patchCubeDescriptor(imageDesc, dim);
coord = handleFragCoordViewIndex(coord, flags, dim);
@@ -509,7 +509,7 @@ Value *BuilderImpl::CreateImageLoad(Type *resultTy, unsigned dim, unsigned flags
Value *result = imageInst;
if (flags & ImageFlagNonUniformImage)
result = createWaterfallLoop(imageInst, imageDescArgIndex,
- getPipelineState()->getShaderOptions(m_shaderStage).scalarizeWaterfallLoads);
+ getPipelineState()->getShaderOptions(m_shaderStage.value()).scalarizeWaterfallLoads);
else if (flags & ImageFlagEnforceReadFirstLaneImage)
enforceReadFirstLane(imageInst, imageDescArgIndex);
@@ -529,6 +529,13 @@ Value *BuilderImpl::CreateImageLoad(Type *resultTy, unsigned dim, unsigned flags
if (m_pipelineState->getOptions().allowNullDescriptor) {
// Check dword3 against 0 for a null descriptor
Value *descWord3 = CreateExtractElement(imageDesc, 3);
+ if (m_pipelineState->getOptions().maskOffNullDescriptorTypeField) {
+ GfxIpVersion gfxIp = getPipelineState()->getTargetInfo().getGfxIpVersion();
+ SqImgRsrcRegHandler proxySqRsrcRegHelper(this, imageDesc, &gfxIp);
+ unsigned typeMask = proxySqRsrcRegHelper.getRegMask(SqRsrcRegs::Type);
+ // Mask off the type bits for the null descriptor
+ descWord3 = CreateAnd(descWord3, getInt32(~typeMask));
+ }
Value *isNullDesc = CreateICmpEQ(descWord3, getInt32(0));
defaults[2] = CreateSelect(isNullDesc, getInt64(0), getInt64(1));
}
@@ -621,8 +628,7 @@ Value *BuilderImpl::CreateImageLoadWithFmask(Type *resultTy, unsigned dim, unsig
Value *BuilderImpl::CreateImageStore(Value *texel, unsigned dim, unsigned flags, Value *imageDesc, Value *coord,
Value *mipLevel, const Twine &instName) {
// Mark usage of images, to allow the compute workgroup reconfiguration optimization.
- getPipelineState()->getShaderResourceUsage(m_shaderStage)->useImages = true;
- getPipelineState()->getShaderResourceUsage(m_shaderStage)->resourceWrite = true;
+ getPipelineState()->getShaderResourceUsage(m_shaderStage.value())->resourceWrite = true;
assert(coord->getType()->getScalarType()->isIntegerTy(32));
imageDesc = patchCubeDescriptor(imageDesc, dim);
coord = handleFragCoordViewIndex(coord, flags, dim);
@@ -708,7 +714,7 @@ Value *BuilderImpl::CreateImageStore(Value *texel, unsigned dim, unsigned flags,
// Add a waterfall loop if needed.
if (flags & ImageFlagNonUniformImage)
createWaterfallLoop(imageStore, imageDescArgIndex,
- getPipelineState()->getShaderOptions(m_shaderStage).scalarizeWaterfallLoads);
+ getPipelineState()->getShaderOptions(m_shaderStage.value()).scalarizeWaterfallLoads);
else if (flags & ImageFlagEnforceReadFirstLaneImage)
enforceReadFirstLane(imageStore, imageDescArgIndex);
@@ -768,7 +774,7 @@ Value *BuilderImpl::CreateImageSampleConvertYCbCr(Type *resultTy, unsigned dim,
Value *convertingSamplerDesc, ArrayRef<Value *> address,
const Twine &instName) {
// Mark usage of images, to allow the compute workgroup reconfiguration optimization.
- getPipelineState()->getShaderResourceUsage(m_shaderStage)->useImages = true;
+ getPipelineState()->getShaderResourceUsage(m_shaderStage.value())->useImages = true;
Value *result = nullptr;
// Helper function to extract YCbCr meta data from ycbcrSamplerDesc
@@ -843,7 +849,8 @@ Value *BuilderImpl::CreateImageGather(Type *resultTy, unsigned dim, unsigned fla
if (texelComponentTy->isIntegerTy()) {
// Handle integer texel component type.
- gatherTy = FixedVectorType::get(getFloatTy(), 4);
+ Type *replacedTy = texelComponentTy->getIntegerBitWidth() == 16 ? getHalfTy() : getFloatTy();
+ gatherTy = FixedVectorType::get(replacedTy, 4);
if (resultTy != texelTy)
gatherTy = StructType::get(getContext(), {gatherTy, getInt32Ty()});
}
@@ -919,7 +926,7 @@ Value *BuilderImpl::CreateImageSampleGather(Type *resultTy, unsigned dim, unsign
const Twine &instName, bool isSample) {
imageDesc = fixImageDescForRead(imageDesc);
// Mark usage of images, to allow the compute workgroup reconfiguration optimization.
- getPipelineState()->getShaderResourceUsage(m_shaderStage)->useImages = true;
+ getPipelineState()->getShaderResourceUsage(m_shaderStage.value())->useImages = true;
// Set up the mask of address components provided, for use in searching the intrinsic ID table
unsigned addressMask = 0;
for (unsigned i = 0; i != ImageAddressCount; ++i) {
@@ -1058,7 +1065,7 @@ Value *BuilderImpl::CreateImageSampleGather(Type *resultTy, unsigned dim, unsign
if (!nonUniformArgIndexes.empty())
imageOp = createWaterfallLoop(imageOp, nonUniformArgIndexes,
- getPipelineState()->getShaderOptions(m_shaderStage).scalarizeWaterfallLoads);
+ getPipelineState()->getShaderOptions(m_shaderStage.value()).scalarizeWaterfallLoads);
return imageOp;
}
@@ -1111,7 +1118,7 @@ Value *BuilderImpl::CreateImageAtomicCompareSwap(unsigned dim, unsigned flags, A
Value *BuilderImpl::CreateImageAtomicCommon(unsigned atomicOp, unsigned dim, unsigned flags, AtomicOrdering ordering,
Value *imageDesc, Value *coord, Value *inputValue, Value *comparatorValue,
const Twine &instName) {
- getPipelineState()->getShaderResourceUsage(m_shaderStage)->resourceWrite = true;
+ getPipelineState()->getShaderResourceUsage(m_shaderStage.value())->resourceWrite = true;
assert(coord->getType()->getScalarType()->isIntegerTy(32));
coord = handleFragCoordViewIndex(coord, flags, dim);
@@ -1166,8 +1173,9 @@ Value *BuilderImpl::CreateImageAtomicCommon(unsigned atomicOp, unsigned dim, uns
CreateIntrinsic(StructBufferAtomicIntrinsicTable[atomicOp], inputValue->getType(), args, nullptr, instName);
}
if (flags & ImageFlagNonUniformImage)
- atomicInst = createWaterfallLoop(atomicInst, imageDescArgIndex,
- getPipelineState()->getShaderOptions(m_shaderStage).scalarizeWaterfallLoads);
+ atomicInst =
+ createWaterfallLoop(atomicInst, imageDescArgIndex,
+ getPipelineState()->getShaderOptions(m_shaderStage.value()).scalarizeWaterfallLoads);
else if (flags & ImageFlagEnforceReadFirstLaneImage)
enforceReadFirstLane(atomicInst, imageDescArgIndex);
@@ -1195,11 +1203,11 @@ Value *BuilderImpl::CreateImageQueryLevels(unsigned dim, unsigned flags, Value *
dim = dim == DimCubeArray ? DimCube : dim;
Value *numMipLevel = nullptr;
+ GfxIpVersion gfxIp = getPipelineState()->getTargetInfo().getGfxIpVersion();
+ SqImgRsrcRegHandler proxySqRsrcRegHelper(this, imageDesc, &gfxIp);
if (dim == Dim2DMsaa || dim == Dim2DArrayMsaa)
numMipLevel = getInt32(1);
else {
- GfxIpVersion gfxIp = getPipelineState()->getTargetInfo().getGfxIpVersion();
- SqImgRsrcRegHandler proxySqRsrcRegHelper(this, imageDesc, &gfxIp);
Value *lastLevel = proxySqRsrcRegHelper.getReg(SqRsrcRegs::LastLevel);
Value *baseLevel = proxySqRsrcRegHelper.getReg(SqRsrcRegs::BaseLevel);
numMipLevel = CreateSub(lastLevel, baseLevel);
@@ -1210,6 +1218,11 @@ Value *BuilderImpl::CreateImageQueryLevels(unsigned dim, unsigned flags, Value *
if (m_pipelineState->getOptions().allowNullDescriptor) {
// Check dword3 against 0 for a null descriptor
Value *descWord3 = CreateExtractElement(imageDesc, 3);
+ if (m_pipelineState->getOptions().maskOffNullDescriptorTypeField) {
+ // Mask off the type bits for the null descriptor
+ unsigned typeMask = proxySqRsrcRegHelper.getRegMask(SqRsrcRegs::Type);
+ descWord3 = CreateAnd(descWord3, getInt32(~typeMask));
+ }
Value *isNullDesc = CreateICmpEQ(descWord3, getInt32(0));
numMipLevel = CreateSelect(isNullDesc, getInt32(0), numMipLevel);
}
@@ -1245,6 +1258,13 @@ Value *BuilderImpl::CreateImageQuerySamples(unsigned dim, unsigned flags, Value
// The sampler number is clamped 0 if allowNullDescriptor is on and image descriptor is a null descriptor
if (m_pipelineState->getOptions().allowNullDescriptor) {
+ if (m_pipelineState->getOptions().maskOffNullDescriptorTypeField) {
+ GfxIpVersion gfxIp = getPipelineState()->getTargetInfo().getGfxIpVersion();
+ SqImgRsrcRegHandler proxySqRsrcRegHelper(this, imageDesc, &gfxIp);
+ unsigned typeMask = proxySqRsrcRegHelper.getRegMask(SqRsrcRegs::Type);
+ // Mask off the type bits for the null descriptor
+ descWord3 = CreateAnd(descWord3, getInt32(~typeMask));
+ }
// Check dword3 against 0 for a null descriptor
Value *isNullDesc = CreateICmpEQ(descWord3, getInt32(0));
sampleNumber = CreateSelect(isNullDesc, getInt32(0), sampleNumber);
@@ -1314,6 +1334,11 @@ Value *BuilderImpl::CreateImageQuerySize(unsigned dim, unsigned flags, Value *im
if (m_pipelineState->getOptions().allowNullDescriptor) {
// Check dword3 against 0 for a null descriptor
Value *descWord3 = CreateExtractElement(imageDesc, 3);
+ if (m_pipelineState->getOptions().maskOffNullDescriptorTypeField) {
+ // Mask off the type bits for the null descriptor
+ unsigned typeMask = proxySqRsrcRegHelper.getRegMask(SqRsrcRegs::Type);
+ descWord3 = CreateAnd(descWord3, getInt32(~typeMask));
+ }
Value *isNullDesc = CreateICmpEQ(descWord3, getInt32(0));
width = CreateSelect(isNullDesc, getInt32(0), width);
height = CreateSelect(isNullDesc, getInt32(0), height);
@@ -1410,7 +1435,7 @@ Value *BuilderImpl::CreateImageGetLod(unsigned dim, unsigned flags, Value *image
if (!nonUniformArgIndexes.empty())
result = createWaterfallLoop(result, nonUniformArgIndexes,
- getPipelineState()->getShaderOptions(m_shaderStage).scalarizeWaterfallLoads);
+ getPipelineState()->getShaderOptions(m_shaderStage.value()).scalarizeWaterfallLoads);
return result;
}
@@ -1781,6 +1806,13 @@ Value *BuilderImpl::patchCubeDescriptor(Value *desc, unsigned dim) {
// If allowNullDescriptor is on and image descriptor is a null descriptor, keep elem3 and elem4 be zero
if (m_pipelineState->getOptions().allowNullDescriptor) {
+ if (m_pipelineState->getOptions().maskOffNullDescriptorTypeField) {
+ GfxIpVersion gfxIp = getPipelineState()->getTargetInfo().getGfxIpVersion();
+ SqImgRsrcRegHandler proxySqRsrcRegHelper(this, desc, &gfxIp);
+ unsigned typeMask = proxySqRsrcRegHelper.getRegMask(SqRsrcRegs::Type);
+ // Mask off the type bits for the null descriptor
+ originalElem3 = CreateAnd(originalElem3, getInt32(~typeMask));
+ }
// Check dword3 against 0 for a null descriptor
Value *zero = getInt32(0);
Value *isNullDesc = CreateICmpEQ(originalElem3, zero);
@@ -1818,7 +1850,7 @@ Value *BuilderImpl::handleFragCoordViewIndex(Value *coord, unsigned flags, unsig
// Get FragCoord, convert to signed i32, and add its x,y to the coordinate.
// For now, this just generates a call to lgc.input.import.builtin. A future commit will
// change it to use a Builder call to read the built-in.
- getPipelineState()->getShaderResourceUsage(m_shaderStage)->builtInUsage.fs.fragCoord = true;
+ getPipelineState()->getShaderResourceUsage(m_shaderStage.value())->builtInUsage.fs.fragCoord = true;
const static unsigned BuiltInFragCoord = 15;
std::string callName = lgcName::InputImportBuiltIn;
@@ -1841,24 +1873,24 @@ Value *BuilderImpl::handleFragCoordViewIndex(Value *coord, unsigned flags, unsig
// Get ViewIndex and use it as the z coordinate.
// For now, this just generates a call to lgc.input.import.builtin. A future commit will
// change it to use a Builder call to read the built-in.
- auto &builtInUsage = getPipelineState()->getShaderResourceUsage(m_shaderStage)->builtInUsage;
- switch (m_shaderStage) {
- case ShaderStageVertex:
+ auto &builtInUsage = getPipelineState()->getShaderResourceUsage(m_shaderStage.value())->builtInUsage;
+ switch (m_shaderStage.value()) {
+ case ShaderStage::Vertex:
builtInUsage.vs.viewIndex = true;
break;
- case ShaderStageTessControl:
+ case ShaderStage::TessControl:
builtInUsage.tcs.viewIndex = true;
break;
- case ShaderStageTessEval:
+ case ShaderStage::TessEval:
builtInUsage.tes.viewIndex = true;
break;
- case ShaderStageGeometry:
+ case ShaderStage::Geometry:
builtInUsage.gs.viewIndex = true;
break;
- case ShaderStageMesh:
+ case ShaderStage::Mesh:
builtInUsage.mesh.viewIndex = true;
break;
- case ShaderStageFragment:
+ case ShaderStage::Fragment:
builtInUsage.fs.viewIndex = true;
break;
default:
diff --git a/lgc/builder/InOutBuilder.cpp b/lgc/builder/InOutBuilder.cpp
index 1b9995c30f..e5179d8aeb 100644
--- a/lgc/builder/InOutBuilder.cpp
+++ b/lgc/builder/InOutBuilder.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -90,7 +90,7 @@ Value *BuilderImpl::CreateReadPerVertexInput(Type *resultTy, unsigned location,
const Twine &instName) {
assert(!resultTy->isAggregateType());
assert(inputInfo.getInterpMode() == InOutInfo::InterpModeCustom);
- assert(m_shaderStage == ShaderStageFragment);
+ assert(m_shaderStage == ShaderStage::Fragment);
// Fold constant locationOffset into location.
if (auto constLocOffset = dyn_cast<ConstantInt>(locationOffset)) {
@@ -178,7 +178,7 @@ Value *BuilderImpl::readGenericInputOutput(bool isOutput, Type *resultTy, unsign
Value *elemIdx, unsigned locationCount, InOutInfo inOutInfo,
Value *vertexIndex, const Twine &instName) {
assert(resultTy->isAggregateType() == false);
- assert(isOutput == false || m_shaderStage == ShaderStageTessControl);
+ assert(isOutput == false || m_shaderStage == ShaderStage::TessControl);
// Fold constant locationOffset into location. (Currently a variable locationOffset is only supported in
// TCS, TES, mesh shader, and FS custom interpolation.)
@@ -195,17 +195,17 @@ Value *BuilderImpl::readGenericInputOutput(bool isOutput, Type *resultTy, unsign
// Generate LLPC call for reading the input/output.
Value *result = nullptr;
- switch (m_shaderStage) {
- case ShaderStageVertex: {
+ switch (m_shaderStage.value()) {
+ case ShaderStage::Vertex: {
assert(locationOffset == getInt32(0));
result =
create<InputImportGenericOp>(resultTy, false, location, getInt32(0), elemIdx, PoisonValue::get(getInt32Ty()));
break;
}
- case ShaderStageTessControl:
- case ShaderStageTessEval: {
- assert(!isOutput || m_shaderStage == ShaderStageTessControl);
+ case ShaderStage::TessControl:
+ case ShaderStage::TessEval: {
+ assert(!isOutput || m_shaderStage == ShaderStage::TessControl);
bool isPerPrimitive = vertexIndex == nullptr;
if (!vertexIndex)
@@ -218,14 +218,14 @@ Value *BuilderImpl::readGenericInputOutput(bool isOutput, Type *resultTy, unsign
break;
}
- case ShaderStageGeometry: {
+ case ShaderStage::Geometry: {
assert(cast<ConstantInt>(locationOffset)->isZero());
assert(vertexIndex);
result = create<InputImportGenericOp>(resultTy, false, location, locationOffset, elemIdx, vertexIndex);
break;
}
- case ShaderStageFragment: {
+ case ShaderStage::Fragment: {
if (inOutInfo.isPerPrimitive()) {
assert(locationOffset == getInt32(0));
result = create<InputImportGenericOp>(resultTy, true, location, locationOffset, elemIdx,
@@ -283,9 +283,9 @@ Instruction *BuilderImpl::CreateWriteGenericOutput(Value *valueToWrite, unsigned
// Set up the args for the llpc call.
SmallVector<Value *, 6> args;
- switch (m_shaderStage) {
- case ShaderStageVertex:
- case ShaderStageTessEval: {
+ switch (m_shaderStage.value()) {
+ case ShaderStage::Vertex:
+ case ShaderStage::TessEval: {
// VS: @lgc.output.export.generic.%Type%(i32 location, i32 elemIdx, %Type% outputValue)
// TES: @lgc.output.export.generic.%Type%(i32 location, i32 elemIdx, %Type% outputValue)
assert(locationOffset == getInt32(0));
@@ -294,8 +294,8 @@ Instruction *BuilderImpl::CreateWriteGenericOutput(Value *valueToWrite, unsigned
break;
}
- case ShaderStageTessControl:
- case ShaderStageMesh: {
+ case ShaderStage::TessControl:
+ case ShaderStage::Mesh: {
// TCS: @lgc.output.export.generic.%Type%(i32 location, i32 locOffset, i32 elemIdx, i32 vertexIdx,
// %Type% outputValue)
// Mesh: @lgc.output.export.generic.%Type%(i32 location, i32 locOffset, i32 elemIdx, i32 vertexOrPrimitiveIdx, i1
@@ -304,12 +304,12 @@ Instruction *BuilderImpl::CreateWriteGenericOutput(Value *valueToWrite, unsigned
args.push_back(locationOffset);
args.push_back(elemIdx);
args.push_back(vertexOrPrimitiveIndex ? vertexOrPrimitiveIndex : getInt32(InvalidValue));
- if (m_shaderStage == ShaderStageMesh)
+ if (m_shaderStage == ShaderStage::Mesh)
args.push_back(getInt1(outputInfo.isPerPrimitive()));
break;
}
- case ShaderStageGeometry: {
+ case ShaderStage::Geometry: {
// GS: @lgc.output.export.generic.%Type%(i32 location, i32 elemIdx, i32 streamId, %Type% outputValue)
unsigned streamId = outputInfo.hasStreamId() ? outputInfo.getStreamId() : InvalidValue;
assert(locationOffset == getInt32(0));
@@ -319,7 +319,7 @@ Instruction *BuilderImpl::CreateWriteGenericOutput(Value *valueToWrite, unsigned
break;
}
- case ShaderStageFragment: {
+ case ShaderStage::Fragment: {
// Mark fragment output type.
markFsOutputType(valueToWrite->getType(), location, outputInfo);
@@ -355,7 +355,7 @@ Instruction *BuilderImpl::CreateWriteGenericOutput(Value *valueToWrite, unsigned
// @param isDynLocOffset : Whether the location offset is dynamic indexing
void BuilderImpl::markGenericInputOutputUsage(bool isOutput, unsigned location, unsigned locationCount,
InOutInfo &inOutInfo, Value *vertexOrPrimIndex, bool isDynLocOffset) {
- auto resUsage = getPipelineState()->getShaderResourceUsage(m_shaderStage);
+ auto resUsage = getPipelineState()->getShaderResourceUsage(m_shaderStage.value());
// Mark the input or output locations as in use.
std::map<InOutLocationInfo, InOutLocationInfo> *inOutLocInfoMap = nullptr;
@@ -364,44 +364,44 @@ void BuilderImpl::markGenericInputOutputUsage(bool isOutput, unsigned location,
if (!isOutput) {
if (inOutInfo.isPerPrimitive()) {
// Per-primitive input
- assert(m_shaderStage == ShaderStageFragment); // Must be FS
+ assert(m_shaderStage == ShaderStage::Fragment); // Must be FS
perPrimitiveInOutLocMap = &resUsage->inOutUsage.perPrimitiveInputLocMap;
- } else if (m_shaderStage != ShaderStageTessEval || vertexOrPrimIndex) {
+ } else if (m_shaderStage != ShaderStage::TessEval || vertexOrPrimIndex) {
// Per-vertex input
inOutLocInfoMap = &resUsage->inOutUsage.inputLocInfoMap;
} else {
// Per-patch input
- assert(m_shaderStage == ShaderStageTessEval); // Must be TES
+ assert(m_shaderStage == ShaderStage::TessEval); // Must be TES
perPatchInOutLocMap = &resUsage->inOutUsage.perPatchInputLocMap;
}
} else {
if (inOutInfo.isPerPrimitive()) {
// Per-primitive output
- assert(m_shaderStage == ShaderStageMesh); // Must be mesh shader
+ assert(m_shaderStage == ShaderStage::Mesh); // Must be mesh shader
perPrimitiveInOutLocMap = &resUsage->inOutUsage.perPrimitiveOutputLocMap;
- } else if (m_shaderStage != ShaderStageTessControl || vertexOrPrimIndex) {
+ } else if (m_shaderStage != ShaderStage::TessControl || vertexOrPrimIndex) {
// Per-vertex output
inOutLocInfoMap = &resUsage->inOutUsage.outputLocInfoMap;
} else {
// Per-patch output
- assert(m_shaderStage == ShaderStageTessControl); // Must be TCS
+ assert(m_shaderStage == ShaderStage::TessControl); // Must be TCS
perPatchInOutLocMap = &resUsage->inOutUsage.perPatchOutputLocMap;
}
}
- if (!(m_shaderStage == ShaderStageGeometry && isOutput)) {
+ if (!(m_shaderStage == ShaderStage::Geometry && isOutput)) {
// Not GS output
bool keepAllLocations = false;
if (getPipelineState()->isUnlinked()) {
if (isOutput) {
// Keep all locations if the next stage of the output is fragment shader or is unspecified
- if (m_shaderStage != ShaderStageFragment) {
- ShaderStage nextStage = m_pipelineState->getNextShaderStage(m_shaderStage);
- keepAllLocations = nextStage == ShaderStageFragment || nextStage == ShaderStageInvalid;
+ if (m_shaderStage != ShaderStage::Fragment) {
+ ShaderStageEnum nextStage = m_pipelineState->getNextShaderStage(m_shaderStage.value());
+ keepAllLocations = nextStage == ShaderStage::Fragment || nextStage == ShaderStage::Invalid;
}
} else {
// Keep all locations if it is the input of fragment shader
- keepAllLocations = m_shaderStage == ShaderStageFragment;
+ keepAllLocations = m_shaderStage == ShaderStage::Fragment;
}
}
@@ -480,7 +480,7 @@ void BuilderImpl::markGenericInputOutputUsage(bool isOutput, unsigned location,
}
}
- if (!isOutput && m_shaderStage == ShaderStageFragment) {
+ if (!isOutput && m_shaderStage == ShaderStage::Fragment) {
// Mark usage for interpolation info.
markInterpolationInfo(inOutInfo);
}
@@ -491,9 +491,9 @@ void BuilderImpl::markGenericInputOutputUsage(bool isOutput, unsigned location,
//
// @param interpInfo : Interpolation info (location and mode)
void BuilderImpl::markInterpolationInfo(InOutInfo &interpInfo) {
- assert(m_shaderStage == ShaderStageFragment);
+ assert(m_shaderStage == ShaderStage::Fragment);
- auto resUsage = getPipelineState()->getShaderResourceUsage(m_shaderStage);
+ auto resUsage = getPipelineState()->getShaderResourceUsage(m_shaderStage.value());
switch (interpInfo.getInterpMode()) {
case InOutInfo::InterpModeCustom:
return;
@@ -544,7 +544,7 @@ void BuilderImpl::markInterpolationInfo(InOutInfo &interpInfo) {
// @param location : Output location
// @param outputInfo : Extra output info (whether the output is signed)
void BuilderImpl::markFsOutputType(Type *outputTy, unsigned location, InOutInfo outputInfo) {
- assert(m_shaderStage == ShaderStageFragment);
+ assert(m_shaderStage == ShaderStage::Fragment);
// Collect basic types of fragment outputs
BasicType basicTy = BasicType::Unknown;
@@ -574,7 +574,7 @@ void BuilderImpl::markFsOutputType(Type *outputTy, unsigned location, InOutInfo
} else
llvm_unreachable("Should never be called!");
- auto resUsage = getPipelineState()->getShaderResourceUsage(m_shaderStage);
+ auto resUsage = getPipelineState()->getShaderResourceUsage(m_shaderStage.value());
resUsage->inOutUsage.fs.outputTypes[location] = basicTy;
}
@@ -603,7 +603,7 @@ std::tuple<unsigned, llvm::Value *> BuilderImpl::getInterpModeAndValue(InOutInfo
interpLoc = InOutInfo::InterpLocCenter;
}
- auto resUsage = getPipelineState()->getShaderResourceUsage(ShaderStageFragment);
+ auto resUsage = getPipelineState()->getShaderResourceUsage(ShaderStage::Fragment);
if (inputInfo.getInterpMode() == InOutInfo::InterpModeSmooth) {
if (auxInterpValue) {
@@ -735,24 +735,26 @@ Instruction *BuilderImpl::CreateWriteXfbOutput(Value *valueToWrite, bool isBuilt
assert(isa<ConstantInt>(xfbOffset));
// Ignore if not in last-vertex-stage shader (excluding copy shader).
- auto stagesAfterThisOneMask = -shaderStageToMask(static_cast<ShaderStage>(m_shaderStage + 1));
- if ((getPipelineState()->getShaderStageMask() & ~shaderStageToMask(ShaderStageFragment) &
- ~shaderStageToMask(ShaderStageCopyShader) & stagesAfterThisOneMask) != 0)
+ auto stagesAfterThisOneMask = -(ShaderStageMask(m_shaderStage.value()).m_value << 1);
+ if (((getPipelineState()->getShaderStageMask() & ~ShaderStageMask(ShaderStage::Fragment) &
+ ~ShaderStageMask(ShaderStage::CopyShader))
+ .m_value &
+ stagesAfterThisOneMask) != 0)
return nullptr;
// Mark the usage of the XFB buffer.
- auto resUsage = getPipelineState()->getShaderResourceUsage(m_shaderStage);
+ auto resUsage = getPipelineState()->getShaderResourceUsage(m_shaderStage.value());
unsigned streamId = outputInfo.hasStreamId() ? outputInfo.getStreamId() : 0;
assert(xfbBuffer < MaxTransformFeedbackBuffers);
assert(streamId < MaxGsStreams);
- if (m_shaderStage == ShaderStageGeometry && getPipelineState()->enableSwXfb()) {
+ if (m_shaderStage == ShaderStage::Geometry && getPipelineState()->enableSwXfb()) {
// NOTE: For SW-emulated stream-out, we disable GS output packing. This is because
// the packing operation might cause a vector components belong to different vectors after the
// packing. In handling of SW-emulated stream-out, we expect components of the same vector
// should stay in it corresponding to a location all the time.
- getPipelineState()->setPackOutput(ShaderStageGeometry, false);
- getPipelineState()->setPackInput(ShaderStageFragment, false);
+ getPipelineState()->setPackOutput(ShaderStage::Geometry, false);
+ getPipelineState()->setPackInput(ShaderStage::Fragment, false);
}
// Collect the XFB output.
@@ -763,7 +765,7 @@ Instruction *BuilderImpl::CreateWriteXfbOutput(Value *valueToWrite, bool isBuilt
xfbOutInfo.is16bit = valueToWrite->getType()->getScalarSizeInBits() == 16;
// For packed generic GS output, the XFB output should be scalarized to align with the scalarized GS output
- if (getPipelineState()->canPackOutput(m_shaderStage) && !isBuiltIn) {
+ if (getPipelineState()->canPackOutput(m_shaderStage.value()) && !isBuiltIn) {
Type *elementTy = valueToWrite->getType();
unsigned scalarizeBy = 1;
if (auto vectorTy = dyn_cast<FixedVectorType>(elementTy)) {
@@ -834,7 +836,7 @@ Value *BuilderImpl::CreateReadBaryCoord(BuiltInKind builtIn, InOutInfo inputInfo
inputInfo.setInterpLoc(InOutInfo::InterpLocSample);
} else if (inputInfo.getInterpLoc() == InOutInfo::InterpLocSample) {
// gl_BaryCoord is decorated with 'sample'
- auto &usage = getPipelineState()->getShaderResourceUsage(m_shaderStage)->builtInUsage;
+ auto &usage = getPipelineState()->getShaderResourceUsage(m_shaderStage.value())->builtInUsage;
usage.fs.sample = true;
usage.fs.runAtSampleRate = true;
}
@@ -883,7 +885,7 @@ Value *BuilderImpl::CreateReadBuiltInInput(BuiltInKind builtIn, InOutInfo inputI
Value *BuilderImpl::CreateReadBuiltInOutput(BuiltInKind builtIn, InOutInfo outputInfo, Value *vertexIndex, Value *index,
const Twine &instName) {
// Currently this only copes with reading an output in TCS.
- assert(m_shaderStage == ShaderStageTessControl);
+ assert(m_shaderStage == ShaderStage::TessControl);
assert(isBuiltInOutput(builtIn));
return readBuiltIn(true, builtIn, outputInfo, vertexIndex, index, instName);
}
@@ -924,12 +926,12 @@ Value *BuilderImpl::readBuiltIn(bool isOutput, BuiltInKind builtIn, InOutInfo in
if (Value *result = readCommonBuiltIn(builtIn, resultTy, instName))
return result;
- if ((m_shaderStage == ShaderStageCompute || m_shaderStage == ShaderStageTask) && !isOutput) {
+ if ((m_shaderStage == ShaderStage::Compute || m_shaderStage == ShaderStage::Task) && !isOutput) {
// We handle compute shader or task shader inputs directly.
return readCsBuiltIn(builtIn, instName);
}
- if (m_shaderStage == ShaderStageVertex && !isOutput) {
+ if (m_shaderStage == ShaderStage::Vertex && !isOutput) {
// We can handle some vertex shader inputs directly.
Value *result = readVsBuiltIn(builtIn, instName);
if (result)
@@ -942,21 +944,21 @@ Value *BuilderImpl::readBuiltIn(bool isOutput, BuiltInKind builtIn, InOutInfo in
// Currently we can only cope with an array/vector index in TCS/TES.
SmallVector<Value *, 4> args;
args.push_back(getInt32(builtIn));
- switch (m_shaderStage) {
- case ShaderStageTessControl:
- case ShaderStageTessEval:
+ switch (m_shaderStage.value()) {
+ case ShaderStage::TessControl:
+ case ShaderStage::TessEval:
args.push_back(index ? index : getInt32(InvalidValue));
args.push_back(vertexIndex ? vertexIndex : getInt32(InvalidValue));
break;
- case ShaderStageGeometry:
+ case ShaderStage::Geometry:
assert(!index);
args.push_back(vertexIndex ? vertexIndex : getInt32(InvalidValue));
break;
- case ShaderStageMesh:
+ case ShaderStage::Mesh:
assert(!vertexIndex);
args.push_back(index ? index : getInt32(InvalidValue));
break;
- case ShaderStageFragment:
+ case ShaderStage::Fragment:
if (builtIn == BuiltInSamplePosOffset) {
// Special case for BuiltInSamplePosOffset: vertexIndex is the sample number.
// That special case only happens when ReadBuiltIn is called from ModifyAuxInterpValue.
@@ -1093,7 +1095,7 @@ Value *BuilderImpl::readCommonBuiltIn(BuiltInKind builtIn, llvm::Type *resultTy,
// Handle the subgroup mask built-ins directly.
Value *result = nullptr;
Value *localInvocationId = readBuiltIn(false, BuiltInSubgroupLocalInvocationId, {}, nullptr, nullptr, "");
- if (getPipelineState()->getShaderSubgroupSize(m_shaderStage) == 64)
+ if (getPipelineState()->getShaderSubgroupSize(m_shaderStage.value()) == 64)
localInvocationId = CreateZExt(localInvocationId, getInt64Ty());
switch (builtIn) {
@@ -1117,7 +1119,7 @@ Value *BuilderImpl::readCommonBuiltIn(BuiltInKind builtIn, llvm::Type *resultTy,
default:
llvm_unreachable("Should never be called!");
}
- if (getPipelineState()->getShaderSubgroupSize(m_shaderStage) == 64) {
+ if (getPipelineState()->getShaderSubgroupSize(m_shaderStage.value()) == 64) {
result = CreateInsertElement(Constant::getNullValue(FixedVectorType::get(getInt64Ty(), 2)), result, uint64_t(0));
result = CreateBitCast(result, resultTy);
} else
@@ -1128,7 +1130,7 @@ Value *BuilderImpl::readCommonBuiltIn(BuiltInKind builtIn, llvm::Type *resultTy,
case BuiltInSubgroupSize:
// SubgroupSize is a constant.
- return getInt32(getPipelineState()->getShaderSubgroupSize(m_shaderStage));
+ return getInt32(getPipelineState()->getShaderSubgroupSize(m_shaderStage.value()));
case BuiltInSubgroupLocalInvocationId:
// SubgroupLocalInvocationId is the lane number within the wave.
@@ -1159,13 +1161,13 @@ Value *BuilderImpl::readCsBuiltIn(BuiltInKind builtIn, const Twine &instName) {
getInt32(shaderMode.workgroupSizeZ)});
case BuiltInNumWorkgroups: {
- if (m_shaderStage == ShaderStageTask) {
+ if (m_shaderStage == ShaderStage::Task) {
// For task shader, NumWorkgroups is a v3i32 special user data (three SGPRs).
return ShaderInputs::getSpecialUserData(UserDataMapping::MeshTaskDispatchDims, BuilderBase::get(*this));
}
// For compute shader, NumWorkgroups is a v3i32 loaded from an address pointed to by a special user data item.
- assert(m_shaderStage == ShaderStageCompute);
+ assert(m_shaderStage == ShaderStage::Compute);
Value *numWorkgroupPtr = ShaderInputs::getSpecialUserData(UserDataMapping::Workgroup, BuilderBase::get(*this));
LoadInst *load = CreateLoad(FixedVectorType::get(getInt32Ty(), 3), numWorkgroupPtr);
load->setMetadata(LLVMContext::MD_invariant_load, MDNode::get(getContext(), {}));
@@ -1192,8 +1194,8 @@ Value *BuilderImpl::readCsBuiltIn(BuiltInKind builtIn, const Twine &instName) {
ConstantVector::get({getInt32(1), getInt32(1), getInt32(1)}));
// Load control bit from internal buffer
- auto bufferDesc = CreateLoadBufferDesc(options.reverseThreadGroupBufferDescSet,
- options.reverseThreadGroupBufferBinding, getInt32(0), 0);
+ auto bufferDesc = create<lgc::LoadBufferDescOp>(options.reverseThreadGroupBufferDescSet,
+ options.reverseThreadGroupBufferBinding, getInt32(0), 0);
auto controlBitPtr = CreateInBoundsGEP(getInt8Ty(), bufferDesc, getInt32(0));
auto controlBit = CreateTrunc(CreateLoad(getInt32Ty(), controlBitPtr), getInt1Ty());
@@ -1237,7 +1239,7 @@ Value *BuilderImpl::readCsBuiltIn(BuiltInKind builtIn, const Twine &instName) {
localInvocationId = CreateInsertElement(localInvocationId, getInt32(0), 2);
}
- if (m_shaderStage == ShaderStageCompute) {
+ if (m_shaderStage == ShaderStage::Compute) {
// Reconfigure the workgroup layout later if it's necessary.
if (!getPipelineState()->isComputeLibrary()) {
// Insert a call that later on might get lowered to code to reconfigure the workgroup.
@@ -1255,7 +1257,7 @@ Value *BuilderImpl::readCsBuiltIn(BuiltInKind builtIn, const Twine &instName) {
// gl_NumSubgroups = (workgroupSize + gl_SubGroupSize - 1) / gl_SubgroupSize
auto &mode = m_pipelineState->getShaderModes()->getComputeShaderMode();
unsigned workgroupSize = mode.workgroupSizeX * mode.workgroupSizeY * mode.workgroupSizeZ;
- unsigned subgroupSize = m_pipelineState->getShaderSubgroupSize(m_shaderStage);
+ unsigned subgroupSize = m_pipelineState->getShaderSubgroupSize(m_shaderStage.value());
unsigned numSubgroups = (workgroupSize + subgroupSize - 1) / subgroupSize;
return getInt32(numSubgroups);
}
@@ -1298,14 +1300,14 @@ Value *BuilderImpl::readCsBuiltIn(BuiltInKind builtIn, const Twine &instName) {
} else {
// Before Navi21, it should read the value before swizzling which is correct to calculate subgroup id.
Value *localInvocationIndex = readCsBuiltIn(BuiltInUnswizzledLocalInvocationIndex);
- unsigned subgroupSize = getPipelineState()->getShaderSubgroupSize(m_shaderStage);
+ unsigned subgroupSize = getPipelineState()->getShaderSubgroupSize(m_shaderStage.value());
return CreateLShr(localInvocationIndex, getInt32(Log2_32(subgroupSize)));
}
}
}
case BuiltInDrawIndex: {
- assert(m_shaderStage == ShaderStageTask); // Task shader only
+ assert(m_shaderStage == ShaderStage::Task); // Task shader only
return ShaderInputs::getSpecialUserData(UserDataMapping::DrawIndex, BuilderBase::get(*this));
}
@@ -1378,7 +1380,7 @@ Instruction *BuilderImpl::CreateWriteBuiltInOutput(Value *valueToWrite, BuiltInK
builtIn == BuiltInPrimitiveTriangleIndices) {
// The built-ins PrimitivePointIndices, PrimitiveLineIndices, and PrimitiveTriangleIndices are output arrays
// for primitive-based indexing. Writing to the whole array is disallowed.
- assert(m_shaderStage == ShaderStageMesh && vertexOrPrimitiveIndex);
+ assert(m_shaderStage == ShaderStage::Mesh && vertexOrPrimitiveIndex);
assert(expectedTy->isArrayTy());
expectedTy = cast<ArrayType>(expectedTy)->getElementType();
}
@@ -1407,15 +1409,15 @@ Instruction *BuilderImpl::CreateWriteBuiltInOutput(Value *valueToWrite, BuiltInK
// FS: @lgc.output.export.builtin.%BuiltIn%(i32 builtInId, %Type% outputValue)
SmallVector<Value *, 4> args;
args.push_back(getInt32(builtIn));
- switch (m_shaderStage) {
- case ShaderStageTessControl:
- case ShaderStageMesh:
+ switch (m_shaderStage.value()) {
+ case ShaderStage::TessControl:
+ case ShaderStage::Mesh:
args.push_back(index ? index : getInt32(InvalidValue));
args.push_back(vertexOrPrimitiveIndex ? vertexOrPrimitiveIndex : getInt32(InvalidValue));
- if (m_shaderStage == ShaderStageMesh)
+ if (m_shaderStage == ShaderStage::Mesh)
args.push_back(getInt1(outputInfo.isPerPrimitive()));
break;
- case ShaderStageGeometry:
+ case ShaderStage::Geometry:
assert(!index && !vertexOrPrimitiveIndex);
args.push_back(getInt32(streamId));
break;
@@ -1463,10 +1465,10 @@ Type *BuilderImpl::getBuiltInTy(BuiltInKind builtIn, InOutInfo inOutInfo) {
// this built-in might have different array sizes; we take the max)
// @param inOutInfo : Extra input/output info (shader-defined array size)
void BuilderImpl::markBuiltInInputUsage(BuiltInKind &builtIn, unsigned arraySize, InOutInfo inOutInfo) {
- auto &usage = getPipelineState()->getShaderResourceUsage(m_shaderStage)->builtInUsage;
+ auto &usage = getPipelineState()->getShaderResourceUsage(m_shaderStage.value())->builtInUsage;
assert((builtIn != BuiltInClipDistance && builtIn != BuiltInCullDistance) || arraySize != 0);
- switch (m_shaderStage) {
- case ShaderStageVertex: {
+ switch (m_shaderStage.value()) {
+ case ShaderStage::Vertex: {
switch (builtIn) {
case BuiltInPrimitiveId:
usage.vs.primitiveId = true;
@@ -1480,7 +1482,7 @@ void BuilderImpl::markBuiltInInputUsage(BuiltInKind &builtIn, unsigned arraySize
break;
}
- case ShaderStageTessControl: {
+ case ShaderStage::TessControl: {
switch (builtIn) {
case BuiltInPointSize:
usage.tcs.pointSizeIn = true;
@@ -1518,7 +1520,7 @@ void BuilderImpl::markBuiltInInputUsage(BuiltInKind &builtIn, unsigned arraySize
break;
}
- case ShaderStageTessEval: {
+ case ShaderStage::TessEval: {
switch (builtIn) {
case BuiltInPointSize:
usage.tes.pointSizeIn = true;
@@ -1562,7 +1564,7 @@ void BuilderImpl::markBuiltInInputUsage(BuiltInKind &builtIn, unsigned arraySize
break;
}
- case ShaderStageGeometry: {
+ case ShaderStage::Geometry: {
switch (builtIn) {
case BuiltInPointSize:
usage.gs.pointSizeIn = true;
@@ -1597,7 +1599,7 @@ void BuilderImpl::markBuiltInInputUsage(BuiltInKind &builtIn, unsigned arraySize
break;
}
- case ShaderStageMesh: {
+ case ShaderStage::Mesh: {
switch (builtIn) {
case BuiltInDrawIndex:
usage.mesh.drawIndex = true;
@@ -1632,7 +1634,7 @@ void BuilderImpl::markBuiltInInputUsage(BuiltInKind &builtIn, unsigned arraySize
break;
}
- case ShaderStageFragment: {
+ case ShaderStage::Fragment: {
switch (static_cast<unsigned>(builtIn)) {
case BuiltInFragCoord:
usage.fs.fragCoord = true;
@@ -1757,10 +1759,10 @@ void BuilderImpl::markBuiltInInputUsage(BuiltInKind &builtIn, unsigned arraySize
// this built-in might have different array sizes; we take the max)
// @param streamId : GS stream ID, or InvalidValue if not known
void BuilderImpl::markBuiltInOutputUsage(BuiltInKind builtIn, unsigned arraySize, unsigned streamId) {
- auto &usage = getPipelineState()->getShaderResourceUsage(m_shaderStage)->builtInUsage;
+ auto &usage = getPipelineState()->getShaderResourceUsage(m_shaderStage.value())->builtInUsage;
assert((builtIn != BuiltInClipDistance && builtIn != BuiltInCullDistance) || arraySize != 0);
- switch (m_shaderStage) {
- case ShaderStageVertex: {
+ switch (m_shaderStage.value()) {
+ case ShaderStage::Vertex: {
switch (builtIn) {
case BuiltInPointSize:
usage.vs.pointSize = true;
@@ -1792,7 +1794,7 @@ void BuilderImpl::markBuiltInOutputUsage(BuiltInKind builtIn, unsigned arraySize
break;
}
- case ShaderStageTessControl: {
+ case ShaderStage::TessControl: {
switch (builtIn) {
case BuiltInPointSize:
usage.tcs.pointSize = true;
@@ -1824,7 +1826,7 @@ void BuilderImpl::markBuiltInOutputUsage(BuiltInKind builtIn, unsigned arraySize
break;
}
- case ShaderStageTessEval: {
+ case ShaderStage::TessEval: {
switch (builtIn) {
case BuiltInPointSize:
usage.tes.pointSize = true;
@@ -1850,7 +1852,7 @@ void BuilderImpl::markBuiltInOutputUsage(BuiltInKind builtIn, unsigned arraySize
break;
}
- case ShaderStageGeometry: {
+ case ShaderStage::Geometry: {
switch (builtIn) {
case BuiltInPointSize:
usage.gs.pointSize = true;
@@ -1882,7 +1884,7 @@ void BuilderImpl::markBuiltInOutputUsage(BuiltInKind builtIn, unsigned arraySize
break;
}
- case ShaderStageMesh: {
+ case ShaderStage::Mesh: {
switch (builtIn) {
case BuiltInPointSize:
usage.mesh.pointSize = true;
@@ -1917,7 +1919,7 @@ void BuilderImpl::markBuiltInOutputUsage(BuiltInKind builtIn, unsigned arraySize
break;
}
- case ShaderStageFragment: {
+ case ShaderStage::Fragment: {
switch (builtIn) {
case BuiltInFragDepth:
usage.fs.fragDepth = true;
@@ -1940,48 +1942,49 @@ void BuilderImpl::markBuiltInOutputUsage(BuiltInKind builtIn, unsigned arraySize
}
#ifndef NDEBUG
+// See BuiltInDefs.h for an explanation of the letter codes.
+namespace {
+namespace StageValidMask {
+constexpr const ShaderStageMask C(ShaderStage::Compute);
+constexpr const ShaderStageMask D(ShaderStage::TessEval);
+constexpr const ShaderStageMask H(ShaderStage::TessControl);
+constexpr const ShaderStageMask G(ShaderStage::Geometry);
+constexpr const ShaderStageMask HD({ShaderStage::TessControl, ShaderStage::TessEval});
+constexpr const ShaderStageMask HDG({ShaderStage::TessControl, ShaderStage::TessEval, ShaderStage::Geometry});
+constexpr const ShaderStageMask HDGP({ShaderStage::TessControl, ShaderStage::TessEval, ShaderStage::Geometry,
+ ShaderStage::Fragment});
+constexpr const ShaderStageMask HG({ShaderStage::TessControl, ShaderStage::Geometry});
+constexpr const ShaderStageMask M(ShaderStage::Mesh);
+constexpr const ShaderStageMask MG({ShaderStage::Mesh, ShaderStage::Geometry});
+constexpr const ShaderStageMask MVG({ShaderStage::Mesh, ShaderStage::Vertex, ShaderStage::Geometry});
+constexpr const ShaderStageMask MVHDG({ShaderStage::Mesh, ShaderStage::Vertex, ShaderStage::TessControl,
+ ShaderStage::TessEval, ShaderStage::Geometry});
+constexpr const ShaderStageMask MVHDGP({ShaderStage::Mesh, ShaderStage::Vertex, ShaderStage::TessControl,
+ ShaderStage::TessEval, ShaderStage::Geometry, ShaderStage::Fragment});
+constexpr const ShaderStageMask N;
+constexpr const ShaderStageMask P(ShaderStage::Fragment);
+constexpr const ShaderStageMask TMC({ShaderStage::Task, ShaderStage::Mesh, ShaderStage::Compute});
+constexpr const ShaderStageMask TMV({ShaderStage::Task, ShaderStage::Mesh, ShaderStage::Vertex});
+constexpr const ShaderStageMask TMVHDGPC({ShaderStage::Task, ShaderStage::Mesh, ShaderStage::Vertex,
+ ShaderStage::TessControl, ShaderStage::TessEval, ShaderStage::Geometry,
+ ShaderStage::Fragment, ShaderStage::Compute});
+constexpr const ShaderStageMask V(ShaderStage::Vertex);
+} // namespace StageValidMask
+} // anonymous namespace
+
// =====================================================================================================================
// Get a bitmask of which shader stages are valid for a built-in to be an input or output of
//
// @param builtIn : Built-in kind, one of the BuiltIn* constants
// @param isOutput : True to get the mask for output rather than input
-unsigned BuilderImpl::getBuiltInValidMask(BuiltInKind builtIn, bool isOutput) {
- // See BuiltInDefs.h for an explanation of the letter codes.
- enum class StageValidMask : unsigned {
- C = shaderStageToMask(ShaderStageCompute),
- D = shaderStageToMask(ShaderStageTessEval),
- H = shaderStageToMask(ShaderStageTessControl),
- G = shaderStageToMask(ShaderStageGeometry),
- HD = shaderStageToMask(ShaderStageTessControl, ShaderStageTessEval),
- HDG = shaderStageToMask(ShaderStageTessControl, ShaderStageTessEval, ShaderStageGeometry),
- HDGP = shaderStageToMask(ShaderStageTessControl, ShaderStageTessEval, ShaderStageGeometry, ShaderStageFragment),
- HG = shaderStageToMask(ShaderStageTessControl, ShaderStageGeometry),
- M = shaderStageToMask(ShaderStageMesh),
- MG = shaderStageToMask(ShaderStageMesh, ShaderStageGeometry),
- MVG = shaderStageToMask(ShaderStageMesh, ShaderStageVertex, ShaderStageGeometry),
- MVDG = shaderStageToMask(ShaderStageMesh, ShaderStageVertex, ShaderStageTessEval, ShaderStageGeometry),
- MVHDG = shaderStageToMask(ShaderStageMesh, ShaderStageVertex, ShaderStageTessControl, ShaderStageTessEval,
- ShaderStageGeometry),
- MVHDGP = shaderStageToMask(ShaderStageMesh, ShaderStageVertex, ShaderStageTessControl, ShaderStageTessEval,
- ShaderStageGeometry, ShaderStageFragment),
- N = 0,
- P = shaderStageToMask(ShaderStageFragment),
- T = shaderStageToMask(ShaderStageTask),
- TMC = shaderStageToMask(ShaderStageTask, ShaderStageMesh, ShaderStageCompute),
- TMV = shaderStageToMask(ShaderStageTask, ShaderStageMesh, ShaderStageVertex),
- TMVHDGPC = shaderStageToMask(ShaderStageTask, ShaderStageMesh, ShaderStageVertex, ShaderStageTessControl,
- ShaderStageTessEval, ShaderStageGeometry, ShaderStageFragment, ShaderStageCompute),
- V = shaderStageToMask(ShaderStageVertex),
- VDG = shaderStageToMask(ShaderStageVertex, ShaderStageTessEval, ShaderStageGeometry),
- VHDGP = shaderStageToMask(ShaderStageVertex, ShaderStageTessControl, ShaderStageTessEval, ShaderStageGeometry,
- ShaderStageFragment),
- };
-
- unsigned validMask = 0;
+ShaderStageMask BuilderImpl::getBuiltInValidMask(BuiltInKind builtIn, bool isOutput) {
+ ShaderStageMask validMaskIn;
+ ShaderStageMask validMaskOut;
switch (builtIn) {
#define BUILTIN(name, number, out, in, type) \
case BuiltIn##name: \
- validMask = static_cast<unsigned>(StageValidMask::in) | (static_cast<unsigned>(StageValidMask::out) << 16); \
+ validMaskIn = StageValidMask::in; \
+ validMaskOut = StageValidMask::out; \
break;
#include "lgc/BuiltInDefs.h"
#undef BUILTIN
@@ -1989,7 +1992,7 @@ unsigned BuilderImpl::getBuiltInValidMask(BuiltInKind builtIn, bool isOutput) {
llvm_unreachable("Should never be called!");
break;
}
- return isOutput ? (validMask >> 16) : (validMask & 0xFFFF);
+ return isOutput ? validMaskOut : validMaskIn;
}
// =====================================================================================================================
@@ -1997,7 +2000,7 @@ unsigned BuilderImpl::getBuiltInValidMask(BuiltInKind builtIn, bool isOutput) {
//
// @param builtIn : Built-in type, one of the BuiltIn* constants
bool BuilderImpl::isBuiltInInput(BuiltInKind builtIn) {
- return (getBuiltInValidMask(builtIn, false) >> m_shaderStage) & 1;
+ return getBuiltInValidMask(builtIn, false).contains(m_shaderStage.value());
}
// =====================================================================================================================
@@ -2005,6 +2008,6 @@ bool BuilderImpl::isBuiltInInput(BuiltInKind builtIn) {
//
// @param builtIn : Built-in type, one of the BuiltIn* constants
bool BuilderImpl::isBuiltInOutput(BuiltInKind builtIn) {
- return (getBuiltInValidMask(builtIn, true) >> m_shaderStage) & 1;
+ return getBuiltInValidMask(builtIn, true).contains(m_shaderStage.value());
}
#endif
diff --git a/lgc/builder/MatrixBuilder.cpp b/lgc/builder/MatrixBuilder.cpp
index ac70c653a7..1d3e252f0d 100644
--- a/lgc/builder/MatrixBuilder.cpp
+++ b/lgc/builder/MatrixBuilder.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -458,6 +458,25 @@ Value *BuilderCommon::CreateCooperativeMatrixInsert(Value *matrix, Value *value,
return result;
}
+// =====================================================================================================================
+// Create an "fill"-equivalent operation for a cooperative matrix value.
+//
+// @param value : the value to fill the cooperative matrix
+// @param elemType : the matrix element type
+// @param layout : the matrix layout
+// @param instName : name to give instruction(s)
+Value *BuilderCommon::CreateCooperativeMatrixFill(Value *value, CooperativeMatrixElementType elemType,
+ CooperativeMatrixLayout layout, const Twine &instName) {
+ Type *resultTy = getCooperativeMatrixTy(elemType, layout);
+ Value *args[] = {value, getInt32(static_cast<unsigned>(elemType)), getInt32(static_cast<unsigned>(layout))};
+ std::string callName(lgcName::CooperativeMatrixFill);
+ addTypeMangling(resultTy, args, callName);
+ Value *result =
+ CreateNamedCall(callName, resultTy, args, {Attribute::ReadNone, Attribute::Speculatable, Attribute::WillReturn});
+ result->setName(instName);
+ return result;
+}
+
// =====================================================================================================================
// Create cooperative matrix load.
// We only allow the size 16x16 size for a cooperative matrix. So 16 lanes are responsible for reading all data from
diff --git a/lgc/builder/MiscBuilder.cpp b/lgc/builder/MiscBuilder.cpp
index faa084a002..3156266bba 100644
--- a/lgc/builder/MiscBuilder.cpp
+++ b/lgc/builder/MiscBuilder.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -44,7 +44,7 @@ using namespace llvm;
//
// @param streamId : Stream number, 0 if only one stream is present
Instruction *BuilderImpl::CreateEmitVertex(unsigned streamId) {
- assert(m_shaderStage == ShaderStageGeometry);
+ assert(m_shaderStage == ShaderStage::Geometry);
// Mark this vertex stream as active if transform feedback is enabled, or primitive statistics counting is enabled,
// or this is the rasterization stream.
@@ -68,7 +68,7 @@ Instruction *BuilderImpl::CreateEmitVertex(unsigned streamId) {
//
// @param streamId : Stream number, 0 if only one stream is present
Instruction *BuilderImpl::CreateEndPrimitive(unsigned streamId) {
- assert(m_shaderStage == ShaderStageGeometry);
+ assert(m_shaderStage == ShaderStage::Geometry);
// Mark this vertex stream as active if transform feedback is enabled, or primitive statistics counting is enabled,
// or this is the rasterization stream.
@@ -102,7 +102,7 @@ Instruction *BuilderImpl::CreateKill(const Twine &instName) {
// This tells the config builder to set KILL_ENABLE in DB_SHADER_CONTROL.
// Doing it here is suboptimal, as it does not allow for subsequent middle-end optimizations removing the
// section of code containing the kill.
- auto resUsage = getPipelineState()->getShaderResourceUsage(ShaderStageFragment);
+ auto resUsage = getPipelineState()->getShaderResourceUsage(ShaderStage::Fragment);
resUsage->builtInUsage.fs.discard = true;
return CreateIntrinsic(Intrinsic::amdgcn_kill, {}, getFalse(), nullptr, instName);
@@ -122,7 +122,7 @@ Instruction *BuilderImpl::CreateDebugBreak(const Twine &instName) {
// @param instName : Name to give instruction(s)
Instruction *BuilderImpl::CreateDemoteToHelperInvocation(const Twine &instName) {
// Treat a demote as a kill for the purposes of disabling middle-end optimizations.
- auto resUsage = getPipelineState()->getShaderResourceUsage(ShaderStageFragment);
+ auto resUsage = getPipelineState()->getShaderResourceUsage(ShaderStage::Fragment);
resUsage->builtInUsage.fs.discard = true;
return CreateIntrinsic(Intrinsic::amdgcn_wqm_demote, {}, getFalse(), nullptr, instName);
diff --git a/lgc/builder/SubgroupBuilder.cpp b/lgc/builder/SubgroupBuilder.cpp
index b7279a3142..92f755e72a 100644
--- a/lgc/builder/SubgroupBuilder.cpp
+++ b/lgc/builder/SubgroupBuilder.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -61,7 +61,8 @@ Value *BuilderImpl::CreateGetSubgroupSize(const Twine &instName) {
//
// @returns : Subgroup size of current shader stage
unsigned BuilderImpl::getShaderSubgroupSize() {
- return getPipelineState()->getShaderSubgroupSize(getShaderStage(GetInsertBlock()->getParent()));
+ auto shaderStage = getShaderStage(GetInsertBlock()->getParent());
+ return getPipelineState()->getShaderSubgroupSize(shaderStage.value());
}
// =====================================================================================================================
@@ -69,7 +70,8 @@ unsigned BuilderImpl::getShaderSubgroupSize() {
//
// @returns : Wave size of current shader stage
unsigned BuilderImpl::getShaderWaveSize() {
- return getPipelineState()->getShaderWaveSize(getShaderStage(GetInsertBlock()->getParent()));
+ auto shaderStage = getShaderStage(GetInsertBlock()->getParent());
+ return getPipelineState()->getShaderWaveSize(shaderStage.value());
}
// =====================================================================================================================
@@ -91,7 +93,7 @@ Value *BuilderImpl::CreateSubgroupAll(Value *const value, const Twine &instName)
// Helper invocations of whole quad mode should be included in the subgroup vote execution
const auto &fragmentMode = m_pipelineState->getShaderModes()->getFragmentShaderMode();
- if (m_shaderStage == ShaderStageFragment && !fragmentMode.waveOpsExcludeHelperLanes) {
+ if (m_shaderStage == ShaderStage::Fragment && !fragmentMode.waveOpsExcludeHelperLanes) {
result = CreateZExt(result, getInt32Ty());
result = CreateIntrinsic(Intrinsic::amdgcn_softwqm, {getInt32Ty()}, {result});
result = CreateTrunc(result, getInt1Ty());
@@ -110,7 +112,7 @@ Value *BuilderImpl::CreateSubgroupAny(Value *const value, const Twine &instName)
// Helper invocations of whole quad mode should be included in the subgroup vote execution
const auto &fragmentMode = m_pipelineState->getShaderModes()->getFragmentShaderMode();
- if (m_shaderStage == ShaderStageFragment && !fragmentMode.waveOpsExcludeHelperLanes) {
+ if (m_shaderStage == ShaderStage::Fragment && !fragmentMode.waveOpsExcludeHelperLanes) {
result = CreateZExt(result, getInt32Ty());
result = CreateIntrinsic(Intrinsic::amdgcn_softwqm, {getInt32Ty()}, {result});
result = CreateTrunc(result, getInt1Ty());
@@ -208,7 +210,7 @@ Value *BuilderImpl::CreateSubgroupBroadcastWaterfall(Value *const value, Value *
Value *BuilderImpl::CreateSubgroupBroadcastFirst(Value *const value, const Twine &instName) {
const auto &fragmentMode = m_pipelineState->getShaderModes()->getFragmentShaderMode();
// For waveOpsExcludeHelperLanes mode, we need filter out the helperlane and use readlane instead.
- if (m_shaderStage == ShaderStageFragment && fragmentMode.waveOpsExcludeHelperLanes) {
+ if (m_shaderStage == ShaderStage::Fragment && fragmentMode.waveOpsExcludeHelperLanes) {
Value *ballot = createGroupBallot(getTrue());
Value *firstlane = CreateIntrinsic(Intrinsic::cttz, getInt64Ty(), {ballot, getTrue()});
firstlane = CreateTrunc(firstlane, getInt32Ty());
@@ -556,7 +558,7 @@ Value *BuilderImpl::CreateSubgroupClusteredReduction(GroupArithOp groupArithOp,
// For waveOpsExcludeHelperLanes mode, we need mask away the helperlane.
const auto &fragmentMode = m_pipelineState->getShaderModes()->getFragmentShaderMode();
- if (m_shaderStage == ShaderStageFragment && fragmentMode.waveOpsExcludeHelperLanes) {
+ if (m_shaderStage == ShaderStage::Fragment && fragmentMode.waveOpsExcludeHelperLanes) {
auto isLive = CreateIntrinsic(Intrinsic::amdgcn_live_mask, {}, {}, nullptr, {});
result = CreateSelect(isLive, result, identity);
}
@@ -756,7 +758,7 @@ Value *BuilderImpl::CreateSubgroupClusteredExclusive(GroupArithOp groupArithOp,
// For waveOpsExcludeHelperLanes mode, we need mask away the helperlane.
const auto &fragmentMode = m_pipelineState->getShaderModes()->getFragmentShaderMode();
- if (m_shaderStage == ShaderStageFragment && fragmentMode.waveOpsExcludeHelperLanes) {
+ if (m_shaderStage == ShaderStage::Fragment && fragmentMode.waveOpsExcludeHelperLanes) {
auto isLive = CreateIntrinsic(Intrinsic::amdgcn_live_mask, {}, {}, nullptr, {});
setInactive = CreateSelect(isLive, setInactive, identity);
}
@@ -888,7 +890,7 @@ Value *BuilderImpl::CreateSubgroupClusteredMultiExclusive(GroupArithOp groupArit
// For waveOpsExcludeHelperLanes mode, we need mask away the helperlane.
const auto &fragmentMode = m_pipelineState->getShaderModes()->getFragmentShaderMode();
- if (m_shaderStage == ShaderStageFragment && fragmentMode.waveOpsExcludeHelperLanes) {
+ if (m_shaderStage == ShaderStage::Fragment && fragmentMode.waveOpsExcludeHelperLanes) {
auto isLive = CreateIntrinsic(Intrinsic::amdgcn_live_mask, {}, {}, nullptr, {});
result = CreateSelect(isLive, result, identity);
}
@@ -901,6 +903,7 @@ Value *BuilderImpl::CreateSubgroupClusteredMultiExclusive(GroupArithOp groupArit
Value *checkMask = CreateAnd(preLaneMask, clusterMask);
Value *preLaneValue = CreateSubgroupShuffle(result, createFindMsb(checkMask), instName);
+
result = CreateSelect(CreateICmpNE(checkMask, constZero), preLaneValue, identity);
for (unsigned log2ClusterSize = 0; (1 << log2ClusterSize) < getShaderWaveSize(); log2ClusterSize++) {
@@ -914,7 +917,8 @@ Value *BuilderImpl::CreateSubgroupClusteredMultiExclusive(GroupArithOp groupArit
Value *isPreviousLaneValid = CreateICmpNE(preClusterMask, constZero);
Value *previousLaneIndex = createFindMsb(preClusterMask);
- Value *previousLaneValue = CreateSubgroupShuffle(result, previousLaneIndex, instName);
+ Value *previousLaneValue = nullptr;
+ { previousLaneValue = CreateSubgroupShuffle(result, previousLaneIndex, instName); }
// Don't accumulate if there is no valid lane found in previous cluster or current lane is no need for accumulate.
#if LLVM_MAIN_REVISION && LLVM_MAIN_REVISION < 479645
@@ -1361,7 +1365,7 @@ Value *BuilderImpl::createWqm(Value *const value) {
return builder.CreateUnaryIntrinsic(Intrinsic::amdgcn_wqm, mappedArgs[0]);
};
- if (m_shaderStage == ShaderStageFragment)
+ if (m_shaderStage == ShaderStage::Fragment)
return CreateMapToSimpleType(mapFunc, value, {});
return value;
@@ -1429,7 +1433,7 @@ Value *BuilderImpl::createGroupBallot(Value *const value) {
// For waveOpsExcludeHelperLanes mode, we need mask away the helperlane.
const auto &fragmentMode = m_pipelineState->getShaderModes()->getFragmentShaderMode();
- if (m_shaderStage == ShaderStageFragment && fragmentMode.waveOpsExcludeHelperLanes) {
+ if (m_shaderStage == ShaderStage::Fragment && fragmentMode.waveOpsExcludeHelperLanes) {
auto isLive = CreateIntrinsic(Intrinsic::amdgcn_live_mask, {}, {}, nullptr, {});
result = CreateAnd(isLive, result);
}
@@ -1458,3 +1462,70 @@ Value *BuilderImpl::createFindMsb(Value *const mask) {
// reverse the count from the bottom.
return CreateSub(getInt32((getShaderSubgroupSize() == 64) ? 63 : 31), result);
}
+
+// =====================================================================================================================
+// Create a Quad ballot call.
+//
+// @param value : The value to ballot across the Quad. Must be an integer type.
+// @param requireFullQuads : Identify whether it's in wqm.
+// @param instName : Name to give final instruction.
+Value *BuilderImpl::CreateQuadBallot(Value *const value, bool requireFullQuads, const Twine &instName) {
+ Value *ballotValue = createGroupBallot(value);
+
+ // Get the 1st thread_id in the quad
+ Value *threadId = CreateSubgroupMbcnt(getInt64(UINT64_MAX), "");
+
+ // FirstThreadIdInQuad = threadId & (~0x3)
+ Value *threadIdforFirstQuadIndex = CreateAnd(threadId, CreateNot(getInt32(0x3)));
+
+ threadIdforFirstQuadIndex = CreateZExt(threadIdforFirstQuadIndex, getInt64Ty());
+
+ // Get the Quad ballot value for the quad of the thread id: shr(ballotValue, firstThreadidInQuad) & 0xF
+ Value *quadBallotValue = CreateAnd(CreateLShr(ballotValue, threadIdforFirstQuadIndex), getInt64(0xF));
+
+ // Ballot expects a <4 x i32> return, so we need to turn the i64 into that.
+ quadBallotValue = CreateBitCast(quadBallotValue, FixedVectorType::get(getInt32Ty(), 2));
+
+ ElementCount elementCount = cast<VectorType>(quadBallotValue->getType())->getElementCount();
+ quadBallotValue = CreateShuffleVector(quadBallotValue, ConstantVector::getSplat(elementCount, getInt32(0)),
+ ArrayRef<int>{0, 1, 2, 3});
+
+ // Helper invocations of whole quad mode should be included in the quad vote execution
+ if (requireFullQuads)
+ quadBallotValue = createWqm(quadBallotValue);
+ return quadBallotValue;
+}
+
+// =====================================================================================================================
+// Create a quad all call.
+//
+// @param value : The value to compare across the quad. Must be an i1 type.
+// @param requireFullQuads : Identify whether it's in wqm.
+// @param instName : Name to give final instruction.
+Value *BuilderImpl::CreateQuadAll(Value *const value, bool requireFullQuads, const Twine &instName) {
+ // QuadAll(value) = !QuadAny(!value)
+ Value *result = CreateNot(value, instName);
+ result = CreateNot(CreateQuadAny(result, requireFullQuads, instName), instName);
+ return result;
+}
+
+// =====================================================================================================================
+// Create a quad any call.
+//
+// @param value : The value to compare across the quad. Must be an i1 type.
+// @param requireFullQuads : Identify whether it's in wqm.
+// @param instName : Name to give final instruction.
+Value *BuilderImpl::CreateQuadAny(Value *const value, bool requireFullQuads, const Twine &instName) {
+ Value *quadBallotValue = CreateQuadBallot(value, requireFullQuads, instName);
+
+ Value *quadValidValue = CreateAnd(CreateExtractElement(quadBallotValue, getInt32(0)), getInt32(0xF));
+
+ Value *result = CreateICmpNE(quadValidValue, getInt32(0));
+
+ result = CreateSelect(CreateUnaryIntrinsic(Intrinsic::is_constant, value), value, result);
+
+ // Helper invocations of whole quad mode should be included in the quad vote execution
+ if (requireFullQuads)
+ result = createWqm(result);
+ return result;
+}
diff --git a/lgc/builder/YCbCrAddressHandler.cpp b/lgc/builder/YCbCrAddressHandler.cpp
index 8841169d4f..807f528e3c 100644
--- a/lgc/builder/YCbCrAddressHandler.cpp
+++ b/lgc/builder/YCbCrAddressHandler.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/builder/YCbCrAddressHandler.h b/lgc/builder/YCbCrAddressHandler.h
index fdedf22369..9e9f3bb6fa 100644
--- a/lgc/builder/YCbCrAddressHandler.h
+++ b/lgc/builder/YCbCrAddressHandler.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/builder/YCbCrConverter.cpp b/lgc/builder/YCbCrConverter.cpp
index bd5fa54d6b..a9642ae580 100644
--- a/lgc/builder/YCbCrConverter.cpp
+++ b/lgc/builder/YCbCrConverter.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/builder/YCbCrConverter.h b/lgc/builder/YCbCrConverter.h
index ea9f762c87..948eb9828f 100644
--- a/lgc/builder/YCbCrConverter.h
+++ b/lgc/builder/YCbCrConverter.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/disassembler/CMakeLists.txt b/lgc/disassembler/CMakeLists.txt
index d6626c58d5..aec33e8f6b 100644
--- a/lgc/disassembler/CMakeLists.txt
+++ b/lgc/disassembler/CMakeLists.txt
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/lgc/disassembler/Disassembler.cpp b/lgc/disassembler/Disassembler.cpp
index aa92894f6a..d506ca9745 100644
--- a/lgc/disassembler/Disassembler.cpp
+++ b/lgc/disassembler/Disassembler.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -603,7 +603,7 @@ static InstOp parseInstOp(StringRef op) {
return res;
}
- if (op.startswith("s")) {
+ if (op.starts_with("s")) {
StringRef s = op.drop_front(1);
s.consume_front("[");
unsigned n;
diff --git a/lgc/disassembler/PalMetadataRegs.cpp b/lgc/disassembler/PalMetadataRegs.cpp
index b4b44ff508..c263b02200 100644
--- a/lgc/disassembler/PalMetadataRegs.cpp
+++ b/lgc/disassembler/PalMetadataRegs.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/elfLinker/ColorExportShader.cpp b/lgc/elfLinker/ColorExportShader.cpp
index 0b65c9dcfe..713fc8cc1a 100644
--- a/lgc/elfLinker/ColorExportShader.cpp
+++ b/lgc/elfLinker/ColorExportShader.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -183,7 +183,7 @@ Function *ColorExportShader::createColorExportFunc() {
func->addParamAttr(inRegIndex, Attribute::InReg);
func->setDLLStorageClass(GlobalValue::DLLExportStorageClass);
- setShaderStage(func, ShaderStageFragment);
+ setShaderStage(func, ShaderStage::Fragment);
BasicBlock *block = BasicBlock::Create(func->getContext(), "", func);
BuilderBase builder(block);
@@ -192,7 +192,7 @@ Function *ColorExportShader::createColorExportFunc() {
AttrBuilder attribBuilder(func->getContext());
attribBuilder.addAttribute("InitialPSInputAddr", std::to_string(0xFFFFFFFF));
if (m_pipelineState->getTargetInfo().getGfxIpVersion().major >= 10) {
- const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStageFragment);
+ const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Fragment);
attribBuilder.addAttribute("target-features", ",+wavefrontsize" + std::to_string(waveSize)); // Set wavefront size
}
func->addFnAttrs(attribBuilder);
diff --git a/lgc/elfLinker/ColorExportShader.h b/lgc/elfLinker/ColorExportShader.h
index 7a57dc47a6..5fc63b9098 100644
--- a/lgc/elfLinker/ColorExportShader.h
+++ b/lgc/elfLinker/ColorExportShader.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/lgc/elfLinker/ElfLinker.cpp b/lgc/elfLinker/ElfLinker.cpp
index 7182297955..edcb061c9a 100644
--- a/lgc/elfLinker/ElfLinker.cpp
+++ b/lgc/elfLinker/ElfLinker.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -320,8 +320,7 @@ void ElfLinkerImpl::createGlueShaders() {
m_glueShaders.push_back(GlueShader::createFetchShader(m_pipelineState, fetches, vsEntryRegInfo));
}
- if (m_pipelineState->isGraphics() &&
- !(this->m_pipelineState->getShaderStageMask() & shaderStageToMask(ShaderStageFragment))) {
+ if (m_pipelineState->isGraphics() && !this->m_pipelineState->getShaderStageMask().contains(ShaderStage::Fragment)) {
m_glueShaders.push_back(GlueShader::createNullFragmentShader(m_pipelineState));
}
diff --git a/lgc/elfLinker/FetchShader.cpp b/lgc/elfLinker/FetchShader.cpp
index 9da79b455e..6d53861f7d 100644
--- a/lgc/elfLinker/FetchShader.cpp
+++ b/lgc/elfLinker/FetchShader.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -102,7 +102,8 @@ Module *FetchShader::generate() {
// @param [in/out] fetchFunc : The function for the fetch shader.
void FetchShader::generateFetchShaderBody(Function *fetchFunc) { // Process each vertex input.
std::unique_ptr<VertexFetch> vertexFetch(
- VertexFetch::create(m_lgcContext, m_pipelineState->getOptions().useSoftwareVertexBufferDescriptors));
+ VertexFetch::create(m_lgcContext, m_pipelineState->getOptions().useSoftwareVertexBufferDescriptors,
+ m_pipelineState->getOptions().vbAddressLowBitsKnown));
auto ret = cast<ReturnInst>(fetchFunc->back().getTerminator());
BuilderImpl builder(m_pipelineState);
builder.SetInsertPoint(ret);
@@ -151,7 +152,7 @@ void FetchShader::replaceShaderInputBuiltInFunctions(Function *fetchFunc) const
for (Function &func : *fetchFunc->getParent()) {
if (!func.isDeclaration())
continue;
- if (func.getName().startswith(lgcName::SpecialUserData) || func.getName().startswith(lgcName::ShaderInput)) {
+ if (func.getName().starts_with(lgcName::SpecialUserData) || func.getName().starts_with(lgcName::ShaderInput)) {
while (!func.use_empty()) {
auto call = cast<CallInst>(func.use_begin()->getUser());
Value *replacement = nullptr;
@@ -313,7 +314,7 @@ Function *FetchShader::createFetchFunc() {
func->getArg(m_vsEntryRegInfo.sgprCount + m_vsEntryRegInfo.vertexId)->setName("VertexId");
func->getArg(m_vsEntryRegInfo.sgprCount + m_vsEntryRegInfo.instanceId)->setName("InstanceId");
- setShaderStage(func, ShaderStageVertex);
+ setShaderStage(func, ShaderStage::Vertex);
BasicBlock *block = BasicBlock::Create(func->getContext(), "", func);
BuilderBase builder(block);
@@ -336,7 +337,7 @@ Function *FetchShader::createFetchFunc() {
AttrBuilder attribBuilder(func->getContext());
if (m_pipelineState->getTargetInfo().getGfxIpVersion().major >= 10) {
- const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStageVertex);
+ const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Vertex);
attribBuilder.addAttribute("target-features", ",+wavefrontsize" + std::to_string(waveSize)); // Set wavefront size
}
func->addFnAttrs(attribBuilder);
diff --git a/lgc/elfLinker/FetchShader.h b/lgc/elfLinker/FetchShader.h
index bc51b960f7..778303059f 100644
--- a/lgc/elfLinker/FetchShader.h
+++ b/lgc/elfLinker/FetchShader.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/lgc/elfLinker/GlueShader.cpp b/lgc/elfLinker/GlueShader.cpp
index 355926d42e..c3d4ca240e 100644
--- a/lgc/elfLinker/GlueShader.cpp
+++ b/lgc/elfLinker/GlueShader.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/elfLinker/GlueShader.h b/lgc/elfLinker/GlueShader.h
index 9c8b70d3c9..5e00bd6bdc 100644
--- a/lgc/elfLinker/GlueShader.h
+++ b/lgc/elfLinker/GlueShader.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/imported/chip/gfx9/gfx9_plus_merged_enum.h b/lgc/imported/chip/gfx9/gfx9_plus_merged_enum.h
index 039ce8de3f..ebd7e0a7ce 100644
--- a/lgc/imported/chip/gfx9/gfx9_plus_merged_enum.h
+++ b/lgc/imported/chip/gfx9/gfx9_plus_merged_enum.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/lgc/imported/chip/gfx9/gfx9_plus_merged_offset.h b/lgc/imported/chip/gfx9/gfx9_plus_merged_offset.h
index 20787c0d81..1fe01c64b6 100644
--- a/lgc/imported/chip/gfx9/gfx9_plus_merged_offset.h
+++ b/lgc/imported/chip/gfx9/gfx9_plus_merged_offset.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/lgc/imported/chip/gfx9/gfx9_plus_merged_registers.h b/lgc/imported/chip/gfx9/gfx9_plus_merged_registers.h
index 033111d966..2b224cf1bc 100644
--- a/lgc/imported/chip/gfx9/gfx9_plus_merged_registers.h
+++ b/lgc/imported/chip/gfx9/gfx9_plus_merged_registers.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/lgc/imported/chip/gfx9/gfx9_plus_merged_typedef.h b/lgc/imported/chip/gfx9/gfx9_plus_merged_typedef.h
index 8eb989b549..7dd2e4cebf 100644
--- a/lgc/imported/chip/gfx9/gfx9_plus_merged_typedef.h
+++ b/lgc/imported/chip/gfx9/gfx9_plus_merged_typedef.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/lgc/include/lgc/builder/BuilderImpl.h b/lgc/include/lgc/builder/BuilderImpl.h
index d401b4a123..b28856e159 100644
--- a/lgc/include/lgc/builder/BuilderImpl.h
+++ b/lgc/include/lgc/builder/BuilderImpl.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -58,8 +58,10 @@ class BuilderImpl : public BuilderDefs {
bool scalarizeDescriptorLoads = false, bool useVgprForOperands = false,
const llvm::Twine &instName = "");
- // Set the current shader stage, clamp shader stage to the ShaderStageCompute
- void setShaderStage(ShaderStage stage) { m_shaderStage = stage > ShaderStageCompute ? ShaderStageCompute : stage; }
+ // Set the current shader stage, clamp shader stage to the ShaderStage::Compute
+ void setShaderStage(std::optional<ShaderStageEnum> stage) {
+ m_shaderStage = (!stage || *stage > ShaderStage::Compute) ? ShaderStage::Compute : stage;
+ }
// Get the LgcContext
LgcContext *getLgcContext() const { return m_builderContext; }
@@ -121,8 +123,8 @@ class BuilderImpl : public BuilderDefs {
return BuilderBase::get(*this).CreateMapToSimpleType(mapFunc, mappedArgs, passthroughArgs, simpleMode);
}
- PipelineState *m_pipelineState = nullptr; // Pipeline state
- ShaderStage m_shaderStage = ShaderStageInvalid; // Current shader stage being built.
+ PipelineState *m_pipelineState = nullptr; // Pipeline state
+ std::optional<ShaderStageEnum> m_shaderStage; // Current shader stage being built.
private:
BuilderImpl() = delete;
@@ -290,10 +292,6 @@ class BuilderImpl : public BuilderDefs {
// -------------------------------------------------------------------------------------------------------------------
// Descriptor operations
public:
- // Create a load of a buffer descriptor.
- llvm::Value *CreateLoadBufferDesc(uint64_t descSet, unsigned binding, llvm::Value *descIndex, unsigned flags,
- const llvm::Twine &instName = "");
-
// Create a buffer descriptor.
llvm::Value *CreateBufferDesc(uint64_t descSet, unsigned binding, llvm::Value *descIndex, unsigned flags,
const llvm::Twine &instName = "");
@@ -560,7 +558,7 @@ class BuilderImpl : public BuilderDefs {
#ifndef NDEBUG
// Get a bitmask of which shader stages are valid for a built-in to be an input or output of
- unsigned getBuiltInValidMask(BuiltInKind builtIn, bool isOutput);
+ ShaderStageMask getBuiltInValidMask(BuiltInKind builtIn, bool isOutput);
// Determine whether a built-in is an input for a particular shader stage.
bool isBuiltInInput(BuiltInKind builtIn);
@@ -763,6 +761,15 @@ class BuilderImpl : public BuilderDefs {
// Create a subgroup partition.
llvm::Value *CreateSubgroupPartition(llvm::Value *const value, const llvm::Twine &instName = "");
+ // Create a Quad ballot.
+ llvm::Value *CreateQuadBallot(llvm::Value *const value, bool requireFullQuads, const llvm::Twine &instName = "");
+
+ // Create a quad all
+ llvm::Value *CreateQuadAll(llvm::Value *const value, bool requireFullQuads, const llvm::Twine &instName = "");
+
+ // Create a quad all
+ llvm::Value *CreateQuadAny(llvm::Value *const value, bool requireFullQuads, const llvm::Twine &instName = "");
+
private:
unsigned getShaderSubgroupSize();
unsigned getShaderWaveSize();
diff --git a/lgc/include/lgc/builder/BuilderReplayer.h b/lgc/include/lgc/builder/BuilderReplayer.h
index f7dc454a07..c01761e598 100644
--- a/lgc/include/lgc/builder/BuilderReplayer.h
+++ b/lgc/include/lgc/builder/BuilderReplayer.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -54,11 +54,11 @@ class BuilderReplayer final : public llvm::PassInfoMixin<BuilderReplayer> {
llvm::Value *processCall(unsigned opcode, llvm::CallInst *call);
- BuilderImpl *m_builder = nullptr; // The LLPC builder that the builder
- // calls are being replayed on.
- std::map<llvm::Function *, ShaderStage> m_shaderStageMap; // Map function -> shader stage
- llvm::Function *m_enclosingFunc = nullptr; // Last function written with current
- // shader stage
+ BuilderImpl *m_builder = nullptr; // The LLPC builder that the builder
+ // calls are being replayed on.
+ std::map<llvm::Function *, ShaderStageEnum> m_shaderStageMap; // Map function -> shader stage
+ llvm::Function *m_enclosingFunc = nullptr; // Last function written with current
+ // shader stage
};
} // namespace lgc
diff --git a/lgc/include/lgc/patch/CombineCooperativeMatrix.h b/lgc/include/lgc/patch/CombineCooperativeMatrix.h
index 83dbde3d7e..8aebac6885 100644
--- a/lgc/include/lgc/patch/CombineCooperativeMatrix.h
+++ b/lgc/include/lgc/patch/CombineCooperativeMatrix.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/patch/Continufy.h b/lgc/include/lgc/patch/Continufy.h
index dbb52e72e4..24d116aa87 100644
--- a/lgc/include/lgc/patch/Continufy.h
+++ b/lgc/include/lgc/patch/Continufy.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/patch/FragColorExport.h b/lgc/include/lgc/patch/FragColorExport.h
index 6485b9f58b..24ce910fed 100644
--- a/lgc/include/lgc/patch/FragColorExport.h
+++ b/lgc/include/lgc/patch/FragColorExport.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/patch/LowerCooperativeMatrix.h b/lgc/include/lgc/patch/LowerCooperativeMatrix.h
index 6e3b9d4bab..5140cf8570 100644
--- a/lgc/include/lgc/patch/LowerCooperativeMatrix.h
+++ b/lgc/include/lgc/patch/LowerCooperativeMatrix.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -123,6 +123,11 @@ class LowerCooperativeMatrix : public Patch, public llvm::PassInfoMixin<LowerCoo
llvm::Value *index, Builder::CooperativeMatrixElementType elemType,
Builder::CooperativeMatrixLayout layout);
+ // Open-code cooperative matrix fill operation
+ llvm::Value *cooperativeMatrixFill(BuilderCommon &builder, llvm::Value *value,
+ Builder::CooperativeMatrixElementType elemType,
+ Builder::CooperativeMatrixLayout layout);
+
// Create cooperative matrix convert operation
llvm::Value *cooperativeMatrixConvert(llvm::CastInst::CastOps castOp, llvm::Value *source,
Builder::CooperativeMatrixElementType srcElemType,
diff --git a/lgc/include/lgc/patch/LowerDebugPrintf.h b/lgc/include/lgc/patch/LowerDebugPrintf.h
index ae9da2bdd7..9d820f9ecc 100644
--- a/lgc/include/lgc/patch/LowerDebugPrintf.h
+++ b/lgc/include/lgc/patch/LowerDebugPrintf.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/patch/LowerDesc.h b/lgc/include/lgc/patch/LowerDesc.h
new file mode 100644
index 0000000000..8d64effc24
--- /dev/null
+++ b/lgc/include/lgc/patch/LowerDesc.h
@@ -0,0 +1,58 @@
+/*
+ ***********************************************************************************************************************
+ *
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ **********************************************************************************************************************/
+/**
+ ***********************************************************************************************************************
+ * @file LowerDesc.h
+ * @brief LLPC header file : contains declaration of class lgc::LowerDesc
+ ***********************************************************************************************************************
+ */
+#pragma once
+#include "SystemValues.h"
+#include "lgc/Builder.h"
+#include "lgc/patch/Patch.h"
+#include "lgc/state/PipelineShaders.h"
+#include "lgc/state/PipelineState.h"
+#include "lgc/state/TargetInfo.h"
+#include "llvm/ADT/SmallBitVector.h"
+#include "llvm/IR/Function.h"
+
+namespace lgc {
+
+class LoadBufferDescOp;
+
+// =====================================================================================================================
+// Pass to lower buffer descriptor loads.
+class LowerDesc : public llvm::PassInfoMixin<LowerDesc> {
+public:
+ llvm::PreservedAnalyses run(llvm::Module &module, llvm::ModuleAnalysisManager &analysisManager);
+ static llvm::StringRef name() { return "Lower buffer descriptor loads"; }
+
+private:
+ void visitLoadBufferDesc(LoadBufferDescOp &op);
+ llvm::SmallVector<llvm::Instruction *> m_toErase;
+ PipelineState *m_pipelineState = nullptr;
+};
+
+} // namespace lgc
diff --git a/lgc/include/lgc/patch/LowerGpuRt.h b/lgc/include/lgc/patch/LowerGpuRt.h
index 3c07491cdf..8e857b2f31 100644
--- a/lgc/include/lgc/patch/LowerGpuRt.h
+++ b/lgc/include/lgc/patch/LowerGpuRt.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -48,6 +48,7 @@ class GpurtGetBoxSortHeuristicModeOp;
class GpurtGetStaticFlagsOp;
class GpurtGetTriangleCompressionModeOp;
class GpurtGetFlattenedGroupThreadIdOp;
+class GpurtFloatWithRoundModeOp;
class LowerGpuRt : public llvm::PassInfoMixin<LowerGpuRt> {
public:
@@ -71,6 +72,7 @@ class LowerGpuRt : public llvm::PassInfoMixin<LowerGpuRt> {
void visitGetStaticFlags(lgc::GpurtGetStaticFlagsOp &inst);
void visitGetTriangleCompressionMode(lgc::GpurtGetTriangleCompressionModeOp &inst);
void visitGetFlattenedGroupThreadId(lgc::GpurtGetFlattenedGroupThreadIdOp &inst);
+ void visitFloatWithRoundMode(lgc::GpurtFloatWithRoundModeOp &inst);
llvm::Value *m_stack = nullptr; // Stack array to hold stack value
llvm::Type *m_stackTy = nullptr; // Stack type
PipelineState *m_pipelineState = nullptr; // Pipeline state
diff --git a/lgc/include/lgc/patch/Patch.h b/lgc/include/lgc/patch/Patch.h
index 7c52020eae..e3cc5422b8 100644
--- a/lgc/include/lgc/patch/Patch.h
+++ b/lgc/include/lgc/patch/Patch.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -49,7 +49,7 @@ class PassManager;
// Represents the pass of LLVM patching operations, as the base class.
class Patch {
public:
- Patch() : m_module(nullptr), m_context(nullptr), m_shaderStage(ShaderStageInvalid), m_entryPoint(nullptr) {}
+ Patch() : m_module(nullptr), m_context(nullptr), m_shaderStage(ShaderStage::Invalid), m_entryPoint(nullptr) {}
virtual ~Patch() {}
static void addPasses(PipelineState *pipelineState, lgc::PassManager &passMgr, llvm::Timer *patchTimer,
@@ -68,10 +68,10 @@ class Patch {
void init(llvm::Module *module);
- llvm::Module *m_module; // LLVM module to be run on
- llvm::LLVMContext *m_context; // Associated LLVM context of the LLVM module that passes run on
- ShaderStage m_shaderStage; // Shader stage
- llvm::Function *m_entryPoint; // Entry-point
+ llvm::Module *m_module; // LLVM module to be run on
+ llvm::LLVMContext *m_context; // Associated LLVM context of the LLVM module that passes run on
+ ShaderStageEnum m_shaderStage; // Shader stage
+ llvm::Function *m_entryPoint; // Entry-point
};
} // namespace lgc
diff --git a/lgc/include/lgc/patch/PatchBufferOp.h b/lgc/include/lgc/patch/PatchBufferOp.h
index 96ccfe4ffd..b2fbfef3e3 100644
--- a/lgc/include/lgc/patch/PatchBufferOp.h
+++ b/lgc/include/lgc/patch/PatchBufferOp.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -51,6 +51,9 @@ class DivergenceInfo;
namespace lgc {
class BufferDescToPtrOp;
+class StridedBufferDescToPtrOp;
+class StridedBufferAddrAndStrideToPtrOp;
+class StridedIndexAddOp;
class BufferLengthOp;
class BufferPtrDiffOp;
class PipelineState;
@@ -95,6 +98,9 @@ class BufferOpLowering {
void visitAtomicRMWInst(llvm::AtomicRMWInst &atomicRmwInst);
void visitBitCastInst(llvm::BitCastInst &bitCastInst);
void visitBufferDescToPtr(BufferDescToPtrOp &descToPtr);
+ void visitStridedBufferDescToPtr(StridedBufferDescToPtrOp &descToPtr);
+ void visitStridedBufferAddrAndStrideToPtr(StridedBufferAddrAndStrideToPtrOp &addrAndStrideToPtr);
+ void visitStridedIndexAdd(StridedIndexAddOp &indexAdd);
void visitBufferLength(BufferLengthOp &length);
void visitBufferPtrDiff(BufferPtrDiffOp &ptrDiff);
void visitGetElementPtrInst(llvm::GetElementPtrInst &getElemPtrInst);
@@ -113,13 +119,15 @@ class BufferOpLowering {
void postVisitMemSetInst(llvm::MemSetInst &memSetInst);
DescriptorInfo getDescriptorInfo(llvm::Value *desc);
+ bool isAnyBufferPointer(const llvm::Value *const pointerVal);
void copyMetadata(llvm::Value *const dest, const llvm::Value *const src) const;
llvm::Value *getBaseAddressFromBufferDesc(llvm::Value *const bufferDesc);
llvm::Value *replaceLoadStore(llvm::Instruction &inst);
llvm::Instruction *makeLoop(llvm::Value *const loopStart, llvm::Value *const loopEnd, llvm::Value *const loopStride,
llvm::Instruction *const insertPos);
- Value *createGlobalPointerAccess(llvm::Value *const bufferDesc, llvm::Value *const offset, llvm::Type *const type,
- llvm::Instruction &inst, const llvm::function_ref<Value *(Value *)> callback);
+ llvm::Value *createGlobalPointerAccess(llvm::Value *const bufferDesc, llvm::Value *const offset,
+ llvm::Type *const type, llvm::Instruction &inst,
+ const llvm::function_ref<llvm::Value *(llvm::Value *)> callback);
TypeLowering &m_typeLowering;
llvm::IRBuilder<> m_builder;
diff --git a/lgc/include/lgc/patch/PatchCheckShaderCache.h b/lgc/include/lgc/patch/PatchCheckShaderCache.h
index cbd9ec43b8..f875f53591 100644
--- a/lgc/include/lgc/patch/PatchCheckShaderCache.h
+++ b/lgc/include/lgc/patch/PatchCheckShaderCache.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/patch/PatchCopyShader.h b/lgc/include/lgc/patch/PatchCopyShader.h
index 2ab036fbfb..38ae2ffd8b 100644
--- a/lgc/include/lgc/patch/PatchCopyShader.h
+++ b/lgc/include/lgc/patch/PatchCopyShader.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/patch/PatchEntryPointMutate.h b/lgc/include/lgc/patch/PatchEntryPointMutate.h
index f7674d0c1b..daefd8a1b2 100644
--- a/lgc/include/lgc/patch/PatchEntryPointMutate.h
+++ b/lgc/include/lgc/patch/PatchEntryPointMutate.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -122,8 +122,8 @@ class PatchEntryPointMutate : public Patch, public llvm::PassInfoMixin<PatchEntr
void processShader(ShaderInputs *shaderInputs);
void processComputeFuncs(ShaderInputs *shaderInputs, llvm::Module &module);
- void processCalls(llvm::Function &func, llvm::SmallVectorImpl<llvm::Type *> &shaderInputTys,
- llvm::SmallVectorImpl<std::string> &shaderInputNames, uint64_t inRegMask, unsigned argOffset);
+ void processCalls(llvm::Function &func, llvm::ArrayRef<llvm::Type *> shaderInputTys,
+ llvm::ArrayRef<std::string> shaderInputNames, uint64_t inRegMask, unsigned argOffset);
void setFuncAttrs(llvm::Function *entryPoint);
uint64_t generateEntryPointArgTys(ShaderInputs *shaderInputs, llvm::Function *origFunc,
@@ -151,16 +151,16 @@ class PatchEntryPointMutate : public Patch, public llvm::PassInfoMixin<PatchEntr
bool lowerCpsOps(llvm::Function *func, ShaderInputs *shaderInputs);
llvm::Function *lowerCpsFunction(llvm::Function *func, llvm::ArrayRef<llvm::Type *> fixedShaderArgTys,
- llvm::ArrayRef<std::string> argNames, bool isContinufy);
+ llvm::ArrayRef<std::string> argNames);
unsigned lowerCpsJump(llvm::Function *parent, cps::JumpOp *jumpOp, llvm::BasicBlock *tailBlock,
llvm::SmallVectorImpl<CpsExitInfo> &exitInfos);
void lowerAsCpsReference(cps::AsContinuationReferenceOp &asCpsReferenceOp);
// Get UserDataUsage struct for the merged shader stage that contains the given shader stage
- UserDataUsage *getUserDataUsage(ShaderStage stage);
+ UserDataUsage *getUserDataUsage(ShaderStageEnum stage);
// Get the shader stage that the given shader stage is merged into.
- ShaderStage getMergedShaderStage(ShaderStage stage) const;
+ ShaderStageEnum getMergedShaderStage(ShaderStageEnum stage) const;
bool isComputeWithCalls() const;
@@ -172,7 +172,7 @@ class PatchEntryPointMutate : public Patch, public llvm::PassInfoMixin<PatchEntr
PipelineState *m_pipelineState = nullptr; // Pipeline state from PipelineStateWrapper pass
bool m_computeWithCalls = false; // Whether this is compute pipeline with calls or compute library
// Per-HW-shader-stage gathered user data usage information.
- llvm::SmallVector<std::unique_ptr<UserDataUsage>, ShaderStageCount> m_userDataUsage;
+ llvm::SmallVector<std::unique_ptr<UserDataUsage>, ShaderStage::Count> m_userDataUsage;
class CpsShaderInputCache {
public:
diff --git a/lgc/include/lgc/patch/PatchImageDerivatives.h b/lgc/include/lgc/patch/PatchImageDerivatives.h
index e31ebb10f0..03fb89a2ec 100644
--- a/lgc/include/lgc/patch/PatchImageDerivatives.h
+++ b/lgc/include/lgc/patch/PatchImageDerivatives.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/patch/PatchImageOpCollect.h b/lgc/include/lgc/patch/PatchImageOpCollect.h
index ef23f2e5e4..527610877b 100644
--- a/lgc/include/lgc/patch/PatchImageOpCollect.h
+++ b/lgc/include/lgc/patch/PatchImageOpCollect.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/patch/PatchInOutImportExport.h b/lgc/include/lgc/patch/PatchInOutImportExport.h
index 63dd23daa8..edb1c9af39 100644
--- a/lgc/include/lgc/patch/PatchInOutImportExport.h
+++ b/lgc/include/lgc/patch/PatchInOutImportExport.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -58,7 +58,7 @@ class PatchInOutImportExport : public Patch, public llvm::PassInfoMixin<PatchInO
void visitReturnInst(llvm::ReturnInst &retInst);
private:
- void processFunction(llvm::Function &func, ShaderStage shaderStage,
+ void processFunction(llvm::Function &func, ShaderStageEnum shaderStage,
llvm::SmallVectorImpl<llvm::Function *> &inputCallees,
llvm::SmallVectorImpl<llvm::Function *> &otherCallees,
const std::function<llvm::PostDominatorTree &(llvm::Function &)> &getPostDominatorTree);
diff --git a/lgc/include/lgc/patch/PatchInitializeWorkgroupMemory.h b/lgc/include/lgc/patch/PatchInitializeWorkgroupMemory.h
index cfa24f4cd7..43f9b47989 100644
--- a/lgc/include/lgc/patch/PatchInitializeWorkgroupMemory.h
+++ b/lgc/include/lgc/patch/PatchInitializeWorkgroupMemory.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/patch/PatchInvariantLoads.h b/lgc/include/lgc/patch/PatchInvariantLoads.h
index 8490a8c551..3146867bbe 100644
--- a/lgc/include/lgc/patch/PatchInvariantLoads.h
+++ b/lgc/include/lgc/patch/PatchInvariantLoads.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/patch/PatchLlvmIrInclusion.h b/lgc/include/lgc/patch/PatchLlvmIrInclusion.h
index 8dc0893174..f805b9c9f2 100644
--- a/lgc/include/lgc/patch/PatchLlvmIrInclusion.h
+++ b/lgc/include/lgc/patch/PatchLlvmIrInclusion.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/patch/PatchLoadScalarizer.h b/lgc/include/lgc/patch/PatchLoadScalarizer.h
index 82bd3c8278..3bac2f82e5 100644
--- a/lgc/include/lgc/patch/PatchLoadScalarizer.h
+++ b/lgc/include/lgc/patch/PatchLoadScalarizer.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/patch/PatchLoopMetadata.h b/lgc/include/lgc/patch/PatchLoopMetadata.h
index 877bfcf772..b698ab5721 100644
--- a/lgc/include/lgc/patch/PatchLoopMetadata.h
+++ b/lgc/include/lgc/patch/PatchLoopMetadata.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/patch/PatchPeepholeOpt.h b/lgc/include/lgc/patch/PatchPeepholeOpt.h
index 9c46a04cf1..fa552f0cec 100644
--- a/lgc/include/lgc/patch/PatchPeepholeOpt.h
+++ b/lgc/include/lgc/patch/PatchPeepholeOpt.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/patch/PatchPreparePipelineAbi.h b/lgc/include/lgc/patch/PatchPreparePipelineAbi.h
index e3f4630c2f..00481ecdce 100644
--- a/lgc/include/lgc/patch/PatchPreparePipelineAbi.h
+++ b/lgc/include/lgc/patch/PatchPreparePipelineAbi.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/patch/PatchReadFirstLane.h b/lgc/include/lgc/patch/PatchReadFirstLane.h
index 5d84c7e569..f7d822533f 100644
--- a/lgc/include/lgc/patch/PatchReadFirstLane.h
+++ b/lgc/include/lgc/patch/PatchReadFirstLane.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/patch/PatchResourceCollect.h b/lgc/include/lgc/patch/PatchResourceCollect.h
index 6e195ab3ba..6a07653a54 100644
--- a/lgc/include/lgc/patch/PatchResourceCollect.h
+++ b/lgc/include/lgc/patch/PatchResourceCollect.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -137,8 +137,8 @@ class InOutLocationInfoMapManager {
public:
InOutLocationInfoMapManager() {}
- void createMap(llvm::ArrayRef<GenericLocationOp *> calls, ShaderStage shaderStage, bool requireDword);
- void createMap(const std::vector<InOutLocationInfo> &locInfos, ShaderStage shaderStage);
+ void createMap(llvm::ArrayRef<GenericLocationOp *> calls, ShaderStageEnum shaderStage, bool requireDword);
+ void createMap(const std::vector<InOutLocationInfo> &locInfos, ShaderStageEnum shaderStage);
void deserializeMap(llvm::ArrayRef<std::pair<unsigned, unsigned>> serializedMap);
bool findMap(const InOutLocationInfo &origLocInfo, InOutLocationInfoMap::const_iterator &mapIt);
InOutLocationInfoMap &getMap() { return m_locationInfoMap; }
@@ -160,12 +160,12 @@ class InOutLocationInfoMapManager {
InOutLocationInfoMapManager(const InOutLocationInfoMapManager &) = delete;
InOutLocationInfoMapManager &operator=(const InOutLocationInfoMapManager &) = delete;
- void addSpan(llvm::CallInst *call, ShaderStage shaderStage, bool requireDword);
- void buildMap(ShaderStage shaderStage);
+ void addSpan(llvm::CallInst *call, ShaderStageEnum shaderStage, bool requireDword);
+ void buildMap(ShaderStageEnum shaderStage);
- bool isCompatible(const LocationSpan &rSpan, const LocationSpan &lSpan, ShaderStage shaderStage) const {
+ bool isCompatible(const LocationSpan &rSpan, const LocationSpan &lSpan, ShaderStageEnum shaderStage) const {
bool isCompatible = rSpan.getCompatibilityKey() == lSpan.getCompatibilityKey();
- if (isCompatible && shaderStage == ShaderStageGeometry) {
+ if (isCompatible && shaderStage == ShaderStage::Geometry) {
// Outputs with the same stream id are packed together
isCompatible &= rSpan.firstLocationInfo.getStreamId() == lSpan.firstLocationInfo.getStreamId();
}
diff --git a/lgc/include/lgc/patch/PatchSetupTargetFeatures.h b/lgc/include/lgc/patch/PatchSetupTargetFeatures.h
index 3347824c03..ee37ee226c 100644
--- a/lgc/include/lgc/patch/PatchSetupTargetFeatures.h
+++ b/lgc/include/lgc/patch/PatchSetupTargetFeatures.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/patch/PatchWorkarounds.h b/lgc/include/lgc/patch/PatchWorkarounds.h
index 59e442061e..9ac883d11a 100644
--- a/lgc/include/lgc/patch/PatchWorkarounds.h
+++ b/lgc/include/lgc/patch/PatchWorkarounds.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/patch/ShaderInputs.h b/lgc/include/lgc/patch/ShaderInputs.h
index 54f31e01f5..9672d4f9f7 100644
--- a/lgc/include/lgc/patch/ShaderInputs.h
+++ b/lgc/include/lgc/patch/ShaderInputs.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -201,7 +201,7 @@ class ShaderInputs {
void fixupUses(llvm::Module &module, PipelineState *pipelineState, bool computeWithIndirectCall);
// Get argument types for shader inputs
- uint64_t getShaderArgTys(PipelineState *pipelineState, ShaderStage shaderStage, llvm::Function *origFunc,
+ uint64_t getShaderArgTys(PipelineState *pipelineState, ShaderStageEnum shaderStage, llvm::Function *origFunc,
bool isComputeWithCalls, llvm::SmallVectorImpl<llvm::Type *> &argTys,
llvm::SmallVectorImpl<std::string> &argNames, unsigned argOffset);
@@ -219,19 +219,19 @@ class ShaderInputs {
};
// Get ShaderInputsUsage struct for the given shader stage
- ShaderInputsUsage *getShaderInputsUsage(ShaderStage stage);
+ ShaderInputsUsage *getShaderInputsUsage(ShaderStageEnum stage);
// Get (create if necessary) ShaderInputUsage struct for the given system shader input in the given shader stage
- ShaderInputUsage *getShaderInputUsage(ShaderStage stage, ShaderInput inputKind) {
+ ShaderInputUsage *getShaderInputUsage(ShaderStageEnum stage, ShaderInput inputKind) {
return getShaderInputUsage(stage, static_cast<unsigned>(inputKind));
}
- ShaderInputUsage *getShaderInputUsage(ShaderStage stage, unsigned inputKind);
+ ShaderInputUsage *getShaderInputUsage(ShaderStageEnum stage, unsigned inputKind);
// Try to optimize to use the accurate workgroupID arguments and set the function attribute for corresponding
// amdgpu-no-workgroup-id-*
- void tryOptimizeWorkgroupId(PipelineState *pipelineState, ShaderStage shaderStage, llvm::Function *origFunc);
+ void tryOptimizeWorkgroupId(PipelineState *pipelineState, ShaderStageEnum shaderStage, llvm::Function *origFunc);
- llvm::SmallVector<ShaderInputsUsage, ShaderStageCountInternal> m_shaderInputsUsage;
+ llvm::SmallVector<ShaderInputsUsage, ShaderStage::CountInternal> m_shaderInputsUsage;
};
} // namespace lgc
diff --git a/lgc/include/lgc/patch/SystemValues.h b/lgc/include/lgc/patch/SystemValues.h
index 179a28004c..069ea1de16 100644
--- a/lgc/include/lgc/patch/SystemValues.h
+++ b/lgc/include/lgc/patch/SystemValues.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -123,7 +123,7 @@ class ShaderSystemValues {
llvm::Function *m_entryPoint = nullptr; // Shader entrypoint
llvm::LLVMContext *m_context; // LLVM context
PipelineState *m_pipelineState; // Pipeline state
- ShaderStage m_shaderStage; // Shader stage
+ ShaderStageEnum m_shaderStage; // Shader stage
llvm::Value *m_esGsRingBufDesc = nullptr; // ES -> GS ring buffer descriptor (VS, TES, and GS)
llvm::Value *m_tfBufDesc = nullptr; // Descriptor for tessellation factor (TF) buffer (TCS)
diff --git a/lgc/include/lgc/patch/TcsPassthroughShader.h b/lgc/include/lgc/patch/TcsPassthroughShader.h
index 2e34898128..191f26a46a 100644
--- a/lgc/include/lgc/patch/TcsPassthroughShader.h
+++ b/lgc/include/lgc/patch/TcsPassthroughShader.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/patch/VertexFetch.h b/lgc/include/lgc/patch/VertexFetch.h
index c6ef2e03d2..04101071cb 100644
--- a/lgc/include/lgc/patch/VertexFetch.h
+++ b/lgc/include/lgc/patch/VertexFetch.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -46,7 +46,8 @@ class VertexFetch {
virtual ~VertexFetch() {}
// Create a VertexFetch
- static VertexFetch *create(LgcContext *lgcContext, bool useSoftwareVertexBufferDescriptors);
+ static VertexFetch *create(LgcContext *lgcContext, bool useSoftwareVertexBufferDescriptors,
+ bool vbAddressLowBitsKnown);
// Generate code to fetch a vertex value
virtual llvm::Value *fetchVertex(llvm::Type *inputTy, const VertexInputDescription *description, unsigned location,
@@ -54,7 +55,7 @@ class VertexFetch {
// Generate code to fetch a vertex value for uber shader
virtual llvm::Value *fetchVertex(InputImportGenericOp *vertexFetch, llvm::Value *inputDesc, llvm::Value *locMasks,
- BuilderBase &builder) = 0;
+ BuilderBase &builder, bool disablePerCompFetch) = 0;
};
// =====================================================================================================================
diff --git a/lgc/include/lgc/state/Abi.h b/lgc/include/lgc/state/Abi.h
index a30deca3c3..9c7f5a0fbe 100644
--- a/lgc/include/lgc/state/Abi.h
+++ b/lgc/include/lgc/state/Abi.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/state/AbiMetadata.h b/lgc/include/lgc/state/AbiMetadata.h
index 7c334e17e7..f50211a18a 100644
--- a/lgc/include/lgc/state/AbiMetadata.h
+++ b/lgc/include/lgc/state/AbiMetadata.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -621,7 +621,7 @@ typedef enum SPI_SHADER_EX_FORMAT {
SPI_SHADER_32_ABGR = 0x00000009,
} SPI_SHADER_EX_FORMAT;
-// The names of API shader stages used in PAL metadata, in ShaderStage order.
+// The names of API shader stages used in PAL metadata, in ShaderStageEnum order.
static const char *const ApiStageNames[] = {".task", ".vertex", ".hull", ".domain",
".geometry", ".mesh", ".pixel", ".compute"};
diff --git a/lgc/include/lgc/state/AbiUnlinked.h b/lgc/include/lgc/state/AbiUnlinked.h
index fa030ad1a9..1d48b3b3aa 100644
--- a/lgc/include/lgc/state/AbiUnlinked.h
+++ b/lgc/include/lgc/state/AbiUnlinked.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/state/Defs.h b/lgc/include/lgc/state/Defs.h
index bcbef390e9..526ab83c1a 100644
--- a/lgc/include/lgc/state/Defs.h
+++ b/lgc/include/lgc/state/Defs.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -77,6 +77,7 @@ const static char CooperativeMatrix[] = "lgc.cooperative.matrix";
const static char CooperativeMatrixLength[] = "lgc.cooperative.matrix.length";
const static char CooperativeMatrixExtract[] = "lgc.cooperative.matrix.extract";
const static char CooperativeMatrixInsert[] = "lgc.cooperative.matrix.insert";
+const static char CooperativeMatrixFill[] = "lgc.cooperative.matrix.fill";
const static char CooperativeMatrixLoad[] = "lgc.cooperative.matrix.load";
const static char CooperativeMatrixStore[] = "lgc.cooperative.matrix.store";
const static char CooperativeMatrixConvert[] = "lgc.cooperative.matrix.convert";
diff --git a/lgc/include/lgc/state/IntrinsDefs.h b/lgc/include/lgc/state/IntrinsDefs.h
index c2300a1b65..e6a3c32a86 100644
--- a/lgc/include/lgc/state/IntrinsDefs.h
+++ b/lgc/include/lgc/state/IntrinsDefs.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -79,19 +79,6 @@ static const unsigned CopyShaderEntryArgIdxStreamOffset = 4;
// Entry-point argument index for the LDS offset of current vertices in GS-VS ring
static const unsigned CopyShaderEntryArgIdxVertexOffset = 8;
-// Enumerates address spaces valid for AMD GPU (similar to LLVM header AMDGPU.h)
-enum AddrSpace {
- ADDR_SPACE_FLAT = 0, // Flat memory
- ADDR_SPACE_GLOBAL = 1, // Global memory
- ADDR_SPACE_REGION = 2, // GDS memory
- ADDR_SPACE_LOCAL = 3, // Local memory
- ADDR_SPACE_CONST = 4, // Constant memory
- ADDR_SPACE_PRIVATE = 5, // Private memory
- ADDR_SPACE_CONST_32BIT = 6, // Constant 32-bit memory
- ADDR_SPACE_BUFFER_FAT_POINTER = 7, // Buffer fat-pointer memory
- ADDR_SPACE_MAX = ADDR_SPACE_BUFFER_FAT_POINTER
-};
-
// Enumerates the target for "export" instruction.
enum ExportTarget {
EXP_TARGET_MRT_0 = 0, // MRT 0..7
diff --git a/lgc/include/lgc/state/PalMetadata.h b/lgc/include/lgc/state/PalMetadata.h
index 68905aaa53..31c5979d85 100644
--- a/lgc/include/lgc/state/PalMetadata.h
+++ b/lgc/include/lgc/state/PalMetadata.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -113,8 +113,8 @@ class PalMetadata {
llvm::msgpack::Document *getDocument() { return m_document; }
// Set the PAL metadata SPI register for one user data entry
- void setUserDataEntry(ShaderStage stage, unsigned userDataIndex, unsigned userDataValue, unsigned dwordCount = 1);
- void setUserDataEntry(ShaderStage stage, unsigned userDataIndex, UserDataMapping userDataValue,
+ void setUserDataEntry(ShaderStageEnum stage, unsigned userDataIndex, unsigned userDataValue, unsigned dwordCount = 1);
+ void setUserDataEntry(ShaderStageEnum stage, unsigned userDataIndex, UserDataMapping userDataValue,
unsigned dwordCount = 1) {
setUserDataEntry(stage, userDataIndex, static_cast<unsigned>(userDataValue), dwordCount);
}
@@ -208,7 +208,7 @@ class PalMetadata {
unsigned getFragmentShaderBuiltInLoc(unsigned builtIn);
// Get shader stage mask (only called for a link-only pipeline whose shader stage mask has not been set yet).
- unsigned getShaderStageMask();
+ ShaderStageMask getShaderStageMask();
// Serialize Util::Abi::CoverageToShaderSel to a string
llvm::StringRef serializeEnum(Util::Abi::CoverageToShaderSel value);
@@ -230,7 +230,7 @@ class PalMetadata {
void initialize();
// Get the first user data register number for the given shader stage.
- unsigned getUserDataReg0(ShaderStage stage);
+ unsigned getUserDataReg0(ShaderStageEnum stage);
// Get the llvm type that corresponds to tyName. Returns nullptr if no such type exists.
llvm::Type *getLlvmType(llvm::StringRef tyName) const;
@@ -272,8 +272,8 @@ class PalMetadata {
llvm::msgpack::MapDocNode m_registers; // MsgPack map node for amdpal.pipelines[0].registers
llvm::msgpack::ArrayDocNode m_vertexInputs; // MsgPack map node for amdpal.pipelines[0].vertexInputs
llvm::msgpack::DocNode m_colorExports; // MsgPack map node for amdpal.pipelines[0].colorExports
- // Mapping from ShaderStage to SPI user data register start, allowing for merged shaders and NGG.
- unsigned m_userDataRegMapping[ShaderStageCountInternal] = {};
+ // Mapping from ShaderStageEnum to SPI user data register start, allowing for merged shaders and NGG.
+ unsigned m_userDataRegMapping[ShaderStage::CountInternal] = {};
llvm::msgpack::DocNode *m_userDataLimit; // Maximum so far number of user data dwords used
llvm::msgpack::DocNode *m_spillThreshold; // Minimum so far dword offset used in user data spill table
llvm::SmallString<0> m_fsInputMappingsBlob; // Buffer for returning FS input mappings blob to LGC client
diff --git a/lgc/include/lgc/state/PassManagerCache.h b/lgc/include/lgc/state/PassManagerCache.h
index 9ec9eaa109..d0d58bca5b 100644
--- a/lgc/include/lgc/state/PassManagerCache.h
+++ b/lgc/include/lgc/state/PassManagerCache.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/state/PipelineShaders.h b/lgc/include/lgc/state/PipelineShaders.h
index 86dcfb49e5..800a4c4ec8 100644
--- a/lgc/include/lgc/state/PipelineShaders.h
+++ b/lgc/include/lgc/state/PipelineShaders.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -42,12 +42,12 @@ class PipelineShadersResult {
public:
PipelineShadersResult();
- llvm::Function *getEntryPoint(ShaderStage shaderStage) const;
- ShaderStage getShaderStage(const llvm::Function *func) const;
+ llvm::Function *getEntryPoint(ShaderStageEnum shaderStage) const;
+ std::optional<ShaderStageEnum> getShaderStage(const llvm::Function *func) const;
private:
- llvm::Function *m_entryPoints[ShaderStageCountInternal]; // The entry-point for each shader stage.
- std::map<const llvm::Function *, ShaderStage> m_entryPointMap; // Map from shader entry-point to shader stage.
+ llvm::Function *m_entryPoints[ShaderStage::CountInternal]; // The entry-point for each shader stage.
+ std::map<const llvm::Function *, ShaderStageEnum> m_entryPointMap; // Map from shader entry-point to shader stage.
};
// =====================================================================================================================
diff --git a/lgc/include/lgc/state/PipelineState.h b/lgc/include/lgc/state/PipelineState.h
index 2e73720883..26b806677a 100644
--- a/lgc/include/lgc/state/PipelineState.h
+++ b/lgc/include/lgc/state/PipelineState.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -134,7 +134,7 @@ class PipelineState final : public Pipeline {
const Options &getOptions() const override final { return m_options; }
// Set per-shader options
- void setShaderOptions(ShaderStage stage, const ShaderOptions &options) override final;
+ void setShaderOptions(ShaderStageEnum stage, const ShaderOptions &options) override final;
// Set device index
void setDeviceIndex(unsigned deviceIndex) override final { m_deviceIndex = deviceIndex; }
@@ -155,8 +155,15 @@ class PipelineState final : public Pipeline {
// Set the finalized 128-bit cache hash that is used to find this pipeline in the cache for the given version of LLPC.
void set128BitCacheHash(const Hash128 &finalizedCacheHash, const llvm::VersionTuple &version) override final;
+ // Find the shader entry-point from shader module, and set pipeline stage.
+ void attachModule(llvm::Module *modules) override final;
+
+ // Record pipeline state into IR metadata of specified module.
+ void record(llvm::Module *module) override final;
+
// Link the individual shader IR modules into a single pipeline module
- llvm::Module *irLink(llvm::ArrayRef<llvm::Module *> modules, PipelineLink pipelineLink) override final;
+ std::unique_ptr<llvm::Module> irLink(llvm::MutableArrayRef<std::unique_ptr<llvm::Module>> modules,
+ PipelineLink pipelineLink) override final;
// Generate pipeline module
bool generate(std::unique_ptr<llvm::Module> pipelineModule, llvm::raw_pwrite_stream &outStream,
@@ -213,7 +220,7 @@ class PipelineState final : public Pipeline {
// Other methods
// Set shader stage mask
- void setShaderStageMask(unsigned mask) { m_stageMask = mask; }
+ void setShaderStageMask(ShaderStageMask mask) { m_stageMask = mask; }
// Get the embedded ShaderModes object
const ShaderModes *getShaderModes() const { return &m_shaderModes; }
@@ -235,9 +242,6 @@ class PipelineState final : public Pipeline {
// Clear the pipeline state IR metadata.
void clear(llvm::Module *module);
- // Record pipeline state into IR metadata of specified module.
- void record(llvm::Module *module);
-
void recordExceptPalMetadata(llvm::Module *module);
// Print pipeline state
@@ -247,20 +251,20 @@ class PipelineState final : public Pipeline {
#endif
// Accessors for shader stage mask
- unsigned getShaderStageMask();
+ ShaderStageMask getShaderStageMask();
bool getPreRasterHasGs() const { return m_preRasterHasGs; }
- bool hasShaderStage(ShaderStage stage) { return (getShaderStageMask() >> stage) & 1; }
+ bool hasShaderStage(ShaderStageEnum stage) { return getShaderStageMask().contains(stage); }
bool isGraphics();
bool isComputeLibrary() const { return m_computeLibrary; }
- ShaderStage getLastVertexProcessingStage() const;
- ShaderStage getPrevShaderStage(ShaderStage shaderStage) const;
- ShaderStage getNextShaderStage(ShaderStage shaderStage) const;
+ ShaderStageEnum getLastVertexProcessingStage() const;
+ ShaderStageEnum getPrevShaderStage(ShaderStageEnum shaderStage) const;
+ ShaderStageEnum getNextShaderStage(ShaderStageEnum shaderStage) const;
// Get client name
const char *getClient() const { return m_client.c_str(); }
// Get per-shader options
- const ShaderOptions &getShaderOptions(ShaderStage stage);
+ const ShaderOptions &getShaderOptions(ShaderStageEnum stage);
// Set up the pipeline state from the pipeline module.
void readState(llvm::Module *module);
@@ -269,15 +273,15 @@ class PipelineState final : public Pipeline {
llvm::ArrayRef<ResourceNode> getUserDataNodes() const { return m_userDataNodes; }
// Find the push constant resource node
- const ResourceNode *findPushConstantResourceNode(ShaderStage shaderStage = ShaderStageInvalid) const;
+ const ResourceNode *findPushConstantResourceNode(std::optional<ShaderStageEnum> shaderStage = std::nullopt) const;
// Find the resource node for the given set,binding
std::pair<const ResourceNode *, const ResourceNode *>
findResourceNode(ResourceNodeType nodeType, uint64_t descSet, unsigned binding,
- ShaderStage shaderStage = ShaderStageInvalid) const;
+ std::optional<ShaderStageEnum> shaderStage = std::nullopt) const;
// Find the single root resource node of the given type
- const ResourceNode *findSingleRootResourceNode(ResourceNodeType nodeType, ShaderStage shaderStage) const;
+ const ResourceNode *findSingleRootResourceNode(ResourceNodeType nodeType, ShaderStageEnum shaderStage) const;
// Accessors for vertex input descriptions.
llvm::ArrayRef<VertexInputDescription> getVertexInputDescriptions() const { return m_vertexInputDescriptions; }
@@ -307,23 +311,23 @@ class PipelineState final : public Pipeline {
bool canOptimizeTessFactor();
// Gets wave size for the specified shader stage
- unsigned getShaderWaveSize(ShaderStage stage);
+ unsigned getShaderWaveSize(ShaderStageEnum stage);
// Gets wave size for the merged shader stage
- unsigned getMergedShaderWaveSize(ShaderStage stage);
+ unsigned getMergedShaderWaveSize(ShaderStageEnum stage);
// Gets subgroup size for the specified shader stage
- unsigned getShaderSubgroupSize(ShaderStage stage);
+ unsigned getShaderSubgroupSize(ShaderStageEnum stage);
// Set the default wave size for the specified shader stage
- void setShaderDefaultWaveSize(ShaderStage stage);
+ void setShaderDefaultWaveSize(ShaderStageEnum stage);
// Set the wave size for the specified shader stage
- void setShaderWaveSize(ShaderStage stage, unsigned waveSize) {
+ void setShaderWaveSize(ShaderStageEnum stage, unsigned waveSize) {
assert(waveSize == 32 || waveSize == 64);
m_waveSize[stage] = waveSize;
}
// Whether WGP mode is enabled for the given shader stage
- bool getShaderWgpMode(ShaderStage stage) const;
+ bool getShaderWgpMode(ShaderStageEnum stage) const;
// Get NGG control settings
NggControl *getNggControl() { return &m_nggControl; }
@@ -341,10 +345,10 @@ class PipelineState final : public Pipeline {
bool enableSwXfb();
// Gets resource usage of the specified shader stage
- ResourceUsage *getShaderResourceUsage(ShaderStage shaderStage);
+ ResourceUsage *getShaderResourceUsage(ShaderStageEnum shaderStage);
// Gets interface data of the specified shader stage
- InterfaceData *getShaderInterfaceData(ShaderStage shaderStage);
+ InterfaceData *getShaderInterfaceData(ShaderStageEnum shaderStage);
// Accessor for PAL metadata
PalMetadata *getPalMetadata();
@@ -362,16 +366,16 @@ class PipelineState final : public Pipeline {
void initializeInOutPackState();
// Get whether the input locations of the specified shader stage can be packed
- bool canPackInput(ShaderStage shaderStage);
+ bool canPackInput(ShaderStageEnum shaderStage);
// Get whether the output locations of the specified shader stage can be packed
- bool canPackOutput(ShaderStage shaderStage);
+ bool canPackOutput(ShaderStageEnum shaderStage);
// Set the flag to pack the input locations of the specified shader stage
- void setPackInput(ShaderStage shaderStage, bool pack) { m_inputPackState[shaderStage] = pack; }
+ void setPackInput(ShaderStageEnum shaderStage, bool pack) { m_inputPackState[shaderStage] = pack; }
// Set the flag to pack the output locations of the specified shader stage
- void setPackOutput(ShaderStage shaderStage, bool pack) { m_outputPackState[shaderStage] = pack; }
+ void setPackOutput(ShaderStageEnum shaderStage, bool pack) { m_outputPackState[shaderStage] = pack; }
// Get the count of vertices per primitive
unsigned getVerticesPerPrimitive();
@@ -423,13 +427,13 @@ class PipelineState final : public Pipeline {
}
// Set user data for a specific shader stage
- void setUserDataMap(ShaderStage shaderStage, llvm::ArrayRef<unsigned> userDataValues) {
+ void setUserDataMap(ShaderStageEnum shaderStage, llvm::ArrayRef<unsigned> userDataValues) {
m_userDataMaps[shaderStage].clear();
m_userDataMaps[shaderStage].append(userDataValues.begin(), userDataValues.end());
}
// Get user data for a specific shader stage
- llvm::ArrayRef<unsigned> getUserDataMap(ShaderStage shaderStage) const { return m_userDataMaps[shaderStage]; }
+ llvm::ArrayRef<unsigned> getUserDataMap(ShaderStageEnum shaderStage) const { return m_userDataMaps[shaderStage]; }
// -----------------------------------------------------------------------------------------------------------------
// Utility method templates to read and write IR metadata, used by PipelineState and ShaderModes
@@ -577,7 +581,7 @@ class PipelineState final : public Pipeline {
bool m_emitLgc = false; // Whether -emit-lgc is on
// Whether generating pipeline or unlinked part-pipeline
PipelineLink m_pipelineLink = PipelineLink::WholePipeline;
- unsigned m_stageMask = 0; // Mask of active shader stages
+ ShaderStageMask m_stageMask; // Mask of active shader stages
bool m_preRasterHasGs = false; // Whether pre-rasterization part has a geometry shader
bool m_computeLibrary = false; // Whether pipeline is in fact a compute library
std::string m_client; // Client name for PAL metadata
@@ -590,27 +594,27 @@ class PipelineState final : public Pipeline {
// Allocated buffers for immutable sampler data
llvm::SmallVector<std::unique_ptr<uint32_t[]>, 4> m_immutableValueAllocs;
- bool m_gsOnChip = false; // Whether to use GS on-chip mode
- bool m_meshRowExport = false; // Enable mesh shader row export or not
- bool m_registerFieldFormat = false; // Use register field format
- NggControl m_nggControl = {}; // NGG control settings
- ShaderModes m_shaderModes; // Shader modes for this pipeline
- unsigned m_deviceIndex = 0; // Device index
- std::vector<VertexInputDescription> m_vertexInputDescriptions; // Vertex input descriptions
- llvm::SmallVector<ColorExportFormat, 8> m_colorExportFormats; // Color export formats
- ColorExportState m_colorExportState = {}; // Color export state
- InputAssemblyState m_inputAssemblyState = {}; // Input-assembly state
- RasterizerState m_rasterizerState = {}; // Rasterizer state
- DepthStencilState m_depthStencilState = {}; // Depth/stencil state
- std::unique_ptr<ResourceUsage> m_resourceUsage[ShaderStageCompute + 1] = {}; // Per-shader ResourceUsage
- std::unique_ptr<InterfaceData> m_interfaceData[ShaderStageCompute + 1] = {}; // Per-shader InterfaceData
- PalMetadata *m_palMetadata = nullptr; // PAL metadata object
- unsigned m_waveSize[ShaderStageCountInternal] = {}; // Per-shader wave size
- unsigned m_subgroupSize[ShaderStageCountInternal] = {}; // Per-shader subgroup size
- bool m_inputPackState[ShaderStageGfxCount] = {}; // The input packable state per shader stage
- bool m_outputPackState[ShaderStageGfxCount] = {}; // The output packable state per shader stage
- XfbStateMetadata m_xfbStateMetadata = {}; // Transform feedback state metadata
- llvm::SmallVector<unsigned, 32> m_userDataMaps[ShaderStageCountInternal]; // The user data per-shader
+ bool m_gsOnChip = false; // Whether to use GS on-chip mode
+ bool m_meshRowExport = false; // Enable mesh shader row export or not
+ bool m_registerFieldFormat = false; // Use register field format
+ NggControl m_nggControl = {}; // NGG control settings
+ ShaderModes m_shaderModes; // Shader modes for this pipeline
+ unsigned m_deviceIndex = 0; // Device index
+ std::vector<VertexInputDescription> m_vertexInputDescriptions; // Vertex input descriptions
+ llvm::SmallVector<ColorExportFormat, 8> m_colorExportFormats; // Color export formats
+ ColorExportState m_colorExportState = {}; // Color export state
+ InputAssemblyState m_inputAssemblyState = {}; // Input-assembly state
+ RasterizerState m_rasterizerState = {}; // Rasterizer state
+ DepthStencilState m_depthStencilState = {}; // Depth/stencil state
+ std::unique_ptr<ResourceUsage> m_resourceUsage[ShaderStage::Compute + 1] = {}; // Per-shader ResourceUsage
+ std::unique_ptr<InterfaceData> m_interfaceData[ShaderStage::Compute + 1] = {}; // Per-shader InterfaceData
+ PalMetadata *m_palMetadata = nullptr; // PAL metadata object
+ unsigned m_waveSize[ShaderStage::CountInternal] = {}; // Per-shader wave size
+ unsigned m_subgroupSize[ShaderStage::CountInternal] = {}; // Per-shader subgroup size
+ bool m_inputPackState[ShaderStage::GfxCount] = {}; // The input packable state per shader stage
+ bool m_outputPackState[ShaderStage::GfxCount] = {}; // The output packable state per shader stage
+ XfbStateMetadata m_xfbStateMetadata = {}; // Transform feedback state metadata
+ llvm::SmallVector<unsigned, 32> m_userDataMaps[ShaderStage::CountInternal]; // The user data per-shader
struct {
float inner[2]; // default tessellation inner level
diff --git a/lgc/include/lgc/state/ResourceUsage.h b/lgc/include/lgc/state/ResourceUsage.h
index 268641b2b2..9ed5ecc076 100644
--- a/lgc/include/lgc/state/ResourceUsage.h
+++ b/lgc/include/lgc/state/ResourceUsage.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -479,7 +479,7 @@ struct ResourceUsage {
} fs;
} inOutUsage;
- ResourceUsage(ShaderStage shaderStage);
+ ResourceUsage(ShaderStageEnum shaderStage);
};
// Represents stream-out data
diff --git a/lgc/include/lgc/state/ShaderModes.h b/lgc/include/lgc/state/ShaderModes.h
index a9f0800bfb..d297b35914 100644
--- a/lgc/include/lgc/state/ShaderModes.h
+++ b/lgc/include/lgc/state/ShaderModes.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -49,22 +49,23 @@ namespace lgc {
class ShaderModes {
public:
// Set the common shader mode (FP modes) for the given shader stage
- static void setCommonShaderMode(llvm::Module &module, ShaderStage stage, const CommonShaderMode &commonShaderMode);
+ static void setCommonShaderMode(llvm::Module &module, ShaderStageEnum stage,
+ const CommonShaderMode &commonShaderMode);
// Get the common shader modes for the given shader stage: static edition that reads directly from IR.
- static CommonShaderMode getCommonShaderMode(llvm::Module &module, ShaderStage stage);
+ static CommonShaderMode getCommonShaderMode(llvm::Module &module, ShaderStageEnum stage);
// Get the common shader modes for the given shader stage
- const CommonShaderMode &getCommonShaderMode(ShaderStage stage) const;
+ const CommonShaderMode &getCommonShaderMode(ShaderStageEnum stage) const;
// Check if any shader stage has useSubgroupSize set
bool getAnyUseSubgroupSize() const;
// Set the tessellation mode for the given shader stage (TCS or TES).
- static void setTessellationMode(llvm::Module &module, ShaderStage stage, const TessellationMode &inMode);
+ static void setTessellationMode(llvm::Module &module, ShaderStageEnum stage, const TessellationMode &inMode);
// Get the tessellation mode for the given shader stage (TCS or TES): static edition that reads directly from IR.
- static TessellationMode getTessellationMode(llvm::Module &module, ShaderStage shaderStage);
+ static TessellationMode getTessellationMode(llvm::Module &module, ShaderStageEnum shaderStage);
// Get the tessellation state.
const TessellationMode &getTessellationMode() const;
@@ -97,7 +98,7 @@ class ShaderModes {
const ComputeShaderMode &getComputeShaderMode() const;
// Set subgroup size usage.
- static void setSubgroupSizeUsage(llvm::Module &module, ShaderStage stage, bool usage);
+ static void setSubgroupSizeUsage(llvm::Module &module, ShaderStageEnum stage, bool usage);
// Clear all modes
void clear();
@@ -106,12 +107,12 @@ class ShaderModes {
void readModesFromPipeline(llvm::Module *module);
private:
- CommonShaderMode m_commonShaderModes[ShaderStageCompute + 1] = {}; // Per-shader FP modes
- TessellationMode m_tessellationMode = {}; // Tessellation mode
- GeometryShaderMode m_geometryShaderMode = {}; // Geometry shader mode
- MeshShaderMode m_meshShaderMode = {}; // Mesh shader mode
- FragmentShaderMode m_fragmentShaderMode = {}; // Fragment shader mode
- ComputeShaderMode m_computeShaderMode = {}; // Compute shader mode (workgroup size)
+ CommonShaderMode m_commonShaderModes[ShaderStage::Compute + 1] = {}; // Per-shader FP modes
+ TessellationMode m_tessellationMode = {}; // Tessellation mode
+ GeometryShaderMode m_geometryShaderMode = {}; // Geometry shader mode
+ MeshShaderMode m_meshShaderMode = {}; // Mesh shader mode
+ FragmentShaderMode m_fragmentShaderMode = {}; // Fragment shader mode
+ ComputeShaderMode m_computeShaderMode = {}; // Compute shader mode (workgroup size)
};
} // namespace lgc
diff --git a/lgc/include/lgc/state/ShaderStage.h b/lgc/include/lgc/state/ShaderStage.h
index 9c2d30d084..2884e860cb 100644
--- a/lgc/include/lgc/state/ShaderStage.h
+++ b/lgc/include/lgc/state/ShaderStage.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -41,41 +41,20 @@ class Type;
namespace lgc {
-// Translates shader stage to corresponding stage mask.
-constexpr unsigned shaderStageToMask() {
- return 0; // To end the recursive call
-}
-
-template <typename Stage, typename... Stages>
-constexpr unsigned shaderStageToMask(Stage theStage, Stages... otherStages) {
- static_assert(std::is_enum<Stage>::value, "Can only be used with ShaderStage enums");
- return (1U << static_cast<unsigned>(theStage)) | shaderStageToMask(otherStages...);
-}
-
-// Return true iff `stage` is present in the `stageMask`.
-//
-// @param stage : Shader stage to look for
-// @param stageMask : Stage mask to check
-// @returns : True iff `stageMask` contains `stage`
-inline bool isShaderStageInMask(ShaderStage stage, unsigned stageMask) {
- assert(stage != ShaderStageInvalid);
- return (shaderStageToMask(stage) & stageMask) != 0;
-}
-
// Set shader stage metadata on every defined function in a module
-void setShaderStage(llvm::Module *module, ShaderStage stage);
+void setShaderStage(llvm::Module *module, std::optional<ShaderStageEnum> stage);
// Set shader stage metadata on a function
-void setShaderStage(llvm::Function *func, ShaderStage stage);
+void setShaderStage(llvm::Function *func, std::optional<ShaderStageEnum> stage);
// Gets the shader stage from the specified LLVM function.
-ShaderStage getShaderStage(const llvm::Function *func);
+std::optional<ShaderStageEnum> getShaderStage(const llvm::Function *func);
// Determine whether the function is a shader entry-point.
bool isShaderEntryPoint(const llvm::Function *func);
// Gets name string of the abbreviation for the specified shader stage
-const char *getShaderStageAbbreviation(ShaderStage shaderStage);
+const char *getShaderStageAbbreviation(ShaderStageEnum shaderStage);
enum AddFunctionArgsFlag : unsigned {
AddFunctionArgsAppend = 0x1,
diff --git a/lgc/include/lgc/state/TargetInfo.h b/lgc/include/lgc/state/TargetInfo.h
index 9301d081cb..caee7e9ab5 100644
--- a/lgc/include/lgc/state/TargetInfo.h
+++ b/lgc/include/lgc/state/TargetInfo.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/util/AddressExtender.h b/lgc/include/lgc/util/AddressExtender.h
index 878fd3534e..ab555b2265 100644
--- a/lgc/include/lgc/util/AddressExtender.h
+++ b/lgc/include/lgc/util/AddressExtender.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/util/BuilderBase.h b/lgc/include/lgc/util/BuilderBase.h
index bec0c5fa73..fa4782b5f8 100644
--- a/lgc/include/lgc/util/BuilderBase.h
+++ b/lgc/include/lgc/util/BuilderBase.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/util/Debug.h b/lgc/include/lgc/util/Debug.h
index 3f9f9a624e..021d2d099c 100644
--- a/lgc/include/lgc/util/Debug.h
+++ b/lgc/include/lgc/util/Debug.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/util/GfxRegHandler.h b/lgc/include/lgc/util/GfxRegHandler.h
index 06c84368d3..541a153d2c 100644
--- a/lgc/include/lgc/util/GfxRegHandler.h
+++ b/lgc/include/lgc/util/GfxRegHandler.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -142,6 +142,7 @@ enum class SqRsrcRegs {
Height,
DstSelXYZW,
SwizzleMode,
+ Type,
Depth,
Pitch,
BcSwizzle,
@@ -169,6 +170,9 @@ class SqImgRsrcRegHandler : public GfxRegHandler {
// Set the current value for the hardware register
void setReg(SqRsrcRegs regId, llvm::Value *regValue);
+ // Get the mask that covers the hardware register
+ unsigned getRegMask(SqRsrcRegs regId);
+
private:
BitsState m_bitsState[static_cast<unsigned>(SqRsrcRegs::Count)];
};
diff --git a/lgc/include/lgc/util/GfxRegHandlerBase.h b/lgc/include/lgc/util/GfxRegHandlerBase.h
index 69656c48c0..c9c6a3c5e0 100644
--- a/lgc/include/lgc/util/GfxRegHandlerBase.h
+++ b/lgc/include/lgc/util/GfxRegHandlerBase.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/include/lgc/util/Internal.h b/lgc/include/lgc/util/Internal.h
index caad44c1a8..663160fe84 100644
--- a/lgc/include/lgc/util/Internal.h
+++ b/lgc/include/lgc/util/Internal.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/interface/lgc/Builder.h b/lgc/interface/lgc/Builder.h
index d2e86991d8..d4a31b7835 100644
--- a/lgc/interface/lgc/Builder.h
+++ b/lgc/interface/lgc/Builder.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -885,19 +885,6 @@ class Builder : public BuilderDefs {
// ways). This API is formulated to allow the front-end to implement that. Step (c) can be
// performed without needing to see the resource node used in (a).
- // Create a load of a buffer descriptor.
- //
- // If descSet = -1, this is an internal user data, which is a plain 64-bit pointer, flags must be 'BufferFlagAddress'
- // i64 address is returned.
- //
- // @param descSet : Descriptor set
- // @param binding : Descriptor binding
- // @param descIndex : Descriptor index
- // @param flags : BufferFlag* bit settings
- // @param instName : Name to give instruction(s)
- llvm::Value *CreateLoadBufferDesc(uint64_t descSet, unsigned binding, llvm::Value *descIndex, unsigned flags,
- const llvm::Twine &instName = "");
-
// Get address space of constant memory.
static unsigned getAddrSpaceConst();
@@ -1648,6 +1635,20 @@ class Builder : public BuilderDefs {
// @param instName : Name to give instruction(s)
llvm::Value *CreateSubgroupPartition(llvm::Value *const value, const llvm::Twine &instName = "");
+ // Create a quad all.
+ //
+ // @param value : The value to compare
+ // @param requireFullQuads: Identify whether help invocations will be spawned in fs.
+ // @param instName : Name to give instruction(s)
+ llvm::Value *CreateQuadAll(llvm::Value *const value, bool requireFullQuads, const llvm::Twine &instName = "");
+
+ // Create a quad any.
+ //
+ // @param value : The value to compare
+ // @param requireFullQuads: Identify whether help invocations will be spawned in fs.
+ // @param instName : Name to give instruction(s)
+ llvm::Value *CreateQuadAny(llvm::Value *const value, bool requireFullQuads, const llvm::Twine &instName = "");
+
private:
Builder() = delete;
Builder(const Builder &) = delete;
diff --git a/lgc/interface/lgc/BuilderCommon.h b/lgc/interface/lgc/BuilderCommon.h
index ff57b1001f..e86d56db06 100644
--- a/lgc/interface/lgc/BuilderCommon.h
+++ b/lgc/interface/lgc/BuilderCommon.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -153,10 +153,14 @@ class BuilderCommon : public llvm_dialects::Builder {
CooperativeMatrixElementType elemType, CooperativeMatrixLayout layout,
const llvm::Twine &instName = "");
+ // Create an "fill"-equaivalent operation for a cooperative matrix value.
+ llvm::Value *CreateCooperativeMatrixFill(llvm::Value *value, CooperativeMatrixElementType elemType,
+ CooperativeMatrixLayout layout, const llvm::Twine &instName = "");
+
// Create cooperative matrix load.
//
// @param pointer : The pointer to a data array.
- // @param stride : The number of elements in the array in memory between the first component of consecutive rows (or
+ // @param stride : The number of bytes in memory between the first component of consecutive rows (or
// columns) in the result.
// @param colMaj : Whether the values loaded from memory are arrayed in column-major or row-major.
// @param layout : Identify it's factor or accumulator
@@ -170,7 +174,7 @@ class BuilderCommon : public llvm_dialects::Builder {
//
// @param pointer : The pointer to a data array.
// @param matrix : The cooperative matrix to store.
- // @param stride : The number of elements in the array in memory between the first component of consecutive rows (or
+ // @param stride : The number of bytes in memory between the first component of consecutive rows (or
// columns) in the result.
// @param colMaj : Whether the values loaded from memory are arrayed in column-major or row-major.
// @param layout : Identify it's factor or accumulator
diff --git a/lgc/interface/lgc/BuiltInDefs.h b/lgc/interface/lgc/BuiltInDefs.h
index 5857aab2a4..771439c1bf 100644
--- a/lgc/interface/lgc/BuiltInDefs.h
+++ b/lgc/interface/lgc/BuiltInDefs.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/interface/lgc/BuiltIns.h b/lgc/interface/lgc/BuiltIns.h
index d84279a524..4ef272e9a3 100644
--- a/lgc/interface/lgc/BuiltIns.h
+++ b/lgc/interface/lgc/BuiltIns.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/interface/lgc/CommonDefs.h b/lgc/interface/lgc/CommonDefs.h
index 994fc46911..b2cb37fd0b 100644
--- a/lgc/interface/lgc/CommonDefs.h
+++ b/lgc/interface/lgc/CommonDefs.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -40,28 +40,116 @@ namespace lgc {
using Hash128 = std::array<uint64_t, 2>;
/// Enumerates LGC shader stages.
+namespace ShaderStage {
enum ShaderStage : unsigned {
- ShaderStageTask = 0, ///< Task shader
- ShaderStageVertex, ///< Vertex shader
- ShaderStageTessControl, ///< Tessellation control shader
- ShaderStageTessEval, ///< Tessellation evaluation shader
- ShaderStageGeometry, ///< Geometry shader
- ShaderStageMesh, ///< Mesh shader
- ShaderStageFragment, ///< Fragment shader
- ShaderStageCompute, ///< Compute shader
- ShaderStageCount, ///< Count of shader stages
- ShaderStageInvalid = ~0u, ///< Invalid shader stage
- ShaderStageNativeStageCount = ShaderStageCompute + 1, ///< Native supported shader stage count
- ShaderStageGfxCount = ShaderStageFragment + 1, ///< Count of shader stages for graphics pipeline
-
- ShaderStageCopyShader = ShaderStageCount, ///< Copy shader (internal-use)
- ShaderStageCountInternal, ///< Count of shader stages (internal-use)
+ Task = 0, ///< Task shader
+ Vertex, ///< Vertex shader
+ TessControl, ///< Tessellation control shader
+ TessEval, ///< Tessellation evaluation shader
+ Geometry, ///< Geometry shader
+ Mesh, ///< Mesh shader
+ Fragment, ///< Fragment shader
+ Compute, ///< Compute shader
+ Count, ///< Count of shader stages
+ Invalid = ~0u, ///< Invalid shader stage
+ NativeStageCount = Compute + 1, ///< Native supported shader stage count
+ GfxCount = Fragment + 1, ///< Count of shader stages for graphics pipeline
+
+ CopyShader = Count, ///< Copy shader (internal-use)
+ CountInternal, ///< Count of shader stages (internal-use)
+};
+} // namespace ShaderStage
+
+// TODO Temporary definition until ShaderStage is converted to a class enum.
+using ShaderStageEnum = ShaderStage::ShaderStage;
+
+class ShaderStageMask {
+public:
+ constexpr ShaderStageMask() {}
+
+ constexpr explicit ShaderStageMask(ShaderStageEnum stage) {
+ assert(static_cast<uint32_t>(stage) < 32 && "ShaderStage mask overflowed");
+ m_value = 1U << static_cast<uint32_t>(stage);
+ };
+
+ constexpr explicit ShaderStageMask(std::initializer_list<ShaderStageEnum> stages) {
+ for (auto stage : stages)
+ *this |= ShaderStageMask(stage);
+ };
+
+ constexpr static ShaderStageMask fromRaw(uint32_t mask) {
+ ShaderStageMask result;
+ result.m_value = mask;
+ return result;
+ }
+ constexpr uint32_t toRaw() const { return m_value; }
+
+ constexpr bool operator==(const ShaderStageMask &other) const { return m_value == other.m_value; }
+
+ constexpr bool operator!=(const ShaderStageMask &other) const { return !(*this == other); }
+
+ constexpr ShaderStageMask &operator|=(const ShaderStageMask &other);
+ constexpr ShaderStageMask &operator&=(const ShaderStageMask &other);
+ constexpr ShaderStageMask operator~() const {
+ ShaderStageMask result;
+ result.m_value = ~m_value;
+ return result;
+ }
+
+ constexpr bool contains(ShaderStageEnum stage) const;
+ constexpr bool contains_any(std::initializer_list<ShaderStageEnum> stages) const;
+ constexpr bool empty() const { return m_value == 0; }
+
+ uint32_t m_value = 0;
+};
+
+constexpr ShaderStageMask operator|(const ShaderStageMask &lhs, const ShaderStageMask &rhs) {
+ ShaderStageMask result;
+ result.m_value = lhs.m_value | rhs.m_value;
+ return result;
+}
+
+constexpr ShaderStageMask operator&(const ShaderStageMask &lhs, const ShaderStageMask &rhs) {
+ ShaderStageMask result;
+ result.m_value = lhs.m_value & rhs.m_value;
+ return result;
+}
+
+constexpr ShaderStageMask &ShaderStageMask::operator|=(const ShaderStageMask &other) {
+ *this = *this | other;
+ return *this;
+}
+
+constexpr ShaderStageMask &ShaderStageMask::operator&=(const ShaderStageMask &other) {
+ *this = *this & other;
+ return *this;
+}
+
+constexpr bool ShaderStageMask::contains(ShaderStageEnum stage) const {
+ return (*this & ShaderStageMask(stage)).m_value != 0;
+}
+
+constexpr bool ShaderStageMask::contains_any(std::initializer_list<ShaderStageEnum> stages) const {
+ return (*this & ShaderStageMask(stages)).m_value != 0;
+}
+
+enum AddrSpace {
+ ADDR_SPACE_FLAT = 0, // Flat memory
+ ADDR_SPACE_GLOBAL = 1, // Global memory
+ ADDR_SPACE_REGION = 2, // GDS memory
+ ADDR_SPACE_LOCAL = 3, // Local memory
+ ADDR_SPACE_CONST = 4, // Constant memory
+ ADDR_SPACE_PRIVATE = 5, // Private memory
+ ADDR_SPACE_CONST_32BIT = 6, // Constant 32-bit memory
+ ADDR_SPACE_BUFFER_FAT_POINTER = 7, // Buffer fat-pointer memory
+ ADDR_SPACE_BUFFER_STRIDED_POINTER = 9, // Strided Buffer pointer memory
+ ADDR_SPACE_MAX = ADDR_SPACE_BUFFER_STRIDED_POINTER
};
} // namespace lgc
namespace llvm {
-// Enable iteration over shader stages with `lgc::enumRange<lgc::ShaderStage>()`.
-LGC_DEFINE_ZERO_BASED_ITERABLE_ENUM(lgc::ShaderStage, lgc::ShaderStage::ShaderStageCountInternal);
+// Enable iteration over shader stages with `lgc::enumRange<lgc::ShaderStageEnum>()`.
+LGC_DEFINE_ZERO_BASED_ITERABLE_ENUM(lgc::ShaderStageEnum, lgc::ShaderStage::CountInternal);
} // namespace llvm
namespace lgc {
diff --git a/lgc/interface/lgc/Disassembler.h b/lgc/interface/lgc/Disassembler.h
index 0ef05c492b..8eca22eefe 100644
--- a/lgc/interface/lgc/Disassembler.h
+++ b/lgc/interface/lgc/Disassembler.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/interface/lgc/ElfLinker.h b/lgc/interface/lgc/ElfLinker.h
index f71d20ed81..5826a70f42 100644
--- a/lgc/interface/lgc/ElfLinker.h
+++ b/lgc/interface/lgc/ElfLinker.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/interface/lgc/LgcContext.h b/lgc/interface/lgc/LgcContext.h
index efc48e4de1..7413023c7c 100644
--- a/lgc/interface/lgc/LgcContext.h
+++ b/lgc/interface/lgc/LgcContext.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/interface/lgc/LgcDialect.h b/lgc/interface/lgc/LgcDialect.h
index e340910626..74e34df252 100644
--- a/lgc/interface/lgc/LgcDialect.h
+++ b/lgc/interface/lgc/LgcDialect.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/interface/lgc/LgcDialect.td b/lgc/interface/lgc/LgcDialect.td
index 9d1177fd08..10b299cadc 100644
--- a/lgc/interface/lgc/LgcDialect.td
+++ b/lgc/interface/lgc/LgcDialect.td
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -33,6 +33,7 @@ def LgcDialect : Dialect {
def ConstantPointer : TgConstant<(PointerType 4)>, Type;
def PrivatePointer : TgConstant<(PointerType 5)>, Type;
def BufferPointer : TgConstant<(PointerType 7)>, Type;
+def BufferStridedPointer : TgConstant<(PointerType 9)>, Type;
def TaskPayloadPointer : TgConstant<(PointerType 7)>, Type;
def V4I32 : TgConstant<(FixedVectorType I32, 4)>, Type;
@@ -53,6 +54,37 @@ def BufferDescToPtrOp : LgcOp<"buffer.desc.to.ptr", [Memory<[]>, WillReturn]> {
}];
}
+def StridedBufferDescToPtrOp : LgcOp<"strided.buffer.desc.to.ptr", [Memory<[]>, WillReturn]> {
+ let arguments = (ins V4I32:$desc);
+ let results = (outs BufferStridedPointer:$result);
+
+ let summary = "convert a buffer descriptor into a strided buffer pointer";
+ let description = [{
+ Given a buffer descriptor for a storage buffer, returns an indexed buffer pointer to the start of the buffer.
+ }];
+}
+
+def StridedBufferAddrAndStrideToPtrOp : LgcOp<"strided.buffer.addr.and.stride.to.ptr", [Memory<[]>, WillReturn]> {
+ let arguments = (ins I64:$address, I32:$stride);
+ let results = (outs BufferStridedPointer:$result);
+
+ let summary = "convert a buffer address and a stride into a strided buffer pointer";
+ let description = [{
+ Given a buffer address and stride, returns an indexed buffer pointer to the start of the buffer.
+ }];
+}
+
+def StridedIndexAddOp : LgcOp<"strided.index.add", [Memory<[]>, WillReturn]> {
+ let arguments = (ins BufferStridedPointer:$ptr, I32:$delta_idx);
+ let results = (outs BufferStridedPointer:$result);
+
+ let summary = "add to the index of a strided buffer pointer";
+ let description = [{
+ Given a strided buffer pointer and a delta index, adds the delta index to the current index
+ and returns a pointer to the location pointed to by the new index.
+ }];
+}
+
def BufferLengthOp : LgcOp<"buffer.length", [Memory<[]>, WillReturn]> {
let arguments = (ins BufferPointer:$pointer, I32:$offset);
let results = (outs I32:$result);
@@ -83,6 +115,19 @@ def BufferPtrDiffOp : LgcOp<"buffer.ptr.diff", [Memory<[]>, WillReturn]> {
}];
}
+def LoadBufferDescOp : LgcOp<"load.buffer.desc", [Memory<[]>, WillReturn]> {
+ let arguments = (ins AttrI64:$desc_set, AttrI32:$binding, I32:$desc_index,
+ AttrI32:$flags);
+ let results = (outs BufferPointer:$result);
+
+ let summary = "create a load of a buffer descriptor";
+ let description = [{
+ Return the buffer descriptor pointer.
+
+ `flags` must not contain `BufferFlagAddress` for this Op.
+ }];
+}
+
def DebugPrintfOp : LgcOp<"debug.printf", [Memory<[(readwrite InaccessibleMem)]>, WillReturn]> {
let arguments = (ins BufferPointer:$buffer, ConstantPointer:$format, varargs:$args);
let results = (outs);
diff --git a/lgc/interface/lgc/MbStandardInstrumentations.h b/lgc/interface/lgc/MbStandardInstrumentations.h
index d3fa9137f7..f2fabf78d9 100644
--- a/lgc/interface/lgc/MbStandardInstrumentations.h
+++ b/lgc/interface/lgc/MbStandardInstrumentations.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/lgc/interface/lgc/ModuleBunch.h b/lgc/interface/lgc/ModuleBunch.h
index 0639885d23..742edca661 100644
--- a/lgc/interface/lgc/ModuleBunch.h
+++ b/lgc/interface/lgc/ModuleBunch.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/lgc/interface/lgc/PassManager.h b/lgc/interface/lgc/PassManager.h
index c5b602cfab..fa068a321d 100644
--- a/lgc/interface/lgc/PassManager.h
+++ b/lgc/interface/lgc/PassManager.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/interface/lgc/Pipeline.h b/lgc/interface/lgc/Pipeline.h
index e39c3609ad..2fab40cd88 100644
--- a/lgc/interface/lgc/Pipeline.h
+++ b/lgc/interface/lgc/Pipeline.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -127,7 +127,7 @@ static const char SampleShadingMetaName[] = "lgc.sample.shading";
// The front-end should zero-initialize a struct with "= {}" in case future changes add new fields.
// Note: new fields must be added to the end of this structure to maintain test compatibility.
union Options {
- unsigned u32All[40];
+ unsigned u32All[42];
struct {
uint64_t hash[2]; // Pipeline hash to set in ELF PAL metadata
unsigned includeDisassembly; // If set, the disassembly for all compiled shaders will be included
@@ -187,7 +187,11 @@ union Options {
unsigned rtStaticPipelineFlags; // Ray tracing static pipeline flags
unsigned rtTriCompressMode; // Ray tracing triangle compression mode
bool useGpurt; // Whether GPURT is used
- bool enableExtendedRobustBufferAccess; // Enable the extended robust buffer access
+ bool reserved21;
+ bool disablePerCompFetch; // Disable per component fetch in uber fetch shader.
+ bool maskOffNullDescriptorTypeField; // If true, mask off the type field of word3 from a null descriptor.
+ bool vbAddressLowBitsKnown; // Use vertex buffer offset low bits from driver.
+ bool enableExtendedRobustBufferAccess; // Enable the extended robust buffer access
};
};
static_assert(sizeof(Options) == sizeof(Options::u32All));
@@ -319,7 +323,7 @@ struct ResourceNode {
ResourceNodeType concreteType; // Underlying actual type of this node
ResourceNodeType abstractType; // Node type for resource node matching
- unsigned visibility; // Visibility bitmap: bit N set means entry is visible to ShaderStage(N); value 0
+ unsigned visibility; // Visibility bitmap: bit N set means entry is visible to ShaderStageEnum(N); value 0
// means visible to all shader stages
unsigned sizeInDwords; // Size in dwords
unsigned offsetInDwords; // Offset in dwords
@@ -367,7 +371,7 @@ enum class PrimitiveType : unsigned {
// Data format of vertex buffer entry. For ones that exist in GFX9 hardware, these match the hardware
// encoding. But this also includes extra formats.
-enum BufDataFormat {
+enum BufDataFormat : unsigned {
BufDataFormatInvalid = 0,
BufDataFormat8 = 1,
BufDataFormat16 = 2,
@@ -407,7 +411,7 @@ enum BufDataFormat {
};
// Numeric format of vertex buffer entry. These match the GFX9 hardware encoding.
-enum BufNumFormat {
+enum BufNumFormat : unsigned {
BufNumFormatUnorm = 0,
BufNumFormatSnorm = 1,
BufNumFormatUscaled = 2,
@@ -429,19 +433,24 @@ enum VertexInputRate {
};
// Structure for a vertex input
-struct VertexInputDescription {
- unsigned location; // Location of input, as provided to CreateReadGenericInput
- unsigned binding; // Index of the vertex buffer descriptor in the vertex buffer table
- unsigned offset; // Byte offset of the input in the binding's vertex buffer
- unsigned stride; // Byte stride of per-vertex/per-instance elements in the vertex buffer, 0 if unknown.
- // The stride is passed only to ensure that a valid load is used, not to actually calculate
- // the load address. Instead, we use the index as the index in a structured tbuffer load
- // instruction, and rely on the driver setting up the descriptor with the correct stride.
- BufDataFormat dfmt; // Data format of input; one of the BufDataFormat* values
- BufNumFormat nfmt; // Numeric format of input; one of the BufNumFormat* values
- unsigned inputRate; // Vertex input rate for the binding
- unsigned divisor; // Instance divisor
+union VertexInputDescription {
+ unsigned u32All[9];
+ struct {
+ unsigned location; // Location of input, as provided to CreateReadGenericInput
+ unsigned binding; // Index of the vertex buffer descriptor in the vertex buffer table
+ unsigned offset; // Byte offset of the input in the binding's vertex buffer
+ unsigned stride; // Byte stride of per-vertex/per-instance elements in the vertex buffer, 0 if unknown.
+ // The stride is passed only to ensure that a valid load is used, not to actually calculate
+ // the load address. Instead, we use the index as the index in a structured tbuffer load
+ // instruction, and rely on the driver setting up the descriptor with the correct stride.
+ BufDataFormat dfmt; // Data format of input; one of the BufDataFormat* values
+ BufNumFormat nfmt; // Numeric format of input; one of the BufNumFormat* values
+ unsigned inputRate; // Vertex input rate for the binding
+ unsigned divisor; // Instance divisor
+ uint8_t vbAddrLowBits; // Lowest two bits of vertex inputs offsets.
+ };
};
+static_assert(sizeof(VertexInputDescription) == sizeof(VertexInputDescription::u32All));
// Represents assistant info for each vertex attribute in uber fetch shader
struct UberFetchShaderAttribInfo {
@@ -662,6 +671,7 @@ struct FragmentShaderMode {
unsigned earlyAndLatFragmentTests;
unsigned innerCoverage;
unsigned waveOpsExcludeHelperLanes;
+ unsigned noReciprocalFragCoordW;
ConservativeDepth conservativeDepth;
ConservativeDepth conservativeStencilFront;
ConservativeDepth conservativeStencilBack;
@@ -678,11 +688,12 @@ enum class DerivativeMode : unsigned { None, Linear, Quads };
// All fields are unsigned, even those that could be bool, because the way the state is written to and read
// from IR metadata relies on that.
struct ComputeShaderMode {
- unsigned workgroupSizeX; // X dimension of workgroup size. 0 is taken to be 1
- unsigned workgroupSizeY; // Y dimension of workgroup size. 0 is taken to be 1
- unsigned workgroupSizeZ; // Z dimension of workgroup size. 0 is taken to be 1
- unsigned subgroupSize; // Override for the wave size if it is non-zero
- DerivativeMode derivatives; // derivativeMode for computeShader
+ unsigned workgroupSizeX; // X dimension of workgroup size. 0 is taken to be 1
+ unsigned workgroupSizeY; // Y dimension of workgroup size. 0 is taken to be 1
+ unsigned workgroupSizeZ; // Z dimension of workgroup size. 0 is taken to be 1
+ unsigned subgroupSize; // Override for the wave size if it is non-zero
+ DerivativeMode derivatives; // derivativeMode for computeShader
+ unsigned noLocalInvocationIdInCalls; // For compute with calls, assume local invocation ID is never used in callees
};
// Enum passed to Pipeline::irLink to give information on whether this is a whole or part pipeline.
@@ -729,22 +740,22 @@ class Pipeline {
// Set the common shader mode for the given shader stage, containing hardware FP round and denorm modes.
// The client should always zero-initialize the struct before setting it up, in case future versions
// add more fields. A local struct variable can be zero-initialized with " = {}".
- static void setCommonShaderMode(llvm::Module &module, ShaderStage shaderStage,
+ static void setCommonShaderMode(llvm::Module &module, ShaderStageEnum shaderStage,
const CommonShaderMode &commonShaderMode);
// Get the common shader mode for the given shader stage.
- static CommonShaderMode getCommonShaderMode(llvm::Module &module, ShaderStage shaderStage);
+ static CommonShaderMode getCommonShaderMode(llvm::Module &module, ShaderStageEnum shaderStage);
// Set the tessellation mode. This can be called in multiple shaders, and the values are merged
// together -- a zero value in one call is overridden by a non-zero value in another call. LLPC needs
// that because SPIR-V allows some of these execution mode items to appear in either the TCS or TES.
// The client should always zero-initialize the struct before setting it up, in case future versions
// add more fields. A local struct variable can be zero-initialized with " = {}".
- static void setTessellationMode(llvm::Module &module, ShaderStage shaderStage,
+ static void setTessellationMode(llvm::Module &module, ShaderStageEnum shaderStage,
const TessellationMode &tessellationMode);
// Get the tessellation mode for the given shader stage.
- static TessellationMode getTessellationMode(llvm::Module &module, ShaderStage shaderStage);
+ static TessellationMode getTessellationMode(llvm::Module &module, ShaderStageEnum shaderStage);
// Set the geometry shader state.
// The client should always zero-initialize the struct before setting it up, in case future versions
@@ -767,7 +778,7 @@ class Pipeline {
static void setComputeShaderMode(llvm::Module &module, const ComputeShaderMode &computeShaderMode);
// Set subgroup size usage.
- static void setSubgroupSizeUsage(llvm::Module &module, ShaderStage stage, bool usage);
+ static void setSubgroupSizeUsage(llvm::Module &module, ShaderStageEnum stage, bool usage);
// Get the compute shader mode (workgroup size)
static ComputeShaderMode getComputeShaderMode(llvm::Module &module);
@@ -787,7 +798,7 @@ class Pipeline {
virtual const Options &getOptions() const = 0;
// Set per-shader options
- virtual void setShaderOptions(ShaderStage stage, const ShaderOptions &options) = 0;
+ virtual void setShaderOptions(ShaderStageEnum stage, const ShaderOptions &options) = 0;
// Set the resource mapping nodes for the pipeline. "nodes" describes the user data
// supplied to the shader as a hierarchical table (max two levels) of descriptors.
@@ -858,14 +869,24 @@ class Pipeline {
// in the front-end before a shader is associated with a pipeline.
//
// @param func : Function to mark
- // @param stage : Shader stage, or ShaderStageInvalid if none
- static void markShaderEntryPoint(llvm::Function *func, ShaderStage stage);
+ // @param stage : Shader stage, or ShaderStage::Invalid if none
+ static void markShaderEntryPoint(llvm::Function *func, ShaderStageEnum stage);
// Get a function's shader stage.
//
// @param func : Function to check
- // @returns stage : Shader stage, or ShaderStageInvalid if none
- static ShaderStage getShaderStage(llvm::Function *func);
+ // @returns stage : Shader stage, or nullopt if none
+ static std::optional<ShaderStageEnum> getShaderStage(llvm::Function *func);
+
+ // Find the shader entry-point from shader module, and set pipeline stage.
+ //
+ // @param module : Shader module to attach
+ virtual void attachModule(llvm::Module *modules) = 0;
+
+ // Record pipeline state into IR metadata of specified module.
+ //
+ // @param [in/out] module : Module to record the IR metadata in
+ virtual void record(llvm::Module *module) = 0;
// Link the individual shader modules into a single pipeline module. The front-end must have
// finished calling Builder::Create* methods and finished building the IR. In the case that
@@ -886,7 +907,8 @@ class Pipeline {
//
// @param modules : Array of modules
// @param pipelineLink : Enum saying whether this is a pipeline, unlinked or part-pipeline compile.
- virtual llvm::Module *irLink(llvm::ArrayRef<llvm::Module *> modules, PipelineLink pipelineLink) = 0;
+ virtual std::unique_ptr<llvm::Module> irLink(llvm::MutableArrayRef<std::unique_ptr<llvm::Module>> modules,
+ PipelineLink pipelineLink) = 0;
// Typedef of function passed in to Generate to check the shader cache.
// Returns the updated shader stage mask, allowing the client to decide not to compile shader stages
@@ -895,8 +917,8 @@ class Pipeline {
// @param stageMask : Shader stage mask
// @param stageHashes : Per-stage hash of in/out usage
// @returns : Stage mask of stages not found in cache
- using CheckShaderCacheFunc = std::function<unsigned(const llvm::Module *module, unsigned stageMask,
- llvm::ArrayRef<llvm::ArrayRef<uint8_t>> stageHashes)>;
+ using CheckShaderCacheFunc = std::function<ShaderStageMask(const llvm::Module *module, ShaderStageMask stageMask,
+ llvm::ArrayRef<llvm::ArrayRef<uint8_t>> stageHashes)>;
// Do an early check for ability to use unlinked shader compilation then ELF linking.
// Intended to be used when doing unlinked shader compilation with pipeline state already available.
diff --git a/lgc/interface/lgc/RayTracingLibrarySummary.h b/lgc/interface/lgc/RayTracingLibrarySummary.h
new file mode 100644
index 0000000000..a1698c3988
--- /dev/null
+++ b/lgc/interface/lgc/RayTracingLibrarySummary.h
@@ -0,0 +1,81 @@
+/*
+ ***********************************************************************************************************************
+ *
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ **********************************************************************************************************************/
+/**
+ ***********************************************************************************************************************
+ * @file RayTracingLibrarySummary.h
+ * @brief Declaration of raytracing library summaries
+ *
+ * LLPC raytracing compiles can be thought of as libraries that may or may not be linked into other raytracing
+ * compiles.
+ *
+ * Raytracing library summaries represent summary information about libraries that can enable certain optimizations.
+ * The information is cumulative, i.e. if library A is linked into library B, then the summary of library B takes also
+ * the summary of library A into account.
+ ***********************************************************************************************************************
+ */
+#pragma once
+
+#include "llvm/ADT/StringRef.h"
+#include "llvm/Support/Error.h"
+
+namespace lgc {
+
+struct RayTracingLibrarySummary {
+ // Whether the library contains uses of TraceRay (e.g. OpTraceRay in SPIR-V).
+ bool usesTraceRay = false;
+
+ // If the library uses TraceRay, bit masks of ray flags that are statically known to always be set or unset.
+ unsigned knownSetRayFlags = 0;
+ unsigned knownUnsetRayFlags = 0;
+
+ // The maximum ray payload size in bytes used by any shader in the pipeline (includes outgoing ray payload uses in
+ // RGS/CHS/Miss). Must be 0 if the library never uses ray payloads (only callable shaders and RGS without TraceRay
+ // calls).
+ unsigned maxRayPayloadSize = 0;
+
+ // The maximum hit attribute size in bytes used by any shader in the pipeline. Must be 0 if the library never uses hit
+ // attributes (no AHS/IS/CHS).
+ unsigned maxHitAttributeSize = 0;
+
+ // Whether a kernel entry function was built for this library.
+ bool hasKernelEntry = false;
+
+ // Whether a suitable traversal / TraceRay module was built for this library.
+ //
+ // A library that wasn't compiled for pipeline use may be missing such a function even if it uses TraceRay. In that
+ // case, compiling a pipeline that includes the library must produce such traversal / TraceRay module.
+ //
+ // A library that has a suitable traversal module can be included in a larger library or pipeline, and that traversal
+ // may no longer be suitable for the larger library or pipeline (e.g. due to incompatibilities in statically known ray
+ // flags).
+ bool hasTraceRayModule = false;
+
+ static llvm::Expected<RayTracingLibrarySummary> decodeMsgpack(llvm::StringRef data);
+ std::string encodeMsgpack() const;
+
+ void merge(const RayTracingLibrarySummary &other);
+};
+
+} // namespace lgc
diff --git a/lgc/patch/CombineCooperativeMatrix.cpp b/lgc/patch/CombineCooperativeMatrix.cpp
index 91aa4acdc3..8dabd3aad4 100644
--- a/lgc/patch/CombineCooperativeMatrix.cpp
+++ b/lgc/patch/CombineCooperativeMatrix.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -113,14 +113,14 @@ bool CooperativeMatrixCombiner::run() {
if (!fn.isDeclaration())
continue;
- if (fn.getName().startswith(lgcName::CooperativeMatrixTranspose)) {
+ if (fn.getName().starts_with(lgcName::CooperativeMatrixTranspose)) {
for (User *user : fn.users()) {
if (auto *call = dyn_cast<CallInst>(user)) {
if (call->getFunction() == &m_function)
ops.push_back(call);
}
}
- } else if (fn.getName().startswith(lgcName::CooperativeMatrixConvert)) {
+ } else if (fn.getName().starts_with(lgcName::CooperativeMatrixConvert)) {
for (User *user : fn.users()) {
if (auto *call = dyn_cast<CallInst>(user)) {
if (call->getFunction() == &m_function)
@@ -129,7 +129,7 @@ bool CooperativeMatrixCombiner::run() {
}
#if !defined(LLVM_MAIN_REVISION) || LLVM_MAIN_REVISION >= 479080
// wmma packing on gfx11 only possible with new wmma_f16_tied intrinsic
- } else if (m_gfxIpVersion.major == 11 && fn.getName().startswith(lgcName::CooperativeMatrixMulAdd)) {
+ } else if (m_gfxIpVersion.major == 11 && fn.getName().starts_with(lgcName::CooperativeMatrixMulAdd)) {
for (User *user : fn.users()) {
if (auto *call = dyn_cast<CallInst>(user)) {
Builder::CooperativeMatrixElementType accumElemType = static_cast<Builder::CooperativeMatrixElementType>(
@@ -218,11 +218,11 @@ void CooperativeMatrixCombiner::foldTo(Value *from, Value *to) {
bool CooperativeMatrixCombiner::tryFold(CallInst *op) {
Value *src;
bool isConvert = false;
- if (op->getCalledFunction()->getName().startswith(lgcName::CooperativeMatrixConvert)) {
+ if (op->getCalledFunction()->getName().starts_with(lgcName::CooperativeMatrixConvert)) {
src = op->getArgOperand(1);
isConvert = true;
} else {
- assert(op->getCalledFunction()->getName().startswith(lgcName::CooperativeMatrixTranspose));
+ assert(op->getCalledFunction()->getName().starts_with(lgcName::CooperativeMatrixTranspose));
src = op->getArgOperand(0);
}
@@ -390,14 +390,14 @@ bool CooperativeMatrixCombiner::tryFoldComponentContaining(Value *start) {
if (auto *call = dyn_cast<CallInst>(input)) {
if (auto *callee = call->getCalledFunction()) {
- if (callee->getName().startswith(lgcName::CooperativeMatrixLoad))
+ if (callee->getName().starts_with(lgcName::CooperativeMatrixLoad))
continue; // loads can be adjusted at zero cost
- if (callee->getName().startswith(lgcName::CooperativeMatrixTranspose)) {
+ if (callee->getName().starts_with(lgcName::CooperativeMatrixTranspose)) {
foundComponentShape(getShapeOfTranspose(call));
++numTransposeInputs;
continue;
}
- if (callee->getName().startswith(lgcName::CooperativeMatrixConvert)) {
+ if (callee->getName().starts_with(lgcName::CooperativeMatrixConvert)) {
auto srcElemType =
(Builder::CooperativeMatrixElementType)cast<ConstantInt>(call->getArgOperand(2))->getZExtValue();
auto dstElemType =
@@ -427,14 +427,14 @@ bool CooperativeMatrixCombiner::tryFoldComponentContaining(Value *start) {
for (Use *use : component.outputs) {
if (auto *call = dyn_cast<CallInst>(use->getUser())) {
if (auto *callee = call->getCalledFunction()) {
- if (callee->getName().startswith(lgcName::CooperativeMatrixStore))
+ if (callee->getName().starts_with(lgcName::CooperativeMatrixStore))
continue; // stores can be adapted at zero cost
- if (callee->getName().startswith(lgcName::CooperativeMatrixTranspose)) {
+ if (callee->getName().starts_with(lgcName::CooperativeMatrixTranspose)) {
foundComponentShape(getShapeOfTranspose(call));
transposeOutputs.insert(use->get());
continue;
}
- if (callee->getName().startswith(lgcName::CooperativeMatrixConvert)) {
+ if (callee->getName().starts_with(lgcName::CooperativeMatrixConvert)) {
auto srcElemType =
(Builder::CooperativeMatrixElementType)cast<ConstantInt>(call->getArgOperand(2))->getZExtValue();
auto dstElemType =
@@ -473,7 +473,7 @@ bool CooperativeMatrixCombiner::tryFoldComponentContaining(Value *start) {
// Handle inputs that can be folded away / absorbed.
if (auto *call = dyn_cast<CallInst>(input)) {
if (auto *callee = call->getCalledFunction()) {
- if (callee->getName().startswith(lgcName::CooperativeMatrixTranspose)) {
+ if (callee->getName().starts_with(lgcName::CooperativeMatrixTranspose)) {
Value *src = call->getArgOperand(0);
foldTo(input, src);
@@ -481,7 +481,7 @@ bool CooperativeMatrixCombiner::tryFoldComponentContaining(Value *start) {
outTransposed.try_emplace(src, input);
continue;
}
- if (callee->getName().startswith(lgcName::CooperativeMatrixLoad)) {
+ if (callee->getName().starts_with(lgcName::CooperativeMatrixLoad)) {
bool colMajor = cast<ConstantInt>(call->getArgOperand(2))->getZExtValue();
call->setArgOperand(2, b.getInt1(!colMajor));
continue;
@@ -507,11 +507,11 @@ bool CooperativeMatrixCombiner::tryFoldComponentContaining(Value *start) {
// Handle outputs that can be folded away / absorbed.
if (auto *call = dyn_cast<CallInst>(use->getUser())) {
if (auto *callee = call->getCalledFunction()) {
- if (callee->getName().startswith(lgcName::CooperativeMatrixTranspose)) {
+ if (callee->getName().starts_with(lgcName::CooperativeMatrixTranspose)) {
foldTo(call, use->get());
continue;
}
- if (callee->getName().startswith(lgcName::CooperativeMatrixStore)) {
+ if (callee->getName().starts_with(lgcName::CooperativeMatrixStore)) {
bool colMajor = cast<ConstantInt>(call->getArgOperand(2))->getZExtValue();
call->setArgOperand(2, b.getInt1(!colMajor));
continue;
@@ -587,7 +587,7 @@ bool CooperativeMatrixCombiner::tryFoldComponentContaining(Value *start) {
// Handle inputs for which the relayout can be folded or absorbed.
if (auto *call = dyn_cast<CallInst>(input)) {
if (auto *callee = call->getCalledFunction()) {
- if (callee->getName().startswith(lgcName::CooperativeMatrixConvert)) {
+ if (callee->getName().starts_with(lgcName::CooperativeMatrixConvert)) {
unsigned srcElemType = cast<ConstantInt>(call->getArgOperand(2))->getZExtValue();
unsigned dstElemType = cast<ConstantInt>(call->getArgOperand(3))->getZExtValue();
@@ -609,7 +609,7 @@ bool CooperativeMatrixCombiner::tryFoldComponentContaining(Value *start) {
call->setArgOperand(5, b.getInt32((unsigned)*otherLayout));
continue;
}
- if (callee->getName().startswith(lgcName::CooperativeMatrixLoad)) {
+ if (callee->getName().starts_with(lgcName::CooperativeMatrixLoad)) {
call->setArgOperand(4, b.getInt32((unsigned)*otherLayout));
continue;
}
@@ -635,7 +635,7 @@ bool CooperativeMatrixCombiner::tryFoldComponentContaining(Value *start) {
// Handle outputs for which the relayout can be folded or absorbed.
if (auto *call = dyn_cast<CallInst>(use->getUser())) {
if (auto *callee = call->getCalledFunction()) {
- if (callee->getName().startswith(lgcName::CooperativeMatrixConvert)) {
+ if (callee->getName().starts_with(lgcName::CooperativeMatrixConvert)) {
unsigned srcElemType = cast<ConstantInt>(call->getArgOperand(2))->getZExtValue();
unsigned dstElemType = cast<ConstantInt>(call->getArgOperand(3))->getZExtValue();
@@ -649,7 +649,7 @@ bool CooperativeMatrixCombiner::tryFoldComponentContaining(Value *start) {
continue;
}
}
- if (callee->getName().startswith(lgcName::CooperativeMatrixStore)) {
+ if (callee->getName().starts_with(lgcName::CooperativeMatrixStore)) {
call->setArgOperand(4, b.getInt32((unsigned)*otherLayout));
continue;
}
@@ -837,7 +837,7 @@ bool CooperativeMatrixCombiner::tryFoldMuladd(SmallVector<CallInst *> muladds) {
auto *candidate = llvm::find_if(unpackedUses, [&](auto pair) {
if (auto *call = dyn_cast<CallInst>(pair.first.getUser())) {
if (auto *callee = call->getCalledFunction()) {
- if (callee->getName().startswith(lgcName::CooperativeMatrixTimesScalar) &&
+ if (callee->getName().starts_with(lgcName::CooperativeMatrixTimesScalar) &&
call->getArgOperand(0) == current.matrixLo) {
return true;
}
@@ -871,7 +871,7 @@ bool CooperativeMatrixCombiner::tryFoldMuladd(SmallVector<CallInst *> muladds) {
continue;
if (auto *call = dyn_cast<CallInst>(use.first.getUser())) {
- if (call->getCalledFunction()->getName().startswith(lgcName::CooperativeMatrixPack) &&
+ if (call->getCalledFunction()->getName().starts_with(lgcName::CooperativeMatrixPack) &&
call->getArgOperand(0) == current.matrixLo && call->getArgOperand(1) == current.matrixHi) {
foldTo(call, current.packedAccum);
continue;
diff --git a/lgc/patch/ConfigBuilderBase.cpp b/lgc/patch/ConfigBuilderBase.cpp
index 721bb2b2ec..f699ec1f66 100644
--- a/lgc/patch/ConfigBuilderBase.cpp
+++ b/lgc/patch/ConfigBuilderBase.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -47,12 +47,12 @@ ConfigBuilderBase::ConfigBuilderBase(Module *module, PipelineState *pipelineStat
: m_module(module), m_pipelineState(pipelineState) {
m_context = &module->getContext();
- m_hasVs = m_pipelineState->hasShaderStage(ShaderStageVertex);
- m_hasTcs = m_pipelineState->hasShaderStage(ShaderStageTessControl);
- m_hasTes = m_pipelineState->hasShaderStage(ShaderStageTessEval);
- m_hasGs = m_pipelineState->hasShaderStage(ShaderStageGeometry);
- m_hasTask = m_pipelineState->hasShaderStage(ShaderStageTask);
- m_hasMesh = m_pipelineState->hasShaderStage(ShaderStageMesh);
+ m_hasVs = m_pipelineState->hasShaderStage(ShaderStage::Vertex);
+ m_hasTcs = m_pipelineState->hasShaderStage(ShaderStage::TessControl);
+ m_hasTes = m_pipelineState->hasShaderStage(ShaderStage::TessEval);
+ m_hasGs = m_pipelineState->hasShaderStage(ShaderStage::Geometry);
+ m_hasTask = m_pipelineState->hasShaderStage(ShaderStage::Task);
+ m_hasMesh = m_pipelineState->hasShaderStage(ShaderStage::Mesh);
m_gfxIp = m_pipelineState->getTargetInfo().getGfxIpVersion();
@@ -70,7 +70,7 @@ ConfigBuilderBase::ConfigBuilderBase(Module *module, PipelineState *pipelineStat
if (m_pipelineState->isGraphics())
m_graphicsRegistersNode = m_pipelineNode[Util::Abi::PipelineMetadataKey::GraphicsRegisters].getMap(true);
- if (m_pipelineState->hasShaderStage(ShaderStageCompute) || m_pipelineState->hasShaderStage(ShaderStageTask))
+ if (m_pipelineState->hasShaderStage(ShaderStage::Compute) || m_pipelineState->hasShaderStage(ShaderStage::Task))
m_computeRegistersNode = m_pipelineNode[Util::Abi::PipelineMetadataKey::ComputeRegisters].getMap(true);
}
@@ -87,7 +87,7 @@ ConfigBuilderBase::~ConfigBuilderBase() {
/// @param [in] apiStage : The API shader stage
/// @param [in] hwStages : The HW stage(s) that the API shader is mapped to, as a combination of
/// @ref Util::Abi::HardwareStageFlagBits.
-void ConfigBuilderBase::addApiHwShaderMapping(ShaderStage apiStage, unsigned hwStages) {
+void ConfigBuilderBase::addApiHwShaderMapping(ShaderStageEnum apiStage, unsigned hwStages) {
auto hwMappingNode = getApiShaderNode(apiStage)[Util::Abi::ShaderMetadataKey::HardwareMapping].getArray(true);
for (unsigned hwStage = 0; hwStage < unsigned(Util::Abi::HardwareStage::Count); ++hwStage) {
if (hwStages & (1 << hwStage))
@@ -125,7 +125,7 @@ msgpack::MapDocNode ConfigBuilderBase::getHwShaderNode(Util::Abi::HardwareStage
// a shader checksum for performance profiling where applicable.
//
// @param apiStage : API shader stage
-unsigned ConfigBuilderBase::setShaderHash(ShaderStage apiStage) {
+unsigned ConfigBuilderBase::setShaderHash(ShaderStageEnum apiStage) {
const ShaderOptions &shaderOptions = m_pipelineState->getShaderOptions(apiStage);
auto hashNode = getApiShaderNode(unsigned(apiStage))[Util::Abi::ShaderMetadataKey::ApiShaderHash].getArray(true);
hashNode[0] = shaderOptions.hash[0];
@@ -377,10 +377,10 @@ void ConfigBuilderBase::writePalMetadata() {
// Sets up floating point mode from the specified floating point control flags.
//
// @param shaderStage : Shader stage
-unsigned ConfigBuilderBase::setupFloatingPointMode(ShaderStage shaderStage) {
+unsigned ConfigBuilderBase::setupFloatingPointMode(ShaderStageEnum shaderStage) {
FloatMode floatMode = {};
floatMode.bits.fp16fp64DenormMode = FP_DENORM_FLUSH_NONE;
- if (shaderStage != ShaderStageCopyShader) {
+ if (shaderStage != ShaderStage::CopyShader) {
const auto &shaderMode = m_pipelineState->getShaderModes()->getCommonShaderMode(shaderStage);
// The HW rounding mode values happen to be one less than the FpRoundMode value, other than
diff --git a/lgc/patch/ConfigBuilderBase.h b/lgc/patch/ConfigBuilderBase.h
index 0e822d1da6..84f030e6a0 100644
--- a/lgc/patch/ConfigBuilderBase.h
+++ b/lgc/patch/ConfigBuilderBase.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -70,9 +70,9 @@ class ConfigBuilderBase {
llvm::msgpack::MapDocNode getHwShaderNode(Util::Abi::HardwareStage hwStage);
protected:
- void addApiHwShaderMapping(ShaderStage apiStage, unsigned hwStages);
+ void addApiHwShaderMapping(ShaderStageEnum apiStage, unsigned hwStages);
- unsigned setShaderHash(ShaderStage apiStage);
+ unsigned setShaderHash(ShaderStageEnum apiStage);
void setNumAvailSgprs(Util::Abi::HardwareStage hwStage, unsigned value);
void setNumAvailVgprs(Util::Abi::HardwareStage hwStage, unsigned value);
void setUsesViewportArrayIndex(bool useViewportIndex);
@@ -87,7 +87,7 @@ class ConfigBuilderBase {
void setNggSubgroupSize(unsigned value);
void setThreadgroupDimensions(llvm::ArrayRef<unsigned> values);
void setStreamOutVertexStrides(llvm::ArrayRef<unsigned> values);
- unsigned setupFloatingPointMode(ShaderStage shaderStage);
+ unsigned setupFloatingPointMode(ShaderStageEnum shaderStage);
void appendConfig(llvm::ArrayRef<PalMetadataNoteEntry> config);
void appendConfig(unsigned key, unsigned value);
@@ -130,7 +130,7 @@ class ConfigBuilderBase {
llvm::msgpack::Document *m_document; // The MsgPack document
llvm::msgpack::MapDocNode m_pipelineNode; // MsgPack map node for amdpal.pipelines[0]
- llvm::msgpack::MapDocNode m_apiShaderNodes[ShaderStageNativeStageCount];
+ llvm::msgpack::MapDocNode m_apiShaderNodes[ShaderStage::NativeStageCount];
// MsgPack map node for each API shader's node in
// ".shaders"
llvm::msgpack::MapDocNode m_hwShaderNodes[unsigned(Util::Abi::HardwareStage::Count)];
diff --git a/lgc/patch/Continufy.cpp b/lgc/patch/Continufy.cpp
index 18dedc09b2..6f0162f307 100644
--- a/lgc/patch/Continufy.cpp
+++ b/lgc/patch/Continufy.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -50,9 +50,10 @@ namespace lgc {
using RtStage = rt::RayTracingShaderStage;
static Function *insertCpsArguments(Function &fn) {
- // Mutate function arguments, add ({} %state, %rcr).
+ // Mutate function arguments, add ({} %state, %rcr, %shader-index).
LLVMContext &context = fn.getContext();
- SmallVector<Type *> argTys = {StructType::get(context, {}), IntegerType::get(context, 32)};
+ SmallVector<Type *> argTys = {StructType::get(context, {}), IntegerType::get(context, 32),
+ IntegerType::get(context, 32)};
auto *fnTy = fn.getFunctionType();
argTys.append(fnTy->params().begin(), fnTy->params().end());
@@ -61,12 +62,13 @@ static Function *insertCpsArguments(Function &fn) {
fn.replaceAllUsesWith(newFn);
for (unsigned idx = 0; idx < fn.arg_size(); idx++) {
Value *oldArg = fn.getArg(idx);
- Value *newArg = newFn->getArg(idx + 2);
+ Value *newArg = newFn->getArg(idx + 3);
newArg->setName(oldArg->getName());
oldArg->replaceAllUsesWith(newArg);
}
newFn->getArg(0)->setName("state");
newFn->getArg(1)->setName("rcr");
+ newFn->getArg(2)->setName("shader-index");
return newFn;
}
@@ -169,8 +171,10 @@ PreservedAnalyses Continufy::run(Module &module, ModuleAnalysisManager &analysis
if (calleeLevel != CpsLevel::RayGen)
continuationRef = builder.CreateOr(continuationRef, builder.getInt32((uint32_t)calleeLevel));
- SmallVector<Value *> callArgs(call.args());
- auto *newCall = builder.create<AwaitOp>(call.getType(), continuationRef, 1u << (unsigned)calleeLevel, callArgs);
+ // Always put a shader-index.
+ SmallVector<Value *> tailArgs = {PoisonValue::get(builder.getInt32Ty())};
+ tailArgs.append(call.arg_begin(), call.arg_end());
+ auto *newCall = builder.create<AwaitOp>(call.getType(), continuationRef, 1u << (unsigned)calleeLevel, tailArgs);
call.replaceAllUsesWith(newCall);
tobeErased.push_back(&call);
}
@@ -185,8 +189,9 @@ PreservedAnalyses Continufy::run(Module &module, ModuleAnalysisManager &analysis
if (auto *retInst = dyn_cast<ReturnInst>(term)) {
builder.SetInsertPoint(term);
auto *retValue = retInst->getReturnValue();
- // %rcr
- SmallVector<Value *> tailArgs = {PoisonValue::get(builder.getInt32Ty())};
+ // %rcr, %shader-index
+ SmallVector<Value *> tailArgs = {PoisonValue::get(builder.getInt32Ty()),
+ PoisonValue::get(builder.getInt32Ty())};
// return value
if (retValue)
tailArgs.push_back(retValue);
diff --git a/lgc/patch/FragColorExport.cpp b/lgc/patch/FragColorExport.cpp
index 2899035029..427a9fb6f9 100644
--- a/lgc/patch/FragColorExport.cpp
+++ b/lgc/patch/FragColorExport.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -439,9 +439,9 @@ bool LowerFragColorExport::runImpl(Module &module, PipelineShadersResult &pipeli
PipelineState *pipelineState) {
m_context = &module.getContext();
m_pipelineState = pipelineState;
- m_resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageFragment);
+ m_resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Fragment);
- Function *fragEntryPoint = pipelineShaders.getEntryPoint(ShaderStageFragment);
+ Function *fragEntryPoint = pipelineShaders.getEntryPoint(ShaderStage::Fragment);
if (!fragEntryPoint)
return false;
@@ -536,7 +536,7 @@ void LowerFragColorExport::collectExportInfoForGenericOutputs(Function *fragEntr
// Collect all of the exports in the fragment shader
for (auto &func : *fragEntryPoint->getParent()) {
- if (!func.isDeclaration() || !func.getName().startswith(lgcName::OutputExportGeneric))
+ if (!func.isDeclaration() || !func.getName().starts_with(lgcName::OutputExportGeneric))
continue;
for (auto user : func.users()) {
auto callInst = cast<CallInst>(user);
@@ -668,7 +668,7 @@ void LowerFragColorExport::collectExportInfoForBuiltinOutput(Function *module, B
Value *m_fragStencilRef = nullptr;
Value *m_sampleMask = nullptr;
for (auto &func : *module->getParent()) {
- if (!func.isDeclaration() || !func.getName().startswith(lgcName::OutputExportBuiltIn))
+ if (!func.isDeclaration() || !func.getName().starts_with(lgcName::OutputExportBuiltIn))
continue;
for (auto user : func.users()) {
auto callInst = cast<CallInst>(user);
@@ -797,7 +797,7 @@ void FragColorExport::setDoneFlag(Value *exportInst, BuilderBase &builder) {
// @param builder : The builder object that will be used to create new instructions.
Value *FragColorExport::dualSourceSwizzle(BuilderBase &builder) {
Value *result0[4], *result1[4];
- unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStageFragment);
+ unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Fragment);
auto undefFloat = PoisonValue::get(builder.getFloatTy());
Value *threadId =
@@ -1129,10 +1129,10 @@ Function *FragColorExport::generateNullFragmentEntryPoint(Module &module, Pipeli
FunctionType *entryPointTy = FunctionType::get(Type::getVoidTy(module.getContext()), ArrayRef<Type *>(), false);
Function *entryPoint = Function::Create(entryPointTy, GlobalValue::ExternalLinkage, entryPointName, &module);
entryPoint->setDLLStorageClass(GlobalValue::DLLExportStorageClass);
- setShaderStage(entryPoint, ShaderStageFragment);
+ setShaderStage(entryPoint, ShaderStage::Fragment);
entryPoint->setCallingConv(CallingConv::AMDGPU_PS);
if (pipelineState->getTargetInfo().getGfxIpVersion().major >= 10) {
- const unsigned waveSize = pipelineState->getShaderWaveSize(ShaderStageFragment);
+ const unsigned waveSize = pipelineState->getShaderWaveSize(ShaderStage::Fragment);
entryPoint->addFnAttr("target-features", ",+wavefrontsize" + std::to_string(waveSize)); // Set wavefront size
}
return entryPoint;
diff --git a/lgc/patch/Gfx9Chip.cpp b/lgc/patch/Gfx9Chip.cpp
index ee4c4e08eb..2ae401747c 100644
--- a/lgc/patch/Gfx9Chip.cpp
+++ b/lgc/patch/Gfx9Chip.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/patch/Gfx9Chip.h b/lgc/patch/Gfx9Chip.h
index 9a87d34507..6bb0b37419 100644
--- a/lgc/patch/Gfx9Chip.h
+++ b/lgc/patch/Gfx9Chip.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/patch/Gfx9ConfigBuilder.cpp b/lgc/patch/Gfx9ConfigBuilder.cpp
index 61faaf0830..952cb11b27 100644
--- a/lgc/patch/Gfx9ConfigBuilder.cpp
+++ b/lgc/patch/Gfx9ConfigBuilder.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -98,23 +98,23 @@ void ConfigBuilder::buildPipelineVsFsRegConfig() {
PipelineVsFsRegConfig config(m_gfxIp);
- addApiHwShaderMapping(ShaderStageFragment, Util::Abi::HwShaderPs);
+ addApiHwShaderMapping(ShaderStage::Fragment, Util::Abi::HwShaderPs);
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, MAX_PRIMGRP_IN_WAVE, 2);
- if (m_pipelineState->hasShaderStage(ShaderStageVertex)) {
+ if (m_pipelineState->hasShaderStage(ShaderStage::Vertex)) {
setPipelineType(Util::Abi::PipelineType::VsPs);
- addApiHwShaderMapping(ShaderStageVertex, Util::Abi::HwShaderVs);
- buildVsRegConfig<PipelineVsFsRegConfig>(ShaderStageVertex, &config);
+ addApiHwShaderMapping(ShaderStage::Vertex, Util::Abi::HwShaderVs);
+ buildVsRegConfig<PipelineVsFsRegConfig>(ShaderStage::Vertex, &config);
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, VS_EN, VS_STAGE_REAL);
- const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStageVertex);
+ const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Vertex);
SET_REG_GFX10_PLUS_FIELD(&config, VGT_SHADER_STAGES_EN, VS_W32_EN, (waveSize == 32));
if (m_gfxIp.major == 10)
setWaveFrontSize(Util::Abi::HardwareStage::Vs, waveSize);
- unsigned checksum = setShaderHash(ShaderStageVertex);
+ unsigned checksum = setShaderHash(ShaderStage::Vertex);
SET_REG(&config, VGT_GS_ONCHIP_CNTL, 0);
if (m_pipelineState->getTargetInfo().getGpuProperty().supportShaderPowerProfiling) {
@@ -141,8 +141,8 @@ void ConfigBuilder::buildPipelineVsFsRegConfig() {
invalidRegConfig(config.vsRegs);
}
- if (m_pipelineState->hasShaderStage(ShaderStageFragment)) {
- buildPsRegConfig<PipelineVsFsRegConfig>(ShaderStageFragment, &config);
+ if (m_pipelineState->hasShaderStage(ShaderStage::Fragment)) {
+ buildPsRegConfig<PipelineVsFsRegConfig>(ShaderStage::Fragment, &config);
} else {
invalidRegConfig(config.psRegs);
}
@@ -157,10 +157,10 @@ void ConfigBuilder::buildPipelineVsTsFsRegConfig() {
PipelineVsTsFsRegConfig config(m_gfxIp);
- addApiHwShaderMapping(ShaderStageVertex, Util::Abi::HwShaderHs);
- addApiHwShaderMapping(ShaderStageTessControl, Util::Abi::HwShaderHs);
- addApiHwShaderMapping(ShaderStageTessEval, Util::Abi::HwShaderVs);
- addApiHwShaderMapping(ShaderStageFragment, Util::Abi::HwShaderPs);
+ addApiHwShaderMapping(ShaderStage::Vertex, Util::Abi::HwShaderHs);
+ addApiHwShaderMapping(ShaderStage::TessControl, Util::Abi::HwShaderHs);
+ addApiHwShaderMapping(ShaderStage::TessEval, Util::Abi::HwShaderVs);
+ addApiHwShaderMapping(ShaderStage::Fragment, Util::Abi::HwShaderPs);
setPipelineType(Util::Abi::PipelineType::Tess);
@@ -169,15 +169,16 @@ void ConfigBuilder::buildPipelineVsTsFsRegConfig() {
// to set VGT_SHADER_STAGES_EN.DYNAMIC_HS=1 and VGT_TF_PARAM.NUM_DS_WAVES_PER_SIMD=0
SET_REG_GFX10_PLUS_FIELD(&config, VGT_SHADER_STAGES_EN, DYNAMIC_HS, true);
- if (m_pipelineState->hasShaderStage(ShaderStageVertex) || m_pipelineState->hasShaderStage(ShaderStageTessControl)) {
- const bool hasVs = m_pipelineState->hasShaderStage(ShaderStageVertex);
- const bool hasTcs = m_pipelineState->hasShaderStage(ShaderStageTessControl);
+ if (m_pipelineState->hasShaderStage(ShaderStage::Vertex) ||
+ m_pipelineState->hasShaderStage(ShaderStage::TessControl)) {
+ const bool hasVs = m_pipelineState->hasShaderStage(ShaderStage::Vertex);
+ const bool hasTcs = m_pipelineState->hasShaderStage(ShaderStage::TessControl);
- buildLsHsRegConfig<PipelineVsTsFsRegConfig>(hasVs ? ShaderStageVertex : ShaderStageInvalid,
- hasTcs ? ShaderStageTessControl : ShaderStageInvalid, &config);
+ buildLsHsRegConfig<PipelineVsTsFsRegConfig>(hasVs ? ShaderStage::Vertex : ShaderStage::Invalid,
+ hasTcs ? ShaderStage::TessControl : ShaderStage::Invalid, &config);
- unsigned checksum = setShaderHash(ShaderStageVertex);
- checksum = checksum ^ setShaderHash(ShaderStageTessControl);
+ unsigned checksum = setShaderHash(ShaderStage::Vertex);
+ checksum = checksum ^ setShaderHash(ShaderStage::TessControl);
if (m_pipelineState->getTargetInfo().getGpuProperty().supportShaderPowerProfiling) {
SET_REG_FIELD(&config.lsHsRegs, SPI_SHADER_PGM_CHKSUM_HS, CHECKSUM, checksum);
@@ -186,7 +187,7 @@ void ConfigBuilder::buildPipelineVsTsFsRegConfig() {
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, HS_EN, HS_STAGE_ON);
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, LS_EN, LS_STAGE_ON);
- const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStageTessControl);
+ const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::TessControl);
SET_REG_GFX10_PLUS_FIELD(&config, VGT_SHADER_STAGES_EN, HS_W32_EN, (waveSize == 32));
if (m_gfxIp.major == 10)
@@ -195,18 +196,18 @@ void ConfigBuilder::buildPipelineVsTsFsRegConfig() {
invalidRegConfig(config.lsHsRegs);
}
- if (m_pipelineState->hasShaderStage(ShaderStageTessEval)) {
- buildVsRegConfig<PipelineVsTsFsRegConfig>(ShaderStageTessEval, &config);
+ if (m_pipelineState->hasShaderStage(ShaderStage::TessEval)) {
+ buildVsRegConfig<PipelineVsTsFsRegConfig>(ShaderStage::TessEval, &config);
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, VS_EN, VS_STAGE_DS);
- const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStageTessEval);
+ const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::TessEval);
SET_REG_GFX10_PLUS_FIELD(&config, VGT_SHADER_STAGES_EN, VS_W32_EN, (waveSize == 32));
if (m_gfxIp.major == 10)
setWaveFrontSize(Util::Abi::HardwareStage::Vs, waveSize);
- unsigned checksum = setShaderHash(ShaderStageTessEval);
+ unsigned checksum = setShaderHash(ShaderStage::TessEval);
if (m_pipelineState->getTargetInfo().getGpuProperty().supportShaderPowerProfiling) {
SET_REG(&config.vsRegs, SPI_SHADER_PGM_CHKSUM_VS, checksum);
@@ -215,8 +216,8 @@ void ConfigBuilder::buildPipelineVsTsFsRegConfig() {
invalidRegConfig(config.vsRegs);
}
- if (m_pipelineState->hasShaderStage(ShaderStageFragment)) {
- buildPsRegConfig<PipelineVsTsFsRegConfig>(ShaderStageFragment, &config);
+ if (m_pipelineState->hasShaderStage(ShaderStage::Fragment)) {
+ buildPsRegConfig<PipelineVsTsFsRegConfig>(ShaderStage::Fragment, &config);
} else {
invalidRegConfig(config.psRegs);
}
@@ -224,8 +225,8 @@ void ConfigBuilder::buildPipelineVsTsFsRegConfig() {
// Set up IA_MULTI_VGT_PARAM
regIA_MULTI_VGT_PARAM iaMultiVgtParam = {};
- const auto &tcsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl)->builtInUsage.tcs;
- const auto &tesBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessEval)->builtInUsage.tes;
+ const auto &tcsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl)->builtInUsage.tcs;
+ const auto &tesBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessEval)->builtInUsage.tes;
if (tcsBuiltInUsage.primitiveId || tesBuiltInUsage.primitiveId) {
iaMultiVgtParam.bits.PARTIAL_ES_WAVE_ON = true;
@@ -252,23 +253,23 @@ void ConfigBuilder::buildPipelineVsGsFsRegConfig() {
PipelineVsGsFsRegConfig config(m_gfxIp);
- addApiHwShaderMapping(ShaderStageVertex, Util::Abi::HwShaderGs);
- addApiHwShaderMapping(ShaderStageGeometry, Util::Abi::HwShaderGs | Util::Abi::HwShaderVs);
- addApiHwShaderMapping(ShaderStageFragment, Util::Abi::HwShaderPs);
+ addApiHwShaderMapping(ShaderStage::Vertex, Util::Abi::HwShaderGs);
+ addApiHwShaderMapping(ShaderStage::Geometry, Util::Abi::HwShaderGs | Util::Abi::HwShaderVs);
+ addApiHwShaderMapping(ShaderStage::Fragment, Util::Abi::HwShaderPs);
setPipelineType(Util::Abi::PipelineType::Gs);
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, MAX_PRIMGRP_IN_WAVE, 2);
- if (m_pipelineState->hasShaderStage(ShaderStageVertex) || m_pipelineState->hasShaderStage(ShaderStageGeometry)) {
- const bool hasVs = m_pipelineState->hasShaderStage(ShaderStageVertex);
- const bool hasGs = m_pipelineState->hasShaderStage(ShaderStageGeometry);
+ if (m_pipelineState->hasShaderStage(ShaderStage::Vertex) || m_pipelineState->hasShaderStage(ShaderStage::Geometry)) {
+ const bool hasVs = m_pipelineState->hasShaderStage(ShaderStage::Vertex);
+ const bool hasGs = m_pipelineState->hasShaderStage(ShaderStage::Geometry);
- buildEsGsRegConfig<PipelineVsGsFsRegConfig>(hasVs ? ShaderStageVertex : ShaderStageInvalid,
- hasGs ? ShaderStageGeometry : ShaderStageInvalid, &config);
+ buildEsGsRegConfig<PipelineVsGsFsRegConfig>(hasVs ? ShaderStage::Vertex : ShaderStage::Invalid,
+ hasGs ? ShaderStage::Geometry : ShaderStage::Invalid, &config);
- unsigned checksum = setShaderHash(ShaderStageVertex);
- checksum = checksum ^ setShaderHash(ShaderStageGeometry);
+ unsigned checksum = setShaderHash(ShaderStage::Vertex);
+ checksum = checksum ^ setShaderHash(ShaderStage::Geometry);
if (m_pipelineState->getTargetInfo().getGpuProperty().supportShaderPowerProfiling) {
SET_REG_FIELD(&config.esGsRegs, SPI_SHADER_PGM_CHKSUM_GS, CHECKSUM, checksum);
@@ -277,7 +278,7 @@ void ConfigBuilder::buildPipelineVsGsFsRegConfig() {
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, ES_EN, ES_STAGE_REAL);
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, GS_EN, GS_STAGE_ON);
- const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStageGeometry);
+ const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Geometry);
SET_REG_GFX10_PLUS_FIELD(&config, VGT_SHADER_STAGES_EN, GS_W32_EN, (waveSize == 32));
if (m_gfxIp.major == 10)
@@ -286,18 +287,18 @@ void ConfigBuilder::buildPipelineVsGsFsRegConfig() {
invalidRegConfig(config.esGsRegs);
}
- if (m_pipelineState->hasShaderStage(ShaderStageFragment)) {
- buildPsRegConfig<PipelineVsGsFsRegConfig>(ShaderStageFragment, &config);
+ if (m_pipelineState->hasShaderStage(ShaderStage::Fragment)) {
+ buildPsRegConfig<PipelineVsGsFsRegConfig>(ShaderStage::Fragment, &config);
} else {
invalidRegConfig(config.psRegs);
}
- if (m_pipelineState->hasShaderStage(ShaderStageCopyShader)) {
- buildVsRegConfig<PipelineVsGsFsRegConfig>(ShaderStageCopyShader, &config);
+ if (m_pipelineState->hasShaderStage(ShaderStage::CopyShader)) {
+ buildVsRegConfig<PipelineVsGsFsRegConfig>(ShaderStage::CopyShader, &config);
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, VS_EN, VS_STAGE_COPY_SHADER);
- const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStageCopyShader);
+ const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::CopyShader);
SET_REG_GFX10_PLUS_FIELD(&config, VGT_SHADER_STAGES_EN, VS_W32_EN, (waveSize == 32));
if (m_gfxIp.major == 10)
@@ -328,25 +329,26 @@ void ConfigBuilder::buildPipelineVsTsGsFsRegConfig() {
PipelineVsTsGsFsRegConfig config(m_gfxIp);
- addApiHwShaderMapping(ShaderStageVertex, Util::Abi::HwShaderHs);
- addApiHwShaderMapping(ShaderStageTessControl, Util::Abi::HwShaderHs);
- addApiHwShaderMapping(ShaderStageTessEval, Util::Abi::HwShaderGs);
- addApiHwShaderMapping(ShaderStageGeometry, Util::Abi::HwShaderGs | Util::Abi::HwShaderVs);
- addApiHwShaderMapping(ShaderStageFragment, Util::Abi::HwShaderPs);
+ addApiHwShaderMapping(ShaderStage::Vertex, Util::Abi::HwShaderHs);
+ addApiHwShaderMapping(ShaderStage::TessControl, Util::Abi::HwShaderHs);
+ addApiHwShaderMapping(ShaderStage::TessEval, Util::Abi::HwShaderGs);
+ addApiHwShaderMapping(ShaderStage::Geometry, Util::Abi::HwShaderGs | Util::Abi::HwShaderVs);
+ addApiHwShaderMapping(ShaderStage::Fragment, Util::Abi::HwShaderPs);
setPipelineType(Util::Abi::PipelineType::GsTess);
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, MAX_PRIMGRP_IN_WAVE, 2);
- if (m_pipelineState->hasShaderStage(ShaderStageVertex) || m_pipelineState->hasShaderStage(ShaderStageTessControl)) {
- const bool hasVs = m_pipelineState->hasShaderStage(ShaderStageVertex);
- const bool hasTcs = m_pipelineState->hasShaderStage(ShaderStageTessControl);
+ if (m_pipelineState->hasShaderStage(ShaderStage::Vertex) ||
+ m_pipelineState->hasShaderStage(ShaderStage::TessControl)) {
+ const bool hasVs = m_pipelineState->hasShaderStage(ShaderStage::Vertex);
+ const bool hasTcs = m_pipelineState->hasShaderStage(ShaderStage::TessControl);
- buildLsHsRegConfig<PipelineVsTsGsFsRegConfig>(hasVs ? ShaderStageVertex : ShaderStageInvalid,
- hasTcs ? ShaderStageTessControl : ShaderStageInvalid, &config);
+ buildLsHsRegConfig<PipelineVsTsGsFsRegConfig>(hasVs ? ShaderStage::Vertex : ShaderStage::Invalid,
+ hasTcs ? ShaderStage::TessControl : ShaderStage::Invalid, &config);
- unsigned checksum = setShaderHash(ShaderStageVertex);
- checksum = checksum ^ setShaderHash(ShaderStageTessControl);
+ unsigned checksum = setShaderHash(ShaderStage::Vertex);
+ checksum = checksum ^ setShaderHash(ShaderStage::TessControl);
if (m_pipelineState->getTargetInfo().getGpuProperty().supportShaderPowerProfiling) {
SET_REG_FIELD(&config.lsHsRegs, SPI_SHADER_PGM_CHKSUM_HS, CHECKSUM, checksum);
@@ -354,7 +356,7 @@ void ConfigBuilder::buildPipelineVsTsGsFsRegConfig() {
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, HS_EN, HS_STAGE_ON);
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, LS_EN, LS_STAGE_ON);
- const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStageTessControl);
+ const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::TessControl);
SET_REG_GFX10_PLUS_FIELD(&config, VGT_SHADER_STAGES_EN, HS_W32_EN, (waveSize == 32));
if (m_gfxIp.major == 10)
@@ -367,15 +369,16 @@ void ConfigBuilder::buildPipelineVsTsGsFsRegConfig() {
invalidRegConfig(config.lsHsRegs);
}
- if (m_pipelineState->hasShaderStage(ShaderStageTessEval) || m_pipelineState->hasShaderStage(ShaderStageGeometry)) {
- const bool hasTes = m_pipelineState->hasShaderStage(ShaderStageTessEval);
- const bool hasGs = m_pipelineState->hasShaderStage(ShaderStageGeometry);
+ if (m_pipelineState->hasShaderStage(ShaderStage::TessEval) ||
+ m_pipelineState->hasShaderStage(ShaderStage::Geometry)) {
+ const bool hasTes = m_pipelineState->hasShaderStage(ShaderStage::TessEval);
+ const bool hasGs = m_pipelineState->hasShaderStage(ShaderStage::Geometry);
- buildEsGsRegConfig<PipelineVsTsGsFsRegConfig>(hasTes ? ShaderStageTessEval : ShaderStageInvalid,
- hasGs ? ShaderStageGeometry : ShaderStageInvalid, &config);
+ buildEsGsRegConfig<PipelineVsTsGsFsRegConfig>(hasTes ? ShaderStage::TessEval : ShaderStage::Invalid,
+ hasGs ? ShaderStage::Geometry : ShaderStage::Invalid, &config);
- unsigned checksum = setShaderHash(ShaderStageTessEval);
- checksum = checksum ^ setShaderHash(ShaderStageGeometry);
+ unsigned checksum = setShaderHash(ShaderStage::TessEval);
+ checksum = checksum ^ setShaderHash(ShaderStage::Geometry);
if (m_pipelineState->getTargetInfo().getGpuProperty().supportShaderPowerProfiling) {
SET_REG_FIELD(&config.esGsRegs, SPI_SHADER_PGM_CHKSUM_GS, CHECKSUM, checksum);
@@ -384,7 +387,7 @@ void ConfigBuilder::buildPipelineVsTsGsFsRegConfig() {
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, ES_EN, ES_STAGE_DS);
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, GS_EN, GS_STAGE_ON);
- const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStageGeometry);
+ const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Geometry);
SET_REG_GFX10_PLUS_FIELD(&config, VGT_SHADER_STAGES_EN, GS_W32_EN, (waveSize == 32));
if (m_gfxIp.major == 10)
@@ -393,18 +396,18 @@ void ConfigBuilder::buildPipelineVsTsGsFsRegConfig() {
invalidRegConfig(config.esGsRegs);
}
- if (m_pipelineState->hasShaderStage(ShaderStageFragment)) {
- buildPsRegConfig<PipelineVsTsGsFsRegConfig>(ShaderStageFragment, &config);
+ if (m_pipelineState->hasShaderStage(ShaderStage::Fragment)) {
+ buildPsRegConfig<PipelineVsTsGsFsRegConfig>(ShaderStage::Fragment, &config);
} else {
invalidRegConfig(config.psRegs);
}
- if (m_pipelineState->hasShaderStage(ShaderStageCopyShader)) {
- buildVsRegConfig<PipelineVsTsGsFsRegConfig>(ShaderStageCopyShader, &config);
+ if (m_pipelineState->hasShaderStage(ShaderStage::CopyShader)) {
+ buildVsRegConfig<PipelineVsTsGsFsRegConfig>(ShaderStage::CopyShader, &config);
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, VS_EN, VS_STAGE_COPY_SHADER);
- const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStageCopyShader);
+ const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::CopyShader);
SET_REG_GFX10_PLUS_FIELD(&config, VGT_SHADER_STAGES_EN, VS_W32_EN, (waveSize == 32));
if (m_gfxIp.major == 10)
@@ -416,9 +419,9 @@ void ConfigBuilder::buildPipelineVsTsGsFsRegConfig() {
// Set up IA_MULTI_VGT_PARAM
regIA_MULTI_VGT_PARAM iaMultiVgtParam = {};
- const auto &tcsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl)->builtInUsage.tcs;
- const auto &tesBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessEval)->builtInUsage.tes;
- const auto &gsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->builtInUsage.gs;
+ const auto &tcsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl)->builtInUsage.tcs;
+ const auto &tesBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessEval)->builtInUsage.tes;
+ const auto &gsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->builtInUsage.gs;
// With tessellation, SWITCH_ON_EOI and PARTIAL_ES_WAVE_ON must be set if primitive ID is used by either the TCS, TES,
// or GS.
@@ -444,13 +447,13 @@ void ConfigBuilder::buildPipelineNggVsFsRegConfig() {
PipelineNggVsFsRegConfig config(m_gfxIp);
- addApiHwShaderMapping(ShaderStageFragment, Util::Abi::HwShaderPs);
+ addApiHwShaderMapping(ShaderStage::Fragment, Util::Abi::HwShaderPs);
- if (m_pipelineState->hasShaderStage(ShaderStageVertex)) {
+ if (m_pipelineState->hasShaderStage(ShaderStage::Vertex)) {
const auto nggControl = m_pipelineState->getNggControl();
assert(nggControl->enableNgg);
- addApiHwShaderMapping(ShaderStageVertex, Util::Abi::HwShaderGs);
+ addApiHwShaderMapping(ShaderStage::Vertex, Util::Abi::HwShaderGs);
setPipelineType(Util::Abi::PipelineType::Ngg);
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, MAX_PRIMGRP_IN_WAVE, 2);
@@ -465,19 +468,19 @@ void ConfigBuilder::buildPipelineNggVsFsRegConfig() {
SET_REG_GFX10_PLUS_FIELD(&config, VGT_SHADER_STAGES_EN, NGG_WAVE_ID_EN, m_pipelineState->enableSwXfb());
}
- buildPrimShaderRegConfig<PipelineNggVsFsRegConfig>(ShaderStageVertex, ShaderStageInvalid, &config);
+ buildPrimShaderRegConfig<PipelineNggVsFsRegConfig>(ShaderStage::Vertex, ShaderStage::Invalid, &config);
if (m_gfxIp.major <= 11) {
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, ES_EN, ES_STAGE_REAL);
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, VS_EN, VS_STAGE_REAL);
}
- const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStageVertex);
+ const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Vertex);
SET_REG_GFX10_PLUS_FIELD(&config, VGT_SHADER_STAGES_EN, GS_W32_EN, (waveSize == 32));
setWaveFrontSize(Util::Abi::HardwareStage::Gs, waveSize);
- unsigned checksum = setShaderHash(ShaderStageVertex);
+ unsigned checksum = setShaderHash(ShaderStage::Vertex);
if (m_pipelineState->getTargetInfo().getGpuProperty().supportShaderPowerProfiling) {
SET_REG_FIELD(&config.primShaderRegs, SPI_SHADER_PGM_CHKSUM_GS, CHECKSUM, checksum);
@@ -499,8 +502,8 @@ void ConfigBuilder::buildPipelineNggVsFsRegConfig() {
invalidRegConfig(config.primShaderRegs);
}
- if (m_pipelineState->hasShaderStage(ShaderStageFragment)) {
- buildPsRegConfig<PipelineNggVsFsRegConfig>(ShaderStageFragment, &config);
+ if (m_pipelineState->hasShaderStage(ShaderStage::Fragment)) {
+ buildPsRegConfig<PipelineNggVsFsRegConfig>(ShaderStage::Fragment, &config);
} else {
invalidRegConfig(config.psRegs);
}
@@ -518,10 +521,10 @@ void ConfigBuilder::buildPipelineNggVsTsFsRegConfig() {
PipelineNggVsTsFsRegConfig config(m_gfxIp);
- addApiHwShaderMapping(ShaderStageVertex, Util::Abi::HwShaderHs);
- addApiHwShaderMapping(ShaderStageTessControl, Util::Abi::HwShaderHs);
- addApiHwShaderMapping(ShaderStageTessEval, Util::Abi::HwShaderGs);
- addApiHwShaderMapping(ShaderStageFragment, Util::Abi::HwShaderPs);
+ addApiHwShaderMapping(ShaderStage::Vertex, Util::Abi::HwShaderHs);
+ addApiHwShaderMapping(ShaderStage::TessControl, Util::Abi::HwShaderHs);
+ addApiHwShaderMapping(ShaderStage::TessEval, Util::Abi::HwShaderGs);
+ addApiHwShaderMapping(ShaderStage::Fragment, Util::Abi::HwShaderPs);
setPipelineType(Util::Abi::PipelineType::NggTess);
@@ -537,15 +540,16 @@ void ConfigBuilder::buildPipelineNggVsTsFsRegConfig() {
SET_REG_GFX10_PLUS_FIELD(&config, VGT_SHADER_STAGES_EN, NGG_WAVE_ID_EN, m_pipelineState->enableSwXfb());
}
- if (m_pipelineState->hasShaderStage(ShaderStageVertex) || m_pipelineState->hasShaderStage(ShaderStageTessControl)) {
- const bool hasVs = m_pipelineState->hasShaderStage(ShaderStageVertex);
- const bool hasTcs = m_pipelineState->hasShaderStage(ShaderStageTessControl);
+ if (m_pipelineState->hasShaderStage(ShaderStage::Vertex) ||
+ m_pipelineState->hasShaderStage(ShaderStage::TessControl)) {
+ const bool hasVs = m_pipelineState->hasShaderStage(ShaderStage::Vertex);
+ const bool hasTcs = m_pipelineState->hasShaderStage(ShaderStage::TessControl);
- buildLsHsRegConfig<PipelineNggVsTsFsRegConfig>(hasVs ? ShaderStageVertex : ShaderStageInvalid,
- hasTcs ? ShaderStageTessControl : ShaderStageInvalid, &config);
+ buildLsHsRegConfig<PipelineNggVsTsFsRegConfig>(hasVs ? ShaderStage::Vertex : ShaderStage::Invalid,
+ hasTcs ? ShaderStage::TessControl : ShaderStage::Invalid, &config);
- unsigned checksum = setShaderHash(ShaderStageVertex);
- checksum = checksum ^ setShaderHash(ShaderStageTessControl);
+ unsigned checksum = setShaderHash(ShaderStage::Vertex);
+ checksum = checksum ^ setShaderHash(ShaderStage::TessControl);
if (m_pipelineState->getTargetInfo().getGpuProperty().supportShaderPowerProfiling) {
SET_REG_FIELD(&config.lsHsRegs, SPI_SHADER_PGM_CHKSUM_HS, CHECKSUM, checksum);
@@ -555,7 +559,7 @@ void ConfigBuilder::buildPipelineNggVsTsFsRegConfig() {
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, LS_EN, LS_STAGE_ON);
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, HS_EN, HS_STAGE_ON);
- const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStageTessControl);
+ const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::TessControl);
SET_REG_GFX10_PLUS_FIELD(&config, VGT_SHADER_STAGES_EN, HS_W32_EN, (waveSize == 32));
setWaveFrontSize(Util::Abi::HardwareStage::Hs, waveSize);
@@ -563,20 +567,20 @@ void ConfigBuilder::buildPipelineNggVsTsFsRegConfig() {
invalidRegConfig(config.lsHsRegs);
}
- if (m_pipelineState->hasShaderStage(ShaderStageTessEval)) {
- buildPrimShaderRegConfig<PipelineNggVsTsFsRegConfig>(ShaderStageTessEval, ShaderStageInvalid, &config);
+ if (m_pipelineState->hasShaderStage(ShaderStage::TessEval)) {
+ buildPrimShaderRegConfig<PipelineNggVsTsFsRegConfig>(ShaderStage::TessEval, ShaderStage::Invalid, &config);
if (m_gfxIp.major <= 11) {
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, ES_EN, ES_STAGE_DS);
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, VS_EN, VS_STAGE_REAL);
}
- const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStageTessEval);
+ const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::TessEval);
SET_REG_GFX10_PLUS_FIELD(&config, VGT_SHADER_STAGES_EN, GS_W32_EN, (waveSize == 32));
setWaveFrontSize(Util::Abi::HardwareStage::Gs, waveSize);
- unsigned checksum = setShaderHash(ShaderStageTessEval);
+ unsigned checksum = setShaderHash(ShaderStage::TessEval);
if (m_pipelineState->getTargetInfo().getGpuProperty().supportShaderPowerProfiling) {
SET_REG_FIELD(&config.primShaderRegs, SPI_SHADER_PGM_CHKSUM_GS, CHECKSUM, checksum);
@@ -585,8 +589,8 @@ void ConfigBuilder::buildPipelineNggVsTsFsRegConfig() {
invalidRegConfig(config.primShaderRegs);
}
- if (m_pipelineState->hasShaderStage(ShaderStageFragment)) {
- buildPsRegConfig<PipelineNggVsTsFsRegConfig>(ShaderStageFragment, &config);
+ if (m_pipelineState->hasShaderStage(ShaderStage::Fragment)) {
+ buildPsRegConfig<PipelineNggVsTsFsRegConfig>(ShaderStage::Fragment, &config);
} else {
invalidRegConfig(config.psRegs);
}
@@ -594,7 +598,7 @@ void ConfigBuilder::buildPipelineNggVsTsFsRegConfig() {
// Set up IA_MULTI_VGT_PARAM
regIA_MULTI_VGT_PARAM iaMultiVgtParam = {};
- const auto &tcsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl)->builtInUsage.tcs;
+ const auto &tcsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl)->builtInUsage.tcs;
if (tcsBuiltInUsage.primitiveId)
iaMultiVgtParam.bits.SWITCH_ON_EOI = true;
@@ -613,9 +617,9 @@ void ConfigBuilder::buildPipelineNggVsGsFsRegConfig() {
PipelineNggVsGsFsRegConfig config(m_gfxIp);
- addApiHwShaderMapping(ShaderStageVertex, Util::Abi::HwShaderGs);
- addApiHwShaderMapping(ShaderStageGeometry, Util::Abi::HwShaderGs);
- addApiHwShaderMapping(ShaderStageFragment, Util::Abi::HwShaderPs);
+ addApiHwShaderMapping(ShaderStage::Vertex, Util::Abi::HwShaderGs);
+ addApiHwShaderMapping(ShaderStage::Geometry, Util::Abi::HwShaderGs);
+ addApiHwShaderMapping(ShaderStage::Fragment, Util::Abi::HwShaderPs);
setPipelineType(Util::Abi::PipelineType::Ngg);
@@ -631,15 +635,15 @@ void ConfigBuilder::buildPipelineNggVsGsFsRegConfig() {
if (m_gfxIp.major >= 11)
SET_REG_GFX10_PLUS_FIELD(&config, VGT_SHADER_STAGES_EN, NGG_WAVE_ID_EN, m_pipelineState->enableSwXfb());
- if (m_pipelineState->hasShaderStage(ShaderStageVertex) || m_pipelineState->hasShaderStage(ShaderStageGeometry)) {
- const bool hasVs = m_pipelineState->hasShaderStage(ShaderStageVertex);
- const bool hasGs = m_pipelineState->hasShaderStage(ShaderStageGeometry);
+ if (m_pipelineState->hasShaderStage(ShaderStage::Vertex) || m_pipelineState->hasShaderStage(ShaderStage::Geometry)) {
+ const bool hasVs = m_pipelineState->hasShaderStage(ShaderStage::Vertex);
+ const bool hasGs = m_pipelineState->hasShaderStage(ShaderStage::Geometry);
- buildPrimShaderRegConfig<PipelineNggVsGsFsRegConfig>(hasVs ? ShaderStageVertex : ShaderStageInvalid,
- hasGs ? ShaderStageGeometry : ShaderStageInvalid, &config);
+ buildPrimShaderRegConfig<PipelineNggVsGsFsRegConfig>(hasVs ? ShaderStage::Vertex : ShaderStage::Invalid,
+ hasGs ? ShaderStage::Geometry : ShaderStage::Invalid, &config);
- unsigned checksum = setShaderHash(ShaderStageVertex);
- checksum = checksum ^ setShaderHash(ShaderStageGeometry);
+ unsigned checksum = setShaderHash(ShaderStage::Vertex);
+ checksum = checksum ^ setShaderHash(ShaderStage::Geometry);
if (m_pipelineState->getTargetInfo().getGpuProperty().supportShaderPowerProfiling) {
SET_REG_FIELD(&config.primShaderRegs, SPI_SHADER_PGM_CHKSUM_GS, CHECKSUM, checksum);
@@ -651,7 +655,7 @@ void ConfigBuilder::buildPipelineNggVsGsFsRegConfig() {
}
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, GS_EN, GS_STAGE_ON);
- const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStageGeometry);
+ const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Geometry);
SET_REG_GFX10_PLUS_FIELD(&config, VGT_SHADER_STAGES_EN, GS_W32_EN, (waveSize == 32));
setWaveFrontSize(Util::Abi::HardwareStage::Gs, waveSize);
@@ -659,8 +663,8 @@ void ConfigBuilder::buildPipelineNggVsGsFsRegConfig() {
invalidRegConfig(config.primShaderRegs);
}
- if (m_pipelineState->hasShaderStage(ShaderStageFragment)) {
- buildPsRegConfig<PipelineNggVsGsFsRegConfig>(ShaderStageFragment, &config);
+ if (m_pipelineState->hasShaderStage(ShaderStage::Fragment)) {
+ buildPsRegConfig<PipelineNggVsGsFsRegConfig>(ShaderStage::Fragment, &config);
} else {
invalidRegConfig(config.psRegs);
}
@@ -685,11 +689,11 @@ void ConfigBuilder::buildPipelineNggVsTsGsFsRegConfig() {
PipelineNggVsTsGsFsRegConfig config(m_gfxIp);
- addApiHwShaderMapping(ShaderStageVertex, Util::Abi::HwShaderHs);
- addApiHwShaderMapping(ShaderStageTessControl, Util::Abi::HwShaderHs);
- addApiHwShaderMapping(ShaderStageTessEval, Util::Abi::HwShaderGs);
- addApiHwShaderMapping(ShaderStageGeometry, Util::Abi::HwShaderGs);
- addApiHwShaderMapping(ShaderStageFragment, Util::Abi::HwShaderPs);
+ addApiHwShaderMapping(ShaderStage::Vertex, Util::Abi::HwShaderHs);
+ addApiHwShaderMapping(ShaderStage::TessControl, Util::Abi::HwShaderHs);
+ addApiHwShaderMapping(ShaderStage::TessEval, Util::Abi::HwShaderGs);
+ addApiHwShaderMapping(ShaderStage::Geometry, Util::Abi::HwShaderGs);
+ addApiHwShaderMapping(ShaderStage::Fragment, Util::Abi::HwShaderPs);
setPipelineType(Util::Abi::PipelineType::NggTess);
@@ -705,15 +709,16 @@ void ConfigBuilder::buildPipelineNggVsTsGsFsRegConfig() {
if (m_gfxIp.major >= 11)
SET_REG_GFX10_PLUS_FIELD(&config, VGT_SHADER_STAGES_EN, NGG_WAVE_ID_EN, m_pipelineState->enableSwXfb());
- if (m_pipelineState->hasShaderStage(ShaderStageVertex) || m_pipelineState->hasShaderStage(ShaderStageTessControl)) {
- const bool hasVs = m_pipelineState->hasShaderStage(ShaderStageVertex);
- const bool hasTcs = m_pipelineState->hasShaderStage(ShaderStageTessControl);
+ if (m_pipelineState->hasShaderStage(ShaderStage::Vertex) ||
+ m_pipelineState->hasShaderStage(ShaderStage::TessControl)) {
+ const bool hasVs = m_pipelineState->hasShaderStage(ShaderStage::Vertex);
+ const bool hasTcs = m_pipelineState->hasShaderStage(ShaderStage::TessControl);
- buildLsHsRegConfig<PipelineNggVsTsGsFsRegConfig>(hasVs ? ShaderStageVertex : ShaderStageInvalid,
- hasTcs ? ShaderStageTessControl : ShaderStageInvalid, &config);
+ buildLsHsRegConfig<PipelineNggVsTsGsFsRegConfig>(hasVs ? ShaderStage::Vertex : ShaderStage::Invalid,
+ hasTcs ? ShaderStage::TessControl : ShaderStage::Invalid, &config);
- unsigned checksum = setShaderHash(ShaderStageVertex);
- checksum = checksum ^ setShaderHash(ShaderStageTessControl);
+ unsigned checksum = setShaderHash(ShaderStage::Vertex);
+ checksum = checksum ^ setShaderHash(ShaderStage::TessControl);
if (m_pipelineState->getTargetInfo().getGpuProperty().supportShaderPowerProfiling) {
SET_REG_FIELD(&config.lsHsRegs, SPI_SHADER_PGM_CHKSUM_HS, CHECKSUM, checksum);
@@ -723,7 +728,7 @@ void ConfigBuilder::buildPipelineNggVsTsGsFsRegConfig() {
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, LS_EN, LS_STAGE_ON);
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, HS_EN, HS_STAGE_ON);
- const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStageTessControl);
+ const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::TessControl);
SET_REG_GFX10_PLUS_FIELD(&config, VGT_SHADER_STAGES_EN, HS_W32_EN, (waveSize == 32));
setWaveFrontSize(Util::Abi::HardwareStage::Hs, waveSize);
@@ -731,15 +736,17 @@ void ConfigBuilder::buildPipelineNggVsTsGsFsRegConfig() {
invalidRegConfig(config.lsHsRegs);
}
- if (m_pipelineState->hasShaderStage(ShaderStageTessEval) || m_pipelineState->hasShaderStage(ShaderStageGeometry)) {
- const bool hasTes = m_pipelineState->hasShaderStage(ShaderStageTessEval);
- const bool hasGs = m_pipelineState->hasShaderStage(ShaderStageGeometry);
+ if (m_pipelineState->hasShaderStage(ShaderStage::TessEval) ||
+ m_pipelineState->hasShaderStage(ShaderStage::Geometry)) {
+ const bool hasTes = m_pipelineState->hasShaderStage(ShaderStage::TessEval);
+ const bool hasGs = m_pipelineState->hasShaderStage(ShaderStage::Geometry);
- buildPrimShaderRegConfig<PipelineNggVsTsGsFsRegConfig>(hasTes ? ShaderStageTessEval : ShaderStageInvalid,
- hasGs ? ShaderStageGeometry : ShaderStageInvalid, &config);
+ buildPrimShaderRegConfig<PipelineNggVsTsGsFsRegConfig>(hasTes ? ShaderStage::TessEval : ShaderStage::Invalid,
+ hasGs ? ShaderStage::Geometry : ShaderStage::Invalid,
+ &config);
- unsigned checksum = setShaderHash(ShaderStageTessEval);
- checksum = checksum ^ setShaderHash(ShaderStageGeometry);
+ unsigned checksum = setShaderHash(ShaderStage::TessEval);
+ checksum = checksum ^ setShaderHash(ShaderStage::Geometry);
if (m_pipelineState->getTargetInfo().getGpuProperty().supportShaderPowerProfiling) {
SET_REG_FIELD(&config.primShaderRegs, SPI_SHADER_PGM_CHKSUM_GS, CHECKSUM, checksum);
@@ -751,7 +758,7 @@ void ConfigBuilder::buildPipelineNggVsTsGsFsRegConfig() {
}
SET_REG_FIELD(&config, VGT_SHADER_STAGES_EN, GS_EN, GS_STAGE_ON);
- const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStageGeometry);
+ const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Geometry);
SET_REG_GFX10_PLUS_FIELD(&config, VGT_SHADER_STAGES_EN, GS_W32_EN, (waveSize == 32));
setWaveFrontSize(Util::Abi::HardwareStage::Gs, waveSize);
@@ -759,8 +766,8 @@ void ConfigBuilder::buildPipelineNggVsTsGsFsRegConfig() {
invalidRegConfig(config.primShaderRegs);
}
- if (m_pipelineState->hasShaderStage(ShaderStageFragment)) {
- buildPsRegConfig<PipelineNggVsTsGsFsRegConfig>(ShaderStageFragment, &config);
+ if (m_pipelineState->hasShaderStage(ShaderStage::Fragment)) {
+ buildPsRegConfig<PipelineNggVsTsGsFsRegConfig>(ShaderStage::Fragment, &config);
} else {
invalidRegConfig(config.psRegs);
}
@@ -768,8 +775,8 @@ void ConfigBuilder::buildPipelineNggVsTsGsFsRegConfig() {
// Set up IA_MULTI_VGT_PARAM
regIA_MULTI_VGT_PARAM iaMultiVgtParam = {};
- const auto &tcsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl)->builtInUsage.tcs;
- const auto &gsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->builtInUsage.gs;
+ const auto &tcsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl)->builtInUsage.tcs;
+ const auto &gsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->builtInUsage.gs;
if (tcsBuiltInUsage.primitiveId || gsBuiltInUsage.primitiveIdIn)
iaMultiVgtParam.bits.SWITCH_ON_EOI = true;
@@ -789,19 +796,19 @@ void ConfigBuilder::buildPipelineMeshFsConfig() {
PipelineMeshFsRegConfig config(m_gfxIp);
- addApiHwShaderMapping(ShaderStageMesh, Util::Abi::HwShaderGs);
- addApiHwShaderMapping(ShaderStageFragment, Util::Abi::HwShaderPs);
+ addApiHwShaderMapping(ShaderStage::Mesh, Util::Abi::HwShaderGs);
+ addApiHwShaderMapping(ShaderStage::Fragment, Util::Abi::HwShaderPs);
setPipelineType(Util::Abi::PipelineType::Mesh);
// Must contain mesh shader
- assert(m_pipelineState->hasShaderStage(ShaderStageMesh));
- buildMeshRegConfig<PipelineMeshFsRegConfig>(ShaderStageMesh, &config);
+ assert(m_pipelineState->hasShaderStage(ShaderStage::Mesh));
+ buildMeshRegConfig<PipelineMeshFsRegConfig>(ShaderStage::Mesh, &config);
- if (m_pipelineState->hasShaderStage(ShaderStageFragment)) {
- buildPsRegConfig<PipelineMeshFsRegConfig>(ShaderStageFragment, &config);
+ if (m_pipelineState->hasShaderStage(ShaderStage::Fragment)) {
+ buildPsRegConfig<PipelineMeshFsRegConfig>(ShaderStage::Fragment, &config);
- unsigned checksum = setShaderHash(ShaderStageFragment);
+ unsigned checksum = setShaderHash(ShaderStage::Fragment);
if (m_pipelineState->getTargetInfo().getGpuProperty().supportShaderPowerProfiling)
SET_REG_FIELD(&config.psRegs, SPI_SHADER_PGM_CHKSUM_PS, CHECKSUM, checksum);
} else {
@@ -818,25 +825,25 @@ void ConfigBuilder::buildPipelineTaskMeshFsConfig() {
PipelineTaskMeshFsRegConfig config(m_gfxIp);
- addApiHwShaderMapping(ShaderStageTask, Util::Abi::HwShaderCs);
- addApiHwShaderMapping(ShaderStageMesh, Util::Abi::HwShaderGs);
- addApiHwShaderMapping(ShaderStageFragment, Util::Abi::HwShaderPs);
+ addApiHwShaderMapping(ShaderStage::Task, Util::Abi::HwShaderCs);
+ addApiHwShaderMapping(ShaderStage::Mesh, Util::Abi::HwShaderGs);
+ addApiHwShaderMapping(ShaderStage::Fragment, Util::Abi::HwShaderPs);
setPipelineType(Util::Abi::PipelineType::TaskMesh);
// Must contain task shader
- assert(m_pipelineState->hasShaderStage(ShaderStageTask));
- buildCsRegConfig(ShaderStageTask, &config.taskRegs);
+ assert(m_pipelineState->hasShaderStage(ShaderStage::Task));
+ buildCsRegConfig(ShaderStage::Task, &config.taskRegs);
- if (m_pipelineState->hasShaderStage(ShaderStageMesh))
- buildMeshRegConfig<PipelineTaskMeshFsRegConfig>(ShaderStageMesh, &config);
+ if (m_pipelineState->hasShaderStage(ShaderStage::Mesh))
+ buildMeshRegConfig<PipelineTaskMeshFsRegConfig>(ShaderStage::Mesh, &config);
else
invalidRegConfig(config.meshRegs);
- if (m_pipelineState->hasShaderStage(ShaderStageFragment)) {
- buildPsRegConfig<PipelineTaskMeshFsRegConfig>(ShaderStageFragment, &config);
+ if (m_pipelineState->hasShaderStage(ShaderStage::Fragment)) {
+ buildPsRegConfig<PipelineTaskMeshFsRegConfig>(ShaderStage::Fragment, &config);
- unsigned checksum = setShaderHash(ShaderStageFragment);
+ unsigned checksum = setShaderHash(ShaderStage::Fragment);
if (m_pipelineState->getTargetInfo().getGpuProperty().supportShaderPowerProfiling)
SET_REG_FIELD(&config.psRegs, SPI_SHADER_PGM_CHKSUM_PS, CHECKSUM, checksum);
} else {
@@ -849,15 +856,15 @@ void ConfigBuilder::buildPipelineTaskMeshFsConfig() {
// =====================================================================================================================
// Builds register configuration for compute pipeline.
void ConfigBuilder::buildPipelineCsRegConfig() {
- assert(m_pipelineState->hasShaderStage(ShaderStageCompute));
+ assert(m_pipelineState->hasShaderStage(ShaderStage::Compute));
CsRegConfig config(m_gfxIp);
- addApiHwShaderMapping(ShaderStageCompute, Util::Abi::HwShaderCs);
+ addApiHwShaderMapping(ShaderStage::Compute, Util::Abi::HwShaderCs);
setPipelineType(Util::Abi::PipelineType::Cs);
- buildCsRegConfig(ShaderStageCompute, &config);
+ buildCsRegConfig(ShaderStage::Compute, &config);
appendConfig(config);
}
@@ -867,9 +874,9 @@ void ConfigBuilder::buildPipelineCsRegConfig() {
//
// @param shaderStage : Current shader stage (from API side)
// @param [out] config : Register configuration for vertex-shader-specific pipeline
-template <typename T> void ConfigBuilder::buildVsRegConfig(ShaderStage shaderStage, T *config) {
- assert(shaderStage == ShaderStageVertex || shaderStage == ShaderStageTessEval ||
- shaderStage == ShaderStageCopyShader);
+template <typename T> void ConfigBuilder::buildVsRegConfig(ShaderStageEnum shaderStage, T *config) {
+ assert(shaderStage == ShaderStage::Vertex || shaderStage == ShaderStage::TessEval ||
+ shaderStage == ShaderStage::CopyShader);
assert(m_gfxIp.major <= 10); // Must be GFX10 or below
@@ -886,7 +893,7 @@ template <typename T> void ConfigBuilder::buildVsRegConfig(ShaderStage shaderSta
const auto &streamXfbBuffers = m_pipelineState->getStreamXfbBuffers();
const bool enableXfb = m_pipelineState->enableXfb();
const bool enablePrimStats = m_pipelineState->enablePrimStats();
- if (shaderStage == ShaderStageCopyShader) {
+ if (shaderStage == ShaderStage::CopyShader) {
SET_REG_FIELD(&config->vsRegs, SPI_SHADER_PGM_RSRC2_VS, USER_SGPR, lgc::CopyShaderUserSgprCount);
setNumAvailSgprs(Util::Abi::HardwareStage::Vs, m_pipelineState->getTargetInfo().getGpuProperty().maxSgprsAvailable);
setNumAvailVgprs(Util::Abi::HardwareStage::Vs, m_pipelineState->getTargetInfo().getGpuProperty().maxVgprsAvailable);
@@ -939,13 +946,13 @@ template <typename T> void ConfigBuilder::buildVsRegConfig(ShaderStage shaderSta
SET_REG_GFX10_FIELD(&config->vsRegs, SPI_SHADER_PGM_RSRC1_VS, MEM_ORDERED, true);
}
- if (shaderStage == ShaderStageVertex) {
+ if (shaderStage == ShaderStage::Vertex) {
if (builtInUsage.vs.instanceIndex) {
SET_REG_FIELD(&config->vsRegs, SPI_SHADER_PGM_RSRC1_VS, VGPR_COMP_CNT, 3); // 3: Enable instance ID
} else if (builtInUsage.vs.primitiveId) {
SET_REG_FIELD(&config->vsRegs, SPI_SHADER_PGM_RSRC1_VS, VGPR_COMP_CNT, 2);
}
- } else if (shaderStage == ShaderStageTessEval) {
+ } else if (shaderStage == ShaderStage::TessEval) {
if (builtInUsage.tes.primitiveId) {
// NOTE: when primitive ID is used, set vgtCompCnt to 3 directly because primitive ID is the last VGPR.
SET_REG_FIELD(&config->vsRegs, SPI_SHADER_PGM_RSRC1_VS, VGPR_COMP_CNT, 3); // 3: Enable primitive ID
@@ -966,15 +973,15 @@ template <typename T> void ConfigBuilder::buildVsRegConfig(ShaderStage shaderSta
// @param shaderStage2 : Current second shader stage (from API side)
// @param [out] config : Register configuration for local-hull-shader-specific pipeline
template <typename T>
-void ConfigBuilder::buildLsHsRegConfig(ShaderStage shaderStage1, ShaderStage shaderStage2, T *config) {
- assert(shaderStage1 == ShaderStageVertex || shaderStage1 == ShaderStageInvalid);
- assert(shaderStage2 == ShaderStageTessControl || shaderStage2 == ShaderStageInvalid);
+void ConfigBuilder::buildLsHsRegConfig(ShaderStageEnum shaderStage1, ShaderStageEnum shaderStage2, T *config) {
+ assert(shaderStage1 == ShaderStage::Vertex || shaderStage1 == ShaderStage::Invalid);
+ assert(shaderStage2 == ShaderStage::TessControl || shaderStage2 == ShaderStage::Invalid);
- const auto tcsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl);
- const auto vsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageVertex);
+ const auto tcsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl);
+ const auto vsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Vertex);
const auto &vsBuiltInUsage = vsResUsage->builtInUsage.vs;
- unsigned floatMode = setupFloatingPointMode(shaderStage2 != ShaderStageInvalid ? shaderStage2 : shaderStage1);
+ unsigned floatMode = setupFloatingPointMode(shaderStage2 != ShaderStage::Invalid ? shaderStage2 : shaderStage1);
SET_REG_FIELD(&config->lsHsRegs, SPI_SHADER_PGM_RSRC1_HS, FLOAT_MODE, floatMode);
SET_REG_FIELD(&config->lsHsRegs, SPI_SHADER_PGM_RSRC1_HS, DX10_CLAMP, true); // Follow PAL setting
@@ -989,17 +996,17 @@ void ConfigBuilder::buildLsHsRegConfig(ShaderStage shaderStage1, ShaderStage sha
}
SET_REG_FIELD(&config->lsHsRegs, SPI_SHADER_PGM_RSRC1_HS, LS_VGPR_COMP_CNT, lsVgprCompCnt);
- const auto &vsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStageVertex);
- const auto &tcsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStageTessControl);
+ const auto &vsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStage::Vertex);
+ const auto &tcsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStage::TessControl);
unsigned userDataCount = std::max(vsIntfData->userDataCount, tcsIntfData->userDataCount);
- const auto &tcsShaderOptions = m_pipelineState->getShaderOptions(ShaderStageTessControl);
+ const auto &tcsShaderOptions = m_pipelineState->getShaderOptions(ShaderStage::TessControl);
SET_REG_FIELD(&config->lsHsRegs, SPI_SHADER_PGM_RSRC1_HS, DEBUG_MODE, tcsShaderOptions.debugMode);
const bool userSgprMsb = (userDataCount > 31);
if (m_gfxIp.major >= 10) {
- bool wgpMode = (m_pipelineState->getShaderWgpMode(ShaderStageVertex) ||
- m_pipelineState->getShaderWgpMode(ShaderStageTessControl));
+ bool wgpMode = (m_pipelineState->getShaderWgpMode(ShaderStage::Vertex) ||
+ m_pipelineState->getShaderWgpMode(ShaderStage::TessControl));
SET_REG_GFX10_PLUS_FIELD(&config->lsHsRegs, SPI_SHADER_PGM_RSRC1_HS, MEM_ORDERED, true);
SET_REG_GFX10_PLUS_FIELD(&config->lsHsRegs, SPI_SHADER_PGM_RSRC1_HS, WGP_MODE, wgpMode);
@@ -1065,23 +1072,23 @@ void ConfigBuilder::buildLsHsRegConfig(ShaderStage shaderStage1, ShaderStage sha
// @param shaderStage2 : Current second shader stage (from API side)
// @param [out] config : Register configuration for export-geometry-shader-specific pipeline
template <typename T>
-void ConfigBuilder::buildEsGsRegConfig(ShaderStage shaderStage1, ShaderStage shaderStage2, T *config) {
- assert(shaderStage1 == ShaderStageVertex || shaderStage1 == ShaderStageTessEval ||
- shaderStage1 == ShaderStageInvalid);
- assert(shaderStage2 == ShaderStageGeometry || shaderStage2 == ShaderStageInvalid);
+void ConfigBuilder::buildEsGsRegConfig(ShaderStageEnum shaderStage1, ShaderStageEnum shaderStage2, T *config) {
+ assert(shaderStage1 == ShaderStage::Vertex || shaderStage1 == ShaderStage::TessEval ||
+ shaderStage1 == ShaderStage::Invalid);
+ assert(shaderStage2 == ShaderStage::Geometry || shaderStage2 == ShaderStage::Invalid);
assert(m_gfxIp.major <= 10); // Must be GFX10 or below
- const bool hasTs =
- m_pipelineState->hasShaderStage(ShaderStageTessControl) || m_pipelineState->hasShaderStage(ShaderStageTessEval);
+ const bool hasTs = m_pipelineState->hasShaderStage(ShaderStage::TessControl) ||
+ m_pipelineState->hasShaderStage(ShaderStage::TessEval);
- const auto vsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageVertex);
+ const auto vsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Vertex);
const auto &vsBuiltInUsage = vsResUsage->builtInUsage.vs;
- const auto tesResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessEval);
+ const auto tesResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessEval);
const auto &tesBuiltInUsage = tesResUsage->builtInUsage.tes;
- const auto gsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry);
+ const auto gsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry);
const auto &gsBuiltInUsage = gsResUsage->builtInUsage.gs;
const auto &geometryMode = m_pipelineState->getShaderModes()->getGeometryShaderMode();
const auto &gsInOutUsage = gsResUsage->inOutUsage;
@@ -1097,23 +1104,23 @@ void ConfigBuilder::buildEsGsRegConfig(ShaderStage shaderStage1, ShaderStage sha
SET_REG_FIELD(&config->esGsRegs, SPI_SHADER_PGM_RSRC1_GS, GS_VGPR_COMP_CNT, gsVgprCompCnt);
- unsigned floatMode = setupFloatingPointMode(shaderStage2 != ShaderStageInvalid ? shaderStage2 : shaderStage1);
+ unsigned floatMode = setupFloatingPointMode(shaderStage2 != ShaderStage::Invalid ? shaderStage2 : shaderStage1);
SET_REG_FIELD(&config->esGsRegs, SPI_SHADER_PGM_RSRC1_GS, FLOAT_MODE, floatMode);
SET_REG_FIELD(&config->esGsRegs, SPI_SHADER_PGM_RSRC1_GS, DX10_CLAMP, true); // Follow PAL setting
- const auto vsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStageVertex);
- const auto tesIntfData = m_pipelineState->getShaderInterfaceData(ShaderStageTessEval);
- const auto gsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStageGeometry);
+ const auto vsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStage::Vertex);
+ const auto tesIntfData = m_pipelineState->getShaderInterfaceData(ShaderStage::TessEval);
+ const auto gsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStage::Geometry);
unsigned userDataCount =
std::max((hasTs ? tesIntfData->userDataCount : vsIntfData->userDataCount), gsIntfData->userDataCount);
- const auto &gsShaderOptions = m_pipelineState->getShaderOptions(ShaderStageGeometry);
+ const auto &gsShaderOptions = m_pipelineState->getShaderOptions(ShaderStage::Geometry);
SET_REG_FIELD(&config->esGsRegs, SPI_SHADER_PGM_RSRC1_GS, DEBUG_MODE, gsShaderOptions.debugMode);
const bool userSgprMsb = (userDataCount > 31);
if (m_gfxIp.major == 10) {
- bool wgpMode = m_pipelineState->getShaderWgpMode(hasTs ? ShaderStageTessEval : ShaderStageVertex) ||
- m_pipelineState->getShaderWgpMode(ShaderStageGeometry);
+ bool wgpMode = m_pipelineState->getShaderWgpMode(hasTs ? ShaderStage::TessEval : ShaderStage::Vertex) ||
+ m_pipelineState->getShaderWgpMode(ShaderStage::Geometry);
SET_REG_GFX10_PLUS_FIELD(&config->esGsRegs, SPI_SHADER_PGM_RSRC1_GS, MEM_ORDERED, true);
SET_REG_GFX10_PLUS_FIELD(&config->esGsRegs, SPI_SHADER_PGM_RSRC1_GS, WGP_MODE, wgpMode);
@@ -1257,27 +1264,27 @@ void ConfigBuilder::buildEsGsRegConfig(ShaderStage shaderStage1, ShaderStage sha
// @param shaderStage2 : Current second shader stage (from API side)
// @param [out] config : Register configuration for primitive-shader-specific pipeline
template <typename T>
-void ConfigBuilder::buildPrimShaderRegConfig(ShaderStage shaderStage1, ShaderStage shaderStage2, T *config) {
- assert(shaderStage1 == ShaderStageVertex || shaderStage1 == ShaderStageTessEval ||
- shaderStage1 == ShaderStageInvalid);
- assert(shaderStage2 == ShaderStageGeometry || shaderStage2 == ShaderStageInvalid);
+void ConfigBuilder::buildPrimShaderRegConfig(ShaderStageEnum shaderStage1, ShaderStageEnum shaderStage2, T *config) {
+ assert(shaderStage1 == ShaderStage::Vertex || shaderStage1 == ShaderStage::TessEval ||
+ shaderStage1 == ShaderStage::Invalid);
+ assert(shaderStage2 == ShaderStage::Geometry || shaderStage2 == ShaderStage::Invalid);
assert(m_gfxIp.major >= 10); // Must be GFX10 or above
const auto nggControl = m_pipelineState->getNggControl();
assert(nggControl->enableNgg);
- const bool hasTs =
- m_pipelineState->hasShaderStage(ShaderStageTessControl) || m_pipelineState->hasShaderStage(ShaderStageTessEval);
- const bool hasGs = m_pipelineState->hasShaderStage(ShaderStageGeometry);
+ const bool hasTs = m_pipelineState->hasShaderStage(ShaderStage::TessControl) ||
+ m_pipelineState->hasShaderStage(ShaderStage::TessEval);
+ const bool hasGs = m_pipelineState->hasShaderStage(ShaderStage::Geometry);
- const auto vsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageVertex);
+ const auto vsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Vertex);
const auto &vsBuiltInUsage = vsResUsage->builtInUsage.vs;
- const auto tesResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessEval);
+ const auto tesResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessEval);
const auto &tesBuiltInUsage = tesResUsage->builtInUsage.tes;
- const auto gsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry);
+ const auto gsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry);
const auto &gsBuiltInUsage = gsResUsage->builtInUsage.gs;
const auto &geometryMode = m_pipelineState->getShaderModes()->getGeometryShaderMode();
const auto &gsInOutUsage = gsResUsage->inOutUsage;
@@ -1307,20 +1314,20 @@ void ConfigBuilder::buildPrimShaderRegConfig(ShaderStage shaderStage1, ShaderSta
}
SET_REG_FIELD(&config->primShaderRegs, SPI_SHADER_PGM_RSRC1_GS, GS_VGPR_COMP_CNT, gsVgprCompCnt);
- unsigned floatMode = setupFloatingPointMode(shaderStage2 != ShaderStageInvalid ? shaderStage2 : shaderStage1);
+ unsigned floatMode = setupFloatingPointMode(shaderStage2 != ShaderStage::Invalid ? shaderStage2 : shaderStage1);
SET_REG_FIELD(&config->primShaderRegs, SPI_SHADER_PGM_RSRC1_GS, FLOAT_MODE, floatMode);
SET_REG_FIELD(&config->primShaderRegs, SPI_SHADER_PGM_RSRC1_GS, DX10_CLAMP, true); // Follow PAL setting
- const auto vsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStageVertex);
- const auto tesIntfData = m_pipelineState->getShaderInterfaceData(ShaderStageTessEval);
- const auto gsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStageGeometry);
+ const auto vsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStage::Vertex);
+ const auto tesIntfData = m_pipelineState->getShaderInterfaceData(ShaderStage::TessEval);
+ const auto gsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStage::Geometry);
unsigned userDataCount =
std::max((hasTs ? tesIntfData->userDataCount : vsIntfData->userDataCount), gsIntfData->userDataCount);
- const auto &gsShaderOptions = m_pipelineState->getShaderOptions(ShaderStageGeometry);
- bool wgpMode = m_pipelineState->getShaderWgpMode(hasTs ? ShaderStageTessEval : ShaderStageVertex);
+ const auto &gsShaderOptions = m_pipelineState->getShaderOptions(ShaderStage::Geometry);
+ bool wgpMode = m_pipelineState->getShaderWgpMode(hasTs ? ShaderStage::TessEval : ShaderStage::Vertex);
if (hasGs)
- wgpMode = (wgpMode || m_pipelineState->getShaderWgpMode(ShaderStageGeometry));
+ wgpMode = (wgpMode || m_pipelineState->getShaderWgpMode(ShaderStage::Geometry));
SET_REG_FIELD(&config->primShaderRegs, SPI_SHADER_PGM_RSRC1_GS, DEBUG_MODE, gsShaderOptions.debugMode);
SET_REG_GFX10_PLUS_FIELD(&config->primShaderRegs, SPI_SHADER_PGM_RSRC1_GS, MEM_ORDERED, true);
@@ -1523,8 +1530,8 @@ void ConfigBuilder::buildPrimShaderRegConfig(ShaderStage shaderStage1, ShaderSta
//
// @param shaderStage : Current shader stage (from API side)
// @param [out] config : Register configuration for pixel-shader-specific pipeline
-template <typename T> void ConfigBuilder::buildPsRegConfig(ShaderStage shaderStage, T *config) {
- assert(shaderStage == ShaderStageFragment);
+template <typename T> void ConfigBuilder::buildPsRegConfig(ShaderStageEnum shaderStage, T *config) {
+ assert(shaderStage == ShaderStage::Fragment);
const auto intfData = m_pipelineState->getShaderInterfaceData(shaderStage);
const auto &options = m_pipelineState->getOptions();
@@ -1746,8 +1753,8 @@ template <typename T> void ConfigBuilder::buildPsRegConfig(ShaderStage shaderSta
//
// @param shaderStage : Current shader stage (from API side)
// @param [out] config : Register configuration for mesh-shader-specific pipeline
-template <typename T> void ConfigBuilder::buildMeshRegConfig(ShaderStage shaderStage, T *config) {
- assert(shaderStage == ShaderStageMesh);
+template <typename T> void ConfigBuilder::buildMeshRegConfig(ShaderStageEnum shaderStage, T *config) {
+ assert(shaderStage == ShaderStage::Mesh);
assert(m_gfxIp >= GfxIpVersion({10, 3})); // Must be GFX10.3+
@@ -1757,7 +1764,7 @@ template <typename T> void ConfigBuilder::buildMeshRegConfig(ShaderStage shaderS
const auto &builtInUsage = resUsage->builtInUsage.mesh;
const auto &meshMode = m_pipelineState->getShaderModes()->getMeshShaderMode();
- const auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->inOutUsage.gs.calcFactor;
+ const auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->inOutUsage.gs.calcFactor;
SET_REG_FIELD(&config->meshRegs, VGT_SHADER_STAGES_EN, MAX_PRIMGRP_IN_WAVE, 2);
@@ -1888,7 +1895,7 @@ template <typename T> void ConfigBuilder::buildMeshRegConfig(ShaderStage shaderS
setNumAvailSgprs(Util::Abi::HardwareStage::Gs, resUsage->numSgprsAvailable);
setNumAvailVgprs(Util::Abi::HardwareStage::Gs, resUsage->numVgprsAvailable);
- const unsigned checksum = setShaderHash(ShaderStageMesh);
+ const unsigned checksum = setShaderHash(ShaderStage::Mesh);
if (m_pipelineState->getTargetInfo().getGpuProperty().supportShaderPowerProfiling)
SET_REG_FIELD(&config->meshRegs, SPI_SHADER_PGM_CHKSUM_GS, CHECKSUM, checksum);
@@ -1908,8 +1915,8 @@ template <typename T> void ConfigBuilder::buildMeshRegConfig(ShaderStage shaderS
//
// @param shaderStage : Current shader stage (from API side)
// @param [out] config : Register configuration for compute
-void ConfigBuilder::buildCsRegConfig(ShaderStage shaderStage, CsRegConfig *config) {
- assert(shaderStage == ShaderStageCompute || shaderStage == ShaderStageTask);
+void ConfigBuilder::buildCsRegConfig(ShaderStageEnum shaderStage, CsRegConfig *config) {
+ assert(shaderStage == ShaderStage::Compute || shaderStage == ShaderStage::Task);
const auto intfData = m_pipelineState->getShaderInterfaceData(shaderStage);
const auto &shaderOptions = m_pipelineState->getShaderOptions(shaderStage);
@@ -1917,7 +1924,7 @@ void ConfigBuilder::buildCsRegConfig(ShaderStage shaderStage, CsRegConfig *confi
const auto &computeMode = m_pipelineState->getShaderModes()->getComputeShaderMode();
unsigned workgroupSizes[3] = {};
- if (shaderStage == ShaderStageCompute) {
+ if (shaderStage == ShaderStage::Compute) {
const auto &builtInUsage = resUsage->builtInUsage.cs;
if (builtInUsage.foldWorkgroupXY) {
workgroupSizes[0] = computeMode.workgroupSizeX * computeMode.workgroupSizeY;
@@ -1929,7 +1936,7 @@ void ConfigBuilder::buildCsRegConfig(ShaderStage shaderStage, CsRegConfig *confi
workgroupSizes[2] = computeMode.workgroupSizeZ;
}
} else {
- assert(shaderStage == ShaderStageTask);
+ assert(shaderStage == ShaderStage::Task);
workgroupSizes[0] = computeMode.workgroupSizeX;
workgroupSizes[1] = computeMode.workgroupSizeY;
workgroupSizes[2] = computeMode.workgroupSizeZ;
@@ -2056,11 +2063,11 @@ void ConfigBuilder::setupVgtTfParam(LsHsRegConfig *config) {
//
// @param [out] config : Register configuration
template <typename T> void ConfigBuilder::setupPaSpecificRegisters(T *config) {
- const bool hasTs =
- m_pipelineState->hasShaderStage(ShaderStageTessControl) || m_pipelineState->hasShaderStage(ShaderStageTessEval);
- const bool hasGs = m_pipelineState->hasShaderStage(ShaderStageGeometry);
+ const bool hasTs = m_pipelineState->hasShaderStage(ShaderStage::TessControl) ||
+ m_pipelineState->hasShaderStage(ShaderStage::TessEval);
+ const bool hasGs = m_pipelineState->hasShaderStage(ShaderStage::Geometry);
const bool meshPipeline =
- m_pipelineState->hasShaderStage(ShaderStageTask) || m_pipelineState->hasShaderStage(ShaderStageMesh);
+ m_pipelineState->hasShaderStage(ShaderStage::Task) || m_pipelineState->hasShaderStage(ShaderStage::Mesh);
bool rasterizerDiscardEnable = m_pipelineState->getRasterizerState().rasterizerDiscardEnable;
SET_REG_FIELD(config, PA_CL_CLIP_CNTL, DX_LINEAR_ATTR_CLIP_ENA, true);
@@ -2094,7 +2101,7 @@ template <typename T> void ConfigBuilder::setupPaSpecificRegisters(T *config) {
// Mesh pipeline
assert(m_gfxIp >= GfxIpVersion({10, 3})); // Must be GFX10.3+
- const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageMesh);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Mesh);
const auto &builtInUsage = resUsage->builtInUsage.mesh;
usePointSize = builtInUsage.pointSize;
@@ -2110,7 +2117,7 @@ template <typename T> void ConfigBuilder::setupPaSpecificRegisters(T *config) {
bool usePrimitiveId = false;
if (hasGs) {
- const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry);
const auto &builtInUsage = resUsage->builtInUsage.gs;
usePointSize = builtInUsage.pointSize;
@@ -2125,14 +2132,14 @@ template <typename T> void ConfigBuilder::setupPaSpecificRegisters(T *config) {
// NOTE: For ES-GS merged shader, the actual use of primitive ID should take both ES and GS into consideration.
if (hasTs) {
- const auto &tesBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessEval)->builtInUsage.tes;
+ const auto &tesBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessEval)->builtInUsage.tes;
usePrimitiveId = usePrimitiveId || tesBuiltInUsage.primitiveId;
} else {
- const auto &vsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageVertex)->builtInUsage.vs;
+ const auto &vsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Vertex)->builtInUsage.vs;
usePrimitiveId = usePrimitiveId || vsBuiltInUsage.primitiveId;
}
} else if (hasTs) {
- const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessEval);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessEval);
const auto &builtInUsage = resUsage->builtInUsage.tes;
usePointSize = builtInUsage.pointSize;
@@ -2143,7 +2150,7 @@ template <typename T> void ConfigBuilder::setupPaSpecificRegisters(T *config) {
expCount = resUsage->inOutUsage.expCount;
} else {
- const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageVertex);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Vertex);
const auto &builtInUsage = resUsage->builtInUsage.vs;
usePointSize = builtInUsage.pointSize;
diff --git a/lgc/patch/Gfx9ConfigBuilder.h b/lgc/patch/Gfx9ConfigBuilder.h
index 8a30ec303d..28d0b6bdde 100644
--- a/lgc/patch/Gfx9ConfigBuilder.h
+++ b/lgc/patch/Gfx9ConfigBuilder.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -65,13 +65,14 @@ class ConfigBuilder : public ConfigBuilderBase {
ConfigBuilder(const ConfigBuilder &) = delete;
ConfigBuilder &operator=(const ConfigBuilder &) = delete;
- template <typename T> void buildVsRegConfig(ShaderStage shaderStage, T *config);
- template <typename T> void buildLsHsRegConfig(ShaderStage shaderStage1, ShaderStage shaderStage2, T *config);
- template <typename T> void buildEsGsRegConfig(ShaderStage shaderStage1, ShaderStage shaderStage2, T *config);
- template <typename T> void buildPrimShaderRegConfig(ShaderStage shaderStage1, ShaderStage shaderStage2, T *config);
- template <typename T> void buildPsRegConfig(ShaderStage shaderStage, T *config);
- template <typename T> void buildMeshRegConfig(ShaderStage shaderStage, T *config);
- void buildCsRegConfig(ShaderStage shaderStage, CsRegConfig *config);
+ template <typename T> void buildVsRegConfig(ShaderStageEnum shaderStage, T *config);
+ template <typename T> void buildLsHsRegConfig(ShaderStageEnum shaderStage1, ShaderStageEnum shaderStage2, T *config);
+ template <typename T> void buildEsGsRegConfig(ShaderStageEnum shaderStage1, ShaderStageEnum shaderStage2, T *config);
+ template <typename T>
+ void buildPrimShaderRegConfig(ShaderStageEnum shaderStage1, ShaderStageEnum shaderStage2, T *config);
+ template <typename T> void buildPsRegConfig(ShaderStageEnum shaderStage, T *config);
+ template <typename T> void buildMeshRegConfig(ShaderStageEnum shaderStage, T *config);
+ void buildCsRegConfig(ShaderStageEnum shaderStage, CsRegConfig *config);
void setupVgtTfParam(LsHsRegConfig *config);
template <typename T> void setupPaSpecificRegisters(T *config);
diff --git a/lgc/patch/LowerCooperativeMatrix.cpp b/lgc/patch/LowerCooperativeMatrix.cpp
index 599fd0f04a..d8c23464da 100644
--- a/lgc/patch/LowerCooperativeMatrix.cpp
+++ b/lgc/patch/LowerCooperativeMatrix.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -76,13 +76,13 @@ bool LowerCooperativeMatrix::runImpl(Module &module, PipelineShadersResult &pipe
Patch::init(&module);
m_pipelineState = pipelineState;
m_pipelineShaders = &pipelineShaders;
- m_shaderStage = ShaderStageCompute;
+ m_shaderStage = ShaderStage::Compute;
m_gfxIp = m_pipelineState->getTargetInfo().getGfxIpVersion();
SmallVector<Function *, 16> lowerCoopMatrixCallees;
for (auto &func : module) {
auto name = func.getName();
- if (name.startswith(lgcName::CooperativeMatrix))
+ if (name.starts_with(lgcName::CooperativeMatrix))
lowerCoopMatrixCallees.push_back(&func);
}
if (lowerCoopMatrixCallees.empty())
@@ -127,11 +127,11 @@ void LowerCooperativeMatrix::visitCallInst(CallInst &callInst) {
builder.SetInsertPoint(&callInst);
auto mangledName = callee->getName();
- if (mangledName.startswith(lgcName::CooperativeMatrixLength)) {
+ if (mangledName.starts_with(lgcName::CooperativeMatrixLength)) {
auto layout =
static_cast<Builder::CooperativeMatrixLayout>(cast<ConstantInt>(callInst.getOperand(1))->getZExtValue());
callInst.replaceAllUsesWith(builder.getInt32(getLength(layout)));
- } else if (mangledName.startswith(lgcName::CooperativeMatrixExtract)) {
+ } else if (mangledName.starts_with(lgcName::CooperativeMatrixExtract)) {
Value *matrix = callInst.getOperand(0);
Value *index = callInst.getOperand(1);
auto elemType =
@@ -141,7 +141,7 @@ void LowerCooperativeMatrix::visitCallInst(CallInst &callInst) {
Value *result = cooperativeMatrixExtract(builder, matrix, index, elemType, layout);
result->takeName(&callInst);
callInst.replaceAllUsesWith(result);
- } else if (mangledName.startswith(lgcName::CooperativeMatrixInsert)) {
+ } else if (mangledName.starts_with(lgcName::CooperativeMatrixInsert)) {
Value *matrix = callInst.getOperand(0);
Value *value = callInst.getOperand(1);
Value *index = callInst.getOperand(2);
@@ -152,7 +152,16 @@ void LowerCooperativeMatrix::visitCallInst(CallInst &callInst) {
Value *result = cooperativeMatrixInsert(builder, matrix, value, index, elemType, layout);
result->takeName(&callInst);
callInst.replaceAllUsesWith(result);
- } else if (mangledName.startswith(lgcName::CooperativeMatrixLoad)) {
+ } else if (mangledName.starts_with(lgcName::CooperativeMatrixFill)) {
+ Value *value = callInst.getOperand(0);
+ auto elemType =
+ static_cast<Builder::CooperativeMatrixElementType>(cast<ConstantInt>(callInst.getOperand(1))->getZExtValue());
+ auto layout =
+ static_cast<Builder::CooperativeMatrixLayout>(cast<ConstantInt>(callInst.getOperand(2))->getZExtValue());
+ Value *result = cooperativeMatrixFill(builder, value, elemType, layout);
+ result->takeName(&callInst);
+ callInst.replaceAllUsesWith(result);
+ } else if (mangledName.starts_with(lgcName::CooperativeMatrixLoad)) {
Value *dataPtr = callInst.getOperand(0);
Value *stride = callInst.getOperand(1);
bool colMajor = cast<ConstantInt>(callInst.getOperand(2))->getZExtValue();
@@ -166,7 +175,7 @@ void LowerCooperativeMatrix::visitCallInst(CallInst &callInst) {
callInst.getName(), &callInst);
callInst.replaceAllUsesWith(loadVal);
- } else if (mangledName.startswith(lgcName::CooperativeMatrixStore)) {
+ } else if (mangledName.starts_with(lgcName::CooperativeMatrixStore)) {
Value *dataPtr = callInst.getOperand(0);
Value *stride = callInst.getOperand(1);
bool colMajor = cast<ConstantInt>(callInst.getOperand(2))->getZExtValue();
@@ -180,7 +189,7 @@ void LowerCooperativeMatrix::visitCallInst(CallInst &callInst) {
cooperativeMatrixStoreInternal(dataPtr, stride, colMajor, elemType, layout, memoryAccess, vecVal,
callInst.getName(), &callInst);
- } else if (mangledName.startswith(lgcName::CooperativeMatrixConvert)) {
+ } else if (mangledName.starts_with(lgcName::CooperativeMatrixConvert)) {
CastInst::CastOps castOp =
static_cast<CastInst::CastOps>(cast<ConstantInt>(callInst.getOperand(0))->getZExtValue());
Value *source = callInst.getOperand(1);
@@ -204,7 +213,7 @@ void LowerCooperativeMatrix::visitCallInst(CallInst &callInst) {
}
callInst.replaceAllUsesWith(resultVal);
- } else if (mangledName.startswith(lgcName::CooperativeMatrixTranspose)) {
+ } else if (mangledName.starts_with(lgcName::CooperativeMatrixTranspose)) {
Value *matrix = callInst.getOperand(0);
Builder::CooperativeMatrixElementType elemType =
static_cast<Builder::CooperativeMatrixElementType>(cast<ConstantInt>(callInst.getOperand(1))->getZExtValue());
@@ -214,7 +223,7 @@ void LowerCooperativeMatrix::visitCallInst(CallInst &callInst) {
Value *resultVal = cooperativeMatrixTranspose(matrix, elemType, srcLayout, callInst.getName(), &callInst);
callInst.replaceAllUsesWith(resultVal);
- } else if (mangledName.startswith(lgcName::CooperativeMatrixBinOp)) {
+ } else if (mangledName.starts_with(lgcName::CooperativeMatrixBinOp)) {
Builder::CooperativeMatrixArithOp coopMatArithOp =
static_cast<Builder::CooperativeMatrixArithOp>(cast<ConstantInt>(callInst.getOperand(0))->getZExtValue());
Value *lhs = callInst.getOperand(1);
@@ -228,7 +237,7 @@ void LowerCooperativeMatrix::visitCallInst(CallInst &callInst) {
cooperativeMatrixBinaryOp(coopMatArithOp, lhs, rhs, elemType, srcLayout, callInst.getName(), &callInst);
callInst.replaceAllUsesWith(resultVal);
- } else if (mangledName.startswith(lgcName::CooperativeMatrixTimesScalar)) {
+ } else if (mangledName.starts_with(lgcName::CooperativeMatrixTimesScalar)) {
Value *matrix = callInst.getOperand(0);
Value *scalar = callInst.getOperand(1);
Builder::CooperativeMatrixElementType elemType =
@@ -239,7 +248,7 @@ void LowerCooperativeMatrix::visitCallInst(CallInst &callInst) {
Value *resultVal = coopMatrixTimesScalar(matrix, scalar, elemType, srcLayout, callInst.getName(), &callInst);
callInst.replaceAllUsesWith(resultVal);
- } else if (mangledName.startswith(lgcName::CooperativeMatrixMulAdd)) {
+ } else if (mangledName.starts_with(lgcName::CooperativeMatrixMulAdd)) {
Value *matrixA = callInst.getOperand(0);
Value *matrixB = callInst.getOperand(1);
Value *matrixC = callInst.getOperand(2);
@@ -254,12 +263,12 @@ void LowerCooperativeMatrix::visitCallInst(CallInst &callInst) {
Value *resultVal = cooperativeMatrixMulAdd(matrixA, matrixB, matrixC, isSignedA, isSignedB, isSatOrOpsel, isTied,
accumElemType, factorElemType, callInst.getName(), &callInst);
callInst.replaceAllUsesWith(resultVal);
- } else if (mangledName.startswith(lgcName::CooperativeMatrixPack)) {
+ } else if (mangledName.starts_with(lgcName::CooperativeMatrixPack)) {
Value *matrixA = callInst.getOperand(0);
Value *matrixB = callInst.getOperand(1);
Value *resultVal = cooperativeMatrixPack(matrixA, matrixB, callInst.getName(), &callInst);
callInst.replaceAllUsesWith(resultVal);
- } else if (mangledName.startswith(lgcName::CooperativeMatrixUnpack)) {
+ } else if (mangledName.starts_with(lgcName::CooperativeMatrixUnpack)) {
Value *packedMatrix = callInst.getOperand(0);
bool high = cast<ConstantInt>(callInst.getOperand(1))->getZExtValue();
Value *resultVal = cooperativeMatrixUnpack(packedMatrix, high, callInst.getName(), &callInst);
@@ -476,7 +485,8 @@ Value *LowerCooperativeMatrix::cooperativeMatrixLoadInternal(Value *dataPtr, Val
BuilderBase builder(*m_context);
builder.SetInsertPoint(insertPos);
- auto waveSize = m_pipelineState->getShaderWaveSize(getShaderStage(builder.GetInsertBlock()->getParent()));
+ auto shaderStage = getShaderStage(builder.GetInsertBlock()->getParent());
+ auto waveSize = m_pipelineState->getShaderWaveSize(shaderStage.value());
assert(waveSize == 32 || waveSize == 64);
// Calc element offset in memory
@@ -538,7 +548,8 @@ void LowerCooperativeMatrix::cooperativeMatrixStoreInternal(Value *dataPtr, Valu
BuilderBase builder(*m_context);
builder.SetInsertPoint(insertPos);
- auto waveSize = m_pipelineState->getShaderWaveSize(getShaderStage(builder.GetInsertBlock()->getParent()));
+ auto shaderStage = getShaderStage(builder.GetInsertBlock()->getParent());
+ auto waveSize = m_pipelineState->getShaderWaveSize(shaderStage.value());
assert(waveSize == 32 || waveSize == 64);
// Calc element offset in memory
@@ -631,6 +642,26 @@ Value *LowerCooperativeMatrix::cooperativeMatrixInsert(BuilderCommon &builder, V
return convFlatVecToCoopMatrixVec(builder, vec, elemType, layout);
}
+// =====================================================================================================================
+// Open-code cooperative matrix fill operation
+//
+// @param builder : builder to use
+// @param value : the value to fill the cooperative matrix
+// @param elemType : the matrix element type
+// @param layout : the matrix layout type
+Value *LowerCooperativeMatrix::cooperativeMatrixFill(BuilderCommon &builder, Value *value,
+ Builder::CooperativeMatrixElementType elemType,
+ Builder::CooperativeMatrixLayout layout) {
+ auto props = getTypeProperties(elemType, layout);
+ Type *flatType = FixedVectorType::get(builder.transCooperativeMatrixElementType(elemType), props.numMatrixElements);
+
+ Value *vec = PoisonValue::get(flatType);
+ for (unsigned idx = 0; idx < props.numMatrixElements; idx++)
+ vec = builder.CreateInsertElement(vec, value, idx);
+
+ return convFlatVecToCoopMatrixVec(builder, vec, elemType, layout);
+}
+
// =====================================================================================================================
// Create cooperative matrix conversion without any reshape operations
// Element-wise-conversion
diff --git a/lgc/patch/LowerDebugPrintf.cpp b/lgc/patch/LowerDebugPrintf.cpp
index 3466106602..7de0ef8752 100644
--- a/lgc/patch/LowerDebugPrintf.cpp
+++ b/lgc/patch/LowerDebugPrintf.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/patch/LowerDesc.cpp b/lgc/patch/LowerDesc.cpp
new file mode 100644
index 0000000000..7550d17a83
--- /dev/null
+++ b/lgc/patch/LowerDesc.cpp
@@ -0,0 +1,88 @@
+/*
+ ***********************************************************************************************************************
+ *
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ **********************************************************************************************************************/
+/**
+ ***********************************************************************************************************************
+ * @file LowerDesc.cpp
+ * @brief LLPC source file: contains implementation of class lgc::LowerDesc.
+ ***********************************************************************************************************************
+ */
+#include "lgc/patch/LowerDesc.h"
+#include "lgc/LgcDialect.h"
+#include "lgc/builder/BuilderImpl.h"
+#include "llvm-dialects/Dialect/Visitor.h"
+#include "llvm/Support/Debug.h"
+
+#define DEBUG_TYPE "lower-desc"
+
+using namespace llvm;
+using namespace lgc;
+
+namespace lgc {
+
+// =====================================================================================================================
+// Executes this LLVM patching pass on the specified LLVM module.
+//
+// @param [in/out] module : LLVM module to be run on
+// @param [in/out] analysisManager : Analysis manager to use for this transformation
+// @returns : The preserved analyses (The analyses that are still valid after this pass)
+PreservedAnalyses LowerDesc::run(Module &module, ModuleAnalysisManager &analysisManager) {
+ LLVM_DEBUG(dbgs() << "Run the pass " DEBUG_TYPE "\n");
+ PipelineState *pipelineState = analysisManager.getResult<PipelineStateWrapper>(module).getPipelineState();
+ m_pipelineState = pipelineState;
+
+ static const auto visitor = llvm_dialects::VisitorBuilder<LowerDesc>().add(&LowerDesc::visitLoadBufferDesc).build();
+
+ visitor.visit(*this, module);
+
+ for (auto inst : m_toErase)
+ inst->eraseFromParent();
+
+ if (m_toErase.empty())
+ return PreservedAnalyses::all();
+ return PreservedAnalyses::allInSet<CFGAnalyses>();
+}
+
+// =====================================================================================================================
+// Lower a load.buffer.desc operation
+//
+// @param op : the operation
+void LowerDesc::visitLoadBufferDesc(LoadBufferDescOp &op) {
+ BuilderImpl builder(m_pipelineState);
+ builder.setShaderStage(getShaderStage(op.getFunction()));
+ builder.SetInsertPoint(&op);
+
+ unsigned flags = op.getFlags();
+ // Anyone who wants to get a 64-bit buffer descriptor address should call `CreateBufferDesc` directly. (This is only
+ // available in LGC as we don't expect front-end would required such usage.)
+ assert(!(flags & Builder::BufferFlagAddress) && "Returning a 64-bit address is unsupported by lgc.load.buffer.desc");
+
+ Value *desc = builder.CreateBufferDesc(op.getDescSet(), op.getBinding(), op.getDescIndex(), flags);
+
+ m_toErase.push_back(&op);
+
+ // Convert to fat pointer.
+ op.replaceAllUsesWith(builder.create<BufferDescToPtrOp>(desc));
+}
+} // namespace lgc
diff --git a/lgc/patch/LowerGpuRt.cpp b/lgc/patch/LowerGpuRt.cpp
index 5cd63ea07f..b551128b6c 100644
--- a/lgc/patch/LowerGpuRt.cpp
+++ b/lgc/patch/LowerGpuRt.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -75,6 +75,7 @@ PreservedAnalyses LowerGpuRt::run(Module &module, ModuleAnalysisManager &analysi
.add(&LowerGpuRt::visitGetStaticFlags)
.add(&LowerGpuRt::visitGetTriangleCompressionMode)
.add(&LowerGpuRt::visitGetFlattenedGroupThreadId)
+ .add(&LowerGpuRt::visitFloatWithRoundMode)
.build();
visitor.visit(*this, module);
@@ -116,9 +117,15 @@ unsigned LowerGpuRt::getWorkgroupSize() const {
// =====================================================================================================================
// Get flat thread id in work group/wave
Value *LowerGpuRt::getThreadIdInGroup() const {
- // Todo: for graphics shader, subgroupId * waveSize + subgroupLocalInvocationId()
- unsigned builtIn = m_pipelineState->isGraphics() ? BuiltInSubgroupLocalInvocationId : BuiltInLocalInvocationIndex;
- return m_builder->CreateReadBuiltInInput(static_cast<BuiltInKind>(builtIn));
+ auto stage = getShaderStage(m_builder->GetInsertBlock()->getParent());
+
+ Value *laneId = m_builder->CreateReadBuiltInInput(BuiltInSubgroupLocalInvocationId, {}, nullptr, nullptr);
+ if (stage != ShaderStage::Compute && stage != ShaderStage::Task && stage != ShaderStage::Mesh)
+ return laneId;
+
+ Value *waveId = m_builder->CreateReadBuiltInInput(BuiltInSubgroupId, {}, nullptr, nullptr);
+ Value *tmp = m_builder->CreateMul(waveId, m_builder->getInt32(m_pipelineState->getShaderWaveSize(stage.value())));
+ return m_builder->CreateAdd(tmp, laneId);
}
// =====================================================================================================================
@@ -281,6 +288,53 @@ void LowerGpuRt::visitLdsStackInit(GpurtLdsStackInitOp &inst) {
m_funcsToLower.insert(inst.getCalledFunction());
}
+// =====================================================================================================================
+// Visit "GpurtFloatWithRoundModeOp" instruction
+//
+// @param inst : The dialect instruction to process
+void LowerGpuRt::visitFloatWithRoundMode(lgc::GpurtFloatWithRoundModeOp &inst) {
+ m_builder->SetInsertPoint(&inst);
+
+ // Use setReg to set SQ_WAVE_MODE.
+ // hwRegId : SQ related register index.
+ // Offset : register field offset.
+ // Width : field width.
+ // hwReg : (hwRegId | (Offset << 6) | ((Width - 1) << 11)
+ constexpr uint32_t sqHwRegMode = 1;
+ constexpr uint32_t width = 2;
+ constexpr uint32_t offset = 0;
+ uint32_t hwReg = ((sqHwRegMode) | (offset << 6) | ((width - 1) << 11));
+
+ enum OperationType : uint32_t { Add = 0, Sub, Mul };
+ auto func = inst.getCalledFunction();
+ auto retType = cast<FixedVectorType>(func->getReturnType());
+ Value *src0 = inst.getSrc0();
+ Value *src1 = inst.getSrc1();
+ uint32_t rm = cast<ConstantInt>(inst.getRoundMode())->getZExtValue();
+ uint32_t op = cast<ConstantInt>(inst.getOperation())->getZExtValue();
+
+ // WARNING: This isn't supported robustly by the IR semantics and the backend, but it's the best we can do for now.
+ m_builder->CreateIntrinsic(m_builder->getVoidTy(), Intrinsic::amdgcn_s_setreg,
+ {m_builder->getInt32(hwReg), m_builder->getInt32(rm)});
+
+ Value *result = PoisonValue::get(retType);
+ if (op == OperationType::Add)
+ result = m_builder->CreateFAdd(src0, src1);
+ else if (op == OperationType::Sub)
+ result = m_builder->CreateFSub(src0, src1);
+ else
+ result = m_builder->CreateFMul(src0, src1);
+
+ // set back to RoundTiesToEven.
+ uint32_t roundTiesToEven = 1;
+ m_builder->CreateIntrinsic(m_builder->getVoidTy(), Intrinsic::amdgcn_s_setreg,
+ {m_builder->getInt32(hwReg), m_builder->getInt32(roundTiesToEven)});
+
+ inst.replaceAllUsesWith(result);
+ m_callsToLower.push_back(&inst);
+ m_funcsToLower.insert(func);
+}
+
// =====================================================================================================================
// Visit "GpurtLdsStackStoreOp" instruction
//
diff --git a/lgc/patch/MeshTaskShader.cpp b/lgc/patch/MeshTaskShader.cpp
index 5572680750..4242a871f5 100644
--- a/lgc/patch/MeshTaskShader.cpp
+++ b/lgc/patch/MeshTaskShader.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -72,10 +72,10 @@ MeshTaskShader::~MeshTaskShader() {
// @param ldsLayout : Mesh shader LDS layout (could be null)
unsigned MeshTaskShader::layoutMeshShaderLds(PipelineState *pipelineState, Function *entryPoint,
MeshLdsLayout *ldsLayout) {
- if (!pipelineState->hasShaderStage(ShaderStageMesh))
+ if (!pipelineState->hasShaderStage(ShaderStage::Mesh))
return 0; // Mesh shader absent (standalone compiler tries to compile a single task shader)
- assert(getShaderStage(entryPoint) == ShaderStageMesh); // Must be mesh shader
+ assert(getShaderStage(entryPoint) == ShaderStage::Mesh); // Must be mesh shader
auto gfxIp = pipelineState->getTargetInfo().getGfxIpVersion();
assert(gfxIp >= GfxIpVersion({10, 3})); // Must be GFX10.3+
@@ -104,7 +104,7 @@ unsigned MeshTaskShader::layoutMeshShaderLds(PipelineState *pipelineState, Funct
assert(meshMode.outputVertices <= Gfx9::NggMaxThreadsPerSubgroup);
assert(meshMode.outputPrimitives <= Gfx9::NggMaxThreadsPerSubgroup);
- const auto resUsage = pipelineState->getShaderResourceUsage(ShaderStageMesh);
+ const auto resUsage = pipelineState->getShaderResourceUsage(ShaderStage::Mesh);
unsigned meshLdsSizeInDwords = 0;
unsigned ldsOffsetInDwords = 0;
@@ -322,7 +322,7 @@ unsigned MeshTaskShader::useFlatWorkgroupId(PipelineState *pipelineState) {
if (pipelineState->getTargetInfo().getGfxIpVersion().major >= 11)
return false;
- const auto &builtInUsage = pipelineState->getShaderResourceUsage(ShaderStageMesh)->builtInUsage.mesh;
+ const auto &builtInUsage = pipelineState->getShaderResourceUsage(ShaderStage::Mesh)->builtInUsage.mesh;
return builtInUsage.workgroupId || builtInUsage.globalInvocationId;
}
@@ -331,7 +331,7 @@ unsigned MeshTaskShader::useFlatWorkgroupId(PipelineState *pipelineState) {
//
// @param entryPoint : Entry-point of task shader
void MeshTaskShader::processTaskShader(Function *entryPoint) {
- assert(getShaderStage(entryPoint) == ShaderStageTask);
+ assert(getShaderStage(entryPoint) == ShaderStage::Task);
//
// NOTE: The processing is something like this:
@@ -373,7 +373,7 @@ void MeshTaskShader::processTaskShader(Function *entryPoint) {
//
// @param entryPoint : Entry-point of mesh shader
void MeshTaskShader::processMeshShader(Function *entryPoint) {
- assert(getShaderStage(entryPoint) == ShaderStageMesh);
+ assert(getShaderStage(entryPoint) == ShaderStage::Mesh);
//
// NOTE: The processing is something like this:
@@ -461,7 +461,7 @@ void MeshTaskShader::processMeshShader(Function *entryPoint) {
m_needBarrierFlag = checkNeedBarrierFlag(entryPoint);
auto &meshMode = m_pipelineState->getShaderModes()->getMeshShaderMode();
- const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStageMesh);
+ const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Mesh);
// Setup LDS layout
layoutMeshShaderLds(m_pipelineState, entryPoint, &m_ldsLayout);
@@ -473,7 +473,7 @@ void MeshTaskShader::processMeshShader(Function *entryPoint) {
// Force s_barrier to be present if necessary (ignore optimization)
const unsigned numMeshThreads = meshMode.workgroupSizeX * meshMode.workgroupSizeY * meshMode.workgroupSizeZ;
auto primAmpFactor =
- m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->inOutUsage.gs.calcFactor.primAmpFactor;
+ m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->inOutUsage.gs.calcFactor.primAmpFactor;
// If we enable row export, the actual thread group size is determined by work group size provided from API mesh
// shader.
const unsigned flatWorkgroupSize =
@@ -639,7 +639,7 @@ void MeshTaskShader::processMeshShader(Function *entryPoint) {
// Write flat workgroup ID to LDS if it is required. Otherwise, skip it.
if (useFlatWorkgroupId(m_pipelineState)) {
auto ldsOffset = m_builder.getInt32(getMeshShaderLdsRegionStart(MeshLdsRegion::FlatWorkgroupId));
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageMesh)->entryArgIdxs.mesh;
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Mesh)->entryArgIdxs.mesh;
auto flatWorkgroupId = getFunctionArgument(entryPoint, entryArgIdxs.flatWorkgroupId);
writeValueToLds(flatWorkgroupId, ldsOffset);
}
@@ -964,7 +964,7 @@ void MeshTaskShader::lowerTaskPayloadPtr(TaskPayloadPtrOp &taskPayloadPtrOp) {
auto taskPayloadPtr = m_builder.create<BufferDescToPtrOp>(payloadRingBufDesc);
taskPayloadPtrOp.replaceAllUsesWith(taskPayloadPtr);
- if (getShaderStage(entryPoint) == ShaderStageTask)
+ if (getShaderStage(entryPoint) == ShaderStage::Task)
m_accessTaskPayload = true; // Mark this flag if task shader accesses task payload
m_callsToRemove.push_back(&taskPayloadPtrOp);
@@ -979,7 +979,7 @@ void MeshTaskShader::lowerEmitMeshTasks(EmitMeshTasksOp &emitMeshTasksOp) {
m_builder.SetInsertPoint(&emitMeshTasksOp);
auto entryPoint = emitMeshTasksOp.getFunction();
- assert(getShaderStage(entryPoint) == ShaderStageTask); // Must be task shader
+ assert(getShaderStage(entryPoint) == ShaderStage::Task); // Must be task shader
auto groupCountX = emitMeshTasksOp.getGroupCountX();
auto groupCountY = emitMeshTasksOp.getGroupCountY();
@@ -989,7 +989,7 @@ void MeshTaskShader::lowerEmitMeshTasks(EmitMeshTasksOp &emitMeshTasksOp) {
if (isa<ConstantInt>(groupCountY) && isa<ConstantInt>(groupCountZ)) {
const unsigned constGroupCountY = cast<ConstantInt>(groupCountY)->getZExtValue();
const unsigned constGroupCountZ = cast<ConstantInt>(groupCountZ)->getZExtValue();
- m_pipelineState->getShaderResourceUsage(ShaderStageTask)->builtInUsage.task.meshLinearDispatch =
+ m_pipelineState->getShaderResourceUsage(ShaderStage::Task)->builtInUsage.task.meshLinearDispatch =
constGroupCountY == 1 && constGroupCountZ == 1;
}
@@ -1098,7 +1098,7 @@ void MeshTaskShader::lowerEmitMeshTasks(EmitMeshTasksOp &emitMeshTasksOp) {
void MeshTaskShader::lowerSetMeshOutputs(SetMeshOutputsOp &setMeshOutputsOp) {
m_builder.SetInsertPoint(&setMeshOutputsOp);
- assert(getShaderStage(setMeshOutputsOp.getFunction()) == ShaderStageMesh);
+ assert(getShaderStage(setMeshOutputsOp.getFunction()) == ShaderStage::Mesh);
auto vertexCount = setMeshOutputsOp.getVertexCount();
auto primitiveCount = setMeshOutputsOp.getPrimitiveCount();
@@ -1170,7 +1170,7 @@ void MeshTaskShader::lowerSetMeshOutputs(SetMeshOutputsOp &setMeshOutputsOp) {
void MeshTaskShader::lowerSetMeshPrimitiveIndices(SetMeshPrimitiveIndicesOp &setMeshPrimitiveIndicesOp) {
m_builder.SetInsertPoint(&setMeshPrimitiveIndicesOp);
- assert(getShaderStage(setMeshPrimitiveIndicesOp.getFunction()) == ShaderStageMesh);
+ assert(getShaderStage(setMeshPrimitiveIndicesOp.getFunction()) == ShaderStage::Mesh);
auto primitiveIndex = setMeshPrimitiveIndicesOp.getPrimitiveIndex();
auto primitiveIndices = setMeshPrimitiveIndicesOp.getPrimitiveIndices();
@@ -1236,19 +1236,19 @@ void MeshTaskShader::lowerGetMeshBuiltinInput(GetMeshBuiltinInputOp &getMeshBuil
m_builder.SetInsertPoint(&getMeshBuiltinInputOp);
auto entryPoint = getMeshBuiltinInputOp.getFunction();
- assert(getShaderStage(entryPoint) == ShaderStageMesh);
+ assert(getShaderStage(entryPoint) == ShaderStage::Mesh);
Value *input = PoisonValue::get(getMeshBuiltinInputOp.getType());
auto builtin = getMeshBuiltinInputOp.getBuiltin();
switch (builtin) {
case BuiltInDrawIndex: {
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageMesh)->entryArgIdxs.mesh;
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Mesh)->entryArgIdxs.mesh;
input = getFunctionArgument(entryPoint, entryArgIdxs.drawIndex);
break;
}
case BuiltInViewIndex: {
if (m_pipelineState->getInputAssemblyState().multiView != MultiViewMode::Disable) {
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageMesh)->entryArgIdxs.mesh;
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Mesh)->entryArgIdxs.mesh;
input = getFunctionArgument(entryPoint, entryArgIdxs.viewId);
} else {
input = m_builder.getInt32(0);
@@ -1278,7 +1278,7 @@ void MeshTaskShader::lowerGetMeshBuiltinInput(GetMeshBuiltinInputOp &getMeshBuil
case BuiltInSubgroupId: {
// subgroupId = localInvocationIndex / subgroupSize
auto localInvocationIndex = getMeshLocalInvocationIndex();
- unsigned subgroupSize = m_pipelineState->getShaderSubgroupSize(ShaderStageMesh);
+ unsigned subgroupSize = m_pipelineState->getShaderSubgroupSize(ShaderStage::Mesh);
assert(subgroupSize > 0 && subgroupSize % 32 == 0);
input = m_builder.CreateLShr(localInvocationIndex, m_builder.getInt32(Log2_32(subgroupSize)));
break;
@@ -1287,7 +1287,7 @@ void MeshTaskShader::lowerGetMeshBuiltinInput(GetMeshBuiltinInputOp &getMeshBuil
// numSubgroups = numMeshThreads / subgroupSize
const auto &meshMode = m_pipelineState->getShaderModes()->getMeshShaderMode();
const unsigned numMeshThreads = meshMode.workgroupSizeX * meshMode.workgroupSizeY * meshMode.workgroupSizeZ;
- unsigned subgroupSize = m_pipelineState->getShaderSubgroupSize(ShaderStageMesh);
+ unsigned subgroupSize = m_pipelineState->getShaderSubgroupSize(ShaderStage::Mesh);
assert(subgroupSize > 0 && subgroupSize % 32 == 0);
const unsigned numSubgroups = alignTo(numMeshThreads, subgroupSize) / subgroupSize;
input = m_builder.getInt32(numSubgroups);
@@ -1312,7 +1312,7 @@ void MeshTaskShader::lowerGetMeshBuiltinInput(GetMeshBuiltinInputOp &getMeshBuil
void MeshTaskShader::lowerSetMeshPrimitiveCulled(SetMeshPrimitiveCulledOp &setMeshPrimitiveCulledOp) {
m_builder.SetInsertPoint(&setMeshPrimitiveCulledOp);
- assert(getShaderStage(setMeshPrimitiveCulledOp.getFunction()) == ShaderStageMesh);
+ assert(getShaderStage(setMeshPrimitiveCulledOp.getFunction()) == ShaderStage::Mesh);
auto primitiveIndex = setMeshPrimitiveCulledOp.getPrimitiveIndex();
auto isCulled = setMeshPrimitiveCulledOp.getIsCulled();
@@ -1348,13 +1348,13 @@ void MeshTaskShader::lowerSetMeshPrimitiveCulled(SetMeshPrimitiveCulledOp &setMe
void MeshTaskShader::lowerWriteMeshVertexOutput(WriteMeshVertexOutputOp &writeMeshVertexOutputOp) {
m_builder.SetInsertPoint(&writeMeshVertexOutputOp);
- assert(getShaderStage(writeMeshVertexOutputOp.getFunction()) == ShaderStageMesh);
+ assert(getShaderStage(writeMeshVertexOutputOp.getFunction()) == ShaderStage::Mesh);
auto outputOffset = writeMeshVertexOutputOp.getOutputOffset();
auto vertexIndex = writeMeshVertexOutputOp.getVertexIndex();
auto outputValue = writeMeshVertexOutputOp.getOutputValue();
- const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageMesh);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Mesh);
const unsigned vertexStride = 4 * resUsage->inOutUsage.outputMapLocCount; // Corresponds to vec4 output
Value *ldsStart = m_builder.getInt32(getMeshShaderLdsRegionStart(MeshLdsRegion::VertexOutput));
@@ -1374,13 +1374,13 @@ void MeshTaskShader::lowerWriteMeshVertexOutput(WriteMeshVertexOutputOp &writeMe
void MeshTaskShader::lowerWriteMeshPrimitiveOutput(WriteMeshPrimitiveOutputOp &writeMeshPrimitiveOutputOp) {
m_builder.SetInsertPoint(&writeMeshPrimitiveOutputOp);
- assert(getShaderStage(writeMeshPrimitiveOutputOp.getFunction()) == ShaderStageMesh);
+ assert(getShaderStage(writeMeshPrimitiveOutputOp.getFunction()) == ShaderStage::Mesh);
auto outputOffset = writeMeshPrimitiveOutputOp.getOutputOffset();
auto primitiveIndex = writeMeshPrimitiveOutputOp.getPrimitiveIndex();
auto outputValue = writeMeshPrimitiveOutputOp.getOutputValue();
- const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageMesh);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Mesh);
const unsigned primitiveStride = 4 * resUsage->inOutUsage.perPrimitiveOutputMapLocCount; // Corresponds to vec4 output
Value *ldsStart = m_builder.getInt32(getMeshShaderLdsRegionStart(MeshLdsRegion::PrimitiveOutput));
@@ -1400,9 +1400,9 @@ void MeshTaskShader::lowerWriteMeshPrimitiveOutput(WriteMeshPrimitiveOutputOp &w
void MeshTaskShader::initWaveThreadInfo(Function *entryPoint) {
m_waveThreadInfo = {}; // Reset it
- if (getShaderStage(entryPoint) == ShaderStageTask) {
+ if (getShaderStage(entryPoint) == ShaderStage::Task) {
// Task shader
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageTask)->entryArgIdxs.task;
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Task)->entryArgIdxs.task;
{
// waveId = dispatchInfo[24:20]
@@ -1410,7 +1410,7 @@ void MeshTaskShader::initWaveThreadInfo(Function *entryPoint) {
m_builder.CreateAnd(m_builder.CreateLShr(getFunctionArgument(entryPoint, entryArgIdxs.multiDispatchInfo), 20),
0x1F, "waveIdInSubgroup");
}
- const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStageTask);
+ const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Task);
m_waveThreadInfo.threadIdInWave =
m_builder.CreateIntrinsic(Intrinsic::amdgcn_mbcnt_lo, {}, {m_builder.getInt32(-1), m_builder.getInt32(0)});
@@ -1425,7 +1425,7 @@ void MeshTaskShader::initWaveThreadInfo(Function *entryPoint) {
m_waveThreadInfo.threadIdInWave, "threadIdInSubgroup");
} else {
// Mesh shader
- assert(getShaderStage(entryPoint) == ShaderStageMesh);
+ assert(getShaderStage(entryPoint) == ShaderStage::Mesh);
m_builder.CreateIntrinsic(Intrinsic::amdgcn_init_exec, {}, m_builder.getInt64(-1));
@@ -1435,7 +1435,7 @@ void MeshTaskShader::initWaveThreadInfo(Function *entryPoint) {
m_waveThreadInfo.waveIdInSubgroup =
m_builder.CreateAnd(m_builder.CreateLShr(mergedWaveInfo, 24), 0xF, "waveIdInSubgroup");
- const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStageMesh);
+ const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Mesh);
m_waveThreadInfo.threadIdInWave =
m_builder.CreateIntrinsic(Intrinsic::amdgcn_mbcnt_lo, {}, {m_builder.getInt32(-1), m_builder.getInt32(0)});
@@ -1464,13 +1464,13 @@ void MeshTaskShader::initWaveThreadInfo(Function *entryPoint) {
// @returns : The shader ring entry index of current workgroup
Value *MeshTaskShader::getShaderRingEntryIndex(Function *entryPoint) {
if (!m_shaderRingEntryIndex) {
- if (getShaderStage(entryPoint) == ShaderStageTask) {
+ if (getShaderStage(entryPoint) == ShaderStage::Task) {
// NOTE: The calculation of shader ring entry index should be done at the beginning of the entry block. And the
// value could be reused in subsequent operations.
IRBuilder<>::InsertPointGuard guard(m_builder);
m_builder.SetInsertPointPastAllocas(entryPoint);
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageTask)->entryArgIdxs.task;
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Task)->entryArgIdxs.task;
Value *workgroupIds[3] = {};
if (m_gfxIp.major <= 11) {
@@ -1495,9 +1495,9 @@ Value *MeshTaskShader::getShaderRingEntryIndex(Function *entryPoint) {
auto baseRingEntryIndex = getFunctionArgument(entryPoint, entryArgIdxs.baseRingEntryIndex);
m_shaderRingEntryIndex = m_builder.CreateAdd(baseRingEntryIndex, flatWorkgroupId);
} else {
- assert(getShaderStage(entryPoint) == ShaderStageMesh);
+ assert(getShaderStage(entryPoint) == ShaderStage::Mesh);
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageMesh)->entryArgIdxs.mesh;
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Mesh)->entryArgIdxs.mesh;
m_shaderRingEntryIndex = getFunctionArgument(entryPoint, entryArgIdxs.baseRingEntryIndex);
}
}
@@ -1538,7 +1538,7 @@ Value *MeshTaskShader::getPayloadRingEntryOffset(Function *entryPoint) {
// @param entryPoint : Entry-point of task shader
// @returns : The draw data ring entry offset of current workgroup
Value *MeshTaskShader::getDrawDataRingEntryOffset(Function *entryPoint) {
- assert(getShaderStage(entryPoint) == ShaderStageTask); // Must be task shader
+ assert(getShaderStage(entryPoint) == ShaderStage::Task); // Must be task shader
Value *ringEntryIndex = getShaderRingEntryIndex(entryPoint);
Value *drawDataRingBufDesc = m_pipelineSysValues.get(entryPoint)->getTaskDrawDataRingBufDesc();
@@ -1558,7 +1558,7 @@ Value *MeshTaskShader::getDrawDataRingEntryOffset(Function *entryPoint) {
// @param entryPoint : Entry-point of task shader
// @returns : Flag (i1 typed) indicating whether the draw data is ready for command processor (CP) to fetch.
Value *MeshTaskShader::getDrawDataReadyBit(Function *entryPoint) {
- assert(getShaderStage(entryPoint) == ShaderStageTask); // Must be task shader
+ assert(getShaderStage(entryPoint) == ShaderStage::Task); // Must be task shader
Value *ringEntryIndex = getShaderRingEntryIndex(entryPoint);
Value *drawDataRingBufDesc = m_pipelineSysValues.get(entryPoint)->getTaskDrawDataRingBufDesc();
@@ -1589,7 +1589,7 @@ Value *MeshTaskShader::convertToDivergent(Value *value) {
// @param entryPoint : Entry-point of mesh shader
// @returns : New entry-point of mesh shader after mutation
Function *MeshTaskShader::mutateMeshShaderEntryPoint(Function *entryPoint) {
- assert(getShaderStage(entryPoint) == ShaderStageMesh); // Must be mesh shader
+ assert(getShaderStage(entryPoint) == ShaderStage::Mesh); // Must be mesh shader
// GFX10 special SGPR input names
static const SmallVector<std::string, NumSpecialSgprInputs> SpecialSgprInputNamesGfx10 = {
@@ -1621,7 +1621,7 @@ Function *MeshTaskShader::mutateMeshShaderEntryPoint(Function *entryPoint) {
entryPoint->eraseFromParent();
// Adjust indices of existing entry-point arguments
- auto &entryArgIdx = m_pipelineState->getShaderInterfaceData(ShaderStageMesh)->entryArgIdxs.mesh;
+ auto &entryArgIdx = m_pipelineState->getShaderInterfaceData(ShaderStage::Mesh)->entryArgIdxs.mesh;
entryArgIdx.drawIndex += NumSpecialSgprInputs;
entryArgIdx.viewId += NumSpecialSgprInputs;
entryArgIdx.dispatchDims += NumSpecialSgprInputs;
@@ -1672,7 +1672,7 @@ Function *MeshTaskShader::mutateMeshShaderEntryPoint(Function *entryPoint) {
// @param apiMeshExitBlock : API mesh shader exit block (before any mutation)`
void MeshTaskShader::lowerMeshShaderBody(BasicBlock *apiMeshEntryBlock, BasicBlock *apiMeshExitBlock) {
auto entryPoint = apiMeshEntryBlock->getParent();
- assert(getShaderStage(entryPoint) == ShaderStageMesh);
+ assert(getShaderStage(entryPoint) == ShaderStage::Mesh);
// Handle API mesh shader barrier
if (m_needBarrierFlag) {
@@ -1719,8 +1719,8 @@ void MeshTaskShader::lowerMeshShaderBody(BasicBlock *apiMeshEntryBlock, BasicBlo
// =====================================================================================================================
// Export primitive (primitive connectivity data, primitive payload, and primitive attributes).
void MeshTaskShader::exportPrimitive() {
- const auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageMesh)->builtInUsage.mesh;
- auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStageMesh)->inOutUsage;
+ const auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Mesh)->builtInUsage.mesh;
+ auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Mesh)->inOutUsage;
Value *ldsStart = m_builder.getInt32(getMeshShaderLdsRegionStart(MeshLdsRegion::PrimitiveIndices));
Value *ldsOffset = m_builder.CreateAdd(ldsStart, m_waveThreadInfo.primOrVertexIndex);
@@ -1769,7 +1769,7 @@ void MeshTaskShader::exportPrimitive() {
const bool enableMultiView = m_pipelineState->getInputAssemblyState().multiView != MultiViewMode::Disable;
if (enableMultiView) {
auto entryPoint = m_builder.GetInsertBlock()->getParent();
- const auto entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageMesh)->entryArgIdxs.mesh;
+ const auto entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Mesh)->entryArgIdxs.mesh;
Value *viewId = getFunctionArgument(entryPoint, entryArgIdxs.viewId);
// RT layer is view ID in simple mode (view index only).
@@ -1873,9 +1873,9 @@ void MeshTaskShader::exportPrimitive() {
if (builtInUsage.layer) {
exportLayer = true;
} else {
- const auto nextStage = m_pipelineState->getNextShaderStage(ShaderStageMesh);
- if (nextStage == ShaderStageFragment) {
- const auto &fsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageFragment)->builtInUsage.fs;
+ const auto nextStage = m_pipelineState->getNextShaderStage(ShaderStage::Mesh);
+ if (nextStage == ShaderStage::Fragment) {
+ const auto &fsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Fragment)->builtInUsage.fs;
if (fsBuiltInUsage.layer) {
// NOTE: In such case, mesh shader doesn't export layer while fragment shader expects to read it. We
// export 0 to fragment shader, which is required by the spec.
@@ -1898,9 +1898,9 @@ void MeshTaskShader::exportPrimitive() {
if (builtInUsage.viewportIndex) {
exportViewportIndex = true;
} else {
- const auto nextStage = m_pipelineState->getNextShaderStage(ShaderStageMesh);
- if (nextStage == ShaderStageFragment) {
- const auto &fsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageFragment)->builtInUsage.fs;
+ const auto nextStage = m_pipelineState->getNextShaderStage(ShaderStage::Mesh);
+ if (nextStage == ShaderStage::Fragment) {
+ const auto &fsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Fragment)->builtInUsage.fs;
if (fsBuiltInUsage.viewportIndex) {
// NOTE: In such case, mesh shader doesn't export viewport index while fragment shader expects to read it. We
// export 0 to fragment shader, which is required by spec.
@@ -1925,8 +1925,8 @@ void MeshTaskShader::exportPrimitive() {
// =====================================================================================================================
// Export vertex (vertex position data and vertex attributes).
void MeshTaskShader::exportVertex() {
- const auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageMesh)->builtInUsage.mesh;
- auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStageMesh)->inOutUsage;
+ const auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Mesh)->builtInUsage.mesh;
+ auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Mesh)->inOutUsage;
// Export vertex position data
SmallVector<ExportInfo, 8> posExports;
@@ -2023,9 +2023,9 @@ void MeshTaskShader::exportVertex() {
if (builtInUsage.clipDistance > 0 || builtInUsage.cullDistance > 0) {
bool exportClipCullDistance = true;
- auto nextStage = m_pipelineState->getNextShaderStage(ShaderStageMesh);
- if (nextStage == ShaderStageFragment) {
- const auto &fsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageFragment)->builtInUsage.fs;
+ auto nextStage = m_pipelineState->getNextShaderStage(ShaderStage::Mesh);
+ if (nextStage == ShaderStage::Fragment) {
+ const auto &fsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Fragment)->builtInUsage.fs;
exportClipCullDistance = fsBuiltInUsage.clipDistance > 0 || fsBuiltInUsage.cullDistance > 0;
if (exportClipCullDistance) {
@@ -2264,7 +2264,7 @@ void MeshTaskShader::prepareAttribRingAccess() {
// 2. Vertex attributes mapped from vertex builtins
// 3. Generic primitive attributes
// 4. Primitive attributes mapped from primitive builtins
- const auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStageMesh)->inOutUsage.mesh;
+ const auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Mesh)->inOutUsage.mesh;
unsigned vertAttribCount = inOutUsage.genericOutputMapLocCount;
for (auto &builtInExport : inOutUsage.builtInExportLocs) {
const unsigned exportLoc = builtInExport.second;
@@ -2319,7 +2319,7 @@ void MeshTaskShader::prepareAttribRingAccess() {
//
// @returns : Value of flat workgroup ID
Value *MeshTaskShader::getMeshFlatWorkgroupId() {
- assert(getShaderStage(m_builder.GetInsertBlock()->getParent()) == ShaderStageMesh); // Must be mesh shader
+ assert(getShaderStage(m_builder.GetInsertBlock()->getParent()) == ShaderStage::Mesh); // Must be mesh shader
auto ldsOffset = m_builder.getInt32(getMeshShaderLdsRegionStart(MeshLdsRegion::FlatWorkgroupId));
auto flatWorkgroupId = readValueFromLds(m_builder.getInt32Ty(), ldsOffset);
@@ -2336,9 +2336,9 @@ Value *MeshTaskShader::getMeshFlatWorkgroupId() {
// @returns : Value of the built-in numWorkgroups
Value *MeshTaskShader::getMeshNumWorkgroups() {
auto entryPoint = m_builder.GetInsertBlock()->getParent();
- assert(getShaderStage(entryPoint) == ShaderStageMesh); // Must be mesh shader
+ assert(getShaderStage(entryPoint) == ShaderStage::Mesh); // Must be mesh shader
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageMesh)->entryArgIdxs.mesh;
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Mesh)->entryArgIdxs.mesh;
return getFunctionArgument(entryPoint, entryArgIdxs.dispatchDims);
}
@@ -2348,7 +2348,7 @@ Value *MeshTaskShader::getMeshNumWorkgroups() {
// @returns : Value of the built-in WorkgroupId
Value *MeshTaskShader::getMeshWorkgroupId() {
auto entryPoint = m_builder.GetInsertBlock()->getParent();
- assert(getShaderStage(entryPoint) == ShaderStageMesh); // Must be mesh shader
+ assert(getShaderStage(entryPoint) == ShaderStage::Mesh); // Must be mesh shader
Value *workgroupIdX = nullptr;
Value *workgroupIdY = nullptr;
@@ -2376,7 +2376,7 @@ Value *MeshTaskShader::getMeshWorkgroupId() {
// dispatchDims.x * workgroupId.y
auto flatWorkgroupId = getMeshFlatWorkgroupId();
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageMesh)->entryArgIdxs.mesh;
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Mesh)->entryArgIdxs.mesh;
auto dispatchDims = getFunctionArgument(entryPoint, entryArgIdxs.dispatchDims);
auto dispatchDimX = m_builder.CreateExtractElement(dispatchDims, static_cast<uint64_t>(0));
@@ -2417,7 +2417,7 @@ Value *MeshTaskShader::getMeshWorkgroupId() {
// @returns : Value of the built-in LocalInvocationId
Value *MeshTaskShader::getMeshLocalInvocationId() {
auto entryPoint = m_builder.GetInsertBlock()->getParent();
- assert(getShaderStage(entryPoint) == ShaderStageMesh); // Must be mesh shader
+ assert(getShaderStage(entryPoint) == ShaderStage::Mesh); // Must be mesh shader
Value *localInvocationIdX = nullptr;
Value *localInvocationIdY = nullptr;
@@ -2430,7 +2430,7 @@ Value *MeshTaskShader::getMeshLocalInvocationId() {
// | Local Invocation ID Z | Local Invocation ID Y | Local Invocation ID Z |
// | [29:20] | [19:10] | [9:0] |
// +-----------------------+-----------------------+-----------------------+
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageMesh)->entryArgIdxs.mesh;
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Mesh)->entryArgIdxs.mesh;
Value *localInvocationId = getFunctionArgument(entryPoint, entryArgIdxs.localInvocationId);
// localInvocationIdZ = localInvocationId[29:20]
@@ -2478,7 +2478,7 @@ Value *MeshTaskShader::getMeshLocalInvocationId() {
//
// @returns : Value of the built-in LocalInvocationIndex
Value *MeshTaskShader::getMeshLocalInvocationIndex() {
- assert(getShaderStage(m_builder.GetInsertBlock()->getParent()) == ShaderStageMesh); // Must be mesh shader
+ assert(getShaderStage(m_builder.GetInsertBlock()->getParent()) == ShaderStage::Mesh); // Must be mesh shader
return m_waveThreadInfo.threadIdInSubgroup;
}
@@ -2487,7 +2487,7 @@ Value *MeshTaskShader::getMeshLocalInvocationIndex() {
//
// @returns : Value of the built-in GlobalInvocationId
Value *MeshTaskShader::getMeshGlobalInvocationId() {
- assert(getShaderStage(m_builder.GetInsertBlock()->getParent()) == ShaderStageMesh); // Must be mesh shader
+ assert(getShaderStage(m_builder.GetInsertBlock()->getParent()) == ShaderStage::Mesh); // Must be mesh shader
// globalInvocationId = workgroupId * workgroupSize + localInvocationId
auto workgourpId = getMeshWorkgroupId();
@@ -2510,8 +2510,8 @@ Value *MeshTaskShader::getMeshGlobalInvocationId() {
// @param builtIn : Mesh shader built-in
// @returns : The built-in value from LDS
Value *MeshTaskShader::readMeshBuiltInFromLds(BuiltInKind builtIn) {
- const auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageMesh)->builtInUsage.mesh;
- auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStageMesh)->inOutUsage;
+ const auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Mesh)->builtInUsage.mesh;
+ auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Mesh)->inOutUsage;
bool isPerPrimitive = (builtIn == BuiltInPrimitiveId || builtIn == BuiltInViewportIndex || builtIn == BuiltInLayer ||
builtIn == BuiltInPrimitiveShadingRate);
@@ -2741,16 +2741,16 @@ bool MeshTaskShader::checkNeedBarrierFlag(Function *entryPoint) {
const auto &meshMode = m_pipelineState->getShaderModes()->getMeshShaderMode();
const unsigned numMeshThreads = meshMode.workgroupSizeX * meshMode.workgroupSizeY * meshMode.workgroupSizeZ;
const unsigned numThreads =
- m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->inOutUsage.gs.calcFactor.primAmpFactor;
+ m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->inOutUsage.gs.calcFactor.primAmpFactor;
assert(numThreads >= numMeshThreads);
- const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStageMesh);
+ const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Mesh);
const unsigned numMeshWaves = alignTo(numMeshThreads, waveSize) / waveSize;
const unsigned numWaves = alignTo(numThreads, waveSize) / waveSize;
if (numWaves == numMeshWaves)
return false; // Wave number to run API mesh shader is equal to actual wave number to run HW mesh shader (HW GS)
- assert(getShaderStage(entryPoint) == ShaderStageMesh);
+ assert(getShaderStage(entryPoint) == ShaderStage::Mesh);
auto module = entryPoint->getParent();
for (auto &func : module->functions()) {
if (func.isIntrinsic() && func.getIntrinsicID() == Intrinsic::amdgcn_s_barrier) {
diff --git a/lgc/patch/MeshTaskShader.h b/lgc/patch/MeshTaskShader.h
index 788ee5dfd0..da8fa30c83 100644
--- a/lgc/patch/MeshTaskShader.h
+++ b/lgc/patch/MeshTaskShader.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/patch/NggPrimShader.cpp b/lgc/patch/NggPrimShader.cpp
index 10c97ca880..29763d5c3b 100644
--- a/lgc/patch/NggPrimShader.cpp
+++ b/lgc/patch/NggPrimShader.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -98,9 +98,9 @@ enum {
// @param pipelineState : Pipeline state
NggPrimShader::NggPrimShader(PipelineState *pipelineState)
: m_pipelineState(pipelineState), m_gfxIp(pipelineState->getTargetInfo().getGfxIpVersion()),
- m_nggControl(m_pipelineState->getNggControl()), m_hasVs(pipelineState->hasShaderStage(ShaderStageVertex)),
- m_hasTes(pipelineState->hasShaderStage(ShaderStageTessEval)),
- m_hasGs(pipelineState->hasShaderStage(ShaderStageGeometry)), m_builder(pipelineState->getContext()) {
+ m_nggControl(m_pipelineState->getNggControl()), m_hasVs(pipelineState->hasShaderStage(ShaderStage::Vertex)),
+ m_hasTes(pipelineState->hasShaderStage(ShaderStage::TessEval)),
+ m_hasGs(pipelineState->hasShaderStage(ShaderStage::Geometry)), m_builder(pipelineState->getContext()) {
assert(m_nggControl->enableNgg);
// Always allow approximation, to change fdiv(1.0, x) to rcp(x)
@@ -115,7 +115,7 @@ NggPrimShader::NggPrimShader(PipelineState *pipelineState)
// the base offset of each vertex streams and record them. See 'writeGsOutput' for detail.
if (m_hasGs) {
unsigned vertexItemSizes[MaxGsStreams] = {};
- auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry);
+ auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry);
for (unsigned i = 0; i < MaxGsStreams; ++i)
vertexItemSizes[i] = 4 * resUsage->inOutUsage.gs.outLocCount[i];
@@ -146,8 +146,8 @@ unsigned NggPrimShader::calcEsGsRingItemSize(PipelineState *pipelineState) {
assert(pipelineState->getNggControl()->enableNgg); // Must enable NGG
// API GS is present
- if (pipelineState->hasShaderStage(ShaderStageGeometry)) {
- auto resUsage = pipelineState->getShaderResourceUsage(ShaderStageGeometry);
+ if (pipelineState->hasShaderStage(ShaderStage::Geometry)) {
+ auto resUsage = pipelineState->getShaderResourceUsage(ShaderStage::Geometry);
// NOTE: Make esGsRingItemSize odd by "| 1", to optimize ES -> GS ring layout for LDS bank conflicts.
return (4 * std::max(1u, resUsage->inOutUsage.inputMapLocCount)) | 1;
}
@@ -157,8 +157,8 @@ unsigned NggPrimShader::calcEsGsRingItemSize(PipelineState *pipelineState) {
unsigned esGsRingItemSize = 1;
if (pipelineState->enableSwXfb()) {
- const bool hasTes = pipelineState->hasShaderStage(ShaderStageTessEval);
- auto resUsage = pipelineState->getShaderResourceUsage(hasTes ? ShaderStageTessEval : ShaderStageVertex);
+ const bool hasTes = pipelineState->hasShaderStage(ShaderStage::TessEval);
+ auto resUsage = pipelineState->getShaderResourceUsage(hasTes ? ShaderStage::TessEval : ShaderStage::Vertex);
// NOTE: For GFX11+, transform feedback outputs (each output is <4 x dword>) are stored as a ES-GS ring item.
assert(resUsage->inOutUsage.xfbExpCount > 0);
@@ -187,7 +187,7 @@ PrimShaderLdsUsageInfo NggPrimShader::layoutPrimShaderLds(PipelineState *pipelin
PrimShaderLdsLayout *ldsLayout) {
assert(pipelineState->getNggControl()->enableNgg); // Must enable NGG
- const auto &calcFactor = pipelineState->getShaderResourceUsage(ShaderStageGeometry)->inOutUsage.gs.calcFactor;
+ const auto &calcFactor = pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->inOutUsage.gs.calcFactor;
unsigned ldsOffset = 0; // In dwords
unsigned ldsRegionSize = 0; // In dwords
@@ -207,7 +207,7 @@ PrimShaderLdsUsageInfo NggPrimShader::layoutPrimShaderLds(PipelineState *pipelin
//
// API GS is present
//
- if (pipelineState->hasShaderStage(ShaderStageGeometry)) {
+ if (pipelineState->hasShaderStage(ShaderStage::Geometry)) {
PrimShaderLdsUsageInfo ldsUsageInfo = {};
ldsUsageInfo.needsLds = true;
@@ -340,9 +340,9 @@ PrimShaderLdsUsageInfo NggPrimShader::layoutPrimShaderLds(PipelineState *pipelin
return ldsUsageInfo;
}
- const bool hasTes = pipelineState->hasShaderStage(ShaderStageTessEval);
+ const bool hasTes = pipelineState->hasShaderStage(ShaderStage::TessEval);
const bool distributePrimitiveId =
- !hasTes && pipelineState->getShaderResourceUsage(ShaderStageVertex)->builtInUsage.vs.primitiveId;
+ !hasTes && pipelineState->getShaderResourceUsage(ShaderStage::Vertex)->builtInUsage.vs.primitiveId;
//
// Passthrough mode is enabled (API GS is not present)
@@ -552,7 +552,7 @@ Function *NggPrimShader::generate(Function *esMain, Function *gsMain, Function *
Function *primShader = Function::Create(primShaderTy, GlobalValue::ExternalLinkage, lgcName::NggPrimShaderEntryPoint);
primShader->setDLLStorageClass(GlobalValue::DLLExportStorageClass);
- const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStageGeometry);
+ const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Geometry);
primShader->addFnAttr("target-features", ",+wavefrontsize" + std::to_string(waveSize)); // Set wavefront size
primShader->addFnAttr("amdgpu-flat-work-group-size",
"128,128"); // Force s_barrier to be present (ignore optimization)
@@ -630,7 +630,7 @@ unsigned NggPrimShader::calcVertexCullInfoSizeAndOffsets(PipelineState *pipeline
vertCullInfoOffsets = {};
// Only for NGG culling mode without API GS
- const bool hasGs = pipelineState->hasShaderStage(ShaderStageGeometry);
+ const bool hasGs = pipelineState->hasShaderStage(ShaderStage::Geometry);
if (hasGs || nggControl->passthroughMode)
return 0;
@@ -639,8 +639,8 @@ unsigned NggPrimShader::calcVertexCullInfoSizeAndOffsets(PipelineState *pipeline
unsigned itemSize = 0;
if (pipelineState->enableSwXfb()) {
- const bool hasTes = pipelineState->hasShaderStage(ShaderStageTessEval);
- auto resUsage = pipelineState->getShaderResourceUsage(hasTes ? ShaderStageTessEval : ShaderStageVertex);
+ const bool hasTes = pipelineState->hasShaderStage(ShaderStage::TessEval);
+ auto resUsage = pipelineState->getShaderResourceUsage(hasTes ? ShaderStage::TessEval : ShaderStage::Vertex);
// NOTE: Each transform feedback output is <4 x dword>.
const unsigned xfbOutputCount = resUsage->inOutUsage.xfbExpCount;
@@ -668,9 +668,9 @@ unsigned NggPrimShader::calcVertexCullInfoSizeAndOffsets(PipelineState *pipeline
vertCullInfoOffsets.compactedVertexIndex = cullInfoOffset;
cullInfoOffset += itemSize;
- const bool hasTes = pipelineState->hasShaderStage(ShaderStageTessEval);
+ const bool hasTes = pipelineState->hasShaderStage(ShaderStage::TessEval);
if (hasTes) {
- auto builtInUsage = pipelineState->getShaderResourceUsage(ShaderStageTessEval)->builtInUsage.tes;
+ auto builtInUsage = pipelineState->getShaderResourceUsage(ShaderStage::TessEval)->builtInUsage.tes;
if (builtInUsage.tessCoord) {
itemSize = sizeof(VertexCullInfo::tes.tessCoordX) / sizeof(unsigned);
cullInfoSize += itemSize;
@@ -695,7 +695,7 @@ unsigned NggPrimShader::calcVertexCullInfoSizeAndOffsets(PipelineState *pipeline
cullInfoOffset += itemSize;
}
} else {
- auto builtInUsage = pipelineState->getShaderResourceUsage(ShaderStageVertex)->builtInUsage.vs;
+ auto builtInUsage = pipelineState->getShaderResourceUsage(ShaderStage::Vertex)->builtInUsage.vs;
if (builtInUsage.vertexIndex) {
itemSize = sizeof(VertexCullInfo::vs.vertexId) / sizeof(unsigned);
cullInfoSize += itemSize;
@@ -738,9 +738,9 @@ FunctionType *NggPrimShader::getPrimShaderType(uint64_t &inRegMask) {
// User data (SGPRs)
unsigned userDataCount = 0;
- const auto gsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStageGeometry);
- const auto tesIntfData = m_pipelineState->getShaderInterfaceData(ShaderStageTessEval);
- const auto vsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStageVertex);
+ const auto gsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStage::Geometry);
+ const auto tesIntfData = m_pipelineState->getShaderInterfaceData(ShaderStage::TessEval);
+ const auto vsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStage::Vertex);
if (m_hasGs) {
// GS is present in primitive shader (ES-GS merged shader)
@@ -1087,7 +1087,7 @@ void NggPrimShader::buildPrimShader(Function *primShader) {
assert(!m_nggControl->passthroughMode); // Make sure NGG passthrough mode is not enabled
assert(!m_hasGs); // Make sure API GS is not present
- const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStageGeometry);
+ const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Geometry);
assert(waveSize == 32 || waveSize == 64);
const unsigned waveCountInSubgroup = Gfx9::NggMaxThreadsPerSubgroup / waveSize;
@@ -1230,7 +1230,7 @@ void NggPrimShader::buildPrimShader(Function *primShader) {
const unsigned dummyExportCount = waNggCullingNoEmptySubgroups ? 1 : 0;
const unsigned esGsRingItemSize =
- m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->inOutUsage.gs.calcFactor.esGsRingItemSize;
+ m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->inOutUsage.gs.calcFactor.esGsRingItemSize;
// NOTE: Make sure vertex position data is 4-dword alignment because we will use 128-bit LDS read/write for it.
assert(getLdsRegionStart(PrimShaderLdsRegion::VertexPosition) % 4U == 0);
@@ -1585,7 +1585,8 @@ void NggPrimShader::buildPrimShader(Function *primShader) {
// Write compacted vertex index
writeVertexCullInfoToLds(compactedVertexIndex, vertexItemOffset, m_vertCullInfoOffsets.compactedVertexIndex);
- const auto resUsage = m_pipelineState->getShaderResourceUsage(m_hasTes ? ShaderStageTessEval : ShaderStageVertex);
+ const auto resUsage =
+ m_pipelineState->getShaderResourceUsage(m_hasTes ? ShaderStage::TessEval : ShaderStage::Vertex);
if (m_hasTes) {
// Write X/Y of tessCoord (U/V)
if (resUsage->builtInUsage.tes.tessCoord) {
@@ -1845,7 +1846,7 @@ void NggPrimShader::buildPrimShader(Function *primShader) {
void NggPrimShader::buildPrimShaderWithGs(Function *primShader) {
assert(m_hasGs); // Make sure API GS is present
- const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStageGeometry);
+ const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Geometry);
assert(waveSize == 32 || waveSize == 64);
if (!m_nggControl->compactVertex)
@@ -2436,7 +2437,7 @@ void NggPrimShader::buildPrimShaderWithGs(Function *primShader) {
// @param mergedGroupInfo : Merged group info
// @param mergedWaveInfo : Merged wave info
void NggPrimShader::initWaveThreadInfo(Value *mergedGroupInfo, Value *mergedWaveInfo) {
- const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStageGeometry);
+ const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Geometry);
assert(waveSize == 32 || waveSize == 64);
m_builder.CreateIntrinsic(Intrinsic::amdgcn_init_exec, {}, m_builder.getInt64(-1));
@@ -2525,11 +2526,11 @@ void NggPrimShader::loadStreamOutBufferInfo(Value *userData) {
const auto gsOrEsMain = m_hasGs ? m_gsHandlers.main : m_esHandlers.main;
StreamOutData streamOutData = {};
if (m_hasGs)
- streamOutData = m_pipelineState->getShaderInterfaceData(ShaderStageGeometry)->entryArgIdxs.gs.streamOutData;
+ streamOutData = m_pipelineState->getShaderInterfaceData(ShaderStage::Geometry)->entryArgIdxs.gs.streamOutData;
else if (m_hasTes)
- streamOutData = m_pipelineState->getShaderInterfaceData(ShaderStageTessEval)->entryArgIdxs.tes.streamOutData;
+ streamOutData = m_pipelineState->getShaderInterfaceData(ShaderStage::TessEval)->entryArgIdxs.tes.streamOutData;
else
- streamOutData = m_pipelineState->getShaderInterfaceData(ShaderStageVertex)->entryArgIdxs.vs.streamOutData;
+ streamOutData = m_pipelineState->getShaderInterfaceData(ShaderStage::Vertex)->entryArgIdxs.vs.streamOutData;
assert(userData->getType()->isVectorTy());
const auto constBufferPtrTy = PointerType::get(m_builder.getContext(), ADDR_SPACE_CONST);
@@ -2578,7 +2579,7 @@ void NggPrimShader::distributePrimitiveId(Value *primitiveId) {
if (m_hasGs || m_hasTes)
return; // Not VS-PS pipeline
- if (!m_pipelineState->getShaderResourceUsage(ShaderStageVertex)->builtInUsage.vs.primitiveId)
+ if (!m_pipelineState->getShaderResourceUsage(ShaderStage::Vertex)->builtInUsage.vs.primitiveId)
return; // Primitive ID not used in VS
//
@@ -2785,7 +2786,7 @@ void NggPrimShader::exportPrimitive(Value *primitiveCulled) {
m_builder.SetInsertPoint(compactVertexIndexBlock);
const unsigned esGsRingItemSize =
- m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->inOutUsage.gs.calcFactor.esGsRingItemSize;
+ m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->inOutUsage.gs.calcFactor.esGsRingItemSize;
auto vertexItemOffset0 = m_builder.CreateMul(m_nggInputs.vertexIndex0, m_builder.getInt32(esGsRingItemSize));
auto vertexItemOffset1 = m_builder.CreateMul(m_nggInputs.vertexIndex1, m_builder.getInt32(esGsRingItemSize));
@@ -2994,7 +2995,7 @@ void NggPrimShader::earlyExitWithDummyExport() {
// Determine how many dummy position exports we need
unsigned posExpCount = 1;
if (m_hasGs) {
- const auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->builtInUsage.gs;
+ const auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->builtInUsage.gs;
bool miscExport = builtInUsage.pointSize || builtInUsage.layer || builtInUsage.viewportIndex;
miscExport |= builtInUsage.primitiveShadingRate;
@@ -3003,7 +3004,7 @@ void NggPrimShader::earlyExitWithDummyExport() {
posExpCount += (builtInUsage.clipDistance + builtInUsage.cullDistance) / 4;
} else if (m_hasTes) {
- const auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->builtInUsage.tes;
+ const auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->builtInUsage.tes;
bool miscExport = builtInUsage.pointSize || builtInUsage.layer || builtInUsage.viewportIndex;
if (miscExport)
@@ -3011,7 +3012,7 @@ void NggPrimShader::earlyExitWithDummyExport() {
posExpCount += (builtInUsage.clipDistance + builtInUsage.cullDistance) / 4;
} else {
- const auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->builtInUsage.vs;
+ const auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->builtInUsage.vs;
bool miscExport = builtInUsage.pointSize || builtInUsage.layer || builtInUsage.viewportIndex;
miscExport |= builtInUsage.primitiveShadingRate;
@@ -3059,8 +3060,8 @@ void NggPrimShader::runEs(ArrayRef<Argument *> args) {
Value *esGsOffset = nullptr;
if (m_hasGs) {
- auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->inOutUsage.gs.calcFactor;
- unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStageGeometry);
+ auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->inOutUsage.gs.calcFactor;
+ unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Geometry);
unsigned esGsBytesPerWave = waveSize * sizeof(unsigned) * calcFactor.esGsRingItemSize;
esGsOffset = m_builder.CreateMul(m_nggInputs.waveIdInSubgroup, m_builder.getInt32(esGsBytesPerWave));
}
@@ -3102,8 +3103,9 @@ void NggPrimShader::runEs(ArrayRef<Argument *> args) {
// Setup attribute ring base and relative vertex index in subgroup as two additional arguments to export vertex
// attributes through memory
if (m_gfxIp.major >= 11 && !m_hasGs) { // For GS, vertex attribute exports are in copy shader
- const auto attribCount = m_pipelineState->getShaderResourceUsage(m_hasTes ? ShaderStageTessEval : ShaderStageVertex)
- ->inOutUsage.expCount;
+ const auto attribCount =
+ m_pipelineState->getShaderResourceUsage(m_hasTes ? ShaderStage::TessEval : ShaderStage::Vertex)
+ ->inOutUsage.expCount;
if (attribCount > 0) {
esArgs.push_back(m_nggInputs.attribRingBase);
esArgs.push_back(m_nggInputs.threadIdInSubgroup);
@@ -3112,7 +3114,7 @@ void NggPrimShader::runEs(ArrayRef<Argument *> args) {
// Set up user data SGPRs
const unsigned userDataCount =
- m_pipelineState->getShaderInterfaceData(m_hasTes ? ShaderStageTessEval : ShaderStageVertex)->userDataCount;
+ m_pipelineState->getShaderInterfaceData(m_hasTes ? ShaderStage::TessEval : ShaderStage::Vertex)->userDataCount;
appendUserData(esArgs, m_esHandlers.main, userData, userDataCount);
if (m_hasTes) {
@@ -3227,7 +3229,7 @@ Value *NggPrimShader::runPartEs(ArrayRef<Argument *> args, Value *position) {
m_builder.SetInsertPoint(uncompactVertexBlock);
const unsigned esGsRingItemSize =
- m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->inOutUsage.gs.calcFactor.esGsRingItemSize;
+ m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->inOutUsage.gs.calcFactor.esGsRingItemSize;
auto uncompactedVertexIndex = readPerThreadDataFromLds(m_builder.getInt32Ty(), m_nggInputs.threadIdInSubgroup,
PrimShaderLdsRegion::VertexIndexMap);
@@ -3238,7 +3240,8 @@ Value *NggPrimShader::runPartEs(ArrayRef<Argument *> args, Value *position) {
// NOTE: For deferred vertex export, some system values could be from vertex compaction info rather than from
// VGPRs (caused by NGG culling and vertex compaction)
- const auto resUsage = m_pipelineState->getShaderResourceUsage(m_hasTes ? ShaderStageTessEval : ShaderStageVertex);
+ const auto resUsage =
+ m_pipelineState->getShaderResourceUsage(m_hasTes ? ShaderStage::TessEval : ShaderStage::Vertex);
if (m_hasTes) {
if (resUsage->builtInUsage.tes.tessCoord) {
newTessCoordX =
@@ -3313,8 +3316,9 @@ Value *NggPrimShader::runPartEs(ArrayRef<Argument *> args, Value *position) {
// Setup attribute ring base and relative vertex index in subgroup as two additional arguments to export vertex
// attributes through memory
if (m_gfxIp.major >= 11 && deferredVertexExport) {
- const auto attribCount = m_pipelineState->getShaderResourceUsage(m_hasTes ? ShaderStageTessEval : ShaderStageVertex)
- ->inOutUsage.expCount;
+ const auto attribCount =
+ m_pipelineState->getShaderResourceUsage(m_hasTes ? ShaderStage::TessEval : ShaderStage::Vertex)
+ ->inOutUsage.expCount;
if (attribCount > 0) {
partEsArgs.push_back(m_nggInputs.attribRingBase);
partEsArgs.push_back(m_nggInputs.threadIdInSubgroup);
@@ -3326,7 +3330,7 @@ Value *NggPrimShader::runPartEs(ArrayRef<Argument *> args, Value *position) {
// Set up user data SGPRs
const unsigned userDataCount =
- m_pipelineState->getShaderInterfaceData(m_hasTes ? ShaderStageTessEval : ShaderStageVertex)->userDataCount;
+ m_pipelineState->getShaderInterfaceData(m_hasTes ? ShaderStage::TessEval : ShaderStage::Vertex)->userDataCount;
appendUserData(partEsArgs, partEs, userData, userDataCount);
if (m_hasTes) {
@@ -3369,7 +3373,7 @@ void NggPrimShader::splitEs() {
if (func.isIntrinsic() && func.getIntrinsicID() == Intrinsic::amdgcn_exp)
expFuncs.push_back(&func);
else if (m_gfxIp.major >= 11) {
- if (func.getName().startswith(lgcName::NggAttribExport) || func.getName().startswith(lgcName::NggXfbExport))
+ if (func.getName().starts_with(lgcName::NggAttribExport) || func.getName().starts_with(lgcName::NggXfbExport))
expFuncs.push_back(&func);
}
}
@@ -3382,7 +3386,8 @@ void NggPrimShader::splitEs() {
unsigned cullDistanceCount = 0;
if (m_nggControl->enableCullDistanceCulling) {
- const auto &resUsage = m_pipelineState->getShaderResourceUsage(m_hasTes ? ShaderStageTessEval : ShaderStageVertex);
+ const auto &resUsage =
+ m_pipelineState->getShaderResourceUsage(m_hasTes ? ShaderStage::TessEval : ShaderStage::Vertex);
if (m_hasTes) {
const auto &builtInUsage = resUsage->builtInUsage.tes;
@@ -3607,7 +3612,7 @@ void NggPrimShader::runGs(ArrayRef<Argument *> args) {
SmallVector<Value *, 32> gsArgs;
// Set up user data SGPRs
- const unsigned userDataCount = m_pipelineState->getShaderInterfaceData(ShaderStageGeometry)->userDataCount;
+ const unsigned userDataCount = m_pipelineState->getShaderInterfaceData(ShaderStage::Geometry)->userDataCount;
appendUserData(gsArgs, m_gsHandlers.main, userData, userDataCount);
// Set up system value SGPRs
@@ -3665,7 +3670,7 @@ void NggPrimShader::mutateGs() {
}
// Initialize thread ID in wave
- const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStageGeometry);
+ const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Geometry);
assert(waveSize == 32 || waveSize == 64);
auto threadIdInWave =
@@ -3677,7 +3682,7 @@ void NggPrimShader::mutateGs() {
}
// Initialize thread ID in subgroup
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageGeometry)->entryArgIdxs.gs;
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Geometry)->entryArgIdxs.gs;
auto waveId = getFunctionArgument(m_gsHandlers.main, entryArgIdxs.gsWaveId);
auto threadIdInSubgroup = m_builder.CreateMul(waveId, m_builder.getInt32(waveSize));
@@ -3685,7 +3690,7 @@ void NggPrimShader::mutateGs() {
// Handle GS message and GS output export
for (auto &func : m_gsHandlers.main->getParent()->functions()) {
- if (func.getName().startswith(lgcName::NggWriteGsOutput)) {
+ if (func.getName().starts_with(lgcName::NggWriteGsOutput)) {
// Export GS outputs to GS-VS ring
for (auto user : func.users()) {
CallInst *const call = cast<CallInst>(user);
@@ -3710,7 +3715,7 @@ void NggPrimShader::mutateGs() {
CallInst *const call = cast<CallInst>(user);
m_builder.SetInsertPoint(call);
- if (getShaderStage(call->getParent()->getParent()) != ShaderStageGeometry)
+ if (getShaderStage(call->getParent()->getParent()) != ShaderStage::Geometry)
continue; // Not belong to GS messages
uint64_t message = cast<ConstantInt>(call->getArgOperand(0))->getZExtValue();
@@ -3800,7 +3805,7 @@ void NggPrimShader::runCopyShader(ArrayRef<Argument *> args) {
if (m_gfxIp.major >= 11) {
// Setup attribute ring base and relative vertex index in subgroup as two additional arguments to export vertex
// attributes through memory
- const auto attribCount = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->inOutUsage.expCount;
+ const auto attribCount = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->inOutUsage.expCount;
if (attribCount > 0) {
copyShaderArgs.push_back(m_nggInputs.attribRingBase);
copyShaderArgs.push_back(m_nggInputs.threadIdInSubgroup);
@@ -3835,7 +3840,7 @@ void NggPrimShader::mutateCopyShader() {
SmallVector<Instruction *, 32> removedCalls;
for (auto &func : m_gsHandlers.copyShader->getParent()->functions()) {
- if (func.getName().startswith(lgcName::NggReadGsOutput)) {
+ if (func.getName().starts_with(lgcName::NggReadGsOutput)) {
// Import GS outputs from GS-VS ring
for (auto user : func.users()) {
CallInst *const call = cast<CallInst>(user);
@@ -6039,7 +6044,7 @@ Function *NggPrimShader::createFetchCullingRegister() {
Value *NggPrimShader::ballot(Value *value) {
assert(value->getType()->isIntegerTy(1)); // Should be i1
- const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStageGeometry);
+ const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Geometry);
assert(waveSize == 32 || waveSize == 64);
Value *result = m_builder.CreateIntrinsic(Intrinsic::amdgcn_ballot, m_builder.getIntNTy(waveSize), value);
@@ -6059,7 +6064,8 @@ Value *NggPrimShader::ballot(Value *value) {
void NggPrimShader::processVertexAttribExport(Function *&target) {
assert(m_gfxIp.major >= 11); // For GFX11+
- ShaderStage shaderStage = m_hasGs ? ShaderStageGeometry : (m_hasTes ? ShaderStageTessEval : ShaderStageVertex);
+ ShaderStageEnum shaderStage =
+ m_hasGs ? ShaderStage::Geometry : (m_hasTes ? ShaderStage::TessEval : ShaderStage::Vertex);
const unsigned attribCount = m_pipelineState->getShaderResourceUsage(shaderStage)->inOutUsage.expCount;
if (attribCount == 0)
return; // No vertex attribute exports
@@ -6101,7 +6107,7 @@ void NggPrimShader::processVertexAttribExport(Function *&target) {
SmallVector<CallInst *, 8> removedCalls;
for (auto &func : target->getParent()->functions()) {
- if (func.getName().startswith(lgcName::NggAttribExport)) {
+ if (func.getName().starts_with(lgcName::NggAttribExport)) {
for (auto user : func.users()) {
CallInst *const call = dyn_cast<CallInst>(user);
assert(call);
@@ -6589,7 +6595,7 @@ void NggPrimShader::processSwXfbWithGs(ArrayRef<Argument *> args) {
assert(m_pipelineState->enableSwXfb());
assert(m_hasGs); // GS is present
- const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStageGeometry);
+ const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Geometry);
assert(waveSize == 32 || waveSize == 64);
const unsigned waveCountInSubgroup = Gfx9::NggMaxThreadsPerSubgroup / waveSize;
@@ -7247,7 +7253,8 @@ Value *NggPrimShader::fetchXfbOutput(Function *target, ArrayRef<Argument *> args
const unsigned xfbOutputCount =
m_pipelineState
- ->getShaderResourceUsage(m_hasGs ? ShaderStageGeometry : (m_hasTes ? ShaderStageTessEval : ShaderStageVertex))
+ ->getShaderResourceUsage(m_hasGs ? ShaderStage::Geometry
+ : (m_hasTes ? ShaderStage::TessEval : ShaderStage::Vertex))
->inOutUsage.xfbExpCount;
// Skip following handling if transform feedback output is empty
@@ -7265,11 +7272,11 @@ Value *NggPrimShader::fetchXfbOutput(Function *target, ArrayRef<Argument *> args
SmallVector<Function *, 8> expFuncs;
for (auto &func : target->getParent()->functions()) {
if (dontClone) {
- if (func.getName().startswith(lgcName::NggXfbExport))
+ if (func.getName().starts_with(lgcName::NggXfbExport))
expFuncs.push_back(&func);
} else {
if ((func.isIntrinsic() && func.getIntrinsicID() == Intrinsic::amdgcn_exp) ||
- func.getName().startswith(lgcName::NggAttribExport) || func.getName().startswith(lgcName::NggXfbExport))
+ func.getName().starts_with(lgcName::NggAttribExport) || func.getName().starts_with(lgcName::NggXfbExport))
expFuncs.push_back(&func);
}
}
@@ -7338,7 +7345,7 @@ Value *NggPrimShader::fetchXfbOutput(Function *target, ArrayRef<Argument *> args
if (!dontClone) {
// Remove transform feedback export calls from the target function. No need of doing this if we
// just mutate it without cloning.
- if (call->getFunction() == target && func->getName().startswith(lgcName::NggXfbExport)) {
+ if (call->getFunction() == target && func->getName().starts_with(lgcName::NggXfbExport)) {
removedCalls.push_back(call);
continue;
}
@@ -7349,7 +7356,7 @@ Value *NggPrimShader::fetchXfbOutput(Function *target, ArrayRef<Argument *> args
assert(call->getParent() == retBlock); // Must in return block
- if (func->getName().startswith(lgcName::NggXfbExport)) {
+ if (func->getName().starts_with(lgcName::NggXfbExport)) {
// Lower transform feedback export calls
auto xfbBuffer = cast<ConstantInt>(call->getArgOperand(0))->getZExtValue();
auto xfbOffset = cast<ConstantInt>(call->getArgOperand(1))->getZExtValue();
@@ -7367,7 +7374,7 @@ Value *NggPrimShader::fetchXfbOutput(Function *target, ArrayRef<Argument *> args
if (m_hasGs) {
// NOTE: For GS, the output value must be loaded by GS read output call. This is generated by copy shader.
CallInst *readCall = dyn_cast<CallInst>(outputValue);
- assert(readCall && readCall->getCalledFunction()->getName().startswith(lgcName::NggReadGsOutput));
+ assert(readCall && readCall->getCalledFunction()->getName().starts_with(lgcName::NggReadGsOutput));
streamId = cast<ConstantInt>(call->getArgOperand(2))->getZExtValue();
assert(streamId == cast<ConstantInt>(readCall->getArgOperand(2))->getZExtValue()); // Stream ID must match
location = cast<ConstantInt>(readCall->getArgOperand(0))->getZExtValue();
@@ -7486,7 +7493,7 @@ Value *NggPrimShader::fetchXfbOutput(Function *target, ArrayRef<Argument *> args
// attributes through memory
if (m_gfxIp.major >= 11 && !m_hasGs) { // For GS, vertex attribute exports are in copy shader
const auto attribCount =
- m_pipelineState->getShaderResourceUsage(m_hasTes ? ShaderStageTessEval : ShaderStageVertex)
+ m_pipelineState->getShaderResourceUsage(m_hasTes ? ShaderStage::TessEval : ShaderStage::Vertex)
->inOutUsage.expCount;
if (attribCount > 0) {
xfbFetcherArgs.push_back(m_nggInputs.attribRingBase);
@@ -7497,7 +7504,7 @@ Value *NggPrimShader::fetchXfbOutput(Function *target, ArrayRef<Argument *> args
// Set up user data SGPRs
const unsigned userDataCount =
- m_pipelineState->getShaderInterfaceData(m_hasTes ? ShaderStageTessEval : ShaderStageVertex)->userDataCount;
+ m_pipelineState->getShaderInterfaceData(m_hasTes ? ShaderStage::TessEval : ShaderStage::Vertex)->userDataCount;
appendUserData(xfbFetcherArgs, xfbFetcher, userData, userDataCount);
if (m_hasTes) {
@@ -7789,7 +7796,7 @@ Value *NggPrimShader::readXfbOutputFromLds(Type *readDataTy, Value *vertexIndex,
assert(!m_hasGs);
const unsigned esGsRingItemSize =
- m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->inOutUsage.gs.calcFactor.esGsRingItemSize;
+ m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->inOutUsage.gs.calcFactor.esGsRingItemSize;
auto vertexItemOffset = m_builder.CreateMul(vertexIndex, m_builder.getInt32(esGsRingItemSize));
if (m_nggControl->passthroughMode) {
@@ -7818,7 +7825,7 @@ void NggPrimShader::writeXfbOutputToLds(Value *writeData, Value *vertexIndex, un
assert(!m_hasGs);
const unsigned esGsRingItemSize =
- m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->inOutUsage.gs.calcFactor.esGsRingItemSize;
+ m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->inOutUsage.gs.calcFactor.esGsRingItemSize;
auto vertexItemOffset = m_builder.CreateMul(vertexIndex, m_builder.getInt32(esGsRingItemSize));
if (m_nggControl->passthroughMode) {
@@ -7849,7 +7856,7 @@ Value *NggPrimShader::fetchVertexPositionData(Value *vertexIndex) {
}
// ES-GS
- auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->inOutUsage;
+ auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->inOutUsage;
assert(inOutUsage.builtInOutputLocMap.find(BuiltInPosition) != inOutUsage.builtInOutputLocMap.end());
const unsigned loc = inOutUsage.builtInOutputLocMap[BuiltInPosition];
const unsigned rasterStream = m_pipelineState->getRasterizerState().rasterStream;
@@ -7868,20 +7875,20 @@ Value *NggPrimShader::fetchCullDistanceSignMask(Value *vertexIndex) {
if (!m_hasGs) {
// ES-only
const unsigned esGsRingItemSize =
- m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->inOutUsage.gs.calcFactor.esGsRingItemSize;
+ m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->inOutUsage.gs.calcFactor.esGsRingItemSize;
auto vertexItemOffset = m_builder.CreateMul(vertexIndex, m_builder.getInt32(esGsRingItemSize));
return readVertexCullInfoFromLds(m_builder.getInt32Ty(), vertexItemOffset,
m_vertCullInfoOffsets.cullDistanceSignMask);
}
// ES-GS
- auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->inOutUsage;
+ auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->inOutUsage;
assert(inOutUsage.builtInOutputLocMap.find(BuiltInCullDistance) != inOutUsage.builtInOutputLocMap.end());
const unsigned loc = inOutUsage.builtInOutputLocMap[BuiltInCullDistance];
const unsigned rasterStream = m_pipelineState->getRasterizerState().rasterStream;
auto vertexOffset = calcVertexItemOffset(rasterStream, vertexIndex);
- auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->builtInUsage.gs;
+ auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->builtInUsage.gs;
auto cullDistances = readGsOutput(ArrayType::get(m_builder.getFloatTy(), builtInUsage.cullDistance), loc, 0,
rasterStream, vertexOffset);
@@ -7907,7 +7914,7 @@ Value *NggPrimShader::fetchCullDistanceSignMask(Value *vertexIndex) {
Value *NggPrimShader::calcVertexItemOffset(unsigned streamId, Value *vertexIndex) {
assert(m_hasGs); // GS must be present
- auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->inOutUsage;
+ auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->inOutUsage;
// vertexOffset = gsVsRingStart + streamBases[stream] + vertexIndex * vertexItemSize (in dwords)
const unsigned vertexItemSize = 4 * inOutUsage.gs.outLocCount[streamId];
diff --git a/lgc/patch/NggPrimShader.h b/lgc/patch/NggPrimShader.h
index 3c9defd434..b7fce9bc3b 100644
--- a/lgc/patch/NggPrimShader.h
+++ b/lgc/patch/NggPrimShader.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/patch/PassRegistry.inc b/lgc/patch/PassRegistry.inc
index 9ede6c656d..165f02e918 100644
--- a/lgc/patch/PassRegistry.inc
+++ b/lgc/patch/PassRegistry.inc
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -78,6 +78,7 @@ LLPC_MODULE_PASS("lgc-patch-image-op-collect", PatchImageOpCollect)
LLPC_MODULE_PASS("lgc-vertex-fetch", LowerVertexFetch)
LLPC_MODULE_PASS("lgc-frag-color-export", LowerFragColorExport)
LLPC_MODULE_PASS("lgc-lower-debug-printf", LowerDebugPrintf)
+LLPC_MODULE_PASS("lgc-lower-desc", LowerDesc)
LLPC_FUNCTION_PASS("lgc-combine-cooperative-matrix", CombineCooperativeMatrix)
LLPC_MODULE_PASS("lgc-lower-cooperative-matrix", LowerCooperativeMatrix)
diff --git a/lgc/patch/Patch.cpp b/lgc/patch/Patch.cpp
index 38689b69dc..ba78672338 100644
--- a/lgc/patch/Patch.cpp
+++ b/lgc/patch/Patch.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -40,6 +40,7 @@
#include "lgc/patch/FragColorExport.h"
#include "lgc/patch/LowerCooperativeMatrix.h"
#include "lgc/patch/LowerDebugPrintf.h"
+#include "lgc/patch/LowerDesc.h"
#include "lgc/patch/LowerGpuRt.h"
#include "lgc/patch/PatchBufferOp.h"
#include "lgc/patch/PatchCheckShaderCache.h"
@@ -135,7 +136,7 @@ void Patch::addPasses(PipelineState *pipelineState, lgc::PassManager &passMgr, T
if (pipelineState->getOptions().useGpurt) {
// NOTE: Lower GPURT operations and run InstCombinePass before builder replayer, because some Op are going to be
- // turned into constant value, so that we can eliminate unused `@lgc.create.load.buffer.desc` before getting into
+ // turned into constant value, so that we can eliminate unused `@lgc.load.buffer.desc` before getting into
// replayer. Otherwise, unnecessary `writes_uavs` and `uses_uav` may be set.
passMgr.addPass(LowerGpuRt());
passMgr.addPass(createModuleToFunctionPassAdaptor(InstCombinePass()));
@@ -168,8 +169,8 @@ void Patch::addPasses(PipelineState *pipelineState, lgc::PassManager &passMgr, T
// Lower the cooperative matrix
passMgr.addPass(LowerCooperativeMatrix());
- if (pipelineState->hasShaderStage(ShaderStageVertex) && !pipelineState->hasShaderStage(ShaderStageTessControl) &&
- pipelineState->hasShaderStage(ShaderStageTessEval))
+ if (pipelineState->hasShaderStage(ShaderStage::Vertex) && !pipelineState->hasShaderStage(ShaderStage::TessControl) &&
+ pipelineState->hasShaderStage(ShaderStage::TessEval))
passMgr.addPass(TcsPassthroughShader());
passMgr.addPass(PatchNullFragShader());
@@ -183,15 +184,11 @@ void Patch::addPasses(PipelineState *pipelineState, lgc::PassManager &passMgr, T
passMgr.addPass(PatchCopyShader());
passMgr.addPass(LowerVertexFetch());
passMgr.addPass(LowerFragColorExport());
+ passMgr.addPass(LowerDesc());
passMgr.addPass(PatchEntryPointMutate());
passMgr.addPass(PatchInitializeWorkgroupMemory());
passMgr.addPass(PatchInOutImportExport());
- // Prior to general optimization, do function inlining and dead function removal to remove helper functions that
- // were introduced during lowering (e.g. streamout stores).
- passMgr.addPass(AlwaysInlinerPass());
- passMgr.addPass(GlobalDCEPass());
-
// Patch invariant load and loop metadata.
passMgr.addPass(createModuleToFunctionPassAdaptor(PatchInvariantLoads()));
passMgr.addPass(createModuleToFunctionPassAdaptor(createFunctionToLoopPassAdaptor(PatchLoopMetadata())));
@@ -215,6 +212,10 @@ void Patch::addPasses(PipelineState *pipelineState, lgc::PassManager &passMgr, T
// Second part of lowering to "AMDGCN-style"
passMgr.addPass(PatchPreparePipelineAbi());
+ // Do inlining and global DCE to inline subfunctions that were introduced during preparing pipeline ABI.
+ passMgr.addPass(AlwaysInlinerPass());
+ passMgr.addPass(GlobalDCEPass());
+
const bool canUseNgg = pipelineState->isGraphics() &&
((pipelineState->getTargetInfo().getGfxIpVersion().major == 10 &&
(pipelineState->getOptions().nggFlags & NggFlagDisable) == 0) ||
@@ -226,8 +227,6 @@ void Patch::addPasses(PipelineState *pipelineState, lgc::PassManager &passMgr, T
}
// Extra optimizations after NGG primitive shader creation
- passMgr.addPass(AlwaysInlinerPass());
- passMgr.addPass(GlobalDCEPass());
FunctionPassManager fpm;
fpm.addPass(PromotePass());
fpm.addPass(ADCEPass());
@@ -455,7 +454,7 @@ void Patch::addOptimizationPasses(lgc::PassManager &passMgr, uint32_t optLevel)
void Patch::init(Module *module) {
m_module = module;
m_context = &m_module->getContext();
- m_shaderStage = ShaderStageInvalid;
+ m_shaderStage = ShaderStage::Invalid;
m_entryPoint = nullptr;
}
diff --git a/lgc/patch/PatchBufferOp.cpp b/lgc/patch/PatchBufferOp.cpp
index 3d89ea6ada..49b29dcb7d 100644
--- a/lgc/patch/PatchBufferOp.cpp
+++ b/lgc/patch/PatchBufferOp.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -145,9 +145,19 @@ static SmallVector<Type *> convertBufferPointer(TypeLowering &typeLowering, Type
SmallVector<Type *> types;
if (auto *pointerType = dyn_cast<PointerType>(type)) {
- if (pointerType->getAddressSpace() == ADDR_SPACE_BUFFER_FAT_POINTER) {
- types.push_back(FixedVectorType::get(Type::getInt32Ty(type->getContext()), 4));
- types.push_back(PointerType::get(type->getContext(), ADDR_SPACE_CONST_32BIT));
+ auto &context = type->getContext();
+ switch (pointerType->getAddressSpace()) {
+ case ADDR_SPACE_BUFFER_FAT_POINTER:
+ types.push_back(FixedVectorType::get(Type::getInt32Ty(context), 4));
+ types.push_back(PointerType::get(context, ADDR_SPACE_CONST_32BIT));
+ break;
+ case ADDR_SPACE_BUFFER_STRIDED_POINTER:
+ types.push_back(FixedVectorType::get(Type::getInt32Ty(context), 4));
+ types.push_back(PointerType::get(context, ADDR_SPACE_CONST_32BIT));
+ types.push_back(Type::getInt32Ty(context));
+ break;
+ default:
+ break;
}
}
@@ -186,6 +196,9 @@ void BufferOpLowering::registerVisitors(llvm_dialects::VisitorBuilder<BufferOpLo
builder.add(&BufferOpLowering::visitAtomicRMWInst);
builder.add(&BufferOpLowering::visitBitCastInst);
builder.add(&BufferOpLowering::visitBufferDescToPtr);
+ builder.add(&BufferOpLowering::visitStridedBufferDescToPtr);
+ builder.add(&BufferOpLowering::visitStridedBufferAddrAndStrideToPtr);
+ builder.add(&BufferOpLowering::visitStridedIndexAdd);
builder.add(&BufferOpLowering::visitBufferLength);
builder.add(&BufferOpLowering::visitBufferPtrDiff);
builder.add(&BufferOpLowering::visitGetElementPtrInst);
@@ -330,13 +343,23 @@ BufferOpLowering::DescriptorInfo BufferOpLowering::getDescriptorInfo(Value *desc
return m_descriptors.find(desc)->second;
}
+// =====================================================================================================================
+// Determine if a value is a buffer pointer. A buffer pointer is either a BUFFER_FAT_POINTER or
+// a BUFFER_STRIDED_POINTER
+//
+// @param value : The value to check
+bool BufferOpLowering::isAnyBufferPointer(const Value *const value) {
+ return value->getType() == m_builder.getPtrTy(ADDR_SPACE_BUFFER_FAT_POINTER) ||
+ value->getType() == m_builder.getPtrTy(ADDR_SPACE_BUFFER_STRIDED_POINTER);
+}
+
// =====================================================================================================================
// Visits "cmpxchg" instruction.
//
// @param atomicCmpXchgInst : The instruction
void BufferOpLowering::visitAtomicCmpXchgInst(AtomicCmpXchgInst &atomicCmpXchgInst) {
- // If the type we are doing an atomic operation on is not a fat pointer, bail.
- if (atomicCmpXchgInst.getPointerAddressSpace() != ADDR_SPACE_BUFFER_FAT_POINTER)
+ // If the type we are doing an atomic operation on is not a buffer pointer, bail.
+ if (!isAnyBufferPointer(atomicCmpXchgInst.getPointerOperand()))
return;
m_builder.SetInsertPoint(&atomicCmpXchgInst);
@@ -437,7 +460,7 @@ void BufferOpLowering::visitAtomicCmpXchgInst(AtomicCmpXchgInst &atomicCmpXchgIn
//
// @param atomicRmwInst : The instruction
void BufferOpLowering::visitAtomicRMWInst(AtomicRMWInst &atomicRmwInst) {
- if (atomicRmwInst.getPointerAddressSpace() == ADDR_SPACE_BUFFER_FAT_POINTER) {
+ if (isAnyBufferPointer(atomicRmwInst.getPointerOperand())) {
m_builder.SetInsertPoint(&atomicRmwInst);
auto values = m_typeLowering.getValue(atomicRmwInst.getPointerOperand());
@@ -623,14 +646,8 @@ void BufferOpLowering::visitAtomicRMWInst(AtomicRMWInst &atomicRmwInst) {
//
// @param bitCastInst : The instruction
void BufferOpLowering::visitBitCastInst(BitCastInst &bitCastInst) {
- Type *const destType = bitCastInst.getType();
-
- // If the type is not a pointer type, bail.
- if (!destType->isPointerTy())
- return;
-
- // If the pointer is not a fat pointer, bail.
- if (destType->getPointerAddressSpace() != ADDR_SPACE_BUFFER_FAT_POINTER)
+ // If the pointer is not a buffer pointer, bail.
+ if (!isAnyBufferPointer(&bitCastInst))
return;
m_typeLowering.replaceInstruction(&bitCastInst, m_typeLowering.getValue(bitCastInst.getOperand(0)));
@@ -643,20 +660,125 @@ void BufferOpLowering::visitBitCastInst(BitCastInst &bitCastInst) {
void BufferOpLowering::visitBufferDescToPtr(BufferDescToPtrOp &descToPtr) {
m_builder.SetInsertPoint(&descToPtr);
- Constant *const nullPointer = ConstantPointerNull::get(m_offsetType);
- m_typeLowering.replaceInstruction(&descToPtr, {descToPtr.getDesc(), nullPointer});
+ auto *descriptor = descToPtr.getDesc();
+ m_typeLowering.replaceInstruction(&descToPtr, {descriptor, ConstantPointerNull::get(m_offsetType)});
+
+ auto &di = m_descriptors[descriptor];
+
+#if LLVM_MAIN_REVISION && LLVM_MAIN_REVISION < 458033
+ // Old version of the code
+ di.divergent = m_uniformityInfo.isDivergent(*descriptor);
+#else
+ // New version of the code (also handles unknown version, which we treat as latest)
+ di.divergent = m_uniformityInfo.isDivergent(descriptor);
+#endif
+}
+
+// =====================================================================================================================
+// Visits "strided.buffer.desc.to.ptr" instruction.
+//
+// @param descToPtr : The instruction
+void BufferOpLowering::visitStridedBufferDescToPtr(StridedBufferDescToPtrOp &descToPtr) {
+ m_builder.SetInsertPoint(&descToPtr);
+
+ auto *descriptor = descToPtr.getDesc();
+ m_typeLowering.replaceInstruction(&descToPtr,
+ {descriptor, ConstantPointerNull::get(m_offsetType), m_builder.getInt32(0)});
+
+ auto &di = m_descriptors[descriptor];
+
+#if LLVM_MAIN_REVISION && LLVM_MAIN_REVISION < 458033
+ // Old version of the code
+ di.divergent = m_uniformityInfo.isDivergent(*descriptor);
+#else
+ // New version of the code (also handles unknown version, which we treat as latest)
+ di.divergent = m_uniformityInfo.isDivergent(descriptor);
+#endif
+}
+
+// =====================================================================================================================
+// Visits "strided.buffer.addr.and.stride.to.ptr" instruction.
+//
+// @param addrAndStrideToPtr : The instruction
+void BufferOpLowering::visitStridedBufferAddrAndStrideToPtr(StridedBufferAddrAndStrideToPtrOp &addrAndStrideToPtr) {
+ m_builder.SetInsertPoint(&addrAndStrideToPtr);
+
+ auto *addrLo = m_builder.CreateTrunc(addrAndStrideToPtr.getAddress(), m_builder.getInt32Ty());
+
+ // Build normal buffer descriptor
+ // Dword 0
+ Value *bufDesc = PoisonValue::get(FixedVectorType::get(m_builder.getInt32Ty(), 4));
+ bufDesc = m_builder.CreateInsertElement(bufDesc, addrLo, uint64_t(0));
+
+ // Dword 1
+ auto *addrHi =
+ m_builder.CreateTrunc(m_builder.CreateLShr(addrAndStrideToPtr.getAddress(), 32), m_builder.getInt32Ty());
+ auto *stride = m_builder.CreateShl(addrAndStrideToPtr.getStride(), 16);
+ addrHi = m_builder.CreateOr(addrHi, stride);
+ bufDesc = m_builder.CreateInsertElement(bufDesc, addrHi, 1);
+
+ // Dword 2
+ SqBufRsrcWord2 sqBufRsrcWord2{};
+ sqBufRsrcWord2.bits.numRecords = UINT32_MAX;
+ bufDesc = m_builder.CreateInsertElement(bufDesc, m_builder.getInt32(sqBufRsrcWord2.u32All), 2);
+
+ // Dword 3
+ SqBufRsrcWord3 sqBufRsrcWord3{};
+ sqBufRsrcWord3.bits.dstSelX = BUF_DST_SEL_X;
+ sqBufRsrcWord3.bits.dstSelY = BUF_DST_SEL_Y;
+ sqBufRsrcWord3.bits.dstSelZ = BUF_DST_SEL_Z;
+ sqBufRsrcWord3.bits.dstSelW = BUF_DST_SEL_W;
+
+ auto gfxIp = m_pipelineState.getTargetInfo().getGfxIpVersion();
+ if (gfxIp.major == 10) {
+ sqBufRsrcWord3.gfx10.format = BUF_FORMAT_32_UINT;
+ sqBufRsrcWord3.gfx10.resourceLevel = 1;
+ sqBufRsrcWord3.gfx10.oobSelect = 2;
+ assert(sqBufRsrcWord3.u32All == 0x21014FAC);
+ } else if (gfxIp.major >= 11) {
+ sqBufRsrcWord3.gfx11.format = BUF_FORMAT_32_UINT;
+ sqBufRsrcWord3.gfx11.oobSelect = 2;
+ assert(sqBufRsrcWord3.u32All == 0x20014FAC);
+ } else {
+ llvm_unreachable("Not implemented!");
+ }
+ bufDesc = m_builder.CreateInsertElement(bufDesc, m_builder.getInt32(sqBufRsrcWord3.u32All), 3);
- auto &di = m_descriptors[descToPtr.getDesc()];
+ Constant *const nullPointerOff = ConstantPointerNull::get(m_offsetType);
+ m_typeLowering.replaceInstruction(&addrAndStrideToPtr, {bufDesc, nullPointerOff, m_builder.getInt32(0)});
+
+ auto &di = m_descriptors[bufDesc];
#if LLVM_MAIN_REVISION && LLVM_MAIN_REVISION < 458033
// Old version of the code
- di.divergent = m_uniformityInfo.isDivergent(*descToPtr.getDesc());
+ di.divergent = m_uniformityInfo.isDivergent(*bufDesc);
#else
// New version of the code (also handles unknown version, which we treat as latest)
- di.divergent = m_uniformityInfo.isDivergent(descToPtr.getDesc());
+ di.divergent = m_uniformityInfo.isDivergent(bufDesc);
#endif
}
+// =====================================================================================================================
+// Visits "strided.index.add" instruction.
+//
+// @param indexAdd : The instruction
+void BufferOpLowering::visitStridedIndexAdd(StridedIndexAddOp &indexAdd) {
+ auto values = m_typeLowering.getValue(indexAdd.getPtr());
+ auto deltaIndex = indexAdd.getDeltaIdx();
+
+ if (auto deltaIndexInt = dyn_cast<ConstantInt>(deltaIndex); deltaIndexInt && deltaIndexInt->isZero()) {
+ m_typeLowering.replaceInstruction(&indexAdd, values);
+ return;
+ }
+
+ // If the old index zero, we can skip the addition and just take the delta index
+ // Otherwise, we need to add the delta index to the old one.
+ if (auto oldIndexInt = dyn_cast<ConstantInt>(values[2]); !oldIndexInt || !(oldIndexInt->isZero()))
+ deltaIndex = m_builder.CreateAdd(values[2], deltaIndex);
+
+ m_typeLowering.replaceInstruction(&indexAdd, {values[0], values[1], deltaIndex});
+}
+
// =====================================================================================================================
// Visits "buffer.length" instruction.
//
@@ -718,8 +840,8 @@ void BufferOpLowering::visitBufferPtrDiff(BufferPtrDiffOp &ptrDiff) {
//
// @param getElemPtrInst : The instruction
void BufferOpLowering::visitGetElementPtrInst(GetElementPtrInst &getElemPtrInst) {
- // If the type we are GEPing into is not a fat pointer, bail.
- if (getElemPtrInst.getAddressSpace() != ADDR_SPACE_BUFFER_FAT_POINTER)
+ // If the type we are GEPing into is not a fat or strided pointer, bail.
+ if (!isAnyBufferPointer(getElemPtrInst.getPointerOperand()))
return;
m_builder.SetInsertPoint(&getElemPtrInst);
@@ -739,7 +861,10 @@ void BufferOpLowering::visitGetElementPtrInst(GetElementPtrInst &getElemPtrInst)
copyMetadata(newGetElemPtr, &getElemPtrInst);
- m_typeLowering.replaceInstruction(&getElemPtrInst, {values[0], newGetElemPtr});
+ if (getElemPtrInst.getAddressSpace() == ADDR_SPACE_BUFFER_STRIDED_POINTER)
+ m_typeLowering.replaceInstruction(&getElemPtrInst, {values[0], newGetElemPtr, values[2]});
+ else
+ m_typeLowering.replaceInstruction(&getElemPtrInst, {values[0], newGetElemPtr});
}
// =====================================================================================================================
@@ -747,9 +872,9 @@ void BufferOpLowering::visitGetElementPtrInst(GetElementPtrInst &getElemPtrInst)
//
// @param loadInst : The instruction
void BufferOpLowering::visitLoadInst(LoadInst &loadInst) {
- const unsigned addrSpace = loadInst.getPointerAddressSpace();
+ const auto pointerOperand = loadInst.getPointerOperand();
- if (addrSpace != ADDR_SPACE_BUFFER_FAT_POINTER)
+ if (!isAnyBufferPointer(pointerOperand))
return;
m_postVisitInsts.push_back(&loadInst);
@@ -776,11 +901,8 @@ void BufferOpLowering::visitMemCpyInst(MemCpyInst &memCpyInst) {
Value *const dest = memCpyInst.getArgOperand(0);
Value *const src = memCpyInst.getArgOperand(1);
- const unsigned destAddrSpace = dest->getType()->getPointerAddressSpace();
- const unsigned srcAddrSpace = src->getType()->getPointerAddressSpace();
-
- // If either of the address spaces are fat pointers.
- if (destAddrSpace == ADDR_SPACE_BUFFER_FAT_POINTER || srcAddrSpace == ADDR_SPACE_BUFFER_FAT_POINTER) {
+ // If either of the address spaces are buffer pointers.
+ if (isAnyBufferPointer(src) || isAnyBufferPointer(dest)) {
// Handling memcpy requires us to modify the CFG, so we need to do it after the initial visit pass.
m_postVisitInsts.push_back(&memCpyInst);
}
@@ -794,11 +916,8 @@ void BufferOpLowering::visitMemMoveInst(MemMoveInst &memMoveInst) {
Value *const dest = memMoveInst.getArgOperand(0);
Value *const src = memMoveInst.getArgOperand(1);
- const unsigned destAddrSpace = dest->getType()->getPointerAddressSpace();
- const unsigned srcAddrSpace = src->getType()->getPointerAddressSpace();
-
- // If either of the address spaces are not fat pointers, bail.
- if (destAddrSpace != ADDR_SPACE_BUFFER_FAT_POINTER && srcAddrSpace != ADDR_SPACE_BUFFER_FAT_POINTER)
+ // If either of the address spaces are not buffer pointers, bail.
+ if (!isAnyBufferPointer(dest) || !isAnyBufferPointer(src))
return;
m_builder.SetInsertPoint(&memMoveInst);
@@ -833,10 +952,8 @@ void BufferOpLowering::visitMemMoveInst(MemMoveInst &memMoveInst) {
void BufferOpLowering::visitMemSetInst(MemSetInst &memSetInst) {
Value *const dest = memSetInst.getArgOperand(0);
- const unsigned destAddrSpace = dest->getType()->getPointerAddressSpace();
-
- // If the address spaces is a fat pointer.
- if (destAddrSpace == ADDR_SPACE_BUFFER_FAT_POINTER) {
+ // If the address spaces is a buffer pointer.
+ if (isAnyBufferPointer(dest)) {
// Handling memset requires us to modify the CFG, so we need to do it after the initial visit pass.
m_postVisitInsts.push_back(&memSetInst);
}
@@ -850,14 +967,15 @@ void BufferOpLowering::visitMemSetInst(MemSetInst &memSetInst) {
//
// We do this because:
//
-// - phi nodes of fat pointers are very often divergent, but the descriptor part is actually uniform; only the offset
+// - phi nodes of buffer pointers are very often divergent, but the descriptor part is actually uniform; only the
+// offset
// part that is divergent. So we do our own mini-divergence analysis on the descriptor values after the first visitor
// pass.
// - TypeLowering helps us by automatically eliminating descriptor phi nodes in typical cases where they're redundant.
//
// @param phi : The instruction
void BufferOpLowering::visitPhiInst(llvm::PHINode &phi) {
- if (!phi.getType()->isPointerTy() || phi.getType()->getPointerAddressSpace() != ADDR_SPACE_BUFFER_FAT_POINTER)
+ if (!isAnyBufferPointer(&phi))
return;
#if LLVM_MAIN_REVISION && LLVM_MAIN_REVISION < 458033
@@ -875,8 +993,8 @@ void BufferOpLowering::visitPhiInst(llvm::PHINode &phi) {
//
// @param storeInst : The instruction
void BufferOpLowering::visitStoreInst(StoreInst &storeInst) {
- // If the address space of the store pointer is not a buffer fat pointer, bail.
- if (storeInst.getPointerAddressSpace() != ADDR_SPACE_BUFFER_FAT_POINTER)
+ // If the address space of the store pointer is not a buffer pointer, bail.
+ if (!isAnyBufferPointer(storeInst.getPointerOperand()))
return;
m_postVisitInsts.push_back(&storeInst);
@@ -899,14 +1017,10 @@ void BufferOpLowering::postVisitStoreInst(StoreInst &storeInst) {
//
// @param icmpInst : The instruction
void BufferOpLowering::visitICmpInst(ICmpInst &icmpInst) {
- Type *const type = icmpInst.getOperand(0)->getType();
-
- // If the type is not a pointer type, bail.
- if (!type->isPointerTy())
- return;
+ Value *const pointer = icmpInst.getOperand(0);
// If the pointer is not a fat pointer, bail.
- if (type->getPointerAddressSpace() != ADDR_SPACE_BUFFER_FAT_POINTER)
+ if (!isAnyBufferPointer(pointer))
return;
m_builder.SetInsertPoint(&icmpInst);
@@ -950,7 +1064,7 @@ void BufferOpLowering::visitICmpInst(ICmpInst &icmpInst) {
// @param intrinsic : The intrinsic
void BufferOpLowering::visitInvariantStart(llvm::IntrinsicInst &intrinsic) {
Value *ptr = intrinsic.getArgOperand(1);
- if (ptr->getType()->getPointerAddressSpace() != ADDR_SPACE_BUFFER_FAT_POINTER)
+ if (!isAnyBufferPointer(ptr))
return;
auto values = m_typeLowering.getValue(ptr);
@@ -1038,9 +1152,9 @@ void BufferOpLowering::postVisitMemCpyInst(MemCpyInst &memCpyInst) {
if (GetElementPtrInst *const getElemPtr = dyn_cast<GetElementPtrInst>(destPtr))
visitGetElementPtrInst(*getElemPtr);
- if (srcPtr->getType()->getPointerAddressSpace() == ADDR_SPACE_BUFFER_FAT_POINTER)
+ if (isAnyBufferPointer(srcPtr))
postVisitLoadInst(*srcLoad);
- if (destPtr->getType()->getPointerAddressSpace() == ADDR_SPACE_BUFFER_FAT_POINTER)
+ if (isAnyBufferPointer(destPtr))
postVisitStoreInst(*destStore);
} else {
// Get an vector type that is the length of the memcpy.
@@ -1052,9 +1166,9 @@ void BufferOpLowering::postVisitMemCpyInst(MemCpyInst &memCpyInst) {
StoreInst *const destStore = m_builder.CreateAlignedStore(srcLoad, dest, destAlignment);
copyMetadata(destStore, &memCpyInst);
- if (src->getType()->getPointerAddressSpace() == ADDR_SPACE_BUFFER_FAT_POINTER)
+ if (isAnyBufferPointer(src))
postVisitLoadInst(*srcLoad);
- if (dest->getType()->getPointerAddressSpace() == ADDR_SPACE_BUFFER_FAT_POINTER)
+ if (isAnyBufferPointer(dest))
postVisitStoreInst(*destStore);
}
@@ -1408,7 +1522,13 @@ Value *BufferOpLowering::replaceLoadStore(Instruction &inst) {
// TODO For stores?
coherent.bits.dlc = isDlc;
}
- if (isInvariant && accessSize >= 4) {
+ if (pointerOperand->getType()->getPointerAddressSpace() == ADDR_SPACE_BUFFER_STRIDED_POINTER) {
+ CallInst *call = m_builder.CreateIntrinsic(
+ Intrinsic::amdgcn_struct_buffer_load, intAccessType,
+ {bufferDesc, pointerValues[2], offsetVal, m_builder.getInt32(0), m_builder.getInt32(coherent.u32All)});
+ copyMetadata(call, &inst);
+ part = call;
+ } else if (isInvariant && accessSize >= 4) {
CallInst *call = m_builder.CreateIntrinsic(Intrinsic::amdgcn_s_buffer_load, intAccessType,
{bufferDesc, offsetVal, m_builder.getInt32(coherent.u32All)});
call->setMetadata(LLVMContext::MD_invariant_load, MDNode::get(m_builder.getContext(), {}));
@@ -1436,9 +1556,15 @@ Value *BufferOpLowering::replaceLoadStore(Instruction &inst) {
}
part = m_builder.CreateBitCast(part, intAccessType);
copyMetadata(part, &inst);
- part = m_builder.CreateIntrinsic(
- Intrinsic::amdgcn_raw_buffer_store, intAccessType,
- {part, bufferDesc, offsetVal, m_builder.getInt32(0), m_builder.getInt32(coherent.u32All)});
+ if (pointerOperand->getType()->getPointerAddressSpace() == ADDR_SPACE_BUFFER_STRIDED_POINTER) {
+ part = m_builder.CreateIntrinsic(Intrinsic::amdgcn_struct_buffer_store, intAccessType,
+ {part, bufferDesc, pointerValues[2], offsetVal, m_builder.getInt32(0),
+ m_builder.getInt32(coherent.u32All)});
+ } else {
+ part = m_builder.CreateIntrinsic(
+ Intrinsic::amdgcn_raw_buffer_store, intAccessType,
+ {part, bufferDesc, offsetVal, m_builder.getInt32(0), m_builder.getInt32(coherent.u32All)});
+ }
}
copyMetadata(part, &inst);
@@ -1480,7 +1606,7 @@ Value *BufferOpLowering::replaceLoadStore(Instruction &inst) {
assert(newInst);
if (type->isPointerTy()) {
- assert(type->getPointerAddressSpace() != ADDR_SPACE_BUFFER_FAT_POINTER);
+ assert(!isAnyBufferPointer(&inst));
newInst = m_builder.CreateBitCast(newInst, m_builder.getIntNTy(bytesToHandle * 8));
copyMetadata(newInst, &inst);
newInst = m_builder.CreateIntToPtr(newInst, type);
@@ -1584,19 +1710,30 @@ Value *BufferOpLowering::createGlobalPointerAccess(Value *const bufferDesc, Valu
// Global pointer access
m_builder.SetInsertPoint(terminator);
Value *baseAddr = getBaseAddressFromBufferDesc(bufferDesc);
- // NOTE: The offset of out-of-bound overridden as 0 may causes unexpected result when the extended robustness access
- // is disabled.
- Value *newOffset = m_builder.CreateSelect(inBound, offset, m_builder.getInt32(0));
+ Value *newOffset = nullptr;
+ if (m_pipelineState.getOptions().enableExtendedRobustBufferAccess) {
+ // No need to check out-of-bind if the extended robustness check is already done
+ newOffset = offset;
+ } else {
+ // NOTE: The offset of out-of-bound overridden as 0 may causes unexpected result when the extended robustness access
+ // is disabled.
+ newOffset = m_builder.CreateSelect(inBound, offset, m_builder.getInt32(0));
+ }
+
// Add on the index to the address.
Value *pointer = m_builder.CreateGEP(m_builder.getInt8Ty(), baseAddr, newOffset);
pointer = m_builder.CreateBitCast(pointer, type->getPointerTo(ADDR_SPACE_GLOBAL));
Value *newValue = callback(pointer);
- m_builder.SetInsertPoint(&inst);
- assert(!type->isVoidTy());
- auto phi = m_builder.CreatePHI(type, 2, "newValue");
- phi->addIncoming(Constant::getNullValue(type), origBlock);
- phi->addIncoming(newValue, terminator->getParent());
+ // Store inst doesn't need return a value from a phi node
+ if (!dyn_cast<StoreInst>(&inst)) {
+ m_builder.SetInsertPoint(&inst);
+ assert(!type->isVoidTy());
+ auto phi = m_builder.CreatePHI(type, 2, "newValue");
+ phi->addIncoming(Constant::getNullValue(type), origBlock);
+ phi->addIncoming(newValue, terminator->getParent());
- return phi;
+ return phi;
+ }
+ return nullptr;
}
diff --git a/lgc/patch/PatchCheckShaderCache.cpp b/lgc/patch/PatchCheckShaderCache.cpp
index 5ac6f3fc6d..17ca81ae71 100644
--- a/lgc/patch/PatchCheckShaderCache.cpp
+++ b/lgc/patch/PatchCheckShaderCache.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -90,13 +90,13 @@ bool PatchCheckShaderCache::runImpl(Module &module, PipelineState *pipelineState
Patch::init(&module);
- std::string inOutUsageStreams[ShaderStageGfxCount];
- ArrayRef<uint8_t> inOutUsageValues[ShaderStageGfxCount];
+ std::string inOutUsageStreams[ShaderStage::GfxCount];
+ ArrayRef<uint8_t> inOutUsageValues[ShaderStage::GfxCount];
auto stageMask = pipelineState->getShaderStageMask();
// Build input/output layout hash per shader stage
- for (const ShaderStage stage : enumRange(ShaderStageGfxCount)) {
- if ((stageMask & shaderStageToMask(stage)) == 0)
+ for (const ShaderStageEnum stage : enumRange(ShaderStage::GfxCount)) {
+ if (!stageMask.contains(stage))
continue;
auto resUsage = pipelineState->getShaderResourceUsage(stage);
@@ -116,11 +116,11 @@ bool PatchCheckShaderCache::runImpl(Module &module, PipelineState *pipelineState
streamMapEntries(resUsage->inOutUsage.perPrimitiveBuiltInInputLocMap, stream);
streamMapEntries(resUsage->inOutUsage.perPrimitiveBuiltInOutputLocMap, stream);
- if (stage == ShaderStageGeometry) {
+ if (stage == ShaderStage::Geometry) {
// NOTE: For geometry shader, copy shader will use this special map info (from built-in outputs to
// locations of generic outputs). We have to add it to shader hash calculation.
streamMapEntries(resUsage->inOutUsage.gs.builtInOutLocs, stream);
- } else if (stage == ShaderStageMesh) {
+ } else if (stage == ShaderStage::Mesh) {
// NOTE: For mesh shader, those two special map info (from built-in IDs to export locations of vertex/primitive
// attributes) is used to export vertex/primitive attributes.
streamMapEntries(resUsage->inOutUsage.mesh.builtInExportLocs, stream);
@@ -134,7 +134,7 @@ bool PatchCheckShaderCache::runImpl(Module &module, PipelineState *pipelineState
}
// Ask callback function if it wants to remove any shader stages.
- unsigned stagesLeftToCompile = m_callbackFunc(&module, stageMask, inOutUsageValues);
+ auto stagesLeftToCompile = m_callbackFunc(&module, stageMask, inOutUsageValues);
if (stagesLeftToCompile == stageMask)
return false;
@@ -144,7 +144,7 @@ bool PatchCheckShaderCache::runImpl(Module &module, PipelineState *pipelineState
for (auto &func : module) {
if (isShaderEntryPoint(&func)) {
auto stage = getShaderStage(&func);
- if (stage != ShaderStageInvalid && (shaderStageToMask(stage) & ~stagesLeftToCompile) != 0) {
+ if (stage && !stagesLeftToCompile.contains(stage.value())) {
func.deleteBody();
func.setDLLStorageClass(GlobalValue::DefaultStorageClass);
}
diff --git a/lgc/patch/PatchCopyShader.cpp b/lgc/patch/PatchCopyShader.cpp
index d109a44c62..a57cd6cb7e 100644
--- a/lgc/patch/PatchCopyShader.cpp
+++ b/lgc/patch/PatchCopyShader.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -77,14 +77,14 @@ bool PatchCopyShader::runImpl(Module &module, PipelineShadersResult &pipelineSha
m_pipelineState = pipelineState;
m_pipelineSysValues.initialize(m_pipelineState);
- auto gsEntryPoint = pipelineShaders.getEntryPoint(ShaderStageGeometry);
+ auto gsEntryPoint = pipelineShaders.getEntryPoint(ShaderStage::Geometry);
if (!gsEntryPoint) {
// Skip copy shader generation if GS is absent
return false;
}
// Tell pipeline state there is a copy shader.
- m_pipelineState->setShaderStageMask(m_pipelineState->getShaderStageMask() | (1U << ShaderStageCopyShader));
+ m_pipelineState->setShaderStageMask(m_pipelineState->getShaderStageMask() | ShaderStageMask(ShaderStage::CopyShader));
// Gather GS generic export details.
collectGsGenericOutputInfo(gsEntryPoint);
@@ -116,17 +116,9 @@ bool PatchCopyShader::runImpl(Module &module, PipelineShadersResult &pipelineSha
argTys = {int32Ty, int32Ty, int32Ty, int32Ty, int32Ty, int32Ty, int32Ty, int32Ty, int32Ty};
argInReg = {true, true, true, true, true, true, true, true, false};
- // clang-format off
- argNames = {"globalTable",
- "streamOutTable",
- "streamOutInfo",
- "streamOutWriteIndex",
- "streamOutOffset0",
- "streamOutOffset1",
- "streamOutOffset2",
- "streamOutOffset3",
- "vertexOffset"};
- // clang-format on
+
+ argNames = {"globalTable", "streamOutTable", "streamOutInfo", "streamOutWriteIndex", "streamOutOffset0",
+ "streamOutOffset1", "streamOutOffset2", "streamOutOffset3", "vertexOffset"};
} else {
// If NGG, the copy shader is not a real HW VS and will be incorporated into NGG primitive shader finally. Thus,
// the argument definitions are decided by compiler not by HW. We could have such variable layout (not fixed with
@@ -159,10 +151,10 @@ bool PatchCopyShader::runImpl(Module &module, PipelineShadersResult &pipelineSha
entryPoint->setCallingConv(CallingConv::AMDGPU_VS);
// Set the shader stage on the new function.
- setShaderStage(entryPoint, ShaderStageCopyShader);
+ setShaderStage(entryPoint, ShaderStage::CopyShader);
auto insertPos = module.getFunctionList().end();
- auto fsEntryPoint = pipelineShaders.getEntryPoint(ShaderStageFragment);
+ auto fsEntryPoint = pipelineShaders.getEntryPoint(ShaderStage::Fragment);
if (fsEntryPoint)
insertPos = fsEntryPoint->getIterator();
module.getFunctionList().insert(insertPos, entryPoint);
@@ -175,7 +167,7 @@ bool PatchCopyShader::runImpl(Module &module, PipelineShadersResult &pipelineSha
}
// Set wavefront size
- const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStageCopyShader);
+ const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::CopyShader);
if (m_pipelineState->getTargetInfo().getGfxIpVersion().major >= 10)
entryPoint->addFnAttr("target-features", ",+wavefrontsize" + std::to_string(waveSize));
@@ -188,7 +180,7 @@ bool PatchCopyShader::runImpl(Module &module, PipelineShadersResult &pipelineSha
auto entryBlock = BasicBlock::Create(*m_context, "", entryPoint, endBlock);
builder.SetInsertPoint(entryBlock);
- auto intfData = m_pipelineState->getShaderInterfaceData(ShaderStageCopyShader);
+ auto intfData = m_pipelineState->getShaderInterfaceData(ShaderStage::CopyShader);
if (!m_pipelineState->getNggControl()->enableNgg) {
intfData->userDataUsage.gs.copyShaderStreamOutTable = 1;
@@ -208,11 +200,11 @@ bool PatchCopyShader::runImpl(Module &module, PipelineShadersResult &pipelineSha
if (m_pipelineState->enableXfb())
userData[intfData->userDataUsage.gs.copyShaderStreamOutTable] =
static_cast<unsigned>(UserDataMapping::StreamOutTable);
- m_pipelineState->setUserDataMap(ShaderStageCopyShader, userData);
+ m_pipelineState->setUserDataMap(ShaderStage::CopyShader, userData);
} else {
- m_pipelineState->getPalMetadata()->setUserDataEntry(ShaderStageCopyShader, 0, UserDataMapping::GlobalTable);
+ m_pipelineState->getPalMetadata()->setUserDataEntry(ShaderStage::CopyShader, 0, UserDataMapping::GlobalTable);
if (m_pipelineState->enableXfb()) {
- m_pipelineState->getPalMetadata()->setUserDataEntry(ShaderStageCopyShader,
+ m_pipelineState->getPalMetadata()->setUserDataEntry(ShaderStage::CopyShader,
intfData->userDataUsage.gs.copyShaderStreamOutTable,
UserDataMapping::StreamOutTable);
}
@@ -313,13 +305,13 @@ bool PatchCopyShader::runImpl(Module &module, PipelineShadersResult &pipelineSha
//
// @param gsEntryPoint : Geometry shader entrypoint
void PatchCopyShader::collectGsGenericOutputInfo(Function *gsEntryPoint) {
- auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageCopyShader);
+ auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::CopyShader);
const auto &outputLocInfoMap = resUsage->inOutUsage.outputLocInfoMap;
std::set<InOutLocationInfo> visitedLocInfos;
// Collect the byte sizes of the output value at each mapped location
for (auto &func : *gsEntryPoint->getParent()) {
- if (func.getName().startswith(lgcName::OutputExportGeneric)) {
+ if (func.getName().starts_with(lgcName::OutputExportGeneric)) {
for (auto user : func.users()) {
auto callInst = dyn_cast<CallInst>(user);
if (!callInst || callInst->getParent()->getParent() != gsEntryPoint)
@@ -343,7 +335,7 @@ void PatchCopyShader::collectGsGenericOutputInfo(Function *gsEntryPoint) {
visitedLocInfos.insert(origLocInfo);
unsigned dwordSize = 1; // Each output call is scalarized and exports 1 dword for packing
- if (!m_pipelineState->canPackOutput(ShaderStageGeometry)) {
+ if (!m_pipelineState->canPackOutput(ShaderStage::Geometry)) {
unsigned compCount = 1;
auto compTy = outputTy;
auto outputVecTy = dyn_cast<FixedVectorType>(outputTy);
@@ -381,7 +373,7 @@ void PatchCopyShader::collectGsGenericOutputInfo(Function *gsEntryPoint) {
// @param streamId : Export output of this stream
// @param builder : BuilderBase to use for instruction constructing
void PatchCopyShader::exportOutput(unsigned streamId, BuilderBase &builder) {
- auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageCopyShader);
+ auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::CopyShader);
auto &builtInUsage = resUsage->builtInUsage.gs;
auto &locInfoXfbOutInfoMap = resUsage->inOutUsage.locInfoXfbOutInfoMap;
auto &outputLocInfoMap = resUsage->inOutUsage.outputLocInfoMap;
@@ -520,7 +512,7 @@ Value *PatchCopyShader::calcGsVsRingOffsetForInput(unsigned location, unsigned c
auto entryPoint = builder.GetInsertBlock()->getParent();
Value *vertexOffset = getFunctionArgument(entryPoint, CopyShaderEntryArgIdxVertexOffset);
- auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageCopyShader);
+ auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::CopyShader);
Value *ringOffset = nullptr;
if (m_pipelineState->isGsOnChip()) {
@@ -666,7 +658,7 @@ void PatchCopyShader::exportXfbOutput(Value *outputValue, const XfbOutInfo &xfbO
// Collect transform feedback export calls, used in SW-emulated stream-out.
if (m_pipelineState->enableSwXfb()) {
- auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStageCopyShader)->inOutUsage;
+ auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::CopyShader)->inOutUsage;
// A transform feedback export call is expected to be <4 x dword> at most
inOutUsage.xfbExpCount += outputValue->getType()->getPrimitiveSizeInBits() > 128 ? 2 : 1;
}
@@ -688,7 +680,7 @@ void PatchCopyShader::exportXfbOutput(Value *outputValue, const XfbOutInfo &xfbO
// @param builder : BuilderBase to use for instruction constructing
void PatchCopyShader::exportBuiltInOutput(Value *outputValue, BuiltInKind builtInId, unsigned streamId,
BuilderBase &builder) {
- auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageCopyShader);
+ auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::CopyShader);
if (m_pipelineState->enableXfb()) {
InOutLocationInfo outLocInfo;
@@ -701,7 +693,7 @@ void PatchCopyShader::exportBuiltInOutput(Value *outputValue, BuiltInKind builtI
if (locInfoXfbOutInfoMapIt != locInfoXfbOutInfoMap.end()) {
// Collect transform feedback export calls, used in SW-emulated stream-out.
if (m_pipelineState->enableSwXfb()) {
- auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStageCopyShader)->inOutUsage;
+ auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::CopyShader)->inOutUsage;
// A transform feedback export call is expected to be <4 x dword> at most
inOutUsage.xfbExpCount += outputValue->getType()->getPrimitiveSizeInBits() > 128 ? 2 : 1;
}
diff --git a/lgc/patch/PatchEntryPointMutate.cpp b/lgc/patch/PatchEntryPointMutate.cpp
index b48913c152..4f8179e804 100644
--- a/lgc/patch/PatchEntryPointMutate.cpp
+++ b/lgc/patch/PatchEntryPointMutate.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -134,9 +134,9 @@ bool PatchEntryPointMutate::runImpl(Module &module, PipelineShadersResult &pipel
stackLowering = std::make_unique<CpsStackLowering>(module.getContext(), ADDR_SPACE_PRIVATE);
- const unsigned stageMask = m_pipelineState->getShaderStageMask();
- m_hasTs = (stageMask & (shaderStageToMask(ShaderStageTessControl) | shaderStageToMask(ShaderStageTessEval))) != 0;
- m_hasGs = (stageMask & shaderStageToMask(ShaderStageGeometry)) != 0;
+ const auto stageMask = m_pipelineState->getShaderStageMask();
+ m_hasTs = stageMask.contains_any({ShaderStage::TessControl, ShaderStage::TessEval});
+ m_hasGs = stageMask.contains(ShaderStage::Geometry);
// Gather user data usage.
gatherUserDataUsage(&module);
@@ -148,13 +148,13 @@ bool PatchEntryPointMutate::runImpl(Module &module, PipelineShadersResult &pipel
if (m_pipelineState->isGraphics()) {
// Process each shader in turn, but not the copy shader.
- for (unsigned shaderStage = 0; shaderStage < ShaderStageNativeStageCount; ++shaderStage) {
- m_entryPoint = pipelineShaders.getEntryPoint(static_cast<ShaderStage>(shaderStage));
+ for (unsigned shaderStage = 0; shaderStage < ShaderStage::NativeStageCount; ++shaderStage) {
+ m_entryPoint = pipelineShaders.getEntryPoint(static_cast<ShaderStageEnum>(shaderStage));
if (m_entryPoint) {
// ToDo: This should always be skipped since we don't implement CPS metadata yet.
assert(!lgc::cps::isCpsFunction(*m_entryPoint) && "CPS support not implemented yet");
- m_shaderStage = static_cast<ShaderStage>(shaderStage);
+ m_shaderStage = static_cast<ShaderStageEnum>(shaderStage);
processShader(&shaderInputs);
}
}
@@ -277,7 +277,7 @@ void PatchEntryPointMutate::processGroupMemcpy(Module &module) {
void PatchEntryPointMutate::lowerGroupMemcpy(GroupMemcpyOp &groupMemcpyOp) {
BuilderImpl builder(m_pipelineState);
Function *entryPoint = groupMemcpyOp.getFunction();
- ShaderStage stage = getShaderStage(entryPoint);
+ auto stage = getShaderStage(entryPoint);
builder.setShaderStage(stage);
builder.SetInsertPoint(&groupMemcpyOp);
@@ -294,12 +294,12 @@ void PatchEntryPointMutate::lowerGroupMemcpy(GroupMemcpyOp &groupMemcpyOp) {
if (scope == 2) {
unsigned workgroupSize[3] = {};
auto shaderModes = m_pipelineState->getShaderModes();
- if (stage == ShaderStageTask || stage == ShaderStageCompute) {
+ if (stage == ShaderStage::Task || stage == ShaderStage::Compute) {
Module &module = *groupMemcpyOp.getModule();
workgroupSize[0] = shaderModes->getComputeShaderMode(module).workgroupSizeX;
workgroupSize[1] = shaderModes->getComputeShaderMode(module).workgroupSizeY;
workgroupSize[2] = shaderModes->getComputeShaderMode(module).workgroupSizeZ;
- } else if (stage == ShaderStageMesh) {
+ } else if (stage == ShaderStage::Mesh) {
workgroupSize[0] = shaderModes->getMeshShaderMode().workgroupSizeX;
workgroupSize[1] = shaderModes->getMeshShaderMode().workgroupSizeY;
workgroupSize[2] = shaderModes->getMeshShaderMode().workgroupSizeZ;
@@ -309,19 +309,19 @@ void PatchEntryPointMutate::lowerGroupMemcpy(GroupMemcpyOp &groupMemcpyOp) {
// LocalInvocationId is a function argument now and CreateReadBuiltInInput cannot retrieve it.
unsigned argIndex = 0xFFFFFFFF;
- switch (stage) {
- case ShaderStageTask: {
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageTask)->entryArgIdxs.task;
+ switch (stage.value()) {
+ case ShaderStage::Task: {
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Task)->entryArgIdxs.task;
argIndex = entryArgIdxs.localInvocationId;
break;
}
- case ShaderStageMesh: {
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageMesh)->entryArgIdxs.mesh;
+ case ShaderStage::Mesh: {
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Mesh)->entryArgIdxs.mesh;
argIndex = entryArgIdxs.localInvocationId;
break;
}
- case ShaderStageCompute: {
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageCompute)->entryArgIdxs.cs;
+ case ShaderStage::Compute: {
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Compute)->entryArgIdxs.cs;
argIndex = entryArgIdxs.localInvocationId;
break;
}
@@ -330,12 +330,12 @@ void PatchEntryPointMutate::lowerGroupMemcpy(GroupMemcpyOp &groupMemcpyOp) {
break;
}
- const unsigned waveSize = m_pipelineState->getShaderWaveSize(stage);
+ const unsigned waveSize = m_pipelineState->getShaderWaveSize(stage.value());
// For mesh shader the following two ids are required.
Value *waveIdInSubgroupMesh = nullptr;
Value *threadIdInWaveMesh = nullptr;
- if (stage == ShaderStageMesh) {
+ if (stage == ShaderStage::Mesh) {
builder.CreateIntrinsic(Intrinsic::amdgcn_init_exec, {}, builder.getInt64(-1));
// waveId = mergedWaveInfo[27:24]
Value *mergedWaveInfo =
@@ -356,7 +356,7 @@ void PatchEntryPointMutate::lowerGroupMemcpy(GroupMemcpyOp &groupMemcpyOp) {
scopeSize = workgroupTotalSize;
// localInvocationId argument for mesh shader is available from GFX11+. But it can be retrieved in anther way.
- if (stage == ShaderStageMesh) {
+ if (stage == ShaderStage::Mesh) {
threadIndex = builder.CreateAdd(builder.CreateMul(waveIdInSubgroupMesh, builder.getInt32(waveSize)),
threadIdInWaveMesh, "threadIdInSubgroupMesh");
} else {
@@ -456,14 +456,14 @@ void PatchEntryPointMutate::lowerGroupMemcpy(GroupMemcpyOp &groupMemcpyOp) {
//
// @param asCpsReferenceOp: the instruction
void PatchEntryPointMutate::lowerAsCpsReference(cps::AsContinuationReferenceOp &asCpsReferenceOp) {
- IRBuilder<> builder(&asCpsReferenceOp);
+ BuilderBase builder(&asCpsReferenceOp);
+ Value *ref = nullptr;
Function &callee = cast<Function>(*asCpsReferenceOp.getFn());
auto level = cps::getCpsLevelFromFunction(callee);
- // Use GEP since that is easier for the backend to combine into a relocation fixup.
- Value *ref = builder.CreateConstGEP1_32(builder.getInt8Ty(), asCpsReferenceOp.getFn(), static_cast<uint32_t>(level));
- ref = builder.CreatePtrToInt(ref, builder.getInt32Ty());
+ { ref = builder.CreatePtrToInt(&callee, builder.getInt32Ty()); }
+ ref = builder.CreateAdd(ref, builder.getInt32(static_cast<uint32_t>(level)));
asCpsReferenceOp.replaceAllUsesWith(ref);
}
@@ -506,26 +506,28 @@ bool PatchEntryPointMutate::lowerCpsOps(Function *func, ShaderInputs *shaderInpu
if (!isCpsFunc) {
IRBuilder<> builder(func->getContext());
builder.SetInsertPointPastAllocas(func);
- Value *vspStorage =
- builder.CreateAlloca(builder.getPtrTy(stackLowering->getLoweredCpsStackAddrSpace()), ADDR_SPACE_PRIVATE);
+ Value *vspStorage = builder.CreateAlloca(builder.getInt32Ty());
m_funcCpsStackMap[func] = vspStorage;
}
// Get the number of user-data arguments.
+ const auto &mode = m_pipelineState->getShaderModes()->getComputeShaderMode();
+ bool haveLocalInvocationId = !mode.noLocalInvocationIdInCalls;
unsigned numShaderArg;
+ unsigned numUserdata;
if (!isCpsFunc) {
SmallVector<Type *, 8> argTys;
SmallVector<std::string, 8> argNames;
generateEntryPointArgTys(shaderInputs, nullptr, argTys, argNames, 0);
- numShaderArg = argTys.size();
- assert(!shaderInputs || argNames.back() == "LocalInvocationId");
+ assert(argNames.back() == "LocalInvocationId");
+ numShaderArg = haveLocalInvocationId ? argTys.size() - 1 : argTys.size();
+ numUserdata = argTys.size() - 1;
} else {
numShaderArg = m_cpsShaderInputCache.getTypes().size();
+ assert(haveLocalInvocationId == (m_cpsShaderInputCache.getNames().back() == "LocalInvocationId"));
+ numUserdata = haveLocalInvocationId ? numShaderArg - 1 : numShaderArg;
}
- // Exclude LocalInvocationId if shaderInputs is non-null (for Continufy based continuation).
- unsigned numUserdata = shaderInputs ? numShaderArg - 1 : numShaderArg;
-
// Get all the return instructions.
SmallVector<ReturnInst *> retInstrs;
for (BasicBlock &block : *func)
@@ -559,7 +561,7 @@ bool PatchEntryPointMutate::lowerCpsOps(Function *func, ShaderInputs *shaderInpu
SmallVector<Value *> newVgpr;
// Put LocalInvocationId before {vcr, vsp}.
- if (shaderInputs)
+ if (haveLocalInvocationId)
newVgpr.push_back(func->getArg(numUserdata));
builder.SetInsertPoint(tailBlock);
@@ -588,10 +590,6 @@ bool PatchEntryPointMutate::lowerCpsOps(Function *func, ShaderInputs *shaderInpu
for (unsigned idx = 0; idx != numUserdata; ++idx)
userData.push_back(func->getArg(idx));
- const DataLayout &layout = func->getParent()->getDataLayout();
- SmallVector<Value *> userDataI32;
- splitIntoI32(layout, builder, userData, userDataI32);
- Value *userDataVec = mergeDwordsIntoVector(builder, userDataI32);
// tail:
// Merge vgpr values from different exits.
// Check if we have pending cps call
@@ -602,8 +600,8 @@ bool PatchEntryPointMutate::lowerCpsOps(Function *func, ShaderInputs *shaderInpu
// ret void
unsigned waveSize = m_pipelineState->getShaderWaveSize(m_shaderStage);
Type *waveMaskTy = builder.getIntNTy(waveSize);
- // For continufy based continuation, the vgpr list: LocalInvocationId, vcr, vsp, ...
- unsigned vcrIndexInVgpr = shaderInputs ? 1 : 0;
+ // For continufy based continuation, the vgpr list: LocalInvocationId(optional), vcr, vsp, ...
+ unsigned vcrIndexInVgpr = haveLocalInvocationId ? 1 : 0;
auto *vcr = builder.CreateExtractValue(vgprArg, vcrIndexInVgpr);
auto *vcrTy = vcr->getType();
@@ -655,12 +653,23 @@ bool PatchEntryPointMutate::lowerCpsOps(Function *func, ShaderInputs *shaderInpu
AddressExtender addressExtender(func);
Value *jumpTarget = addressExtender.extend(addr32, builder.getInt32(HighAddrPc), builder.getPtrTy(), builder);
- Value *chainArgs[] = {jumpTarget, execMask, userDataVec, vgprArg, builder.getInt32(0)};
+ const DataLayout &layout = func->getParent()->getDataLayout();
+ SmallVector<Value *> userDataI32;
+ splitIntoI32(layout, builder, userData, userDataI32);
+ Value *userDataVec = mergeDwordsIntoVector(builder, userDataI32);
+
+ SmallVector<Value *> chainArgs = {jumpTarget, execMask, userDataVec, vgprArg};
+
+ {
+ // No flags
+ chainArgs.push_back(builder.getInt32(0));
+ }
#if LLVM_MAIN_REVISION && LLVM_MAIN_REVISION < 465197
// Old version of the code
- Type *chainArgTys[] = {builder.getPtrTy(), builder.getIntNTy(waveSize), userDataVec->getType(), vgprArg->getType(),
- builder.getInt32Ty()};
+ SmallVector<Type *> chainArgTys = {builder.getPtrTy(), builder.getIntNTy(waveSize), userDataVec->getType(),
+ vgprArg->getType(), builder.getInt32Ty()};
+
FunctionType *chainFuncTy = FunctionType::get(builder.getVoidTy(), chainArgTys, true);
auto chainFunc =
Function::Create(chainFuncTy, GlobalValue::ExternalLinkage, "llvm.amdgcn.cs.chain", func->getParent());
@@ -703,9 +712,8 @@ bool PatchEntryPointMutate::lowerCpsOps(Function *func, ShaderInputs *shaderInpu
// @param func : the cps function to be mutated
// @param fixedShaderArgTys : the types of the fixed shader arguments(userdata + possibly shader inputs)
// @param argNames : the name string of the fixed shader arguments
-// @param isContinufy : whether the function is output of Continufy pass.
Function *PatchEntryPointMutate::lowerCpsFunction(Function *func, ArrayRef<Type *> fixedShaderArgTys,
- ArrayRef<std::string> argNames, bool isContinufy) {
+ ArrayRef<std::string> argNames) {
Value *state = func->getArg(0);
const DataLayout &layout = func->getParent()->getDataLayout();
IRBuilder<> builder(func->getContext());
@@ -726,15 +734,17 @@ Function *PatchEntryPointMutate::lowerCpsFunction(Function *func, ArrayRef<Type
AttributeSet emptyAttrSet;
AttributeSet inRegAttrSet = emptyAttrSet.addAttribute(func->getContext(), Attribute::InReg);
+ bool haveLocalInvocationId = !m_pipelineState->getShaderModes()->getComputeShaderMode().noLocalInvocationIdInCalls;
+ assert(haveLocalInvocationId == (argNames.back() == "LocalInvocationId"));
+
AttributeList oldAttrs = func->getAttributes();
SmallVector<AttributeSet, 8> argAttrs;
- assert(!isContinufy || argNames.back() == "LocalInvocationId");
- unsigned numUserdataArg = isContinufy ? fixedShaderArgTys.size() - 1 : fixedShaderArgTys.size();
+ unsigned numUserdataArg = haveLocalInvocationId ? fixedShaderArgTys.size() - 1 : fixedShaderArgTys.size();
for (unsigned idx = 0; idx != numUserdataArg; ++idx)
argAttrs.push_back(inRegAttrSet);
- // %LocalInvocationId for Continufy path.
- if (isContinufy)
+ // %LocalInvocationId when required
+ if (haveLocalInvocationId)
argAttrs.push_back(emptyAttrSet);
// %vcr attribute
@@ -750,8 +760,7 @@ Function *PatchEntryPointMutate::lowerCpsFunction(Function *func, ArrayRef<Type
newFunc->splice(newFunc->begin(), func);
builder.SetInsertPointPastAllocas(newFunc);
- Value *vspStorage =
- builder.CreateAlloca(builder.getPtrTy(stackLowering->getLoweredCpsStackAddrSpace()), ADDR_SPACE_PRIVATE);
+ Value *vspStorage = builder.CreateAlloca(builder.getInt32Ty());
m_funcCpsStackMap[newFunc] = vspStorage;
// Function arguments: {fixed_shader_arguments, vcr, vsp, original_func_arguments_exclude_state}
@@ -760,9 +769,10 @@ Function *PatchEntryPointMutate::lowerCpsFunction(Function *func, ArrayRef<Type
// Get stack address of pushed state and load it from continuation stack.
unsigned stateSize = layout.getTypeStoreSize(state->getType());
vsp = builder.CreateConstInBoundsGEP1_32(builder.getInt8Ty(), vsp, -alignTo(stateSize, ContinuationStackAlignment));
- Value *newState = builder.CreateAlignedLoad(state->getType(), vsp, Align(ContinuationStackAlignment), "cps.state");
+ Value *newState = builder.CreateLoad(state->getType(), vsp, "cps.state");
state->replaceAllUsesWith(newState);
}
+ vsp = builder.CreatePtrToInt(vsp, builder.getInt32Ty());
builder.CreateStore(vsp, vspStorage);
// Set name string for arguments.
@@ -809,9 +819,8 @@ unsigned PatchEntryPointMutate::lowerCpsJump(Function *parent, cps::JumpOp *jump
// Pushing state onto stack and get new vsp.
Value *state = jumpOp->getState();
- Value *vsp =
- builder.CreateAlignedLoad(builder.getPtrTy(stackLowering->getLoweredCpsStackAddrSpace()),
- m_funcCpsStackMap[parent], Align(stackLowering->getLoweredCpsStackPointerSize(layout)));
+ Value *vsp = builder.CreateLoad(builder.getInt32Ty(), m_funcCpsStackMap[parent]);
+ vsp = builder.CreateIntToPtr(vsp, builder.getPtrTy(stackLowering->getLoweredCpsStackAddrSpace()));
unsigned stateSize = 0;
if (!state->getType()->isEmptyTy()) {
stateSize = layout.getTypeStoreSize(state->getType());
@@ -865,7 +874,7 @@ void PatchEntryPointMutate::setupComputeWithCalls(Module *module) {
// functions and intrinsics).
for (Function &func : *module) {
if (func.isDeclaration() && func.getIntrinsicID() == Intrinsic::not_intrinsic &&
- !func.getName().startswith(lgcName::InternalCallPrefix) && !func.user_empty()) {
+ !func.getName().starts_with(lgcName::InternalCallPrefix) && !func.user_empty()) {
m_computeWithCalls = true;
return;
}
@@ -893,9 +902,9 @@ void PatchEntryPointMutate::gatherUserDataUsage(Module *module) {
static const auto visitor =
llvm_dialects::VisitorBuilder<PatchEntryPointMutate>()
.add<UserDataOp>([](PatchEntryPointMutate &self, UserDataOp &op) {
- ShaderStage stage = getShaderStage(op.getFunction());
- assert(stage != ShaderStageCopyShader);
- auto userDataUsage = self.getUserDataUsage(stage);
+ auto stage = getShaderStage(op.getFunction());
+ assert(stage != ShaderStage::CopyShader);
+ auto userDataUsage = self.getUserDataUsage(stage.value());
userDataUsage->userDataOps.push_back(&op);
// Attempt to find all loads with a constant dword-aligned offset and push into
@@ -953,9 +962,9 @@ void PatchEntryPointMutate::gatherUserDataUsage(Module *module) {
}
})
.add<LoadUserDataOp>([](PatchEntryPointMutate &self, LoadUserDataOp &op) {
- ShaderStage stage = getShaderStage(op.getFunction());
- assert(stage != ShaderStageCopyShader);
- auto *userDataUsage = self.getUserDataUsage(stage);
+ auto stage = getShaderStage(op.getFunction());
+ assert(stage != ShaderStage::CopyShader);
+ auto *userDataUsage = self.getUserDataUsage(stage.value());
UserDataLoad load;
load.load = &op;
@@ -973,12 +982,12 @@ void PatchEntryPointMutate::gatherUserDataUsage(Module *module) {
if (!func.isDeclaration())
continue;
- if (func.getName().startswith(lgcName::SpecialUserData)) {
+ if (func.getName().starts_with(lgcName::SpecialUserData)) {
for (User *user : func.users()) {
CallInst *call = cast<CallInst>(user);
- ShaderStage stage = getShaderStage(call->getFunction());
- assert(stage != ShaderStageCopyShader);
- auto &specialUserData = getUserDataUsage(stage)->specialUserData;
+ auto stage = getShaderStage(call->getFunction());
+ assert(stage != ShaderStage::CopyShader);
+ auto &specialUserData = getUserDataUsage(stage.value())->specialUserData;
unsigned index = cast<ConstantInt>(call->getArgOperand(0))->getZExtValue() -
static_cast<unsigned>(UserDataMapping::GlobalTable);
specialUserData.resize(std::max(specialUserData.size(), size_t(index + 1)));
@@ -987,11 +996,11 @@ void PatchEntryPointMutate::gatherUserDataUsage(Module *module) {
continue;
}
- if ((func.getName().startswith(lgcName::OutputExportXfb) && !func.use_empty()) || m_pipelineState->enableSwXfb()) {
+ if ((func.getName().starts_with(lgcName::OutputExportXfb) && !func.use_empty()) || m_pipelineState->enableSwXfb()) {
// NOTE: For GFX11+, SW emulated stream-out will always use stream-out buffer descriptors and stream-out buffer
// offsets to calculate numbers of written primitives/dwords and update the counters. auto lastVertexStage =
auto lastVertexStage = m_pipelineState->getLastVertexProcessingStage();
- lastVertexStage = lastVertexStage == ShaderStageCopyShader ? ShaderStageGeometry : lastVertexStage;
+ lastVertexStage = lastVertexStage == ShaderStage::CopyShader ? ShaderStage::Geometry : lastVertexStage;
getUserDataUsage(lastVertexStage)->usesStreamOutTable = true;
}
}
@@ -1059,8 +1068,12 @@ void PatchEntryPointMutate::fixupUserDataUses(Module &module) {
if (func.isDeclaration())
continue;
- ShaderStage stage = getShaderStage(&func);
- auto userDataUsage = getUserDataUsage(stage);
+ auto stage = getShaderStage(&func);
+
+ if (!stage)
+ continue;
+
+ auto userDataUsage = getUserDataUsage(stage.value());
// If needed, generate code for the spill table pointer (as pointer to i8) at the start of the function.
Instruction *spillTable = nullptr;
@@ -1150,33 +1163,33 @@ void PatchEntryPointMutate::processShader(ShaderInputs *shaderInputs) {
// We always deal with pre-merge functions here, so set the fitting pre-merge calling conventions.
switch (m_shaderStage) {
- case ShaderStageTask:
+ case ShaderStage::Task:
entryPoint->setCallingConv(CallingConv::AMDGPU_CS);
break;
- case ShaderStageMesh:
+ case ShaderStage::Mesh:
entryPoint->setCallingConv(CallingConv::AMDGPU_GS);
break;
- case ShaderStageVertex:
- if (m_pipelineState->hasShaderStage(ShaderStageTessControl))
+ case ShaderStage::Vertex:
+ if (m_pipelineState->hasShaderStage(ShaderStage::TessControl))
entryPoint->setCallingConv(CallingConv::AMDGPU_LS);
- else if (m_pipelineState->hasShaderStage(ShaderStageGeometry))
+ else if (m_pipelineState->hasShaderStage(ShaderStage::Geometry))
entryPoint->setCallingConv(CallingConv::AMDGPU_ES);
else
entryPoint->setCallingConv(CallingConv::AMDGPU_VS);
break;
- case ShaderStageTessControl:
+ case ShaderStage::TessControl:
entryPoint->setCallingConv(CallingConv::AMDGPU_HS);
break;
- case ShaderStageTessEval:
- if (m_pipelineState->hasShaderStage(ShaderStageGeometry))
+ case ShaderStage::TessEval:
+ if (m_pipelineState->hasShaderStage(ShaderStage::Geometry))
entryPoint->setCallingConv(CallingConv::AMDGPU_ES);
else
entryPoint->setCallingConv(CallingConv::AMDGPU_VS);
break;
- case ShaderStageGeometry:
+ case ShaderStage::Geometry:
entryPoint->setCallingConv(CallingConv::AMDGPU_GS);
break;
- case ShaderStageFragment:
+ case ShaderStage::Fragment:
entryPoint->setCallingConv(CallingConv::AMDGPU_PS);
break;
default:
@@ -1196,7 +1209,7 @@ void PatchEntryPointMutate::processShader(ShaderInputs *shaderInputs) {
// @param shaderInputs : ShaderInputs object representing hardware-provided shader inputs
// @param [in/out] module : Module
void PatchEntryPointMutate::processComputeFuncs(ShaderInputs *shaderInputs, Module &module) {
- m_shaderStage = ShaderStageCompute;
+ m_shaderStage = ShaderStage::Compute;
// We no longer support compute shader fixed layout required before PAL interface version 624.
if (m_pipelineState->getLgcContext()->getPalAbiVersion() < 624)
@@ -1206,7 +1219,7 @@ void PatchEntryPointMutate::processComputeFuncs(ShaderInputs *shaderInputs, Modu
SmallVector<Function *, 4> origFuncs;
for (Function &func : module) {
if (func.isDeclaration()) {
- if (!func.isIntrinsic() && !func.getName().startswith(lgcName::InternalCallPrefix)) {
+ if (!func.isIntrinsic() && !func.getName().starts_with(lgcName::InternalCallPrefix)) {
// This is the declaration of a callable function that is defined in a different module.
func.setCallingConv(CallingConv::AMDGPU_Gfx);
}
@@ -1215,32 +1228,50 @@ void PatchEntryPointMutate::processComputeFuncs(ShaderInputs *shaderInputs, Modu
}
}
+ SmallVector<Type *, 20> shaderInputTys;
+ SmallVector<std::string, 20> shaderInputNames;
+ ArrayRef<Type *> calleeArgTys;
+ ArrayRef<std::string> calleeArgNames;
+ uint64_t inRegMask;
+
for (Function *origFunc : origFuncs) {
auto *origType = origFunc->getFunctionType();
- // Determine what args need to be added on to all functions.
- SmallVector<Type *, 20> shaderInputTys;
- SmallVector<std::string, 20> shaderInputNames;
- uint64_t inRegMask;
// Create the new function and transfer code and attributes to it.
Function *newFunc = nullptr;
// For continufy based ray-tracing, we still need to add shader inputs like workgroupId and LocalInvocationId.
- bool isContinufy = m_pipelineState->getOptions().rtIndirectMode == RayTracingIndirectMode::ContinuationsContinufy;
- ShaderInputs *cpsShaderInputs = isContinufy ? shaderInputs : nullptr;
+ bool haveLocalInvocationIdInCalls =
+ !m_pipelineState->getShaderModes()->getComputeShaderMode().noLocalInvocationIdInCalls;
if (cps::isCpsFunction(*origFunc)) {
assert(origType->getReturnType()->isVoidTy());
if (!m_cpsShaderInputCache.isAvailable()) {
- generateEntryPointArgTys(cpsShaderInputs, nullptr, shaderInputTys, shaderInputNames, 0);
+ generateEntryPointArgTys(shaderInputs, nullptr, shaderInputTys, shaderInputNames, 0, false);
+ assert(shaderInputNames.back() == "LocalInvocationId");
+ if (!haveLocalInvocationIdInCalls) {
+ shaderInputTys.pop_back();
+ shaderInputNames.pop_back();
+ }
m_cpsShaderInputCache.set(shaderInputTys, shaderInputNames);
}
- newFunc =
- lowerCpsFunction(origFunc, m_cpsShaderInputCache.getTypes(), m_cpsShaderInputCache.getNames(), isContinufy);
+ newFunc = lowerCpsFunction(origFunc, m_cpsShaderInputCache.getTypes(), m_cpsShaderInputCache.getNames());
} else {
- inRegMask = generateEntryPointArgTys(shaderInputs, origFunc, shaderInputTys, shaderInputNames,
- origType->getNumParams(), true);
- newFunc = addFunctionArgs(origFunc, origType->getReturnType(), shaderInputTys, shaderInputNames, inRegMask,
- AddFunctionArgsAppend);
- const bool isEntryPoint = isShaderEntryPoint(newFunc);
+ if (shaderInputTys.empty()) {
+ inRegMask = generateEntryPointArgTys(shaderInputs, origFunc, shaderInputTys, shaderInputNames,
+ origType->getNumParams(), true);
+ calleeArgTys = ArrayRef(shaderInputTys);
+ calleeArgNames = ArrayRef(shaderInputNames);
+ const bool isEntryPoint = isShaderEntryPoint(origFunc);
+ if (!isEntryPoint && m_pipelineState->getShaderModes()->getComputeShaderMode().noLocalInvocationIdInCalls) {
+ assert(calleeArgNames.back() == "LocalInvocationId");
+ calleeArgTys = calleeArgTys.drop_back();
+ calleeArgNames = calleeArgNames.drop_back();
+ }
+ }
+
+ const bool isEntryPoint = isShaderEntryPoint(origFunc);
+ newFunc =
+ addFunctionArgs(origFunc, origType->getReturnType(), isEntryPoint ? ArrayRef(shaderInputTys) : calleeArgTys,
+ isEntryPoint ? ArrayRef(shaderInputNames) : calleeArgNames, inRegMask, AddFunctionArgsAppend);
newFunc->setCallingConv(isEntryPoint ? CallingConv::AMDGPU_CS : CallingConv::AMDGPU_Gfx);
}
// Set Attributes on new function.
@@ -1250,20 +1281,20 @@ void PatchEntryPointMutate::processComputeFuncs(ShaderInputs *shaderInputs, Modu
// Remove original function.
origFunc->eraseFromParent();
- if (lowerCpsOps(newFunc, cpsShaderInputs))
+ if (lowerCpsOps(newFunc, shaderInputs))
continue;
int argOffset = origType->getNumParams();
if (isComputeWithCalls())
- processCalls(*newFunc, shaderInputTys, shaderInputNames, inRegMask, argOffset);
+ processCalls(*newFunc, calleeArgTys, calleeArgNames, inRegMask, argOffset);
}
}
// =====================================================================================================================
// Process all real function calls and passes arguments to them.
//
// @param [in/out] module : Module
-void PatchEntryPointMutate::processCalls(Function &func, SmallVectorImpl<Type *> &shaderInputTys,
- SmallVectorImpl<std::string> &shaderInputNames, uint64_t inRegMask,
+void PatchEntryPointMutate::processCalls(Function &func, ArrayRef<Type *> shaderInputTys,
+ ArrayRef<std::string> shaderInputNames, uint64_t inRegMask,
unsigned argOffset) {
// This is one of:
// - a compute pipeline with non-inlined functions;
@@ -1281,7 +1312,7 @@ void PatchEntryPointMutate::processCalls(Function &func, SmallVectorImpl<Type *>
Value *calledVal = call->getCalledOperand();
Function *calledFunc = dyn_cast<Function>(calledVal);
if (calledFunc) {
- if (calledFunc->isIntrinsic() || calledFunc->getName().startswith(lgcName::InternalCallPrefix))
+ if (calledFunc->isIntrinsic() || calledFunc->getName().starts_with(lgcName::InternalCallPrefix))
continue;
} else if (call->isInlineAsm()) {
continue;
@@ -1303,15 +1334,7 @@ void PatchEntryPointMutate::processCalls(Function &func, SmallVectorImpl<Type *>
// If the old called value was a function declaration, we did not insert a bitcast
FunctionType *calledTy = FunctionType::get(call->getType(), argTys, false);
builder.SetInsertPoint(call);
- Type *calledPtrTy = calledTy->getPointerTo(calledVal->getType()->getPointerAddressSpace());
- auto bitCast = dyn_cast<BitCastOperator>(calledVal);
- Value *newCalledVal = nullptr;
- if (bitCast && bitCast->getOperand(0)->getType() == calledPtrTy)
- newCalledVal = bitCast->getOperand(0);
- else
- newCalledVal = builder.CreateBitCast(calledVal, calledPtrTy);
- // Create the call.
- CallInst *newCall = builder.CreateCall(calledTy, newCalledVal, args);
+ CallInst *newCall = builder.CreateCall(calledTy, calledVal, args);
newCall->setCallingConv(CallingConv::AMDGPU_Gfx);
// Mark sgpr arguments as inreg
@@ -1331,8 +1354,8 @@ void PatchEntryPointMutate::processCalls(Function &func, SmallVectorImpl<Type *>
// Set Attributes on new function
void PatchEntryPointMutate::setFuncAttrs(Function *entryPoint) {
AttrBuilder builder(entryPoint->getContext());
- if (m_shaderStage == ShaderStageFragment) {
- auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageFragment)->builtInUsage.fs;
+ if (m_shaderStage == ShaderStage::Fragment) {
+ auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Fragment)->builtInUsage.fs;
SpiPsInputAddr spiPsInputAddr = {};
spiPsInputAddr.bits.perspSampleEna =
@@ -1416,10 +1439,10 @@ void PatchEntryPointMutate::setFuncAttrs(Function *entryPoint) {
if (shaderOptions->maxThreadGroupsPerComputeUnit != 0) {
unsigned tgSize;
- if (m_shaderStage == ShaderStageCompute || m_shaderStage == ShaderStageTask) {
+ if (m_shaderStage == ShaderStage::Compute || m_shaderStage == ShaderStage::Task) {
const auto &mode = m_pipelineState->getShaderModes()->getComputeShaderMode();
tgSize = std::max(1u, mode.workgroupSizeX * mode.workgroupSizeY * mode.workgroupSizeZ);
- } else if (m_shaderStage == ShaderStageMesh) {
+ } else if (m_shaderStage == ShaderStage::Mesh) {
const auto &mode = m_pipelineState->getShaderModes()->getMeshShaderMode();
tgSize = std::max(1u, mode.workgroupSizeX * mode.workgroupSizeY * mode.workgroupSizeZ);
} else {
@@ -1442,7 +1465,7 @@ void PatchEntryPointMutate::setFuncAttrs(Function *entryPoint) {
if (shaderOptions->ldsSpillLimitDwords != 0) {
// Sanity check: LDS spilling is only supported in Fragment and Compute.
- if (m_shaderStage == ShaderStageFragment || m_shaderStage == ShaderStageCompute)
+ if (m_shaderStage == ShaderStage::Fragment || m_shaderStage == ShaderStage::Compute)
builder.addAttribute("amdgpu-lds-spill-limit-dwords", std::to_string(shaderOptions->ldsSpillLimitDwords));
}
@@ -1572,9 +1595,9 @@ uint64_t PatchEntryPointMutate::generateEntryPointArgTys(ShaderInputs *shaderInp
// Only applies to wave32
// TODO: Can we further exclude PS if LDS_GROUP_SIZE == 0
if (m_pipelineState->getShaderWaveSize(m_shaderStage) == 32 &&
- (m_shaderStage == ShaderStageCompute || m_shaderStage == ShaderStageFragment ||
- m_shaderStage == ShaderStageMesh)) {
- unsigned userDataLimit = m_shaderStage == ShaderStageMesh ? 8 : 16;
+ (m_shaderStage == ShaderStage::Compute || m_shaderStage == ShaderStage::Fragment ||
+ m_shaderStage == ShaderStage::Mesh)) {
+ unsigned userDataLimit = m_shaderStage == ShaderStage::Mesh ? 8 : 16;
while (userDataIdx < userDataLimit) {
argTys.push_back(builder.getInt32Ty());
@@ -1588,7 +1611,7 @@ uint64_t PatchEntryPointMutate::generateEntryPointArgTys(ShaderInputs *shaderInp
// the SGPR corresponding to scratch offset (s2) of PS is incorrectly initialized. This leads to invalid scratch
// memory access, causing GPU hang. Thus, we detect such case and add a dummy user SGPR in order not to map scratch
// offset to s2.
- if (m_pipelineState->getTargetInfo().getGfxIpVersion().major == 9 && m_shaderStage == ShaderStageFragment) {
+ if (m_pipelineState->getTargetInfo().getGfxIpVersion().major == 9 && m_shaderStage == ShaderStage::Fragment) {
if (userDataIdx == 1) {
argTys.push_back(builder.getInt32Ty());
argNames.push_back("dummyInit");
@@ -1667,8 +1690,8 @@ void PatchEntryPointMutate::addSpecialUserDataArgs(SmallVectorImpl<UserDataArg>
auto &entryArgIdxs = intfData->entryArgIdxs;
bool enableNgg = m_pipelineState->isGraphics() ? m_pipelineState->getNggControl()->enableNgg : false;
- if (m_shaderStage == ShaderStageVertex || m_shaderStage == ShaderStageTessControl ||
- m_shaderStage == ShaderStageTessEval || m_shaderStage == ShaderStageGeometry) {
+ if (m_shaderStage == ShaderStage::Vertex || m_shaderStage == ShaderStage::TessControl ||
+ m_shaderStage == ShaderStage::TessEval || m_shaderStage == ShaderStage::Geometry) {
// Shader stage in the vertex-processing half of a graphics pipeline.
// We need to ensure that the layout is the same between two shader stages that will be merged on GFX9+,
// that is, VS-TCS, VS-GS (if no tessellation), TES-GS.
@@ -1679,16 +1702,16 @@ void PatchEntryPointMutate::addSpecialUserDataArgs(SmallVectorImpl<UserDataArg>
unsigned *argIdx = nullptr;
auto userDataValue = UserDataMapping::ViewId;
switch (m_shaderStage) {
- case ShaderStageVertex:
+ case ShaderStage::Vertex:
argIdx = &entryArgIdxs.vs.viewId;
break;
- case ShaderStageTessControl:
+ case ShaderStage::TessControl:
argIdx = &entryArgIdxs.tcs.viewId;
break;
- case ShaderStageTessEval:
+ case ShaderStage::TessEval:
argIdx = &entryArgIdxs.tes.viewId;
break;
- case ShaderStageGeometry:
+ case ShaderStage::Geometry:
argIdx = &entryArgIdxs.gs.viewId;
break;
default:
@@ -1697,10 +1720,10 @@ void PatchEntryPointMutate::addSpecialUserDataArgs(SmallVectorImpl<UserDataArg>
specialUserDataArgs.push_back(UserDataArg(builder.getInt32Ty(), "viewId", userDataValue, argIdx));
}
- if (getMergedShaderStage(m_shaderStage) == getMergedShaderStage(ShaderStageVertex)) {
+ if (getMergedShaderStage(m_shaderStage) == getMergedShaderStage(ShaderStage::Vertex)) {
// This is the VS, or the shader that VS is merged into on GFX9+.
- auto vsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStageVertex);
- auto vsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageVertex);
+ auto vsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStage::Vertex);
+ auto vsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Vertex);
// Detect whether this is an unlinked compile that will need a fetch shader. If so, we need to
// add the vertex buffer table and base vertex and base instance, even if they appear unused here.
@@ -1728,7 +1751,7 @@ void PatchEntryPointMutate::addSpecialUserDataArgs(SmallVectorImpl<UserDataArg>
specialUserDataArgs.push_back(UserDataArg(builder.getInt32Ty(), "drawIndex", UserDataMapping::DrawIndex));
}
- } else if (m_shaderStage == ShaderStageCompute) {
+ } else if (m_shaderStage == ShaderStage::Compute) {
// Pass the gl_NumWorkgroups pointer in user data registers.
// Always enable this, even if unused, if compute library is in use.
// Unlike all the special user data values above, which go after the user data node args, this goes before.
@@ -1738,7 +1761,7 @@ void PatchEntryPointMutate::addSpecialUserDataArgs(SmallVectorImpl<UserDataArg>
auto numWorkgroupsPtrTy = PointerType::get(FixedVectorType::get(builder.getInt32Ty(), 3), ADDR_SPACE_CONST);
userDataArgs.push_back(UserDataArg(numWorkgroupsPtrTy, "numWorkgroupsPtr", UserDataMapping::Workgroup, nullptr));
}
- } else if (m_shaderStage == ShaderStageTask) {
+ } else if (m_shaderStage == ShaderStage::Task) {
// Draw index.
if (userDataUsage->isSpecialUserDataUsed(UserDataMapping::DrawIndex))
specialUserDataArgs.push_back(UserDataArg(builder.getInt32Ty(), "drawIndex", UserDataMapping::DrawIndex));
@@ -1754,8 +1777,8 @@ void PatchEntryPointMutate::addSpecialUserDataArgs(SmallVectorImpl<UserDataArg>
UserDataMapping::MeshPipeStatsBuf,
&intfData->entryArgIdxs.task.pipeStatsBuf));
}
- } else if (m_shaderStage == ShaderStageMesh) {
- if (m_pipelineState->getShaderResourceUsage(ShaderStageMesh)->builtInUsage.mesh.drawIndex) {
+ } else if (m_shaderStage == ShaderStage::Mesh) {
+ if (m_pipelineState->getShaderResourceUsage(ShaderStage::Mesh)->builtInUsage.mesh.drawIndex) {
specialUserDataArgs.push_back(UserDataArg(builder.getInt32Ty(), "drawIndex", UserDataMapping::DrawIndex,
&intfData->entryArgIdxs.mesh.drawIndex));
}
@@ -1774,9 +1797,9 @@ void PatchEntryPointMutate::addSpecialUserDataArgs(SmallVectorImpl<UserDataArg>
UserDataMapping::MeshPipeStatsBuf,
&intfData->entryArgIdxs.mesh.pipeStatsBuf));
}
- } else if (m_shaderStage == ShaderStageFragment) {
+ } else if (m_shaderStage == ShaderStage::Fragment) {
if (m_pipelineState->getInputAssemblyState().multiView != MultiViewMode::Disable &&
- m_pipelineState->getShaderResourceUsage(ShaderStageFragment)->builtInUsage.fs.viewIndex) {
+ m_pipelineState->getShaderResourceUsage(ShaderStage::Fragment)->builtInUsage.fs.viewIndex) {
// NOTE: Only add special user data of view index when multi-view is enabled and gl_ViewIndex is used in fragment
// shader.
specialUserDataArgs.push_back(
@@ -1789,7 +1812,7 @@ void PatchEntryPointMutate::addSpecialUserDataArgs(SmallVectorImpl<UserDataArg>
UserDataArg(builder.getInt32Ty(), "colorExpAddr", UserDataMapping::ColorExportAddr));
}
- if (m_pipelineState->getShaderResourceUsage(ShaderStageFragment)->builtInUsage.fs.runAtSampleRate &&
+ if (m_pipelineState->getShaderResourceUsage(ShaderStage::Fragment)->builtInUsage.fs.runAtSampleRate &&
(m_pipelineState->isUnlinked() || m_pipelineState->getRasterizerState().dynamicSampleInfo)) {
specialUserDataArgs.push_back(UserDataArg(builder.getInt32Ty(), "sampleInfo", UserDataMapping::SampleInfo,
&intfData->entryArgIdxs.fs.sampleInfo));
@@ -1805,18 +1828,18 @@ void PatchEntryPointMutate::addSpecialUserDataArgs(SmallVectorImpl<UserDataArg>
// Allocate register for stream-out buffer table, to go before the user data node args (unlike all the ones
// above, which go after the user data node args).
if (userDataUsage->usesStreamOutTable || userDataUsage->isSpecialUserDataUsed(UserDataMapping::StreamOutTable)) {
- if (enableNgg || !m_pipelineState->hasShaderStage(ShaderStageCopyShader) && m_pipelineState->enableXfb()) {
+ if (enableNgg || !m_pipelineState->hasShaderStage(ShaderStage::CopyShader) && m_pipelineState->enableXfb()) {
// If no NGG, stream out table will be set to copy shader's user data entry, we should not set it duplicately.
unsigned *tablePtr = nullptr;
switch (m_shaderStage) {
- case ShaderStageVertex:
+ case ShaderStage::Vertex:
tablePtr = &intfData->entryArgIdxs.vs.streamOutData.tablePtr;
break;
- case ShaderStageTessEval:
+ case ShaderStage::TessEval:
tablePtr = &intfData->entryArgIdxs.tes.streamOutData.tablePtr;
break;
- case ShaderStageGeometry:
+ case ShaderStage::Geometry:
if (m_pipelineState->enableSwXfb()) {
tablePtr = &intfData->entryArgIdxs.gs.streamOutData.tablePtr;
} else {
@@ -1844,13 +1867,13 @@ void PatchEntryPointMutate::addSpecialUserDataArgs(SmallVectorImpl<UserDataArg>
unsigned *controlBufPtr = nullptr;
switch (m_shaderStage) {
- case ShaderStageVertex:
+ case ShaderStage::Vertex:
controlBufPtr = &intfData->entryArgIdxs.vs.streamOutData.controlBufPtr;
break;
- case ShaderStageTessEval:
+ case ShaderStage::TessEval:
controlBufPtr = &intfData->entryArgIdxs.tes.streamOutData.controlBufPtr;
break;
- case ShaderStageGeometry:
+ case ShaderStage::Geometry:
controlBufPtr = &intfData->entryArgIdxs.gs.streamOutData.controlBufPtr;
break;
default:
@@ -1885,7 +1908,7 @@ void PatchEntryPointMutate::finalizeUserDataArgs(SmallVectorImpl<UserDataArg> &u
// Figure out how many sgprs we have available for userDataArgs.
// We have s0-s31 (s0-s15 for <=GFX8, or for a compute/task shader on any chip) for everything, so take off the number
// of registers used by specialUserDataArgs.
- unsigned userDataAvailable = (m_shaderStage == ShaderStageCompute || m_shaderStage == ShaderStageTask)
+ unsigned userDataAvailable = (m_shaderStage == ShaderStage::Compute || m_shaderStage == ShaderStage::Task)
? InterfaceData::MaxCsUserDataCount
: m_pipelineState->getTargetInfo().getGpuProperty().maxUserDataCount;
@@ -2001,7 +2024,7 @@ void PatchEntryPointMutate::finalizeUserDataArgs(SmallVectorImpl<UserDataArg> &u
// Get UserDataUsage struct for the merged shader stage that contains the given shader stage
//
// @param stage : Shader stage
-PatchEntryPointMutate::UserDataUsage *PatchEntryPointMutate::getUserDataUsage(ShaderStage stage) {
+PatchEntryPointMutate::UserDataUsage *PatchEntryPointMutate::getUserDataUsage(ShaderStageEnum stage) {
stage = getMergedShaderStage(stage);
m_userDataUsage.resize(std::max(m_userDataUsage.size(), static_cast<size_t>(stage) + 1));
if (!m_userDataUsage[stage])
@@ -2017,16 +2040,16 @@ PatchEntryPointMutate::UserDataUsage *PatchEntryPointMutate::getUserDataUsage(Sh
// TES -> GS (if it exists)
//
// @param stage : Shader stage
-ShaderStage PatchEntryPointMutate::getMergedShaderStage(ShaderStage stage) const {
+ShaderStageEnum PatchEntryPointMutate::getMergedShaderStage(ShaderStageEnum stage) const {
if (m_pipelineState->getTargetInfo().getGfxIpVersion().major >= 9) {
switch (stage) {
- case ShaderStageVertex:
- if (m_pipelineState->hasShaderStage(ShaderStageTessControl))
- return ShaderStageTessControl;
+ case ShaderStage::Vertex:
+ if (m_pipelineState->hasShaderStage(ShaderStage::TessControl))
+ return ShaderStage::TessControl;
LLVM_FALLTHROUGH;
- case ShaderStageTessEval:
- if (m_pipelineState->hasShaderStage(ShaderStageGeometry))
- return ShaderStageGeometry;
+ case ShaderStage::TessEval:
+ if (m_pipelineState->hasShaderStage(ShaderStage::Geometry))
+ return ShaderStage::Geometry;
break;
default:
break;
diff --git a/lgc/patch/PatchImageDerivatives.cpp b/lgc/patch/PatchImageDerivatives.cpp
index ef56e1508a..8d760d4167 100644
--- a/lgc/patch/PatchImageDerivatives.cpp
+++ b/lgc/patch/PatchImageDerivatives.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -58,7 +58,7 @@ PreservedAnalyses PatchImageDerivatives::run(Module &module, ModuleAnalysisManag
}
static bool usesImplicitDerivatives(StringRef name) {
- if (!(name.startswith("llvm.amdgcn.image.sample") || name.startswith("llvm.amdgcn.image.gather")))
+ if (!(name.starts_with("llvm.amdgcn.image.sample") || name.starts_with("llvm.amdgcn.image.gather")))
return false;
if (name.find(".l.") != std::string::npos || name.find(".d.") != std::string::npos)
return false;
@@ -74,9 +74,9 @@ static bool usesImplicitDerivatives(StringRef name) {
bool PatchImageDerivatives::runImpl(llvm::Module &module, PipelineState *pipelineState) {
LLVM_DEBUG(dbgs() << "Run the pass Patch-Image-Derivatives\n");
- if (!pipelineState->hasShaderStage(ShaderStageFragment))
+ if (!pipelineState->hasShaderStage(ShaderStage::Fragment))
return false;
- ResourceUsage *resUsage = pipelineState->getShaderResourceUsage(ShaderStageFragment);
+ ResourceUsage *resUsage = pipelineState->getShaderResourceUsage(ShaderStage::Fragment);
if (!resUsage->builtInUsage.fs.discard)
return false;
@@ -95,7 +95,7 @@ bool PatchImageDerivatives::runImpl(llvm::Module &module, PipelineState *pipelin
for (User *user : func.users()) {
CallInst *call = cast<CallInst>(user);
// Only record blocks for fragment shader
- if (getShaderStage(call->getFunction()) != ShaderStageFragment)
+ if (getShaderStage(call->getFunction()) != ShaderStage::Fragment)
continue;
if (isKill) {
diff --git a/lgc/patch/PatchImageOpCollect.cpp b/lgc/patch/PatchImageOpCollect.cpp
index 52eabd9de0..4042938af2 100644
--- a/lgc/patch/PatchImageOpCollect.cpp
+++ b/lgc/patch/PatchImageOpCollect.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -66,11 +66,11 @@ bool PatchImageOpCollect::runImpl(llvm::Module &module, PipelineState *pipelineS
for (Function &func : module) {
if (!func.isIntrinsic())
continue;
- if (func.getName().startswith("llvm.amdgcn.image")) {
+ if (func.getName().starts_with("llvm.amdgcn.image")) {
for (User *user : func.users()) {
CallInst *call = cast<CallInst>(user);
- ShaderStage stage = getShaderStage(call->getFunction());
- ResourceUsage *resUsage = pipelineState->getShaderResourceUsage(stage);
+ auto stage = getShaderStage(call->getFunction());
+ ResourceUsage *resUsage = pipelineState->getShaderResourceUsage(stage.value());
resUsage->useImageOp = true;
}
}
diff --git a/lgc/patch/PatchInOutImportExport.cpp b/lgc/patch/PatchInOutImportExport.cpp
index e105ab47de..8baf314d15 100644
--- a/lgc/patch/PatchInOutImportExport.cpp
+++ b/lgc/patch/PatchInOutImportExport.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -112,16 +112,16 @@ bool PatchInOutImportExport::runImpl(Module &module, PipelineShadersResult &pipe
m_gfxIp = m_pipelineState->getTargetInfo().getGfxIpVersion();
m_pipelineSysValues.initialize(m_pipelineState);
- const unsigned stageMask = m_pipelineState->getShaderStageMask();
- m_hasTs = (stageMask & (shaderStageToMask(ShaderStageTessControl) | shaderStageToMask(ShaderStageTessEval))) != 0;
- m_hasGs = (stageMask & shaderStageToMask(ShaderStageGeometry)) != 0;
+ const auto stageMask = m_pipelineState->getShaderStageMask();
+ m_hasTs = stageMask.contains_any({ShaderStage::TessControl, ShaderStage::TessEval});
+ m_hasGs = stageMask.contains(ShaderStage::Geometry);
SmallVector<Function *, 16> inputCallees, otherCallees;
for (auto &func : module.functions()) {
auto name = func.getName();
- if (name.startswith("lgc.input"))
+ if (name.starts_with("lgc.input"))
inputCallees.push_back(&func);
- else if (name.startswith("lgc.output") || name == "llvm.amdgcn.s.sendmsg")
+ else if (name.starts_with("lgc.output") || name == "llvm.amdgcn.s.sendmsg")
otherCallees.push_back(&func);
}
@@ -164,10 +164,10 @@ bool PatchInOutImportExport::runImpl(Module &module, PipelineShadersResult &pipe
// Process each shader in turn, in reverse order (because for example VS uses inOutUsage.tcs.calcFactor
// set by TCS).
- for (int shaderStage = ShaderStageCountInternal - 1; shaderStage >= 0; --shaderStage) {
- auto entryPoint = pipelineShaders.getEntryPoint(static_cast<ShaderStage>(shaderStage));
+ for (int shaderStage = ShaderStage::CountInternal - 1; shaderStage >= 0; --shaderStage) {
+ auto entryPoint = pipelineShaders.getEntryPoint(static_cast<ShaderStageEnum>(shaderStage));
if (entryPoint) {
- processFunction(*entryPoint, static_cast<ShaderStage>(shaderStage), inputCallees, otherCallees,
+ processFunction(*entryPoint, static_cast<ShaderStageEnum>(shaderStage), inputCallees, otherCallees,
getPostDominatorTree);
}
}
@@ -177,9 +177,9 @@ bool PatchInOutImportExport::runImpl(Module &module, PipelineShadersResult &pipe
if (func.isDeclaration())
continue;
auto shaderStage = getShaderStage(&func);
- if (shaderStage == ShaderStage::ShaderStageInvalid || &func == pipelineShaders.getEntryPoint(shaderStage))
+ if (!shaderStage || &func == pipelineShaders.getEntryPoint(shaderStage.value()))
continue;
- processFunction(func, shaderStage, inputCallees, otherCallees, getPostDominatorTree);
+ processFunction(func, shaderStage.value(), inputCallees, otherCallees, getPostDominatorTree);
}
for (auto callInst : m_importCalls) {
@@ -200,7 +200,7 @@ bool PatchInOutImportExport::runImpl(Module &module, PipelineShadersResult &pipe
}
void PatchInOutImportExport::processFunction(
- Function &func, ShaderStage shaderStage, SmallVectorImpl<Function *> &inputCallees,
+ Function &func, ShaderStageEnum shaderStage, SmallVectorImpl<Function *> &inputCallees,
SmallVectorImpl<Function *> &otherCallees,
const std::function<PostDominatorTree &(Function &)> &getPostDominatorTree) {
PostDominatorTree &postDomTree = getPostDominatorTree(func);
@@ -271,10 +271,10 @@ void PatchInOutImportExport::processShader() {
// Initialize the output value for gl_PrimitiveID
const auto &builtInUsage = m_pipelineState->getShaderResourceUsage(m_shaderStage)->builtInUsage;
const auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(m_shaderStage)->entryArgIdxs;
- if (m_shaderStage == ShaderStageVertex) {
+ if (m_shaderStage == ShaderStage::Vertex) {
if (builtInUsage.vs.primitiveId)
m_primitiveId = getFunctionArgument(m_entryPoint, entryArgIdxs.vs.primitiveId);
- } else if (m_shaderStage == ShaderStageTessEval) {
+ } else if (m_shaderStage == ShaderStage::TessEval) {
if (builtInUsage.tes.primitiveId) {
m_primitiveId = getFunctionArgument(m_entryPoint, entryArgIdxs.tes.patchId);
}
@@ -295,11 +295,11 @@ void PatchInOutImportExport::processShader() {
}
// Initialize calculation factors for tessellation shader
- if (m_shaderStage == ShaderStageTessControl || m_shaderStage == ShaderStageTessEval) {
- const unsigned stageMask = m_pipelineState->getShaderStageMask();
- const bool hasTcs = ((stageMask & shaderStageToMask(ShaderStageTessControl)) != 0);
+ if (m_shaderStage == ShaderStage::TessControl || m_shaderStage == ShaderStage::TessEval) {
+ const auto stageMask = m_pipelineState->getShaderStageMask();
+ const bool hasTcs = stageMask.contains(ShaderStage::TessControl);
- auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl)->inOutUsage.tcs.calcFactor;
+ auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl)->inOutUsage.tcs.calcFactor;
if (!calcFactor.initialized) {
calcFactor.initialized = true;
@@ -322,8 +322,8 @@ void PatchInOutImportExport::processShader() {
// patchConstTotalSize = patchConstCount * 4 * patchCountPerThreadGroup
// tessFactorTotalSize = 6 * patchCountPerThreadGroup
//
- const auto &tcsInOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl)->inOutUsage;
- const auto &tesInOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessEval)->inOutUsage;
+ const auto &tcsInOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl)->inOutUsage;
+ const auto &tesInOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessEval)->inOutUsage;
const unsigned inLocCount = std::max(tcsInOutUsage.inputMapLocCount, 1u);
const unsigned outLocCount =
@@ -397,7 +397,7 @@ void PatchInOutImportExport::processShader() {
calcFactor.onChip.specialTfValueStart = calcFactor.onChip.hsPatchCountStart + 1;
const unsigned maxNumHsWaves =
- Gfx9::MaxHsThreadsPerSubgroup / m_pipelineState->getMergedShaderWaveSize(ShaderStageTessControl);
+ Gfx9::MaxHsThreadsPerSubgroup / m_pipelineState->getMergedShaderWaveSize(ShaderStage::TessControl);
calcFactor.specialTfValueSize = maxNumHsWaves * 2;
calcFactor.tessOnChipLdsSize += 1 + calcFactor.specialTfValueSize;
@@ -406,8 +406,8 @@ void PatchInOutImportExport::processShader() {
// NOTE: If ray query uses LDS stack, the expected max thread count in the group is 64. And we force wave size
// to be 64 in order to keep all threads in the same wave. In the future, we could consider to get rid of this
// restriction by providing the capability of querying thread ID in group rather than in wave.
- const auto vsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageVertex);
- const auto tcsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl);
+ const auto vsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Vertex);
+ const auto tcsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl);
if (vsResUsage->useRayQueryLdsStack || tcsResUsage->useRayQueryLdsStack)
calcFactor.rayQueryLdsStackSize = MaxRayQueryLdsStackEntries * MaxRayQueryThreadsPerGroup;
@@ -466,7 +466,7 @@ void PatchInOutImportExport::processShader() {
}
}
- if (m_shaderStage == ShaderStageCompute) {
+ if (m_shaderStage == ShaderStage::Compute) {
// In a compute shader, process lgc.reconfigure.local.invocation.id calls.
// This does not particularly have to be done here; it could be done anywhere after BuilderImpl.
for (Function &func : *m_module) {
@@ -475,7 +475,7 @@ void PatchInOutImportExport::processShader() {
// Different with above, this will force the threadID swizzle which will rearrange thread ID within a group into
// blocks of 8*4, not to reconfig workgroup automatically and will support to be swizzled in 8*4 block
// split.
- if (func.isDeclaration() && func.getName().startswith(lgcName::ReconfigureLocalInvocationId)) {
+ if (func.isDeclaration() && func.getName().starts_with(lgcName::ReconfigureLocalInvocationId)) {
unsigned workgroupSizeX = mode.workgroupSizeX;
unsigned workgroupSizeY = mode.workgroupSizeY;
unsigned workgroupSizeZ = mode.workgroupSizeZ;
@@ -497,7 +497,7 @@ void PatchInOutImportExport::processShader() {
}
}
- if (func.isDeclaration() && func.getName().startswith(lgcName::SwizzleWorkgroupId)) {
+ if (func.isDeclaration() && func.getName().starts_with(lgcName::SwizzleWorkgroupId)) {
createSwizzleThreadGroupFunction();
}
}
@@ -547,10 +547,10 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
auto importBuiltInOutput = lgcName::OutputImportBuiltIn;
const bool isGenericInputImport = isa<InputImportGenericOp>(callInst);
- const bool isBuiltInInputImport = mangledName.startswith(importBuiltInInput);
+ const bool isBuiltInInputImport = mangledName.starts_with(importBuiltInInput);
const bool isInterpolatedInputImport = isa<InputImportInterpolatedOp>(callInst);
const bool isGenericOutputImport = isa<OutputImportGenericOp>(callInst);
- const bool isBuiltInOutputImport = mangledName.startswith(importBuiltInOutput);
+ const bool isBuiltInOutputImport = mangledName.starts_with(importBuiltInOutput);
const bool isImport = (isGenericInputImport || isBuiltInInputImport || isInterpolatedInputImport ||
isGenericOutputImport || isBuiltInOutputImport);
@@ -559,9 +559,9 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
auto exportBuiltInOutput = lgcName::OutputExportBuiltIn;
auto exportXfbOutput = lgcName::OutputExportXfb;
- const bool isGenericOutputExport = mangledName.startswith(exportGenericOutput);
- const bool isBuiltInOutputExport = mangledName.startswith(exportBuiltInOutput);
- const bool isXfbOutputExport = mangledName.startswith(exportXfbOutput);
+ const bool isGenericOutputExport = mangledName.starts_with(exportGenericOutput);
+ const bool isBuiltInOutputExport = mangledName.starts_with(exportBuiltInOutput);
+ const bool isXfbOutputExport = mangledName.starts_with(exportXfbOutput);
const bool isExport = (isGenericOutputExport || isBuiltInOutputExport || isXfbOutputExport);
@@ -582,10 +582,10 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
LLVM_DEBUG(dbgs() << "Find input import call: builtin = " << builtInId << "\n");
switch (m_shaderStage) {
- case ShaderStageVertex:
+ case ShaderStage::Vertex:
// Nothing to do
break;
- case ShaderStageTessControl: {
+ case ShaderStage::TessControl: {
// Builtin Call has different number of operands
Value *elemIdx = nullptr;
Value *vertexIdx = nullptr;
@@ -598,7 +598,7 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
input = patchTcsBuiltInInputImport(inputTy, builtInId, elemIdx, vertexIdx, builder);
break;
}
- case ShaderStageTessEval: {
+ case ShaderStage::TessEval: {
// Builtin Call has different number of operands
Value *elemIdx = nullptr;
Value *vertexIdx = nullptr;
@@ -610,7 +610,7 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
input = patchTesBuiltInInputImport(inputTy, builtInId, elemIdx, vertexIdx, builder);
break;
}
- case ShaderStageGeometry: {
+ case ShaderStage::Geometry: {
// Builtin Call has different number of operands
Value *vertexIdx = nullptr;
if (callInst.arg_size() > 1)
@@ -619,13 +619,13 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
input = patchGsBuiltInInputImport(inputTy, builtInId, vertexIdx, builder);
break;
}
- case ShaderStageMesh: {
+ case ShaderStage::Mesh: {
assert(callInst.arg_size() == 2);
assert(isDontCareValue(callInst.getOperand(1)));
input = patchMeshBuiltInInputImport(inputTy, builtInId, builder);
break;
}
- case ShaderStageFragment: {
+ case ShaderStage::Fragment: {
Value *generalVal = nullptr;
if (callInst.arg_size() >= 2)
generalVal = callInst.getArgOperand(1);
@@ -638,7 +638,7 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
}
}
} else {
- assert(m_shaderStage != ShaderStageVertex && "vertex fetch is handled by LowerVertexFetch");
+ assert(m_shaderStage != ShaderStage::Vertex && "vertex fetch is handled by LowerVertexFetch");
auto &genericLocationOp = cast<GenericLocationOp>(callInst);
assert(isGenericInputImport || isInterpolatedInputImport);
@@ -655,21 +655,22 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
origLoc += constLocOffset->getZExtValue();
locOffset = nullptr;
} else {
- assert(m_shaderStage == ShaderStageTessControl || m_shaderStage == ShaderStageTessEval ||
- m_shaderStage == ShaderStageFragment);
+ assert(m_shaderStage == ShaderStage::TessControl || m_shaderStage == ShaderStage::TessEval ||
+ m_shaderStage == ShaderStage::Fragment);
}
InOutLocationInfo origLocInfo;
origLocInfo.setLocation(origLoc);
- if (m_shaderStage == ShaderStageTessEval ||
- (m_shaderStage == ShaderStageFragment &&
- (m_pipelineState->getPrevShaderStage(m_shaderStage) == ShaderStageMesh || m_pipelineState->isUnlinked()))) {
+ if (m_shaderStage == ShaderStage::TessEval ||
+ (m_shaderStage == ShaderStage::Fragment &&
+ (m_pipelineState->getPrevShaderStage(m_shaderStage) == ShaderStage::Mesh ||
+ m_pipelineState->isUnlinked()))) {
// NOTE: For generic inputs of tessellation evaluation shader or fragment shader whose previous shader stage
// is mesh shader or is in unlinked pipeline, they could be per-patch ones or per-primitive ones.
const bool isPerPrimitive = genericLocationOp.getPerPrimitive();
if (isPerPrimitive) {
- auto &checkedMap = m_shaderStage == ShaderStageTessEval ? resUsage->inOutUsage.perPatchInputLocMap
- : resUsage->inOutUsage.perPrimitiveInputLocMap;
+ auto &checkedMap = m_shaderStage == ShaderStage::TessEval ? resUsage->inOutUsage.perPatchInputLocMap
+ : resUsage->inOutUsage.perPrimitiveInputLocMap;
auto locMapIt = checkedMap.find(origLoc);
if (locMapIt != checkedMap.end())
loc = locMapIt->second;
@@ -690,7 +691,7 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
} else {
if (m_pipelineState->canPackInput(m_shaderStage)) {
// The inputLocInfoMap of {TCS, GS, FS} maps original InOutLocationInfo to tightly compact InOutLocationInfo
- const bool isTcs = m_shaderStage == ShaderStageTessControl;
+ const bool isTcs = m_shaderStage == ShaderStage::TessControl;
(void)isTcs;
// All packing of the VS-TCS interface is disabled if dynamic indexing is detected
assert(!isTcs || (isa<ConstantInt>(genericLocationOp.getLocOffset()) &&
@@ -725,7 +726,7 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
assert(isDontCareValue(elemIdx) == false);
switch (m_shaderStage) {
- case ShaderStageTessControl: {
+ case ShaderStage::TessControl: {
auto &inputOp = cast<InputImportGenericOp>(genericLocationOp);
auto vertexIdx = inputOp.getArrayIndex();
assert(isDontCareValue(vertexIdx) == false);
@@ -733,7 +734,7 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
input = patchTcsGenericInputImport(inputTy, loc, locOffset, elemIdx, vertexIdx, builder);
break;
}
- case ShaderStageTessEval: {
+ case ShaderStage::TessEval: {
auto &inputOp = cast<InputImportGenericOp>(genericLocationOp);
Value *vertexIdx = nullptr;
@@ -743,7 +744,7 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
input = patchTesGenericInputImport(inputTy, loc, locOffset, elemIdx, vertexIdx, builder);
break;
}
- case ShaderStageGeometry: {
+ case ShaderStage::Geometry: {
const unsigned compIdx = cast<ConstantInt>(elemIdx)->getZExtValue();
auto &inputOp = cast<InputImportGenericOp>(genericLocationOp);
@@ -753,7 +754,7 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
input = patchGsGenericInputImport(inputTy, loc, compIdx, vertexIdx, builder);
break;
}
- case ShaderStageFragment: {
+ case ShaderStage::Fragment: {
unsigned interpMode = InOutInfo::InterpModeSmooth;
Value *interpValue = nullptr;
bool isPerPrimitive = false;
@@ -781,7 +782,7 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
callInst.replaceAllUsesWith(input);
} else if (isImport && isOutput) {
// Output imports
- assert(m_shaderStage == ShaderStageTessControl);
+ assert(m_shaderStage == ShaderStage::TessControl);
Value *output = nullptr;
Type *outputTy = callInst.getType();
@@ -858,23 +859,23 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
// NOTE: Transform feedback output will be done in last vertex-processing shader stage.
switch (m_shaderStage) {
- case ShaderStageVertex: {
+ case ShaderStage::Vertex: {
// No TS/GS pipeline, VS is the last stage
if (!m_hasGs && !m_hasTs)
patchXfbOutputExport(output, xfbBuffer, xfbOffset, streamId, builder);
break;
}
- case ShaderStageTessEval: {
+ case ShaderStage::TessEval: {
// TS-only pipeline, TES is the last stage
if (!m_hasGs)
patchXfbOutputExport(output, xfbBuffer, xfbOffset, streamId, builder);
break;
}
- case ShaderStageGeometry: {
+ case ShaderStage::Geometry: {
// Do nothing, transform feedback output is done in copy shader
break;
}
- case ShaderStageCopyShader: {
+ case ShaderStage::CopyShader: {
// TS-GS or GS-only pipeline, copy shader is the last stage
patchXfbOutputExport(output, xfbBuffer, xfbOffset, streamId, builder);
break;
@@ -888,11 +889,11 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
const unsigned builtInId = value;
switch (m_shaderStage) {
- case ShaderStageVertex: {
+ case ShaderStage::Vertex: {
patchVsBuiltInOutputExport(output, builtInId, &callInst);
break;
}
- case ShaderStageTessControl: {
+ case ShaderStage::TessControl: {
assert(callInst.arg_size() == 4);
Value *elemIdx = isDontCareValue(callInst.getOperand(1)) ? nullptr : callInst.getOperand(1);
Value *vertexIdx = isDontCareValue(callInst.getOperand(2)) ? nullptr : callInst.getOperand(2);
@@ -900,15 +901,15 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
patchTcsBuiltInOutputExport(output, builtInId, elemIdx, vertexIdx, &callInst);
break;
}
- case ShaderStageTessEval: {
+ case ShaderStage::TessEval: {
patchTesBuiltInOutputExport(output, builtInId, &callInst);
break;
}
- case ShaderStageGeometry: {
+ case ShaderStage::Geometry: {
patchGsBuiltInOutputExport(output, builtInId, m_pipelineState->getRasterizerState().rasterStream, builder);
break;
}
- case ShaderStageMesh: {
+ case ShaderStage::Mesh: {
assert(callInst.arg_size() == 5);
Value *elemIdx = isDontCareValue(callInst.getOperand(1)) ? nullptr : callInst.getOperand(1);
Value *vertexOrPrimitiveIdx = callInst.getOperand(2);
@@ -917,11 +918,11 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
patchMeshBuiltInOutputExport(output, builtInId, elemIdx, vertexOrPrimitiveIdx, isPerPrimitive, &callInst);
break;
}
- case ShaderStageFragment: {
+ case ShaderStage::Fragment: {
patchFsBuiltInOutputExport(output, builtInId, &callInst);
break;
}
- case ShaderStageCopyShader: {
+ case ShaderStage::CopyShader: {
patchCopyShaderBuiltInOutputExport(output, builtInId, &callInst);
break;
}
@@ -940,21 +941,21 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
InOutLocationInfo origLocInfo;
origLocInfo.setLocation(value);
- if (m_shaderStage == ShaderStageGeometry)
+ if (m_shaderStage == ShaderStage::Geometry)
origLocInfo.setStreamId(cast<ConstantInt>(callInst.getOperand(2))->getZExtValue());
- if (m_shaderStage == ShaderStageTessControl || m_shaderStage == ShaderStageMesh) {
+ if (m_shaderStage == ShaderStage::TessControl || m_shaderStage == ShaderStage::Mesh) {
locOffset = callInst.getOperand(1);
// NOTE: For generic outputs of tessellation control shader or mesh shader, they could be per-patch ones or
// per-primitive ones.
- if (m_shaderStage == ShaderStageMesh && cast<ConstantInt>(callInst.getOperand(4))->getZExtValue() != 0) {
+ if (m_shaderStage == ShaderStage::Mesh && cast<ConstantInt>(callInst.getOperand(4))->getZExtValue() != 0) {
auto locMapIt = resUsage->inOutUsage.perPrimitiveOutputLocMap.find(value);
if (locMapIt != resUsage->inOutUsage.perPrimitiveOutputLocMap.end()) {
loc = locMapIt->second;
exist = true;
}
- } else if (m_shaderStage == ShaderStageTessControl && isDontCareValue(callInst.getOperand(3))) {
+ } else if (m_shaderStage == ShaderStage::TessControl && isDontCareValue(callInst.getOperand(3))) {
auto locMapIt = resUsage->inOutUsage.perPatchOutputLocMap.find(value);
if (locMapIt != resUsage->inOutUsage.perPatchOutputLocMap.end()) {
loc = locMapIt->second;
@@ -976,13 +977,13 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
}
}
}
- } else if (m_shaderStage == ShaderStageCopyShader) {
+ } else if (m_shaderStage == ShaderStage::CopyShader) {
exist = true;
loc = value;
} else {
// Generic output exports of FS should have been handled by the LowerFragColorExport pass
- assert(m_shaderStage == ShaderStageVertex || m_shaderStage == ShaderStageGeometry ||
- m_shaderStage == ShaderStageTessEval);
+ assert(m_shaderStage == ShaderStage::Vertex || m_shaderStage == ShaderStage::Geometry ||
+ m_shaderStage == ShaderStage::TessEval);
// Check component offset and search the location info map once again
unsigned component = cast<ConstantInt>(callInst.getOperand(1))->getZExtValue();
@@ -1010,14 +1011,14 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
assert(loc != InvalidValue);
switch (m_shaderStage) {
- case ShaderStageVertex: {
+ case ShaderStage::Vertex: {
assert(callInst.arg_size() == 3);
if (elemIdx == InvalidValue)
elemIdx = cast<ConstantInt>(callInst.getOperand(1))->getZExtValue();
patchVsGenericOutputExport(output, loc, elemIdx, builder);
break;
}
- case ShaderStageTessControl: {
+ case ShaderStage::TessControl: {
assert(callInst.arg_size() == 5);
auto elemIdx = callInst.getOperand(2);
@@ -1028,14 +1029,14 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
patchTcsGenericOutputExport(output, loc, locOffset, elemIdx, vertexIdx, builder);
break;
}
- case ShaderStageTessEval: {
+ case ShaderStage::TessEval: {
assert(callInst.arg_size() == 3);
if (elemIdx == InvalidValue)
elemIdx = cast<ConstantInt>(callInst.getOperand(1))->getZExtValue();
patchTesGenericOutputExport(output, loc, elemIdx, builder);
break;
}
- case ShaderStageGeometry: {
+ case ShaderStage::Geometry: {
assert(callInst.arg_size() == 4);
if (elemIdx == InvalidValue)
elemIdx = cast<ConstantInt>(callInst.getOperand(1))->getZExtValue();
@@ -1043,7 +1044,7 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
patchGsGenericOutputExport(output, loc, elemIdx, streamId, builder);
break;
}
- case ShaderStageMesh: {
+ case ShaderStage::Mesh: {
assert(callInst.arg_size() == 6);
auto elemIdx = callInst.getOperand(2);
@@ -1054,7 +1055,7 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
patchMeshGenericOutputExport(output, loc, locOffset, elemIdx, vertexOrPrimitiveIdx, isPerPrimitive, builder);
break;
}
- case ShaderStageCopyShader: {
+ case ShaderStage::CopyShader: {
patchCopyShaderGenericOutputExport(output, loc, &callInst);
break;
}
@@ -1077,16 +1078,16 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
}
if (emitStream != InvalidValue) {
- assert(m_shaderStage == ShaderStageGeometry); // Must be geometry shader
+ assert(m_shaderStage == ShaderStage::Geometry); // Must be geometry shader
// NOTE: Implicitly store the value of view index to GS-VS ring buffer for raster stream if multi-view is
// enabled. Copy shader will read the value from GS-VS ring and export it to vertex position data.
if (m_pipelineState->getInputAssemblyState().multiView != MultiViewMode::Disable) {
- auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry);
+ auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry);
auto rasterStream = m_pipelineState->getRasterizerState().rasterStream;
if (emitStream == rasterStream) {
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageGeometry)->entryArgIdxs.gs;
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Geometry)->entryArgIdxs.gs;
auto viewIndex = getFunctionArgument(m_entryPoint, entryArgIdxs.viewId);
const auto &builtInOutLocMap = resUsage->inOutUsage.builtInOutputLocMap;
@@ -1115,15 +1116,15 @@ void PatchInOutImportExport::visitCallInst(CallInst &callInst) {
// @param retInst : "Ret" instruction
void PatchInOutImportExport::visitReturnInst(ReturnInst &retInst) {
// We only handle the "ret" of shader entry point
- if (m_shaderStage == ShaderStageInvalid)
+ if (m_shaderStage == ShaderStage::Invalid)
return;
const auto nextStage = m_pipelineState->getNextShaderStage(m_shaderStage);
// Whether this shader stage has to use "exp" instructions to export outputs
- const bool useExpInst = ((m_shaderStage == ShaderStageVertex || m_shaderStage == ShaderStageTessEval ||
- m_shaderStage == ShaderStageCopyShader) &&
- (nextStage == ShaderStageInvalid || nextStage == ShaderStageFragment));
+ const bool useExpInst = ((m_shaderStage == ShaderStage::Vertex || m_shaderStage == ShaderStage::TessEval ||
+ m_shaderStage == ShaderStage::CopyShader) &&
+ (nextStage == ShaderStage::Invalid || nextStage == ShaderStage::Fragment));
auto zero = ConstantFP::get(Type::getFloatTy(*m_context), 0.0);
auto one = ConstantFP::get(Type::getFloatTy(*m_context), 1.0);
@@ -1132,7 +1133,7 @@ void PatchInOutImportExport::visitReturnInst(ReturnInst &retInst) {
Instruction *insertPos = &retInst;
const bool enableXfb = m_pipelineState->enableXfb();
- if (m_shaderStage == ShaderStageCopyShader && enableXfb) {
+ if (m_shaderStage == ShaderStage::CopyShader && enableXfb) {
if (!m_pipelineState->getNggControl()->enableNgg) {
// NOTE: For copy shader, if transform feedback is enabled for multiple streams, the following processing doesn't
// happen in return block. Rather, they happen in the switch-case branch for the raster stream. See the following:
@@ -1207,8 +1208,8 @@ void PatchInOutImportExport::visitReturnInst(ReturnInst &retInst) {
auto &inOutUsage = m_pipelineState->getShaderResourceUsage(m_shaderStage)->inOutUsage;
- if (m_shaderStage == ShaderStageVertex) {
- auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageVertex)->builtInUsage.vs;
+ if (m_shaderStage == ShaderStage::Vertex) {
+ auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Vertex)->builtInUsage.vs;
usePosition = builtInUsage.position;
usePointSize = builtInUsage.pointSize;
@@ -1219,8 +1220,8 @@ void PatchInOutImportExport::visitReturnInst(ReturnInst &retInst) {
clipDistanceCount = builtInUsage.clipDistance;
cullDistanceCount = builtInUsage.cullDistance;
useEdgeFlag = builtInUsage.edgeFlag;
- } else if (m_shaderStage == ShaderStageTessEval) {
- auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessEval)->builtInUsage.tes;
+ } else if (m_shaderStage == ShaderStage::TessEval) {
+ auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessEval)->builtInUsage.tes;
usePosition = builtInUsage.position;
usePointSize = builtInUsage.pointSize;
@@ -1230,8 +1231,8 @@ void PatchInOutImportExport::visitReturnInst(ReturnInst &retInst) {
clipDistanceCount = builtInUsage.clipDistance;
cullDistanceCount = builtInUsage.cullDistance;
} else {
- assert(m_shaderStage == ShaderStageCopyShader);
- auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageCopyShader)->builtInUsage.gs;
+ assert(m_shaderStage == ShaderStage::CopyShader);
+ auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::CopyShader)->builtInUsage.gs;
usePosition = builtInUsage.position;
usePointSize = builtInUsage.pointSize;
@@ -1245,21 +1246,21 @@ void PatchInOutImportExport::visitReturnInst(ReturnInst &retInst) {
const auto enableMultiView = m_pipelineState->getInputAssemblyState().multiView != MultiViewMode::Disable;
if (enableMultiView) {
- if (m_shaderStage == ShaderStageVertex) {
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageVertex)->entryArgIdxs.vs;
+ if (m_shaderStage == ShaderStage::Vertex) {
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Vertex)->entryArgIdxs.vs;
m_viewIndex = getFunctionArgument(m_entryPoint, entryArgIdxs.viewId);
- } else if (m_shaderStage == ShaderStageTessEval) {
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageTessEval)->entryArgIdxs.tes;
+ } else if (m_shaderStage == ShaderStage::TessEval) {
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::TessEval)->entryArgIdxs.tes;
m_viewIndex = getFunctionArgument(m_entryPoint, entryArgIdxs.viewId);
} else {
- assert(m_shaderStage == ShaderStageCopyShader);
+ assert(m_shaderStage == ShaderStage::CopyShader);
assert(m_viewIndex); // Must have been explicitly loaded in copy shader
}
}
const auto &builtInOutLocs =
- m_shaderStage == ShaderStageCopyShader ? inOutUsage.gs.builtInOutLocs : inOutUsage.builtInOutputLocMap;
- const auto &nextBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageFragment)->builtInUsage.fs;
+ m_shaderStage == ShaderStage::CopyShader ? inOutUsage.gs.builtInOutLocs : inOutUsage.builtInOutputLocMap;
+ const auto &nextBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Fragment)->builtInUsage.fs;
// NOTE: If gl_Position is not present in this shader stage, we have to export a dummy one.
if (!usePosition) {
@@ -1343,10 +1344,10 @@ void PatchInOutImportExport::visitReturnInst(ReturnInst &retInst) {
}
// NOTE: We have to export gl_ClipDistance[] or gl_CullDistancep[] via generic outputs as well.
- assert(nextStage == ShaderStageInvalid || nextStage == ShaderStageFragment);
+ assert(nextStage == ShaderStage::Invalid || nextStage == ShaderStage::Fragment);
bool hasClipCullExport = true;
- if (nextStage == ShaderStageFragment) {
+ if (nextStage == ShaderStage::Fragment) {
hasClipCullExport = (nextBuiltInUsage.clipDistance > 0 || nextBuiltInUsage.cullDistance > 0);
if (hasClipCullExport) {
@@ -1397,12 +1398,12 @@ void PatchInOutImportExport::visitReturnInst(ReturnInst &retInst) {
// Export gl_PrimitiveID before entry-point returns
if (usePrimitiveId) {
bool hasPrimitiveIdExport = false;
- if (nextStage == ShaderStageFragment) {
+ if (nextStage == ShaderStage::Fragment) {
hasPrimitiveIdExport = nextBuiltInUsage.primitiveId;
- } else if (nextStage == ShaderStageInvalid) {
- if (m_shaderStage == ShaderStageCopyShader) {
+ } else if (nextStage == ShaderStage::Invalid) {
+ if (m_shaderStage == ShaderStage::CopyShader) {
hasPrimitiveIdExport =
- m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->builtInUsage.gs.primitiveId;
+ m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->builtInUsage.gs.primitiveId;
}
}
@@ -1481,9 +1482,9 @@ void PatchInOutImportExport::visitReturnInst(ReturnInst &retInst) {
// NOTE: We have to export gl_ViewportIndex via generic outputs as well.
if (useViewportIndex) {
bool hasViewportIndexExport = true;
- if (nextStage == ShaderStageFragment) {
+ if (nextStage == ShaderStage::Fragment) {
hasViewportIndexExport = nextBuiltInUsage.viewportIndex;
- } else if (nextStage == ShaderStageInvalid) {
+ } else if (nextStage == ShaderStage::Invalid) {
hasViewportIndexExport = false;
}
@@ -1500,9 +1501,9 @@ void PatchInOutImportExport::visitReturnInst(ReturnInst &retInst) {
// NOTE: We have to export gl_Layer via generic outputs as well.
if (useLayer) {
bool hasLayerExport = true;
- if (nextStage == ShaderStageFragment) {
+ if (nextStage == ShaderStage::Fragment) {
hasLayerExport = nextBuiltInUsage.layer;
- } else if (nextStage == ShaderStageInvalid) {
+ } else if (nextStage == ShaderStage::Invalid) {
hasLayerExport = false;
}
@@ -1540,14 +1541,14 @@ void PatchInOutImportExport::visitReturnInst(ReturnInst &retInst) {
inOutUsage.expCount = std::max(inOutUsage.expCount, newLoc + 1); // Update export count
}
}
- } else if (m_shaderStage == ShaderStageTessControl) {
+ } else if (m_shaderStage == ShaderStage::TessControl) {
// NOTE: We will read back tessellation factors from on-chip LDS in later phases and write them to TF buffer.
// Add fence and barrier before the return instruction to make sure they have been stored already.
SyncScope::ID syncScope = m_context->getOrInsertSyncScopeID("workgroup");
new FenceInst(*m_context, AtomicOrdering::Release, syncScope, insertPos);
emitCall("llvm.amdgcn.s.barrier", Type::getVoidTy(*m_context), {}, {}, insertPos);
new FenceInst(*m_context, AtomicOrdering::Acquire, syncScope, insertPos);
- } else if (m_shaderStage == ShaderStageGeometry) {
+ } else if (m_shaderStage == ShaderStage::Geometry) {
if (m_gfxIp.major >= 10) {
// NOTE: Per programming guide, we should do a "s_waitcnt 0,0,0 + s_waitcnt_vscnt 0" before issuing a "done", so
// we use fence release to generate s_waitcnt vmcnt lgkmcnt/s_waitcnt_vscnt before s_sendmsg(MSG_GS_DONE)
@@ -1556,12 +1557,12 @@ void PatchInOutImportExport::visitReturnInst(ReturnInst &retInst) {
new FenceInst(*m_context, AtomicOrdering::Release, scope, insertPos);
}
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageGeometry)->entryArgIdxs.gs;
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Geometry)->entryArgIdxs.gs;
auto gsWaveId = getFunctionArgument(m_entryPoint, entryArgIdxs.gsWaveId);
Value *args[] = {ConstantInt::get(Type::getInt32Ty(*m_context), GsDone), gsWaveId};
emitCall("llvm.amdgcn.s.sendmsg", Type::getVoidTy(*m_context), args, {}, insertPos);
- } else if (m_shaderStage == ShaderStageFragment) {
+ } else if (m_shaderStage == ShaderStage::Fragment) {
// Fragment shader export are handled in LowerFragColorExport.
return;
}
@@ -1794,14 +1795,14 @@ Value *PatchInOutImportExport::performFsParameterLoad(BuilderBase &builder, Valu
Value *PatchInOutImportExport::patchFsGenericInputImport(Type *inputTy, unsigned location, Value *locOffset,
Value *compIdx, bool isPerPrimitive, unsigned interpMode,
Value *interpValue, bool highHalf, BuilderBase &builder) {
- auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageFragment);
+ auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Fragment);
auto &interpInfo = resUsage->inOutUsage.fs.interpInfo;
// NOTE: For per-primitive input, the specified location is still per-primitive based. To import the input value, we
// have to adjust it by adding the total number of per-vertex inputs since per-vertex exports/imports are prior to
// per-primitive ones.
if (isPerPrimitive) {
- auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStageFragment)->inOutUsage;
+ auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Fragment)->inOutUsage;
location += inOutUsage.inputMapLocCount;
}
@@ -1836,7 +1837,7 @@ Value *PatchInOutImportExport::patchFsGenericInputImport(Type *inputTy, unsigned
};
}
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageFragment)->entryArgIdxs.fs;
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Fragment)->entryArgIdxs.fs;
auto primMask = getFunctionArgument(m_entryPoint, entryArgIdxs.primMask);
Value *coordI = nullptr;
Value *coordJ = nullptr;
@@ -2119,8 +2120,8 @@ Value *PatchInOutImportExport::patchTcsBuiltInInputImport(Type *inputTy, unsigne
Value *vertexIdx, BuilderBase &builder) {
Value *input = PoisonValue::get(inputTy);
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageTessControl)->entryArgIdxs.tcs;
- auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl);
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::TessControl)->entryArgIdxs.tcs;
+ auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl);
const auto &inoutUsage = resUsage->inOutUsage;
const auto &builtInInLocMap = inoutUsage.builtInInputLocMap;
@@ -2209,9 +2210,9 @@ Value *PatchInOutImportExport::patchTesBuiltInInputImport(Type *inputTy, unsigne
Value *vertexIdx, BuilderBase &builder) {
Value *input = PoisonValue::get(inputTy);
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageTessEval)->entryArgIdxs.tes;
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::TessEval)->entryArgIdxs.tes;
- auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessEval);
+ auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessEval);
const auto &inOutUsage = resUsage->inOutUsage;
const auto &builtInInLocMap = inOutUsage.builtInInputLocMap;
const auto &perPatchBuiltInInLocMap = inOutUsage.perPatchBuiltInInputLocMap;
@@ -2263,7 +2264,7 @@ Value *PatchInOutImportExport::patchTesBuiltInInputImport(Type *inputTy, unsigne
}
case BuiltInPatchVertices: {
unsigned patchVertices = MaxTessPatchVertices;
- const bool hasTcs = m_pipelineState->hasShaderStage(ShaderStageTessControl);
+ const bool hasTcs = m_pipelineState->hasShaderStage(ShaderStage::TessControl);
if (hasTcs)
patchVertices = m_pipelineState->getShaderModes()->getTessellationMode().outputVertices;
@@ -2336,8 +2337,8 @@ Value *PatchInOutImportExport::patchGsBuiltInInputImport(Type *inputTy, unsigned
BuilderBase &builder) {
Value *input = nullptr;
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageGeometry)->entryArgIdxs.gs;
- const auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->inOutUsage;
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Geometry)->entryArgIdxs.gs;
+ const auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->inOutUsage;
switch (builtInId) {
case BuiltInPosition:
@@ -2397,7 +2398,7 @@ Value *PatchInOutImportExport::patchMeshBuiltInInputImport(Type *inputTy, unsign
}
// Handle other built-ins
- const auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageMesh)->builtInUsage.mesh;
+ const auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Mesh)->builtInUsage.mesh;
(void(builtInUsage)); // Unused
switch (builtInId) {
@@ -2447,9 +2448,9 @@ Value *PatchInOutImportExport::patchFsBuiltInInputImport(Type *inputTy, unsigned
BuilderBase &builder) {
Value *input = PoisonValue::get(inputTy);
- const auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageFragment)->entryArgIdxs.fs;
- const auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageFragment)->builtInUsage.fs;
- auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStageFragment)->inOutUsage;
+ const auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Fragment)->entryArgIdxs.fs;
+ const auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Fragment)->builtInUsage.fs;
+ auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Fragment)->inOutUsage;
switch (builtInId) {
case BuiltInSampleMask: {
@@ -2519,7 +2520,7 @@ Value *PatchInOutImportExport::patchFsBuiltInInputImport(Type *inputTy, unsigned
// adjustedFragCoordZ = gl_FragCood.z + dFdxFine(gl_FragCood.z) * 1/16
// adjustedFragCoordZ = gl_ShadingRate.x == 1? adjustedFragCoordZ : gl_FragCood.z
if (m_pipelineState->getTargetInfo().getGpuWorkarounds().gfx10.waAdjustDepthImportVrs &&
- m_pipelineState->getShaderOptions(ShaderStageFragment).adjustDepthImportVrs) {
+ m_pipelineState->getShaderOptions(ShaderStage::Fragment).adjustDepthImportVrs) {
const unsigned firstDppCtrl = 0xF5; // FineX: [0,1,2,3]->[1,1,3,3]
const unsigned secondDppCtrl = 0xA0; // FineX: [0,1,2,3]->[0,0,2,2]
Value *fragCoordZAsInt = builder.CreateBitCast(fragCoord[2], builder.getInt32Ty());
@@ -2545,7 +2546,8 @@ Value *PatchInOutImportExport::patchFsBuiltInInputImport(Type *inputTy, unsigned
fragCoord[2] = adjustedFragCoordZ;
}
- fragCoord[3] = builder.CreateUnaryIntrinsic(Intrinsic::amdgcn_rcp, fragCoord[3]);
+ if (!m_pipelineState->getShaderModes()->getFragmentShaderMode().noReciprocalFragCoordW)
+ fragCoord[3] = builder.CreateUnaryIntrinsic(Intrinsic::amdgcn_rcp, fragCoord[3]);
for (unsigned i = 0; i < 4; ++i) {
input = builder.CreateInsertElement(input, fragCoord[i], i);
@@ -2587,10 +2589,10 @@ Value *PatchInOutImportExport::patchFsBuiltInInputImport(Type *inputTy, unsigned
case BuiltInLayer:
case BuiltInViewportIndex: {
unsigned loc = InvalidValue;
- const auto prevStage = m_pipelineState->getPrevShaderStage(ShaderStageFragment);
+ const auto prevStage = m_pipelineState->getPrevShaderStage(ShaderStage::Fragment);
bool isPerPrimitive = false;
- if (prevStage == ShaderStageMesh) {
+ if (prevStage == ShaderStage::Mesh) {
assert(inOutUsage.perPrimitiveBuiltInInputLocMap.count(builtInId) > 0);
loc = inOutUsage.perPrimitiveBuiltInInputLocMap[builtInId];
// NOTE: If the previous shader stage is mesh shader, those built-ins are exported via primitive attributes.
@@ -2802,7 +2804,7 @@ Value *PatchInOutImportExport::patchTcsBuiltInOutputImport(Type *outputTy, unsig
Value *vertexIdx, BuilderBase &builder) {
Value *output = PoisonValue::get(outputTy);
- const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl);
const auto &builtInUsage = resUsage->builtInUsage.tcs;
const auto &builtInOutLocMap = resUsage->inOutUsage.builtInOutputLocMap;
@@ -2859,7 +2861,8 @@ Value *PatchInOutImportExport::patchTcsBuiltInOutputImport(Type *outputTy, unsig
assert(builtInId != BuiltInTessLevelInner || builtInUsage.tessLevelInner);
(void(builtInUsage)); // Unused
- const auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl)->inOutUsage.tcs.calcFactor;
+ const auto &calcFactor =
+ m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl)->inOutUsage.tcs.calcFactor;
// tessLevelOuter (float[4]) + tessLevelInner (float[2])
// ldsOffset = tessFactorStart + relativeId * MaxTessFactorsPerPatch + elemIdx
@@ -2906,7 +2909,7 @@ void PatchInOutImportExport::patchVsBuiltInOutputExport(Value *output, unsigned
auto outputTy = output->getType();
- const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageVertex);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Vertex);
auto &builtInUsage = resUsage->builtInUsage.vs;
const auto &builtInOutLocMap = resUsage->inOutUsage.builtInOutputLocMap;
@@ -3072,7 +3075,7 @@ void PatchInOutImportExport::patchTcsBuiltInOutputExport(Value *output, unsigned
auto outputTy = output->getType();
- const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl);
const auto &builtInUsage = resUsage->builtInUsage.tcs;
const auto &builtInOutLocMap = resUsage->inOutUsage.builtInOutputLocMap;
const auto &perPatchBuiltInOutLocMap = resUsage->inOutUsage.perPatchBuiltInOutputLocMap;
@@ -3130,7 +3133,7 @@ void PatchInOutImportExport::patchTcsBuiltInOutputExport(Value *output, unsigned
// tessLevelOuter (float[4]) + tessLevelInner (float[2])
// ldsOffset = tessFactorStart + relativeId * MaxTessFactorsPerPatch + elemIdx
- uint32_t tessFactorStart = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl)
+ uint32_t tessFactorStart = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl)
->inOutUsage.tcs.calcFactor.onChip.tessFactorStart;
if (builtInId == BuiltInTessLevelInner)
tessFactorStart += 4;
@@ -3185,7 +3188,7 @@ void PatchInOutImportExport::patchTcsBuiltInOutputExport(Value *output, unsigned
// @param builtInId : ID of the built-in variable
// @param insertPos : Where to insert the patch instruction
void PatchInOutImportExport::patchTesBuiltInOutputExport(Value *output, unsigned builtInId, Instruction *insertPos) {
- const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessEval);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessEval);
auto &builtInUsage = resUsage->builtInUsage.tes;
const auto &builtInOutLocMap = resUsage->inOutUsage.builtInOutputLocMap;
@@ -3297,7 +3300,7 @@ void PatchInOutImportExport::patchTesBuiltInOutputExport(Value *output, unsigned
// @param builder : the builder to use
void PatchInOutImportExport::patchGsBuiltInOutputExport(Value *output, unsigned builtInId, unsigned streamId,
BuilderBase &builder) {
- const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry);
const auto &builtInUsage = resUsage->builtInUsage.gs;
const auto &builtInOutLocMap = resUsage->inOutUsage.builtInOutputLocMap;
@@ -3380,7 +3383,7 @@ void PatchInOutImportExport::patchMeshBuiltInOutputExport(Value *output, unsigne
}
// Handle normal per-vertex or per-primitive built-ins
- const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageMesh);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Mesh);
const auto &builtInUsage = resUsage->builtInUsage.mesh;
unsigned loc = InvalidValue;
@@ -3553,8 +3556,8 @@ void PatchInOutImportExport::patchCopyShaderBuiltInOutputExport(Value *output, u
// @param builder : The IR builder to create and insert IR instruction
void PatchInOutImportExport::patchXfbOutputExport(Value *output, unsigned xfbBuffer, unsigned xfbOffset,
unsigned streamId, BuilderBase &builder) {
- assert(m_shaderStage == ShaderStageVertex || m_shaderStage == ShaderStageTessEval ||
- m_shaderStage == ShaderStageCopyShader);
+ assert(m_shaderStage == ShaderStage::Vertex || m_shaderStage == ShaderStage::TessEval ||
+ m_shaderStage == ShaderStage::CopyShader);
const auto &xfbStrides = m_pipelineState->getXfbBufferStrides();
unsigned xfbStride = xfbStrides[xfbBuffer];
@@ -3726,8 +3729,8 @@ unsigned PatchInOutImportExport::combineBufferLoad(std::vector<Value *> &loadVal
// @param builder : The IR builder to create and insert IR instruction
void PatchInOutImportExport::storeValueToStreamOutBuffer(Value *storeValue, unsigned xfbBuffer, unsigned xfbOffset,
unsigned xfbStride, unsigned streamId, BuilderBase &builder) {
- assert(m_shaderStage == ShaderStageVertex || m_shaderStage == ShaderStageTessEval ||
- m_shaderStage == ShaderStageCopyShader);
+ assert(m_shaderStage == ShaderStage::Vertex || m_shaderStage == ShaderStage::TessEval ||
+ m_shaderStage == ShaderStage::CopyShader);
assert(xfbBuffer < MaxTransformFeedbackBuffers);
if (m_pipelineState->enableSwXfb()) {
@@ -3776,16 +3779,16 @@ void PatchInOutImportExport::storeValueToStreamOutBuffer(Value *storeValue, unsi
Value *streamOffset = nullptr;
const auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(m_shaderStage)->entryArgIdxs;
- if (m_shaderStage == ShaderStageVertex) {
+ if (m_shaderStage == ShaderStage::Vertex) {
streamInfo = getFunctionArgument(m_entryPoint, entryArgIdxs.vs.streamOutData.streamInfo);
writeIndex = getFunctionArgument(m_entryPoint, entryArgIdxs.vs.streamOutData.writeIndex);
streamOffset = getFunctionArgument(m_entryPoint, entryArgIdxs.vs.streamOutData.streamOffsets[xfbBuffer]);
- } else if (m_shaderStage == ShaderStageTessEval) {
+ } else if (m_shaderStage == ShaderStage::TessEval) {
streamInfo = getFunctionArgument(m_entryPoint, entryArgIdxs.tes.streamOutData.streamInfo);
writeIndex = getFunctionArgument(m_entryPoint, entryArgIdxs.tes.streamOutData.writeIndex);
streamOffset = getFunctionArgument(m_entryPoint, entryArgIdxs.tes.streamOutData.streamOffsets[xfbBuffer]);
} else {
- assert(m_shaderStage == ShaderStageCopyShader);
+ assert(m_shaderStage == ShaderStage::CopyShader);
streamInfo = getFunctionArgument(m_entryPoint, CopyShaderEntryArgIdxStreamInfo);
writeIndex = getFunctionArgument(m_entryPoint, CopyShaderEntryArgIdxWriteIndex);
@@ -3909,10 +3912,10 @@ void PatchInOutImportExport::storeValueToEsGsRing(Value *storeValue, unsigned lo
// Call buffer store intrinsic or LDS store
const auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(m_shaderStage)->entryArgIdxs;
Value *esGsOffset = nullptr;
- if (m_shaderStage == ShaderStageVertex)
+ if (m_shaderStage == ShaderStage::Vertex)
esGsOffset = getFunctionArgument(m_entryPoint, entryArgIdxs.vs.esGsOffset);
else {
- assert(m_shaderStage == ShaderStageTessEval);
+ assert(m_shaderStage == ShaderStage::TessEval);
esGsOffset = getFunctionArgument(m_entryPoint, entryArgIdxs.tes.esGsOffset);
}
@@ -4165,8 +4168,8 @@ Value *PatchInOutImportExport::calcEsGsRingOffsetForOutput(unsigned location, un
{
// ringOffset = esGsOffset + threadId * esGsRingItemSize + location * 4 + compIdx
- assert(m_pipelineState->hasShaderStage(ShaderStageGeometry));
- const auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->inOutUsage.gs.calcFactor;
+ assert(m_pipelineState->hasShaderStage(ShaderStage::Geometry));
+ const auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->inOutUsage.gs.calcFactor;
esGsOffset =
BinaryOperator::CreateLShr(esGsOffset, ConstantInt::get(Type::getInt32Ty(*m_context), 2), "", insertPos);
@@ -4229,7 +4232,7 @@ Value *PatchInOutImportExport::calcEsGsRingOffsetForInput(unsigned location, uns
// @param builder : the builder to use
Value *PatchInOutImportExport::calcGsVsRingOffsetForOutput(unsigned location, unsigned compIdx, unsigned streamId,
Value *vertexIdx, Value *gsVsOffset, BuilderBase &builder) {
- auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry);
+ auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry);
Value *ringOffset = nullptr;
@@ -4298,7 +4301,7 @@ Value *PatchInOutImportExport::readValueFromLds(bool offChip, Type *readTy, Valu
if (offChip) {
// Read from off-chip LDS buffer
const auto &offChipLdsBaseArgIdx =
- m_shaderStage == ShaderStageTessEval
+ m_shaderStage == ShaderStage::TessEval
? m_pipelineState->getShaderInterfaceData(m_shaderStage)->entryArgIdxs.tes.offChipLdsBase
: m_pipelineState->getShaderInterfaceData(m_shaderStage)->entryArgIdxs.tcs.offChipLdsBase;
@@ -4440,7 +4443,7 @@ void PatchInOutImportExport::writeValueToLds(bool offChip, Value *writeValue, Va
// @param builder : The IR builder to create and insert IR instruction
Value *PatchInOutImportExport::calcLdsOffsetForVsOutput(Type *outputTy, unsigned location, unsigned compIdx,
BuilderBase &builder) {
- assert(m_shaderStage == ShaderStageVertex);
+ assert(m_shaderStage == ShaderStage::Vertex);
// attribOffset = location * 4 + compIdx
Value *attribOffset = builder.getInt32(location * 4);
@@ -4455,10 +4458,10 @@ Value *PatchInOutImportExport::calcLdsOffsetForVsOutput(Type *outputTy, unsigned
attribOffset = builder.CreateAdd(attribOffset, builder.getInt32(compIdx));
- const auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageVertex)->entryArgIdxs.vs;
+ const auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Vertex)->entryArgIdxs.vs;
auto relVertexId = getFunctionArgument(m_entryPoint, entryArgIdxs.relVertexId);
- const auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl)->inOutUsage.tcs.calcFactor;
+ const auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl)->inOutUsage.tcs.calcFactor;
auto vertexStride = builder.getInt32(calcFactor.inVertexStride);
// dwordOffset = relVertexId * vertexStride + attribOffset
@@ -4479,9 +4482,9 @@ Value *PatchInOutImportExport::calcLdsOffsetForVsOutput(Type *outputTy, unsigned
// @param builder : The IR builder to create and insert IR instruction
Value *PatchInOutImportExport::calcLdsOffsetForTcsInput(Type *inputTy, unsigned location, Value *locOffset,
Value *compIdx, Value *vertexIdx, BuilderBase &builder) {
- assert(m_shaderStage == ShaderStageTessControl);
+ assert(m_shaderStage == ShaderStage::TessControl);
- const auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl)->inOutUsage.tcs;
+ const auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl)->inOutUsage.tcs;
const auto &calcFactor = inOutUsage.calcFactor;
// attribOffset = (location + locOffset) * 4 + compIdx
@@ -4532,9 +4535,9 @@ Value *PatchInOutImportExport::calcLdsOffsetForTcsInput(Type *inputTy, unsigned
// @param builder : The IR builder to create and insert IR instruction
Value *PatchInOutImportExport::calcLdsOffsetForTcsOutput(Type *outputTy, unsigned location, Value *locOffset,
Value *compIdx, Value *vertexIdx, BuilderBase &builder) {
- assert(m_shaderStage == ShaderStageTessControl);
+ assert(m_shaderStage == ShaderStage::TessControl);
- const auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl)->inOutUsage.tcs;
+ const auto &inOutUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl)->inOutUsage.tcs;
const auto &calcFactor = inOutUsage.calcFactor;
auto outPatchStart = calcFactor.offChip.outPatchStart;
@@ -4602,9 +4605,9 @@ Value *PatchInOutImportExport::calcLdsOffsetForTcsOutput(Type *outputTy, unsigne
// @param builder : The IR builder to create and insert IR instruction
Value *PatchInOutImportExport::calcLdsOffsetForTesInput(Type *inputTy, unsigned location, Value *locOffset,
Value *compIdx, Value *vertexIdx, BuilderBase &builder) {
- assert(m_shaderStage == ShaderStageTessEval);
+ assert(m_shaderStage == ShaderStage::TessEval);
- const auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl)->inOutUsage.tcs.calcFactor;
+ const auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl)->inOutUsage.tcs.calcFactor;
auto outPatchStart = calcFactor.offChip.outPatchStart;
auto patchConstStart = calcFactor.offChip.patchConstStart;
@@ -4682,8 +4685,8 @@ unsigned PatchInOutImportExport::calcPatchCountPerThreadGroup(unsigned inVertexC
// to be 64 in order to keep all threads in the same wave. In the future, we could consider to get rid of this
// restriction by providing the capability of querying thread ID in the group rather than in wave.
unsigned rayQueryLdsStackSize = 0;
- const auto vsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageVertex);
- const auto tcsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl);
+ const auto vsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Vertex);
+ const auto tcsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl);
if (vsResUsage->useRayQueryLdsStack || tcsResUsage->useRayQueryLdsStack) {
maxThreadCountPerThreadGroup = std::min(MaxRayQueryThreadsPerGroup, maxThreadCountPerThreadGroup);
rayQueryLdsStackSize = MaxRayQueryLdsStackEntries * MaxRayQueryThreadsPerGroup;
@@ -4706,7 +4709,7 @@ unsigned PatchInOutImportExport::calcPatchCountPerThreadGroup(unsigned inVertexC
// count actual HS patches.
assert(m_gfxIp.major >= 11);
const unsigned maxNumHsWaves =
- Gfx9::MaxHsThreadsPerSubgroup / m_pipelineState->getMergedShaderWaveSize(ShaderStageTessControl);
+ Gfx9::MaxHsThreadsPerSubgroup / m_pipelineState->getMergedShaderWaveSize(ShaderStage::TessControl);
ldsSizePerThreadGroup -= 1 + maxNumHsWaves * 2;
}
ldsSizePerThreadGroup -= rayQueryLdsStackSize; // Exclude LDS space used as ray query stack
@@ -4762,9 +4765,9 @@ void PatchInOutImportExport::addExportInstForGenericOutput(Value *output, unsign
Instruction *insertPos) {
// Check if the shader stage is valid to use "exp" instruction to export output
const auto nextStage = m_pipelineState->getNextShaderStage(m_shaderStage);
- const bool useExpInst = ((m_shaderStage == ShaderStageVertex || m_shaderStage == ShaderStageTessEval ||
- m_shaderStage == ShaderStageCopyShader) &&
- (nextStage == ShaderStageInvalid || nextStage == ShaderStageFragment));
+ const bool useExpInst = ((m_shaderStage == ShaderStage::Vertex || m_shaderStage == ShaderStage::TessEval ||
+ m_shaderStage == ShaderStage::CopyShader) &&
+ (nextStage == ShaderStage::Invalid || nextStage == ShaderStage::Fragment));
assert(useExpInst);
(void(useExpInst)); // unused
@@ -4933,9 +4936,9 @@ void PatchInOutImportExport::addExportInstForBuiltInOutput(Value *output, unsign
// @param centerIj : Center I/J provided by hardware natively
// @param builder : The IR builder to create and insert IR instruction
Value *PatchInOutImportExport::adjustCentroidIj(Value *centroidIj, Value *centerIj, BuilderBase &builder) {
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageFragment)->entryArgIdxs.fs;
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Fragment)->entryArgIdxs.fs;
auto primMask = getFunctionArgument(m_entryPoint, entryArgIdxs.primMask);
- auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageFragment)->builtInUsage.fs;
+ auto &builtInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Fragment)->builtInUsage.fs;
Value *ij = nullptr;
if (builtInUsage.centroid && builtInUsage.center) {
@@ -4974,8 +4977,8 @@ SwizzleWorkgroupLayout PatchInOutImportExport::calculateWorkgroupLayout() {
auto &mode = m_pipelineState->getShaderModes()->getComputeShaderMode();
SwizzleWorkgroupLayout resultLayout = {WorkgroupLayout::Unknown, WorkgroupLayout::Unknown};
- if (m_shaderStage == ShaderStageCompute) {
- auto &resUsage = *m_pipelineState->getShaderResourceUsage(ShaderStageCompute);
+ if (m_shaderStage == ShaderStage::Compute) {
+ auto &resUsage = *m_pipelineState->getShaderResourceUsage(ShaderStage::Compute);
if (resUsage.builtInUsage.cs.foldWorkgroupXY) {
llvm_unreachable("Should never be called!");
}
@@ -5035,7 +5038,7 @@ Value *PatchInOutImportExport::reconfigWorkgroupLayout(Value *localInvocationId,
Value *newLocalInvocationId = PoisonValue::get(localInvocationId->getType());
unsigned bitsX = 0;
unsigned bitsY = 0;
- auto &resUsage = *m_pipelineState->getShaderResourceUsage(ShaderStageCompute);
+ auto &resUsage = *m_pipelineState->getShaderResourceUsage(ShaderStage::Compute);
resUsage.builtInUsage.cs.foldWorkgroupXY = true;
Value *tidXY = builder.CreateExtractElement(localInvocationId, builder.getInt32(0), "tidXY");
@@ -5520,8 +5523,8 @@ Value *PatchInOutImportExport::getShadingRate(Instruction *insertPos) {
assert(m_gfxIp >= GfxIpVersion({10, 3})); // Must be GFX10.3+
- assert(m_shaderStage == ShaderStageFragment);
- auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageFragment)->entryArgIdxs.fs;
+ assert(m_shaderStage == ShaderStage::Fragment);
+ auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::Fragment)->entryArgIdxs.fs;
auto ancillary = getFunctionArgument(m_entryPoint, entryArgIdxs.ancillary);
// Y rate = Ancillary[5:4], X rate = Ancillary[3:2]
@@ -5574,10 +5577,10 @@ Value *PatchInOutImportExport::getShadingRate(Instruction *insertPos) {
// @param location : Vertex attribute location
// @param attribValues : Values of this vertex attribute to export
void PatchInOutImportExport::recordVertexAttribExport(unsigned location, ArrayRef<Value *> attribValues) {
- assert(m_shaderStage == ShaderStageVertex || m_shaderStage == ShaderStageTessEval ||
- m_shaderStage == ShaderStageCopyShader); // Valid shader stages
- assert(location <= MaxInOutLocCount); // 32 attributes at most
- assert(attribValues.size() == 4); // Must have 4 elements, corresponds to <4 x float>
+ assert(m_shaderStage == ShaderStage::Vertex || m_shaderStage == ShaderStage::TessEval ||
+ m_shaderStage == ShaderStage::CopyShader); // Valid shader stages
+ assert(location <= MaxInOutLocCount); // 32 attributes at most
+ assert(attribValues.size() == 4); // Must have 4 elements, corresponds to <4 x float>
auto poison = PoisonValue::get(Type::getFloatTy(*m_context));
@@ -5613,8 +5616,8 @@ void PatchInOutImportExport::recordVertexAttribExport(unsigned location, ArrayRe
//
// @param insertPos : Where to insert instructions.
void PatchInOutImportExport::exportVertexAttribs(Instruction *insertPos) {
- assert(m_shaderStage == ShaderStageVertex || m_shaderStage == ShaderStageTessEval ||
- m_shaderStage == ShaderStageCopyShader); // Valid shader stages
+ assert(m_shaderStage == ShaderStage::Vertex || m_shaderStage == ShaderStage::TessEval ||
+ m_shaderStage == ShaderStage::CopyShader); // Valid shader stages
if (m_attribExports.empty()) {
assert(m_pipelineState->getShaderResourceUsage(m_shaderStage)->inOutUsage.expCount == 0);
return;
diff --git a/lgc/patch/PatchInitializeWorkgroupMemory.cpp b/lgc/patch/PatchInitializeWorkgroupMemory.cpp
index 5730f0cd31..ae044528bf 100644
--- a/lgc/patch/PatchInitializeWorkgroupMemory.cpp
+++ b/lgc/patch/PatchInitializeWorkgroupMemory.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -75,7 +75,7 @@ bool PatchInitializeWorkgroupMemory::runImpl(Module &module, PipelineShadersResu
m_pipelineState = pipelineState;
// This pass works on compute shader.
- if (!m_pipelineState->hasShaderStage(ShaderStageCompute))
+ if (!m_pipelineState->hasShaderStage(ShaderStage::Compute))
return false;
SmallVector<GlobalVariable *> workgroupGlobals;
@@ -91,8 +91,8 @@ bool PatchInitializeWorkgroupMemory::runImpl(Module &module, PipelineShadersResu
return false;
Patch::init(&module);
- m_shaderStage = ShaderStageCompute;
- m_entryPoint = pipelineShaders.getEntryPoint(static_cast<ShaderStage>(m_shaderStage));
+ m_shaderStage = ShaderStage::Compute;
+ m_entryPoint = pipelineShaders.getEntryPoint(static_cast<ShaderStageEnum>(m_shaderStage));
BuilderBase builder(*m_context);
builder.SetInsertPointPastAllocas(m_entryPoint);
diff --git a/lgc/patch/PatchInvariantLoads.cpp b/lgc/patch/PatchInvariantLoads.cpp
index 950f9b26a1..a29af844ef 100644
--- a/lgc/patch/PatchInvariantLoads.cpp
+++ b/lgc/patch/PatchInvariantLoads.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -83,8 +83,8 @@ static unsigned findAddressSpaceAccess(const Instruction *inst) {
auto func = ci->getCalledFunction();
if (func) {
// Treat these as buffer address space as they do not overlap with private.
- if (func->getName().startswith("llvm.amdgcn.image") || func->getName().startswith("llvm.amdgcn.raw") ||
- func->getName().startswith("llvm.amdgcn.struct"))
+ if (func->getName().starts_with("llvm.amdgcn.image") || func->getName().starts_with("llvm.amdgcn.raw") ||
+ func->getName().starts_with("llvm.amdgcn.struct"))
return ADDR_SPACE_BUFFER_FAT_POINTER;
}
}
@@ -102,10 +102,10 @@ bool PatchInvariantLoads::runImpl(Function &function, PipelineState *pipelineSta
LLVM_DEBUG(dbgs() << "Run the pass Patch-Invariant-Loads\n");
auto shaderStage = lgc::getShaderStage(&function);
- if (shaderStage == ShaderStageInvalid)
+ if (!shaderStage)
return false;
- auto &options = pipelineState->getShaderOptions(shaderStage);
+ auto &options = pipelineState->getShaderOptions(shaderStage.value());
bool clearInvariants = options.aggressiveInvariantLoads == ClearInvariants;
bool aggressiveInvariants = options.aggressiveInvariantLoads == EnableOptimization;
@@ -179,7 +179,7 @@ bool PatchInvariantLoads::runImpl(Function &function, PipelineState *pipelineSta
}
} else if (CallInst *ci = dyn_cast<CallInst>(&inst)) {
auto func = ci->getCalledFunction();
- if (func && func->getName().startswith("lgc.ngg."))
+ if (func && func->getName().starts_with("lgc.ngg."))
continue;
}
unsigned addrSpace = findAddressSpaceAccess(&inst);
diff --git a/lgc/patch/PatchLlvmIrInclusion.cpp b/lgc/patch/PatchLlvmIrInclusion.cpp
index c50709b85f..07a98ed3e6 100644
--- a/lgc/patch/PatchLlvmIrInclusion.cpp
+++ b/lgc/patch/PatchLlvmIrInclusion.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/patch/PatchLoadScalarizer.cpp b/lgc/patch/PatchLoadScalarizer.cpp
index af836bb657..90eb5afea2 100644
--- a/lgc/patch/PatchLoadScalarizer.cpp
+++ b/lgc/patch/PatchLoadScalarizer.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -76,8 +76,8 @@ bool PatchLoadScalarizer::runImpl(Function &function, PipelineState *pipelineSta
// If the function is not a valid shader stage, or the optimization is disabled, bail.
m_scalarThreshold = 0;
- if (shaderStage != ShaderStageInvalid)
- m_scalarThreshold = pipelineState->getShaderOptions(shaderStage).loadScalarizerThreshold;
+ if (shaderStage)
+ m_scalarThreshold = pipelineState->getShaderOptions(shaderStage.value()).loadScalarizerThreshold;
if (m_scalarThreshold == 0)
return false;
diff --git a/lgc/patch/PatchLoopMetadata.cpp b/lgc/patch/PatchLoopMetadata.cpp
index ca4eda2669..d1ce7c9eda 100644
--- a/lgc/patch/PatchLoopMetadata.cpp
+++ b/lgc/patch/PatchLoopMetadata.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -66,7 +66,7 @@ MDNode *PatchLoopMetadata::updateMetadata(MDNode *loopId, ArrayRef<StringRef> pr
if (MDNode *mdNode = dyn_cast<MDNode>(op)) {
if (const MDString *mdString = dyn_cast<MDString>(mdNode->getOperand(0))) {
if (any_of(prefixesToRemove,
- [mdString](StringRef prefix) -> bool { return mdString->getString().startswith(prefix); }))
+ [mdString](StringRef prefix) -> bool { return mdString->getString().starts_with(prefix); }))
found = true;
else
mds.push_back(op);
@@ -122,10 +122,10 @@ bool PatchLoopMetadata::runImpl(Loop &loop, PipelineState *pipelineState) {
m_gfxIp = mPipelineState->getTargetInfo().getGfxIpVersion();
bool changed = false;
- ShaderStage stage = getShaderStage(func);
- if (stage == ShaderStageInvalid)
+ auto stage = getShaderStage(func);
+ if (!stage)
return false;
- if (auto shaderOptions = &mPipelineState->getShaderOptions(stage)) {
+ if (auto shaderOptions = &mPipelineState->getShaderOptions(stage.value())) {
m_disableLoopUnroll = shaderOptions->disableLoopUnroll;
m_forceLoopUnrollCount = shaderOptions->forceLoopUnrollCount;
m_disableLicmThreshold = shaderOptions->disableLicmThreshold;
@@ -169,7 +169,7 @@ bool PatchLoopMetadata::runImpl(Loop &loop, PipelineState *pipelineState) {
Metadata *op = loopMetaNode->getOperand(i);
if (MDNode *mdNode = dyn_cast<MDNode>(op)) {
if (const MDString *mdString = dyn_cast<MDString>(mdNode->getOperand(0))) {
- if (m_dontUnrollHintThreshold > 0 && mdString->getString().startswith("llvm.loop.unroll.disable")) {
+ if (m_dontUnrollHintThreshold > 0 && mdString->getString().starts_with("llvm.loop.unroll.disable")) {
LLVM_DEBUG(dbgs() << " relaxing llvm.loop.unroll.disable to amdgpu.loop.unroll.threshold "
<< m_dontUnrollHintThreshold << "\n");
Metadata *thresholdMeta[] = {
@@ -181,7 +181,7 @@ bool PatchLoopMetadata::runImpl(Loop &loop, PipelineState *pipelineState) {
changed = true;
break;
}
- if (m_unrollHintThreshold > 0 && mdString->getString().startswith("llvm.loop.unroll.full")) {
+ if (m_unrollHintThreshold > 0 && mdString->getString().starts_with("llvm.loop.unroll.full")) {
LLVM_DEBUG(dbgs() << " relaxing llvm.loop.unroll.full to amdgpu.loop.unroll.threshold "
<< m_unrollHintThreshold << "\n");
Metadata *thresholdMeta[] = {
diff --git a/lgc/patch/PatchNullFragShader.cpp b/lgc/patch/PatchNullFragShader.cpp
index b66ef50050..b58c7b299d 100644
--- a/lgc/patch/PatchNullFragShader.cpp
+++ b/lgc/patch/PatchNullFragShader.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -74,7 +74,7 @@ bool PatchNullFragShader::runImpl(Module &module, PipelineState *pipelineState)
return false;
// If a fragment shader is not needed, then do not generate one.
- const bool hasFs = pipelineState->hasShaderStage(ShaderStageFragment);
+ const bool hasFs = pipelineState->hasShaderStage(ShaderStage::Fragment);
if (hasFs || !pipelineState->isGraphics())
return false;
@@ -88,8 +88,8 @@ bool PatchNullFragShader::runImpl(Module &module, PipelineState *pipelineState)
//
// @param [in/out] module : The LLVM module in which to add the shader.
void PatchNullFragShader::updatePipelineState(PipelineState *pipelineState) const {
- auto resUsage = pipelineState->getShaderResourceUsage(ShaderStageFragment);
- pipelineState->setShaderStageMask(pipelineState->getShaderStageMask() | shaderStageToMask(ShaderStageFragment));
+ auto resUsage = pipelineState->getShaderResourceUsage(ShaderStage::Fragment);
+ pipelineState->setShaderStageMask(pipelineState->getShaderStageMask() | ShaderStageMask(ShaderStage::Fragment));
// Add usage info for dummy output
resUsage->inOutUsage.fs.isNullFs = true;
diff --git a/lgc/patch/PatchNullFragShader.h b/lgc/patch/PatchNullFragShader.h
index b681e60223..4ce77e77c2 100644
--- a/lgc/patch/PatchNullFragShader.h
+++ b/lgc/patch/PatchNullFragShader.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/patch/PatchPeepholeOpt.cpp b/lgc/patch/PatchPeepholeOpt.cpp
index b804ca3331..4627de134f 100644
--- a/lgc/patch/PatchPeepholeOpt.cpp
+++ b/lgc/patch/PatchPeepholeOpt.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/patch/PatchPreparePipelineAbi.cpp b/lgc/patch/PatchPreparePipelineAbi.cpp
index 8c6d55e25c..fc6bd580a5 100644
--- a/lgc/patch/PatchPreparePipelineAbi.cpp
+++ b/lgc/patch/PatchPreparePipelineAbi.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -93,16 +93,16 @@ bool PatchPreparePipelineAbi::runImpl(Module &module, PipelineShadersResult &pip
m_pipelineShaders = &pipelineShaders;
m_analysisHandlers = &analysisHandlers;
- m_hasVs = m_pipelineState->hasShaderStage(ShaderStageVertex);
- m_hasTcs = m_pipelineState->hasShaderStage(ShaderStageTessControl);
- m_hasTes = m_pipelineState->hasShaderStage(ShaderStageTessEval);
- m_hasGs = m_pipelineState->hasShaderStage(ShaderStageGeometry);
- m_hasTask = m_pipelineState->hasShaderStage(ShaderStageTask);
- m_hasMesh = m_pipelineState->hasShaderStage(ShaderStageMesh);
+ m_hasVs = m_pipelineState->hasShaderStage(ShaderStage::Vertex);
+ m_hasTcs = m_pipelineState->hasShaderStage(ShaderStage::TessControl);
+ m_hasTes = m_pipelineState->hasShaderStage(ShaderStage::TessEval);
+ m_hasGs = m_pipelineState->hasShaderStage(ShaderStage::Geometry);
+ m_hasTask = m_pipelineState->hasShaderStage(ShaderStage::Task);
+ m_hasMesh = m_pipelineState->hasShaderStage(ShaderStage::Mesh);
m_gfxIp = m_pipelineState->getTargetInfo().getGfxIpVersion();
- if (auto hsEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStageTessControl))
+ if (auto hsEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStage::TessControl))
storeTessFactors(hsEntryPoint);
if (m_gfxIp.major >= 9)
@@ -160,7 +160,7 @@ std::pair<Value *, Value *> PatchPreparePipelineAbi::readTessFactors(PipelineSta
}
const auto tessFactorStart =
- pipelineState->getShaderResourceUsage(ShaderStageTessControl)->inOutUsage.tcs.calcFactor.onChip.tessFactorStart;
+ pipelineState->getShaderResourceUsage(ShaderStage::TessControl)->inOutUsage.tcs.calcFactor.onChip.tessFactorStart;
assert(numOuterTfs >= 2 && numOuterTfs <= 4);
// ldsOffset = tessFactorStart + relativeId * MaxTessFactorsPerPatch
@@ -215,7 +215,7 @@ void PatchPreparePipelineAbi::writeTessFactors(PipelineState *pipelineState, Val
// TF[3] = outerTF[3]
// TF[4] = innerTF[0]
// TF[5] = innerTF[1]
- const auto &calcFactor = pipelineState->getShaderResourceUsage(ShaderStageTessControl)->inOutUsage.tcs.calcFactor;
+ const auto &calcFactor = pipelineState->getShaderResourceUsage(ShaderStage::TessControl)->inOutUsage.tcs.calcFactor;
Value *tfBufferOffset = builder.CreateMul(relPatchId, builder.getInt32(calcFactor.tessFactorStride * sizeof(float)));
CoherentFlag coherent = {};
@@ -301,8 +301,8 @@ void PatchPreparePipelineAbi::mergeShader(Module &module) {
if (m_pipelineState->isGraphics()) {
if (m_hasTask || m_hasMesh) {
- auto taskEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStageTask);
- auto meshEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStageMesh);
+ auto taskEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStage::Task);
+ auto meshEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStage::Mesh);
MeshTaskShader meshTaskShader(m_pipelineState, m_analysisHandlers);
meshTaskShader.process(taskEntryPoint, meshEntryPoint);
return;
@@ -313,104 +313,104 @@ void PatchPreparePipelineAbi::mergeShader(Module &module) {
if (hasTs && m_hasGs) {
// TS-GS pipeline
- auto esEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStageTessEval);
- auto gsEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStageGeometry);
+ auto esEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStage::TessEval);
+ auto gsEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStage::Geometry);
if (enableNgg) {
if (gsEntryPoint) {
if (esEntryPoint)
- lgc::setShaderStage(esEntryPoint, ShaderStageGeometry);
- auto copyShaderEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStageCopyShader);
+ lgc::setShaderStage(esEntryPoint, ShaderStage::Geometry);
+ auto copyShaderEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStage::CopyShader);
if (copyShaderEntryPoint)
- lgc::setShaderStage(copyShaderEntryPoint, ShaderStageGeometry);
+ lgc::setShaderStage(copyShaderEntryPoint, ShaderStage::Geometry);
auto primShaderEntryPoint = shaderMerger.buildPrimShader(esEntryPoint, gsEntryPoint, copyShaderEntryPoint);
primShaderEntryPoint->setCallingConv(CallingConv::AMDGPU_GS);
- lgc::setShaderStage(primShaderEntryPoint, ShaderStageGeometry);
+ lgc::setShaderStage(primShaderEntryPoint, ShaderStage::Geometry);
}
} else {
if (gsEntryPoint) {
if (esEntryPoint)
- lgc::setShaderStage(esEntryPoint, ShaderStageGeometry);
+ lgc::setShaderStage(esEntryPoint, ShaderStage::Geometry);
auto esGsEntryPoint = shaderMerger.generateEsGsEntryPoint(esEntryPoint, gsEntryPoint);
esGsEntryPoint->setCallingConv(CallingConv::AMDGPU_GS);
- lgc::setShaderStage(esGsEntryPoint, ShaderStageGeometry);
+ lgc::setShaderStage(esGsEntryPoint, ShaderStage::Geometry);
}
}
// This must be done after generating the EsGs entry point because it must appear first in the module.
if (m_hasTcs) {
- auto lsEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStageVertex);
- auto hsEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStageTessControl);
+ auto lsEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStage::Vertex);
+ auto hsEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStage::TessControl);
if (hsEntryPoint) {
if (lsEntryPoint)
- lgc::setShaderStage(lsEntryPoint, ShaderStageTessControl);
+ lgc::setShaderStage(lsEntryPoint, ShaderStage::TessControl);
auto lsHsEntryPoint = shaderMerger.generateLsHsEntryPoint(lsEntryPoint, hsEntryPoint);
lsHsEntryPoint->setCallingConv(CallingConv::AMDGPU_HS);
- lgc::setShaderStage(lsHsEntryPoint, ShaderStageTessControl);
+ lgc::setShaderStage(lsHsEntryPoint, ShaderStage::TessControl);
}
}
} else if (hasTs) {
// TS-only pipeline
if (m_hasTcs) {
- auto lsEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStageVertex);
- auto hsEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStageTessControl);
+ auto lsEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStage::Vertex);
+ auto hsEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStage::TessControl);
if (hsEntryPoint) {
if (lsEntryPoint)
- lgc::setShaderStage(lsEntryPoint, ShaderStageTessControl);
+ lgc::setShaderStage(lsEntryPoint, ShaderStage::TessControl);
auto lsHsEntryPoint = shaderMerger.generateLsHsEntryPoint(lsEntryPoint, hsEntryPoint);
lsHsEntryPoint->setCallingConv(CallingConv::AMDGPU_HS);
- lgc::setShaderStage(lsHsEntryPoint, ShaderStageTessControl);
+ lgc::setShaderStage(lsHsEntryPoint, ShaderStage::TessControl);
}
}
if (enableNgg) {
// If NGG is enabled, ES-GS merged shader should be present even if GS is absent
- auto esEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStageTessEval);
+ auto esEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStage::TessEval);
if (esEntryPoint) {
- lgc::setShaderStage(esEntryPoint, ShaderStageTessEval);
+ lgc::setShaderStage(esEntryPoint, ShaderStage::TessEval);
auto primShaderEntryPoint = shaderMerger.buildPrimShader(esEntryPoint, nullptr, nullptr);
primShaderEntryPoint->setCallingConv(CallingConv::AMDGPU_GS);
- lgc::setShaderStage(primShaderEntryPoint, ShaderStageTessEval);
+ lgc::setShaderStage(primShaderEntryPoint, ShaderStage::TessEval);
}
}
} else if (m_hasGs) {
// GS-only pipeline
- auto esEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStageVertex);
- auto gsEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStageGeometry);
+ auto esEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStage::Vertex);
+ auto gsEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStage::Geometry);
if (enableNgg) {
if (gsEntryPoint) {
if (esEntryPoint)
- lgc::setShaderStage(esEntryPoint, ShaderStageGeometry);
- auto copyShaderEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStageCopyShader);
+ lgc::setShaderStage(esEntryPoint, ShaderStage::Geometry);
+ auto copyShaderEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStage::CopyShader);
if (copyShaderEntryPoint)
- lgc::setShaderStage(copyShaderEntryPoint, ShaderStageGeometry);
+ lgc::setShaderStage(copyShaderEntryPoint, ShaderStage::Geometry);
auto primShaderEntryPoint = shaderMerger.buildPrimShader(esEntryPoint, gsEntryPoint, copyShaderEntryPoint);
primShaderEntryPoint->setCallingConv(CallingConv::AMDGPU_GS);
- lgc::setShaderStage(primShaderEntryPoint, ShaderStageGeometry);
+ lgc::setShaderStage(primShaderEntryPoint, ShaderStage::Geometry);
}
} else {
if (gsEntryPoint) {
if (esEntryPoint)
- lgc::setShaderStage(esEntryPoint, ShaderStageGeometry);
+ lgc::setShaderStage(esEntryPoint, ShaderStage::Geometry);
auto esGsEntryPoint = shaderMerger.generateEsGsEntryPoint(esEntryPoint, gsEntryPoint);
esGsEntryPoint->setCallingConv(CallingConv::AMDGPU_GS);
- lgc::setShaderStage(esGsEntryPoint, ShaderStageGeometry);
+ lgc::setShaderStage(esGsEntryPoint, ShaderStage::Geometry);
}
}
} else if (m_hasVs) {
// VS_FS pipeline
if (enableNgg) {
// If NGG is enabled, ES-GS merged shader should be present even if GS is absent
- auto esEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStageVertex);
+ auto esEntryPoint = m_pipelineShaders->getEntryPoint(ShaderStage::Vertex);
if (esEntryPoint) {
- lgc::setShaderStage(esEntryPoint, ShaderStageVertex);
+ lgc::setShaderStage(esEntryPoint, ShaderStage::Vertex);
auto primShaderEntryPoint = shaderMerger.buildPrimShader(esEntryPoint, nullptr, nullptr);
primShaderEntryPoint->setCallingConv(CallingConv::AMDGPU_GS);
- lgc::setShaderStage(primShaderEntryPoint, ShaderStageVertex);
+ lgc::setShaderStage(primShaderEntryPoint, ShaderStage::Vertex);
}
}
}
@@ -476,7 +476,7 @@ void PatchPreparePipelineAbi::addAbiMetadata(Module &module) {
//
// @param entryPoint : Entry-point of tessellation control shader
void PatchPreparePipelineAbi::storeTessFactors(Function *entryPoint) {
- assert(getShaderStage(entryPoint) == ShaderStageTessControl); // Must be tessellation control shader
+ assert(getShaderStage(entryPoint) == ShaderStage::TessControl); // Must be tessellation control shader
if (m_pipelineState->canOptimizeTessFactor())
return; // If TF store is to be optimized, skip further processing
@@ -499,7 +499,7 @@ void PatchPreparePipelineAbi::storeTessFactors(Function *entryPoint) {
pipelineSysValues.initialize(m_pipelineState);
const auto tfBufferDesc = pipelineSysValues.get(entryPoint)->getTessFactorBufDesc();
- const auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStageTessControl)->entryArgIdxs.tcs;
+ const auto &entryArgIdxs = m_pipelineState->getShaderInterfaceData(ShaderStage::TessControl)->entryArgIdxs.tcs;
const auto tfBufferBase = getFunctionArgument(entryPoint, entryArgIdxs.tfBufferBase);
const auto relPatchId = pipelineSysValues.get(entryPoint)->getRelativeId();
diff --git a/lgc/patch/PatchReadFirstLane.cpp b/lgc/patch/PatchReadFirstLane.cpp
index 1a5e2e0454..ee9c388585 100644
--- a/lgc/patch/PatchReadFirstLane.cpp
+++ b/lgc/patch/PatchReadFirstLane.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/patch/PatchResourceCollect.cpp b/lgc/patch/PatchResourceCollect.cpp
index fba5c03eb8..6880cf1b5b 100644
--- a/lgc/patch/PatchResourceCollect.cpp
+++ b/lgc/patch/PatchResourceCollect.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -98,8 +98,8 @@ bool PatchResourceCollect::runImpl(Module &module, PipelineShadersResult &pipeli
m_tcsInputHasDynamicIndexing = false;
bool needPack = false;
- for (int shaderStage = 0; shaderStage < ShaderStageGfxCount; ++shaderStage) {
- ShaderStage stage = static_cast<ShaderStage>(shaderStage);
+ for (int shaderStage = 0; shaderStage < ShaderStage::GfxCount; ++shaderStage) {
+ ShaderStageEnum stage = static_cast<ShaderStageEnum>(shaderStage);
if (pipelineState->hasShaderStage(stage) &&
(pipelineState->canPackInput(stage) || pipelineState->canPackOutput(stage))) {
needPack = true;
@@ -113,12 +113,12 @@ bool PatchResourceCollect::runImpl(Module &module, PipelineShadersResult &pipeli
}
// Process each shader stage, in reverse order. We process FS even if it does not exist (part-pipeline compile).
- for (int shaderStage = ShaderStageCountInternal - 1; shaderStage >= 0; --shaderStage) {
- m_entryPoint = pipelineShaders.getEntryPoint(static_cast<ShaderStage>(shaderStage));
- m_shaderStage = static_cast<ShaderStage>(shaderStage);
+ for (int shaderStage = ShaderStage::CountInternal - 1; shaderStage >= 0; --shaderStage) {
+ m_entryPoint = pipelineShaders.getEntryPoint(static_cast<ShaderStageEnum>(shaderStage));
+ m_shaderStage = static_cast<ShaderStageEnum>(shaderStage);
if (m_entryPoint)
processShader();
- else if (m_shaderStage == ShaderStageFragment)
+ else if (m_shaderStage == ShaderStage::Fragment)
processMissingFs();
}
@@ -126,9 +126,10 @@ bool PatchResourceCollect::runImpl(Module &module, PipelineShadersResult &pipeli
for (Function &func : module) {
if (func.isDeclaration())
continue;
- m_shaderStage = getShaderStage(&func);
- if (m_shaderStage == ShaderStage::ShaderStageInvalid || &func == pipelineShaders.getEntryPoint(m_shaderStage))
+ auto stage = getShaderStage(&func);
+ if (!m_shaderStage || &func == pipelineShaders.getEntryPoint(m_shaderStage))
continue;
+ m_shaderStage = stage.value();
m_entryPoint = &func;
processShader();
}
@@ -141,9 +142,9 @@ bool PatchResourceCollect::runImpl(Module &module, PipelineShadersResult &pipeli
setNggControl(&module);
// Determine whether or not GS on-chip mode is valid for this pipeline
- bool hasGs = pipelineState->hasShaderStage(ShaderStageGeometry);
+ bool hasGs = pipelineState->hasShaderStage(ShaderStage::Geometry);
const bool meshPipeline =
- m_pipelineState->hasShaderStage(ShaderStageTask) || m_pipelineState->hasShaderStage(ShaderStageMesh);
+ m_pipelineState->hasShaderStage(ShaderStage::Task) || m_pipelineState->hasShaderStage(ShaderStage::Mesh);
bool checkGsOnChip = hasGs || meshPipeline || pipelineState->getNggControl()->enableNgg;
if (checkGsOnChip) {
@@ -168,24 +169,24 @@ void PatchResourceCollect::setNggControl(Module *module) {
// If mesh pipeline, skip NGG control settings
const bool meshPipeline =
- m_pipelineState->hasShaderStage(ShaderStageTask) || m_pipelineState->hasShaderStage(ShaderStageMesh);
+ m_pipelineState->hasShaderStage(ShaderStage::Task) || m_pipelineState->hasShaderStage(ShaderStage::Mesh);
if (meshPipeline)
return;
- const bool hasTs =
- m_pipelineState->hasShaderStage(ShaderStageTessControl) || m_pipelineState->hasShaderStage(ShaderStageTessEval);
- const bool hasGs = m_pipelineState->hasShaderStage(ShaderStageGeometry);
+ const bool hasTs = m_pipelineState->hasShaderStage(ShaderStage::TessControl) ||
+ m_pipelineState->hasShaderStage(ShaderStage::TessEval);
+ const bool hasGs = m_pipelineState->hasShaderStage(ShaderStage::Geometry);
// Check the use of cull distance for NGG primitive shader
bool useCullDistance = false;
if (hasGs) {
- const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry);
useCullDistance = resUsage->builtInUsage.gs.cullDistance > 0;
} else if (hasTs) {
- const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessEval);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessEval);
useCullDistance = resUsage->builtInUsage.tes.cullDistance > 0;
} else {
- const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageVertex);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Vertex);
useCullDistance = resUsage->builtInUsage.vs.cullDistance > 0;
}
@@ -280,9 +281,9 @@ bool PatchResourceCollect::canUseNgg(Module *module) {
if (m_pipelineState->getTargetInfo().getGfxIpVersion().major >= 11)
return true;
- const bool hasTs =
- m_pipelineState->hasShaderStage(ShaderStageTessControl) || m_pipelineState->hasShaderStage(ShaderStageTessEval);
- const bool hasGs = m_pipelineState->hasShaderStage(ShaderStageGeometry);
+ const bool hasTs = m_pipelineState->hasShaderStage(ShaderStage::TessControl) ||
+ m_pipelineState->hasShaderStage(ShaderStage::TessEval);
+ const bool hasGs = m_pipelineState->hasShaderStage(ShaderStage::Geometry);
// If the workaround flag requests us to disable NGG, respect it. Hardware must have some limitations.
if (m_pipelineState->getTargetInfo().getGpuWorkarounds().gfx10.waNggDisabled)
@@ -329,9 +330,9 @@ bool PatchResourceCollect::canUseNggCulling(Module *module) {
assert(m_pipelineState->isGraphics());
assert(m_pipelineState->getTargetInfo().getGfxIpVersion().major >= 10);
- const bool hasTs =
- m_pipelineState->hasShaderStage(ShaderStageTessControl) || m_pipelineState->hasShaderStage(ShaderStageTessEval);
- const bool hasGs = m_pipelineState->hasShaderStage(ShaderStageGeometry);
+ const bool hasTs = m_pipelineState->hasShaderStage(ShaderStage::TessControl) ||
+ m_pipelineState->hasShaderStage(ShaderStage::TessEval);
+ const bool hasGs = m_pipelineState->hasShaderStage(ShaderStage::Geometry);
// Check topology, disable NGG culling if primitive is not triangle-based
if (hasGs) {
@@ -359,7 +360,7 @@ bool PatchResourceCollect::canUseNggCulling(Module *module) {
// NGG cases when API GS is not present. This is because such write operations have side effect in execution
// sequences. But when GS is present, we can still enable culling. Culling is performed after GS execution.
if (!hasGs) {
- const auto resUsage = m_pipelineState->getShaderResourceUsage(hasTs ? ShaderStageTessEval : ShaderStageVertex);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(hasTs ? ShaderStage::TessEval : ShaderStage::Vertex);
if (resUsage->resourceWrite)
return false;
}
@@ -367,11 +368,11 @@ bool PatchResourceCollect::canUseNggCulling(Module *module) {
// Check the presence of position export, disable NGG culling if position export is absent
bool usePosition = false;
if (hasGs)
- usePosition = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->builtInUsage.gs.position;
+ usePosition = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->builtInUsage.gs.position;
else if (hasTs)
- usePosition = m_pipelineState->getShaderResourceUsage(ShaderStageTessEval)->builtInUsage.tes.position;
+ usePosition = m_pipelineState->getShaderResourceUsage(ShaderStage::TessEval)->builtInUsage.tes.position;
else
- usePosition = m_pipelineState->getShaderResourceUsage(ShaderStageVertex)->builtInUsage.vs.position;
+ usePosition = m_pipelineState->getShaderResourceUsage(ShaderStage::Vertex)->builtInUsage.vs.position;
if (!usePosition)
return false; // No position export
@@ -379,11 +380,11 @@ bool PatchResourceCollect::canUseNggCulling(Module *module) {
// Find position export call
std::string posCallName = lgcName::OutputExportBuiltIn;
posCallName += PipelineState::getBuiltInName(BuiltInPosition);
- auto callStage = hasGs ? ShaderStageGeometry : (hasTs ? ShaderStageTessEval : ShaderStageVertex);
+ auto callStage = hasGs ? ShaderStage::Geometry : (hasTs ? ShaderStage::TessEval : ShaderStage::Vertex);
CallInst *posCall = nullptr;
for (Function &func : *module) {
- if (func.getName().startswith(posCallName)) {
+ if (func.getName().starts_with(posCallName)) {
for (User *user : func.users()) {
auto call = cast<CallInst>(user);
if (m_pipelineShaders->getShaderStage(call->getFunction()) == callStage) {
@@ -437,14 +438,14 @@ bool PatchResourceCollect::canUseNggCulling(Module *module) {
bool PatchResourceCollect::checkGsOnChipValidity() {
bool gsOnChip = true;
- const bool hasTs =
- m_pipelineState->hasShaderStage(ShaderStageTessControl) || m_pipelineState->hasShaderStage(ShaderStageTessEval);
- const bool hasGs = m_pipelineState->hasShaderStage(ShaderStageGeometry);
+ const bool hasTs = m_pipelineState->hasShaderStage(ShaderStage::TessControl) ||
+ m_pipelineState->hasShaderStage(ShaderStage::TessEval);
+ const bool hasGs = m_pipelineState->hasShaderStage(ShaderStage::Geometry);
const bool meshPipeline =
- m_pipelineState->hasShaderStage(ShaderStageTask) || m_pipelineState->hasShaderStage(ShaderStageMesh);
+ m_pipelineState->hasShaderStage(ShaderStage::Task) || m_pipelineState->hasShaderStage(ShaderStage::Mesh);
const auto &geometryMode = m_pipelineState->getShaderModes()->getGeometryShaderMode();
- auto gsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry);
+ auto gsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry);
const GfxIpVersion gfxIp = m_pipelineState->getTargetInfo().getGfxIpVersion();
@@ -514,7 +515,7 @@ bool PatchResourceCollect::checkGsOnChipValidity() {
const unsigned ldsSizeDwordGranularity =
1u << m_pipelineState->getTargetInfo().getGpuProperty().ldsSizeDwordGranularityShift;
auto ldsSizeDwords =
- MeshTaskShader::layoutMeshShaderLds(m_pipelineState, m_pipelineShaders->getEntryPoint(ShaderStageMesh));
+ MeshTaskShader::layoutMeshShaderLds(m_pipelineState, m_pipelineShaders->getEntryPoint(ShaderStage::Mesh));
ldsSizeDwords = alignTo(ldsSizeDwords, ldsSizeDwordGranularity);
// Make sure we don't allocate more than what can legally be allocated by a single subgroup on the hardware.
@@ -636,7 +637,7 @@ bool PatchResourceCollect::checkGsOnChipValidity() {
rayQueryLdsStackSize = MaxRayQueryLdsStackEntries * MaxRayQueryThreadsPerGroup;
}
- auto esResUsage = m_pipelineState->getShaderResourceUsage(hasTs ? ShaderStageTessEval : ShaderStageVertex);
+ auto esResUsage = m_pipelineState->getShaderResourceUsage(hasTs ? ShaderStage::TessEval : ShaderStage::Vertex);
if (esResUsage->useRayQueryLdsStack) {
esVertsPerSubgroup = std::min(MaxRayQueryThreadsPerGroup, esVertsPerSubgroup);
rayQueryLdsStackSize = MaxRayQueryLdsStackEntries * MaxRayQueryThreadsPerGroup;
@@ -746,7 +747,7 @@ bool PatchResourceCollect::checkGsOnChipValidity() {
// gsPrimsPerSubgroup shouldn't be bigger than wave size.
unsigned gsPrimsPerSubgroup =
std::min(m_pipelineState->getTargetInfo().getGpuProperty().gsOnChipDefaultPrimsPerSubgroup,
- m_pipelineState->getShaderWaveSize(ShaderStageGeometry));
+ m_pipelineState->getShaderWaveSize(ShaderStage::Geometry));
// NOTE: Make esGsRingItemSize odd by "| 1", to optimize ES -> GS ring layout for LDS bank conflicts.
const unsigned esGsRingItemSize = (4 * std::max(1u, gsResUsage->inOutUsage.inputMapLocCount)) | 1;
@@ -790,7 +791,7 @@ bool PatchResourceCollect::checkGsOnChipValidity() {
// NOTE: If ray query uses LDS stack, the expected max thread count in the group is 64. And we force wave size
// to be 64 in order to keep all threads in the same wave. In the future, we could consider to get rid of this
// restriction by providing the capability of querying thread ID in the group rather than in wave.
- auto esResUsage = m_pipelineState->getShaderResourceUsage(hasTs ? ShaderStageTessEval : ShaderStageVertex);
+ auto esResUsage = m_pipelineState->getShaderResourceUsage(hasTs ? ShaderStage::TessEval : ShaderStage::Vertex);
unsigned rayQueryLdsStackSize = 0;
if (esResUsage->useRayQueryLdsStack || gsResUsage->useRayQueryLdsStack)
@@ -1021,7 +1022,7 @@ void PatchResourceCollect::processShader() {
mapBuiltInToGenericInOut();
}
- if (m_shaderStage == ShaderStageFragment) {
+ if (m_shaderStage == ShaderStage::Fragment) {
if (m_pipelineState->getRasterizerState().perSampleShading) {
if (m_resUsage->builtInUsage.fs.fragCoord || m_resUsage->builtInUsage.fs.pointCoord ||
m_resUsage->builtInUsage.fs.sampleMaskIn || m_resUsage->resourceWrite)
@@ -1030,7 +1031,7 @@ void PatchResourceCollect::processShader() {
// If we're compiling a fragment shader only, then serialize inputLocInfoMap and builtInInputLocMap
// into PAL metadata, for the other half of the pipeline to be compiled against later.
- if (m_pipelineState->getShaderStageMask() == 1U << ShaderStageFragment) {
+ if (m_pipelineState->getShaderStageMask() == ShaderStageMask(ShaderStage::Fragment)) {
FsInputMappings fsInputMappings = {};
for (const auto &it : m_resUsage->inOutUsage.inputLocInfoMap)
fsInputMappings.locationInfo.push_back({it.first.getData(), it.second.getData()});
@@ -1041,7 +1042,7 @@ void PatchResourceCollect::processShader() {
m_pipelineState->getPalMetadata()->addFragmentInputInfo(fsInputMappings);
}
- } else if (m_shaderStage == ShaderStageVertex) {
+ } else if (m_shaderStage == ShaderStage::Vertex) {
// Collect resource usages from vertex input create info
// TODO: In the future, we might check if the corresponding vertex attribute is active in vertex shader
// and set the usage based on this info.
@@ -1070,7 +1071,7 @@ void PatchResourceCollect::processShader() {
// Process missing fragment shader. This happens in a part-pipeline compile; we deserialize the FS's input mappings
// from PAL metadata that came from the separate FS compilation.
void PatchResourceCollect::processMissingFs() {
- assert(m_shaderStage == ShaderStageFragment);
+ assert(m_shaderStage == ShaderStage::Fragment);
if (!m_processMissingFs)
return;
m_resUsage = m_pipelineState->getShaderResourceUsage(m_shaderStage);
@@ -1107,20 +1108,20 @@ void PatchResourceCollect::processMissingFs() {
// =====================================================================================================================
// Check whether vertex reuse should be disabled.
bool PatchResourceCollect::isVertexReuseDisabled() {
- const bool hasGs = m_pipelineState->hasShaderStage(ShaderStageGeometry);
- const bool hasTs =
- (m_pipelineState->hasShaderStage(ShaderStageTessControl) || m_pipelineState->hasShaderStage(ShaderStageTessEval));
- const bool hasVs = m_pipelineState->hasShaderStage(ShaderStageVertex);
+ const bool hasGs = m_pipelineState->hasShaderStage(ShaderStage::Geometry);
+ const bool hasTs = (m_pipelineState->hasShaderStage(ShaderStage::TessControl) ||
+ m_pipelineState->hasShaderStage(ShaderStage::TessEval));
+ const bool hasVs = m_pipelineState->hasShaderStage(ShaderStage::Vertex);
bool disableVertexReuse = m_pipelineState->getInputAssemblyState().disableVertexReuse;
bool useViewportIndex = false;
if (hasGs)
- useViewportIndex = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->builtInUsage.gs.viewportIndex;
+ useViewportIndex = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->builtInUsage.gs.viewportIndex;
else if (hasTs) {
- useViewportIndex = m_pipelineState->getShaderResourceUsage(ShaderStageTessEval)->builtInUsage.tes.viewportIndex;
+ useViewportIndex = m_pipelineState->getShaderResourceUsage(ShaderStage::TessEval)->builtInUsage.tes.viewportIndex;
} else if (hasVs)
- useViewportIndex = m_pipelineState->getShaderResourceUsage(ShaderStageVertex)->builtInUsage.vs.viewportIndex;
+ useViewportIndex = m_pipelineState->getShaderResourceUsage(ShaderStage::Vertex)->builtInUsage.vs.viewportIndex;
if (m_pipelineState->getInputAssemblyState().multiView == MultiViewMode::PerView)
useViewportIndex = true;
@@ -1145,8 +1146,8 @@ void PatchResourceCollect::checkRayQueryLdsStackUsage(Module *module) {
assert(inst);
auto shaderStage = lgc::getShaderStage(inst->getFunction());
- if (shaderStage != ShaderStageInvalid)
- m_pipelineState->getShaderResourceUsage(shaderStage)->useRayQueryLdsStack = true;
+ if (shaderStage)
+ m_pipelineState->getShaderResourceUsage(shaderStage.value())->useRayQueryLdsStack = true;
}
}
}
@@ -1169,7 +1170,7 @@ void PatchResourceCollect::visitCallInst(CallInst &callInst) {
m_deadCalls.push_back(&callInst);
else
m_inputCalls.push_back(cast<GenericLocationOp>(&callInst));
- } else if (mangledName.startswith(lgcName::InputImportBuiltIn)) {
+ } else if (mangledName.starts_with(lgcName::InputImportBuiltIn)) {
// Built-in input import
if (isDeadCall)
m_deadCalls.push_back(&callInst);
@@ -1179,22 +1180,22 @@ void PatchResourceCollect::visitCallInst(CallInst &callInst) {
}
} else if (auto *outputImport = dyn_cast<OutputImportGenericOp>(&callInst)) {
// Generic output import
- assert(m_shaderStage == ShaderStageTessControl);
+ assert(m_shaderStage == ShaderStage::TessControl);
auto outputTy = outputImport->getType();
assert(outputTy->isSingleValueType());
(void)(outputTy);
m_importedOutputCalls.push_back(outputImport);
- } else if (mangledName.startswith(lgcName::OutputImportBuiltIn)) {
+ } else if (mangledName.starts_with(lgcName::OutputImportBuiltIn)) {
// Built-in output import
- assert(m_shaderStage == ShaderStageTessControl);
+ assert(m_shaderStage == ShaderStage::TessControl);
unsigned builtInId = cast<ConstantInt>(callInst.getOperand(0))->getZExtValue();
m_importedOutputBuiltIns.insert(builtInId);
- } else if (mangledName.startswith(lgcName::OutputExportGeneric)) {
+ } else if (mangledName.starts_with(lgcName::OutputExportGeneric)) {
m_outputCalls.push_back(&callInst);
- } else if (mangledName.startswith(lgcName::OutputExportBuiltIn)) {
+ } else if (mangledName.starts_with(lgcName::OutputExportBuiltIn)) {
// NOTE: If an output value is unspecified, we can safely drop it and remove the output export call.
// Currently, do this for geometry shader.
- if (m_shaderStage == ShaderStageGeometry) {
+ if (m_shaderStage == ShaderStage::Geometry) {
auto outputValue = callInst.getArgOperand(callInst.arg_size() - 1);
if (isa<UndefValue>(outputValue) || isa<PoisonValue>(outputValue))
m_deadCalls.push_back(&callInst);
@@ -1203,7 +1204,7 @@ void PatchResourceCollect::visitCallInst(CallInst &callInst) {
m_activeOutputBuiltIns.insert(builtInId);
}
}
- } else if (mangledName.startswith(lgcName::OutputExportXfb)) {
+ } else if (mangledName.starts_with(lgcName::OutputExportXfb)) {
auto outputValue = callInst.getArgOperand(callInst.arg_size() - 1);
if (isa<UndefValue>(outputValue) || isa<PoisonValue>(outputValue)) {
// NOTE: If an output value is unspecified, we can safely drop it and remove the transform feedback export call.
@@ -1211,12 +1212,18 @@ void PatchResourceCollect::visitCallInst(CallInst &callInst) {
} else if (m_pipelineState->enableSwXfb()) {
// Collect transform feedback export calls, used in SW-emulated stream-out. For GS, the collecting will
// be done when we generate copy shader since GS is primitive-based.
- if (m_shaderStage != ShaderStageGeometry) {
+ if (m_shaderStage != ShaderStage::Geometry) {
auto &inOutUsage = m_pipelineState->getShaderResourceUsage(m_shaderStage)->inOutUsage;
// A transform feedback export call is expected to be <4 x dword> at most
inOutUsage.xfbExpCount += outputValue->getType()->getPrimitiveSizeInBits() > 128 ? 2 : 1;
}
}
+ } else if (auto *loadBufferDescOp = dyn_cast<LoadBufferDescOp>(&callInst)) {
+ unsigned flags = loadBufferDescOp->getFlags();
+ // Mark the shader as reading and writing (if applicable) a resource.
+ m_resUsage->resourceRead = true;
+ if (flags & Builder::BufferFlagWritten)
+ m_resUsage->resourceWrite = true;
}
}
@@ -1228,7 +1235,7 @@ void PatchResourceCollect::clearInactiveBuiltInInput() {
auto &builtInUsage = m_resUsage->builtInUsage;
// Check per-stage built-in usage
- if (m_shaderStage == ShaderStageTessControl) {
+ if (m_shaderStage == ShaderStage::TessControl) {
if (builtInUsage.tcs.pointSizeIn && m_activeInputBuiltIns.find(BuiltInPointSize) == m_activeInputBuiltIns.end())
builtInUsage.tcs.pointSizeIn = false;
@@ -1255,7 +1262,7 @@ void PatchResourceCollect::clearInactiveBuiltInInput() {
if (builtInUsage.tcs.viewIndex && m_activeInputBuiltIns.find(BuiltInViewIndex) == m_activeInputBuiltIns.end())
builtInUsage.tcs.viewIndex = false;
- } else if (m_shaderStage == ShaderStageTessEval) {
+ } else if (m_shaderStage == ShaderStage::TessEval) {
if (builtInUsage.tes.pointSizeIn && m_activeInputBuiltIns.find(BuiltInPointSize) == m_activeInputBuiltIns.end())
builtInUsage.tes.pointSizeIn = false;
@@ -1290,7 +1297,7 @@ void PatchResourceCollect::clearInactiveBuiltInInput() {
if (builtInUsage.tes.viewIndex && m_activeInputBuiltIns.find(BuiltInViewIndex) == m_activeInputBuiltIns.end())
builtInUsage.tes.viewIndex = false;
- } else if (m_shaderStage == ShaderStageGeometry) {
+ } else if (m_shaderStage == ShaderStage::Geometry) {
if (builtInUsage.gs.pointSizeIn && m_activeInputBuiltIns.find(BuiltInPointSize) == m_activeInputBuiltIns.end())
builtInUsage.gs.pointSizeIn = false;
@@ -1313,7 +1320,7 @@ void PatchResourceCollect::clearInactiveBuiltInInput() {
if (builtInUsage.gs.viewIndex && m_activeInputBuiltIns.find(BuiltInViewIndex) == m_activeInputBuiltIns.end())
builtInUsage.gs.viewIndex = false;
- } else if (m_shaderStage == ShaderStageMesh) {
+ } else if (m_shaderStage == ShaderStage::Mesh) {
if (builtInUsage.mesh.drawIndex && m_activeInputBuiltIns.find(BuiltInDrawIndex) == m_activeInputBuiltIns.end())
builtInUsage.mesh.drawIndex = false;
@@ -1345,7 +1352,7 @@ void PatchResourceCollect::clearInactiveBuiltInInput() {
if (builtInUsage.mesh.numSubgroups &&
m_activeInputBuiltIns.find(BuiltInNumSubgroups) == m_activeInputBuiltIns.end())
builtInUsage.mesh.numSubgroups = false;
- } else if (m_shaderStage == ShaderStageFragment) {
+ } else if (m_shaderStage == ShaderStage::Fragment) {
if (builtInUsage.fs.fragCoord && m_activeInputBuiltIns.find(BuiltInFragCoord) == m_activeInputBuiltIns.end())
builtInUsage.fs.fragCoord = false;
@@ -1439,7 +1446,7 @@ void PatchResourceCollect::clearInactiveBuiltInInput() {
// Clears inactive (those actually unused) outputs.
void PatchResourceCollect::clearInactiveBuiltInOutput() {
// Clear inactive output builtins
- if (m_shaderStage == ShaderStageGeometry) {
+ if (m_shaderStage == ShaderStage::Geometry) {
auto &builtInUsage = m_resUsage->builtInUsage.gs;
if (builtInUsage.position && m_activeOutputBuiltIns.find(BuiltInPosition) == m_activeOutputBuiltIns.end())
@@ -1478,11 +1485,11 @@ void PatchResourceCollect::matchGenericInOut() {
// Do input matching and location remapping
bool packInput = m_pipelineState->canPackInput(m_shaderStage);
- if (m_shaderStage == ShaderStageTessControl && m_tcsInputHasDynamicIndexing) {
+ if (m_shaderStage == ShaderStage::TessControl && m_tcsInputHasDynamicIndexing) {
packInput = false;
// Disable to pack VS-TCS
m_pipelineState->setPackInput(m_shaderStage, false);
- m_pipelineState->setPackOutput(ShaderStageVertex, false);
+ m_pipelineState->setPackOutput(ShaderStage::Vertex, false);
}
if (packInput)
updateInputLocInfoMapWithPack();
@@ -1491,13 +1498,13 @@ void PatchResourceCollect::matchGenericInOut() {
// Do output matching and location remapping
bool packOutput = m_pipelineState->canPackOutput(m_shaderStage);
- if (m_shaderStage == ShaderStageVertex && m_tcsInputHasDynamicIndexing)
+ if (m_shaderStage == ShaderStage::Vertex && m_tcsInputHasDynamicIndexing)
assert(!packOutput);
if (packOutput) {
// OutputLocInfoMap is used for computing the shader hash and looking remapped location
updateOutputLocInfoMapWithPack();
// Re-create output export calls to pack exp instruction for the last vertex processing stage
- if (m_shaderStage == m_pipelineState->getLastVertexProcessingStage() && m_shaderStage != ShaderStageGeometry)
+ if (m_shaderStage == m_pipelineState->getLastVertexProcessingStage() && m_shaderStage != ShaderStage::Geometry)
reassembleOutputExportCalls();
m_outputCalls.clear();
} else {
@@ -1506,8 +1513,7 @@ void PatchResourceCollect::matchGenericInOut() {
// Update location count of input/output
LLPC_OUTS("===============================================================================\n");
- LLPC_OUTS("// LLPC location input/output mapping results (" << getShaderStageAbbreviation(m_shaderStage)
- << " shader)\n\n");
+ LLPC_OUTS("// LLPC location input/output mapping results (" << getShaderStageAbbreviation(m_shaderStage) << ")\n\n");
auto &inOutUsage = m_pipelineState->getShaderResourceUsage(m_shaderStage)->inOutUsage;
auto &inLocInfoMap = inOutUsage.inputLocInfoMap;
auto &outLocInfoMap = inOutUsage.outputLocInfoMap;
@@ -1525,8 +1531,8 @@ void PatchResourceCollect::matchGenericInOut() {
const unsigned newComp = locInfoPair.second.getComponent();
assert(newLoc != InvalidValue);
inOutUsage.inputMapLocCount = std::max(inOutUsage.inputMapLocCount, newLoc + 1);
- LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Input: loc = " << origLoc
- << ", comp = " << origComp << " => Mapped = " << newLoc << ", " << newComp << "\n");
+ LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Input: [location, component] = [" << origLoc
+ << ", " << origComp << "] => Mapped = [" << newLoc << ", " << newComp << "]\n");
}
LLPC_OUTS("\n");
}
@@ -1542,19 +1548,19 @@ void PatchResourceCollect::matchGenericInOut() {
const unsigned newLoc = locInfoPair.second.getLocation();
const unsigned newComp = locInfoPair.second.getComponent();
- if (m_shaderStage == ShaderStageGeometry) {
+ if (m_shaderStage == ShaderStage::Geometry) {
const unsigned streamId = locInfoPair.first.getStreamId();
unsigned assignedLocCount = inOutUsage.gs.outLocCount[0] + inOutUsage.gs.outLocCount[1] +
inOutUsage.gs.outLocCount[2] + inOutUsage.gs.outLocCount[3];
inOutUsage.outputMapLocCount = std::max(inOutUsage.outputMapLocCount, assignedLocCount);
LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Output: stream = " << streamId << ", "
- << " loc = " << origLoc << ", comp = " << origComp << " => Mapped = " << newLoc << ", "
- << newComp << "\n");
+ << " [location, component] = [" << origLoc << ", " << origComp << "] => Mapped = [" << newLoc
+ << ", " << newComp << "]\n");
} else {
inOutUsage.outputMapLocCount = std::max(inOutUsage.outputMapLocCount, newLoc + 1);
- LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Output: loc = " << origLoc
- << ", comp = " << origComp << " => Mapped = " << newLoc << ", " << newComp << "\n");
+ LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Output: [location, component] = [" << origLoc
+ << ", " << origComp << "] => Mapped = [" << newLoc << ", " << newComp << "]\n");
}
}
LLPC_OUTS("\n");
@@ -1563,9 +1569,9 @@ void PatchResourceCollect::matchGenericInOut() {
if (!perPatchInLocMap.empty()) {
assert(inOutUsage.perPatchInputMapLocCount == 0);
for (auto locMap : perPatchInLocMap) {
- assert(m_shaderStage == ShaderStageTessEval && locMap.second != InvalidValue);
+ assert(m_shaderStage == ShaderStage::TessEval && locMap.second != InvalidValue);
inOutUsage.perPatchInputMapLocCount = std::max(inOutUsage.perPatchInputMapLocCount, locMap.second + 1);
- LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Input (per-patch): loc = " << locMap.first
+ LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Input (per-patch): location = " << locMap.first
<< " => Mapped = " << locMap.second << "\n");
}
LLPC_OUTS("\n");
@@ -1574,9 +1580,9 @@ void PatchResourceCollect::matchGenericInOut() {
if (!perPatchOutLocMap.empty()) {
assert(inOutUsage.perPatchOutputMapLocCount == 0);
for (auto locMap : perPatchOutLocMap) {
- assert(m_shaderStage == ShaderStageTessControl && locMap.second != InvalidValue);
+ assert(m_shaderStage == ShaderStage::TessControl && locMap.second != InvalidValue);
inOutUsage.perPatchOutputMapLocCount = std::max(inOutUsage.perPatchOutputMapLocCount, locMap.second + 1);
- LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Output (per-patch): loc = " << locMap.first
+ LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Output (per-patch): location = " << locMap.first
<< " => Mapped = " << locMap.second << "\n");
}
LLPC_OUTS("\n");
@@ -1585,10 +1591,10 @@ void PatchResourceCollect::matchGenericInOut() {
if (!perPrimitiveInLocMap.empty()) {
assert(inOutUsage.perPrimitiveInputMapLocCount == 0);
for (auto locMap : perPrimitiveInLocMap) {
- assert(m_shaderStage == ShaderStageFragment && locMap.second != InvalidValue);
+ assert(m_shaderStage == ShaderStage::Fragment && locMap.second != InvalidValue);
inOutUsage.perPrimitiveInputMapLocCount = std::max(inOutUsage.perPrimitiveInputMapLocCount, locMap.second + 1);
- LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Input (per-primitive): loc = " << locMap.first
- << " => Mapped = " << locMap.second << "\n");
+ LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Input (per-primitive): location = "
+ << locMap.first << " => Mapped = " << locMap.second << "\n");
}
LLPC_OUTS("\n");
}
@@ -1596,34 +1602,34 @@ void PatchResourceCollect::matchGenericInOut() {
if (!perPrimitiveOutLocMap.empty()) {
assert(inOutUsage.perPrimitiveOutputMapLocCount == 0);
for (auto locMap : perPrimitiveOutLocMap) {
- assert(m_shaderStage == ShaderStageMesh && locMap.second != InvalidValue);
+ assert(m_shaderStage == ShaderStage::Mesh && locMap.second != InvalidValue);
inOutUsage.perPrimitiveOutputMapLocCount = std::max(inOutUsage.perPrimitiveOutputMapLocCount, locMap.second + 1);
- LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Output (per-primitive): loc = " << locMap.first
- << " => Mapped = " << locMap.second << "\n");
+ LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Output (per-primitive): location = "
+ << locMap.first << " => Mapped = " << locMap.second << "\n");
}
LLPC_OUTS("\n");
}
LLPC_OUTS("// LLPC location count results (after input/output matching) \n\n");
- LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Input: loc count = " << inOutUsage.inputMapLocCount
+ LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Input: locations = " << inOutUsage.inputMapLocCount
<< "\n");
- LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Output: loc count = " << inOutUsage.outputMapLocCount
+ LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Output: locations = " << inOutUsage.outputMapLocCount
<< "\n");
- if (m_shaderStage == ShaderStageTessEval) {
+ if (m_shaderStage == ShaderStage::TessEval) {
LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage)
- << ") Input (per-patch): loc count = " << inOutUsage.perPatchInputMapLocCount << "\n");
+ << ") Input (per-patch): locations = " << inOutUsage.perPatchInputMapLocCount << "\n");
}
- if (m_shaderStage == ShaderStageTessControl) {
+ if (m_shaderStage == ShaderStage::TessControl) {
LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage)
- << ") Output (per-patch): loc count = " << inOutUsage.perPatchOutputMapLocCount << "\n");
+ << ") Output (per-patch): locations = " << inOutUsage.perPatchOutputMapLocCount << "\n");
}
- if (m_shaderStage == ShaderStageFragment) {
+ if (m_shaderStage == ShaderStage::Fragment) {
LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage)
- << ") Input (per-primitive): loc count = " << inOutUsage.perPrimitiveInputMapLocCount << "\n");
+ << ") Input (per-primitive): locations = " << inOutUsage.perPrimitiveInputMapLocCount << "\n");
}
- if (m_shaderStage == ShaderStageMesh) {
+ if (m_shaderStage == ShaderStage::Mesh) {
LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage)
- << ") Output (per-primitive): loc count = " << inOutUsage.perPrimitiveOutputMapLocCount << "\n");
+ << ") Output (per-primitive): locations = " << inOutUsage.perPrimitiveOutputMapLocCount << "\n");
}
LLPC_OUTS("\n");
}
@@ -1641,7 +1647,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
auto &inOutUsage = resUsage->inOutUsage;
const auto nextStage = m_pipelineState->getNextShaderStage(m_shaderStage);
- auto nextResUsage = nextStage != ShaderStageInvalid ? m_pipelineState->getShaderResourceUsage(nextStage) : nullptr;
+ auto nextResUsage = nextStage != ShaderStage::Invalid ? m_pipelineState->getShaderResourceUsage(nextStage) : nullptr;
assert(inOutUsage.builtInInputLocMap.empty()); // Should be empty
assert(inOutUsage.builtInOutputLocMap.empty());
@@ -1651,12 +1657,12 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
// get the mapped location from next shader stage inout usage and use it. If next shader stage
// is absent or it does not have such input used, we allocate the mapped location.
// (2) For built-on inputs, we always allocate the mapped location based its actual usage.
- if (m_shaderStage == ShaderStageVertex) {
+ if (m_shaderStage == ShaderStage::Vertex) {
// VS ==> XXX
unsigned availOutMapLoc = inOutUsage.outputMapLocCount;
// Map built-in outputs to generic ones
- if (nextStage == ShaderStageFragment) {
+ if (nextStage == ShaderStage::Fragment) {
// VS ==> FS
const auto &nextBuiltInUsage = nextResUsage->builtInUsage.fs;
auto &nextInOutUsage = nextResUsage->inOutUsage;
@@ -1693,7 +1699,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
const unsigned mapLoc = nextInOutUsage.builtInInputLocMap[BuiltInViewportIndex];
inOutUsage.builtInOutputLocMap[BuiltInViewportIndex] = mapLoc;
}
- } else if (nextStage == ShaderStageTessControl) {
+ } else if (nextStage == ShaderStage::TessControl) {
// VS ==> TCS
const auto &nextBuiltInUsage = nextResUsage->builtInUsage.tcs;
auto &nextInOutUsage = nextResUsage->inOutUsage;
@@ -1753,7 +1759,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
}
builtInUsage.vs.primitiveShadingRate = false;
- } else if (nextStage == ShaderStageGeometry) {
+ } else if (nextStage == ShaderStage::Geometry) {
// VS ==> GS
const auto &nextBuiltInUsage = nextResUsage->builtInUsage.gs;
auto &nextInOutUsage = nextResUsage->inOutUsage;
@@ -1813,7 +1819,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
}
builtInUsage.vs.primitiveShadingRate = false;
- } else if (nextStage == ShaderStageInvalid) {
+ } else if (nextStage == ShaderStage::Invalid) {
// VS only
if (builtInUsage.vs.clipDistance > 0 || builtInUsage.vs.cullDistance > 0) {
unsigned mapLoc = availOutMapLoc++;
@@ -1840,7 +1846,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
}
inOutUsage.outputMapLocCount = std::max(inOutUsage.outputMapLocCount, availOutMapLoc);
- } else if (m_shaderStage == ShaderStageTessControl) {
+ } else if (m_shaderStage == ShaderStage::TessControl) {
// TCS ==> XXX
unsigned availInMapLoc = inOutUsage.inputMapLocCount;
unsigned availOutMapLoc = inOutUsage.outputMapLocCount;
@@ -1873,7 +1879,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
inOutUsage.builtInInputLocMap[BuiltInViewportIndex] = availInMapLoc++;
// Map built-in outputs to generic ones
- if (nextStage == ShaderStageTessEval) {
+ if (nextStage == ShaderStage::TessEval) {
const auto &nextBuiltInUsage = nextResUsage->builtInUsage.tes;
auto &nextInOutUsage = nextResUsage->inOutUsage;
@@ -1976,7 +1982,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
if (inOutUsage.builtInOutputLocMap.find(BuiltInCullDistance) != inOutUsage.builtInOutputLocMap.end() &&
inOutUsage.builtInOutputLocMap[BuiltInCullDistance] == InvalidValue)
inOutUsage.builtInOutputLocMap[BuiltInCullDistance] = availOutMapLoc++;
- } else if (nextStage == ShaderStageInvalid) {
+ } else if (nextStage == ShaderStage::Invalid) {
// TCS only
if (builtInUsage.tcs.position)
inOutUsage.builtInOutputLocMap[BuiltInPosition] = availOutMapLoc++;
@@ -2012,7 +2018,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
inOutUsage.inputMapLocCount = std::max(inOutUsage.inputMapLocCount, availInMapLoc);
inOutUsage.outputMapLocCount = std::max(inOutUsage.outputMapLocCount, availOutMapLoc);
inOutUsage.perPatchOutputMapLocCount = std::max(inOutUsage.perPatchOutputMapLocCount, availPerPatchOutMapLoc);
- } else if (m_shaderStage == ShaderStageTessEval) {
+ } else if (m_shaderStage == ShaderStage::TessEval) {
// TES ==> XXX
unsigned availInMapLoc = inOutUsage.inputMapLocCount;
unsigned availOutMapLoc = inOutUsage.outputMapLocCount;
@@ -2033,7 +2039,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
// tessellation control shader. The clip distance is the maximum of the two. We do this to avoid
// incorrectness of location assignment during builtin-to-generic mapping.
const auto prevStage = m_pipelineState->getPrevShaderStage(m_shaderStage);
- if (prevStage == ShaderStageTessControl) {
+ if (prevStage == ShaderStage::TessControl) {
const auto &prevBuiltInUsage = m_pipelineState->getShaderResourceUsage(prevStage)->builtInUsage.tcs;
clipDistanceCount = std::max(clipDistanceCount, prevBuiltInUsage.clipDistance);
}
@@ -2047,7 +2053,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
unsigned cullDistanceCount = builtInUsage.tes.cullDistanceIn;
const auto prevStage = m_pipelineState->getPrevShaderStage(m_shaderStage);
- if (prevStage == ShaderStageTessControl) {
+ if (prevStage == ShaderStage::TessControl) {
const auto &prevBuiltInUsage = m_pipelineState->getShaderResourceUsage(prevStage)->builtInUsage.tcs;
cullDistanceCount = std::max(cullDistanceCount, prevBuiltInUsage.clipDistance);
}
@@ -2070,7 +2076,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
inOutUsage.perPatchBuiltInInputLocMap[BuiltInTessLevelInner] = availPerPatchInMapLoc++;
// Map built-in outputs to generic ones
- if (nextStage == ShaderStageFragment) {
+ if (nextStage == ShaderStage::Fragment) {
// TES ==> FS
const auto &nextBuiltInUsage = nextResUsage->builtInUsage.fs;
auto &nextInOutUsage = nextResUsage->inOutUsage;
@@ -2101,7 +2107,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
const unsigned mapLoc = nextInOutUsage.builtInInputLocMap[BuiltInLayer];
inOutUsage.builtInOutputLocMap[BuiltInLayer] = mapLoc;
}
- } else if (nextStage == ShaderStageGeometry) {
+ } else if (nextStage == ShaderStage::Geometry) {
// TES ==> GS
const auto &nextBuiltInUsage = nextResUsage->builtInUsage.gs;
auto &nextInOutUsage = nextResUsage->inOutUsage;
@@ -2159,7 +2165,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
} else {
builtInUsage.tes.viewportIndex = 0;
}
- } else if (nextStage == ShaderStageInvalid) {
+ } else if (nextStage == ShaderStage::Invalid) {
// TES only
if (builtInUsage.tes.clipDistance > 0 || builtInUsage.tes.cullDistance > 0) {
unsigned mapLoc = availOutMapLoc++;
@@ -2189,7 +2195,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
inOutUsage.outputMapLocCount = std::max(inOutUsage.outputMapLocCount, availOutMapLoc);
inOutUsage.perPatchInputMapLocCount = std::max(inOutUsage.perPatchInputMapLocCount, availPerPatchInMapLoc);
- } else if (m_shaderStage == ShaderStageGeometry) {
+ } else if (m_shaderStage == ShaderStage::Geometry) {
// GS ==> XXX
unsigned availInMapLoc = inOutUsage.inputMapLocCount;
@@ -2249,7 +2255,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
// Map built-in outputs to generic ones (for copy shader)
auto &builtInOutLocs = inOutUsage.gs.builtInOutLocs;
- if (nextStage == ShaderStageFragment) {
+ if (nextStage == ShaderStage::Fragment) {
// GS ==> FS
const auto &nextBuiltInUsage = nextResUsage->builtInUsage.fs;
auto &nextInOutUsage = nextResUsage->inOutUsage;
@@ -2283,7 +2289,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
const unsigned mapLoc = nextInOutUsage.builtInInputLocMap[BuiltInViewportIndex];
builtInOutLocs[BuiltInViewportIndex] = mapLoc;
}
- } else if (nextStage == ShaderStageInvalid) {
+ } else if (nextStage == ShaderStage::Invalid) {
// GS only
unsigned availOutMapLoc = inOutUsage.outputLocInfoMap.size(); // Reset available location
@@ -2315,7 +2321,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
}
inOutUsage.inputMapLocCount = std::max(inOutUsage.inputMapLocCount, availInMapLoc);
- } else if (m_shaderStage == ShaderStageMesh) {
+ } else if (m_shaderStage == ShaderStage::Mesh) {
// Mesh shader -> XXX
unsigned availOutMapLoc = inOutUsage.outputMapLocCount;
unsigned availPerPrimitiveOutMapLoc = inOutUsage.perPrimitiveOutputMapLocCount;
@@ -2353,7 +2359,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
inOutUsage.perPrimitiveBuiltInOutputLocMap[BuiltInPrimitiveShadingRate] = availPerPrimitiveOutMapLoc++;
// Map per-vertex built-in outputs to exported locations
- if (nextStage == ShaderStageFragment) {
+ if (nextStage == ShaderStage::Fragment) {
// Mesh shader ==> FS
const auto &nextBuiltInUsage = nextResUsage->builtInUsage.fs;
auto &nextInOutUsage = nextResUsage->inOutUsage;
@@ -2369,7 +2375,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
const unsigned mapLoc = nextInOutUsage.builtInInputLocMap[BuiltInCullDistance];
inOutUsage.mesh.builtInExportLocs[BuiltInCullDistance] = mapLoc;
}
- } else if (nextStage == ShaderStageInvalid) {
+ } else if (nextStage == ShaderStage::Invalid) {
// Mesh shader only
unsigned availExportLoc = inOutUsage.outputMapLocCount;
@@ -2392,7 +2398,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
}
// Map per-primitive built-in outputs to exported locations
- if (nextStage == ShaderStageFragment) {
+ if (nextStage == ShaderStage::Fragment) {
// Mesh shader ==> FS
const auto &nextBuiltInUsage = nextResUsage->builtInUsage.fs;
auto &nextInOutUsage = nextResUsage->inOutUsage;
@@ -2417,7 +2423,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
const unsigned mapLoc = nextInOutUsage.perPrimitiveBuiltInInputLocMap[BuiltInViewportIndex];
inOutUsage.mesh.perPrimitiveBuiltInExportLocs[BuiltInViewportIndex] = mapLoc;
}
- } else if (nextStage == ShaderStageInvalid) {
+ } else if (nextStage == ShaderStage::Invalid) {
// Mesh shader only
unsigned availPerPrimitiveExportLoc = inOutUsage.perPrimitiveOutputMapLocCount;
@@ -2437,7 +2443,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
inOutUsage.outputMapLocCount = std::max(inOutUsage.outputMapLocCount, availOutMapLoc);
inOutUsage.perPrimitiveOutputMapLocCount =
std::max(inOutUsage.perPrimitiveOutputMapLocCount, availPerPrimitiveOutMapLoc);
- } else if (m_shaderStage == ShaderStageFragment) {
+ } else if (m_shaderStage == ShaderStage::Fragment) {
// FS
const auto prevStage = m_pipelineState->getPrevShaderStage(m_shaderStage);
unsigned availInMapLoc = inOutUsage.inputMapLocCount;
@@ -2447,21 +2453,21 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
inOutUsage.builtInInputLocMap[BuiltInPointCoord] = availInMapLoc++;
if (builtInUsage.fs.primitiveId) {
- if (prevStage == ShaderStageMesh)
+ if (prevStage == ShaderStage::Mesh)
inOutUsage.perPrimitiveBuiltInInputLocMap[BuiltInPrimitiveId] = availPerPrimitiveInMapLoc++;
else
inOutUsage.builtInInputLocMap[BuiltInPrimitiveId] = availInMapLoc++;
}
if (builtInUsage.fs.layer) {
- if (prevStage == ShaderStageMesh)
+ if (prevStage == ShaderStage::Mesh)
inOutUsage.perPrimitiveBuiltInInputLocMap[BuiltInLayer] = availPerPrimitiveInMapLoc++;
else
inOutUsage.builtInInputLocMap[BuiltInLayer] = availInMapLoc++;
}
if (builtInUsage.fs.viewportIndex) {
- if (prevStage == ShaderStageMesh)
+ if (prevStage == ShaderStage::Mesh)
inOutUsage.perPrimitiveBuiltInInputLocMap[BuiltInViewportIndex] = availPerPrimitiveInMapLoc++;
else
inOutUsage.builtInInputLocMap[BuiltInViewportIndex] = availInMapLoc++;
@@ -2491,8 +2497,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
// Do builtin-to-generic mapping
LLPC_OUTS("===============================================================================\n");
- LLPC_OUTS("// LLPC builtin-to-generic mapping results (" << getShaderStageAbbreviation(m_shaderStage)
- << " shader)\n\n");
+ LLPC_OUTS("// LLPC builtin-to-generic mapping results (" << getShaderStageAbbreviation(m_shaderStage) << ")\n\n");
for (const auto &builtInMap : inOutUsage.builtInInputLocMap) {
const BuiltInKind builtInId = static_cast<BuiltInKind>(builtInMap.first);
const unsigned loc = builtInMap.second;
@@ -2506,7 +2511,7 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
const BuiltInKind builtInId = static_cast<BuiltInKind>(builtInMap.first);
const unsigned loc = builtInMap.second;
- if (m_shaderStage == ShaderStageGeometry) {
+ if (m_shaderStage == ShaderStage::Geometry) {
LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage)
<< ") Output: stream = " << m_pipelineState->getRasterizerState().rasterStream << " , "
<< "builtin = " << PipelineState::getBuiltInName(builtInId) << " => Mapped = " << loc << "\n");
@@ -2555,25 +2560,25 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
LLPC_OUTS("\n");
LLPC_OUTS("// LLPC location count results (after builtin-to-generic mapping)\n\n");
- LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Input: loc count = " << inOutUsage.inputMapLocCount
+ LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Input: locations = " << inOutUsage.inputMapLocCount
<< "\n");
- LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Output: loc count = " << inOutUsage.outputMapLocCount
+ LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage) << ") Output: locations = " << inOutUsage.outputMapLocCount
<< "\n");
- if (m_shaderStage == ShaderStageTessEval) {
+ if (m_shaderStage == ShaderStage::TessEval) {
LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage)
- << ") Input (per-patch): loc count = " << inOutUsage.perPatchInputMapLocCount << "\n");
+ << ") Input (per-patch): locations = " << inOutUsage.perPatchInputMapLocCount << "\n");
}
- if (m_shaderStage == ShaderStageTessControl) {
+ if (m_shaderStage == ShaderStage::TessControl) {
LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage)
- << ") Output (per-patch): loc count = " << inOutUsage.perPatchOutputMapLocCount << "\n");
+ << ") Output (per-patch): locations = " << inOutUsage.perPatchOutputMapLocCount << "\n");
}
- if (m_shaderStage == ShaderStageFragment) {
+ if (m_shaderStage == ShaderStage::Fragment) {
LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage)
- << ") Input (per-primitive): loc count = " << inOutUsage.perPrimitiveInputMapLocCount << "\n");
+ << ") Input (per-primitive): locations = " << inOutUsage.perPrimitiveInputMapLocCount << "\n");
}
- if (m_shaderStage == ShaderStageMesh) {
+ if (m_shaderStage == ShaderStage::Mesh) {
LLPC_OUTS("(" << getShaderStageAbbreviation(m_shaderStage)
- << ") Output (per-primitive): loc count = " << inOutUsage.perPrimitiveOutputMapLocCount << "\n");
+ << ") Output (per-primitive): locations = " << inOutUsage.perPrimitiveOutputMapLocCount << "\n");
}
LLPC_OUTS("\n");
}
@@ -2584,8 +2589,8 @@ void PatchResourceCollect::mapBuiltInToGenericInOut() {
// @param builtInId : Built-in ID
// @param elemCount : Element count of this built-in
void PatchResourceCollect::mapGsBuiltInOutput(unsigned builtInId, unsigned elemCount) {
- assert(m_shaderStage == ShaderStageGeometry);
- auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry);
+ assert(m_shaderStage == ShaderStage::Geometry);
+ auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry);
auto &inOutUsage = resUsage->inOutUsage.gs;
unsigned streamId = m_pipelineState->getRasterizerState().rasterStream;
@@ -2607,20 +2612,20 @@ void PatchResourceCollect::updateInputLocInfoMapWithUnpack() {
auto &inputLocInfoMap = inOutUsage.inputLocInfoMap;
// Remove unused locationInfo
bool eraseUnusedLocInfo = !m_pipelineState->isUnlinked(); // Should be whole pipeline compilation
- if (m_shaderStage == ShaderStageTessEval) {
+ if (m_shaderStage == ShaderStage::TessEval) {
// TODO: Here, we keep all generic inputs of tessellation evaluation shader. This is because corresponding
// generic outputs of tessellation control shader might involve in output import and dynamic indexing, which
// is easy to cause incorrectness of location mapping.
// m_inputCalls holds the calls that have users
eraseUnusedLocInfo = false;
- } else if (m_shaderStage == ShaderStageFragment) {
+ } else if (m_shaderStage == ShaderStage::Fragment) {
// NOTE: If the previous stage of fragment shader is mesh shader, we skip this because the input/output packing
// is disable between mesh shader and fragment shader.
- auto prevStage = m_pipelineState->getPrevShaderStage(ShaderStageFragment);
- if (prevStage == ShaderStageMesh) {
+ auto prevStage = m_pipelineState->getPrevShaderStage(ShaderStage::Fragment);
+ if (prevStage == ShaderStage::Mesh) {
eraseUnusedLocInfo = false;
}
- } else if (m_shaderStage == ShaderStageTessControl) {
+ } else if (m_shaderStage == ShaderStage::TessControl) {
// NOTE: If location offset or element index (64-bit element type) is dynamic, we keep all generic inputs of TCS.
for (auto call : m_inputCalls) {
auto locOffset = call->getLocOffset();
@@ -2682,7 +2687,7 @@ void PatchResourceCollect::updateInputLocInfoMapWithUnpack() {
// [0,2], we need add the corresponding location info to TES input map. Otherwise, it will cause mismatch when the
// dynamic indexing is in a loop and TES only uses location 1.
auto preStage = m_pipelineState->getPrevShaderStage(m_shaderStage);
- if (preStage == ShaderStageTessControl || preStage == ShaderStageMesh) {
+ if (preStage == ShaderStage::TessControl || preStage == ShaderStage::Mesh) {
if (!inputLocInfoMap.empty()) {
auto &outputLocInfoMap = m_pipelineState->getShaderResourceUsage(preStage)->inOutUsage.outputLocInfoMap;
for (auto &infoPair : outputLocInfoMap) {
@@ -2710,7 +2715,7 @@ void PatchResourceCollect::updateInputLocInfoMapWithUnpack() {
DenseMap<unsigned, unsigned> alreadyMappedLocs; // Map from original location to new location
for (auto &locInfoPair : inputLocInfoMap) {
auto &newLocationInfo = locInfoPair.second;
- if (m_shaderStage == ShaderStageVertex) {
+ if (m_shaderStage == ShaderStage::Vertex) {
// NOTE: For vertex shader, use the original location as the remapped location
newLocationInfo.setData(locInfoPair.first.getData());
} else {
@@ -2758,13 +2763,13 @@ void PatchResourceCollect::updateInputLocInfoMapWithUnpack() {
// =====================================================================================================================
// Clear unused output from outputLocInfoMap, perPatchOutputLocMap, and perPrimitiveOutputLocMap
void PatchResourceCollect::clearUnusedOutput() {
- ShaderStage nextStage = m_pipelineState->getNextShaderStage(m_shaderStage);
+ ShaderStageEnum nextStage = m_pipelineState->getNextShaderStage(m_shaderStage);
auto &inOutUsage = m_pipelineState->getShaderResourceUsage(m_shaderStage)->inOutUsage;
auto &outputLocInfoMap = inOutUsage.outputLocInfoMap;
- if (nextStage != ShaderStageInvalid) {
+ if (nextStage != ShaderStage::Invalid) {
// Collect the locations of TCS's imported outputs
DenseSet<unsigned> importOutputLocs;
- if (m_shaderStage == ShaderStageTessControl) {
+ if (m_shaderStage == ShaderStage::TessControl) {
// Imported output calls
for (auto &outputImport : m_importedOutputCalls) {
unsigned loc = outputImport->getLocation();
@@ -2788,11 +2793,10 @@ void PatchResourceCollect::clearUnusedOutput() {
SmallVector<InOutLocationInfo, 4> unusedLocInfos;
auto nextResUsage = m_pipelineState->getShaderResourceUsage(nextStage);
const auto &nextInLocInfoMap = nextResUsage->inOutUsage.inputLocInfoMap;
- unsigned availInMapLoc = nextResUsage->inOutUsage.inputMapLocCount;
for (auto &locInfoPair : outputLocInfoMap) {
const unsigned origLoc = locInfoPair.first.getLocation();
- if (m_shaderStage == ShaderStageFragment) {
+ if (m_shaderStage == ShaderStage::Fragment) {
// Collect locations with invalid data format
const bool generatingColorExportShader =
m_pipelineState->isUnlinked() && !m_pipelineState->hasColorExportFormats();
@@ -2803,7 +2807,7 @@ void PatchResourceCollect::clearUnusedOutput() {
bool isOutputXfb = false;
bool foundInNextStage = false;
- if (m_shaderStage == ShaderStageGeometry) {
+ if (m_shaderStage == ShaderStage::Geometry) {
isOutputXfb = inOutUsage.locInfoXfbOutInfoMap.count(locInfoPair.first) > 0;
auto locInfo = locInfoPair.first;
@@ -2812,23 +2816,15 @@ void PatchResourceCollect::clearUnusedOutput() {
locInfo.setStreamId(0);
foundInNextStage = (nextInLocInfoMap.find(locInfo) != nextInLocInfoMap.end());
}
- } else
+ } else {
foundInNextStage = (nextInLocInfoMap.find(locInfoPair.first) != nextInLocInfoMap.end());
+ }
if (!isOutputXfb && !foundInNextStage) {
- bool isActiveLoc = false;
- if (m_shaderStage == ShaderStageTessControl) {
- // NOTE: if the output is used as imported in TCS, it is marked as active.
- isActiveLoc = importOutputLocs.find(origLoc) != importOutputLocs.end();
- }
- if (isActiveLoc) {
- // The assigned location must not overlap with those used by inputs of next shader stage.
- auto &newLocationInfo = locInfoPair.second;
- newLocationInfo.setData(0);
- newLocationInfo.setLocation(availInMapLoc++);
- } else {
+ // NOTE: If the output is used as an imported one in TCS, mark it as active to avoid its removal.
+ const bool isActiveLoc = m_shaderStage == ShaderStage::TessControl && importOutputLocs.count(origLoc) > 0;
+ if (!isActiveLoc)
unusedLocInfos.push_back(locInfoPair.first);
- }
}
}
}
@@ -2837,7 +2833,7 @@ void PatchResourceCollect::clearUnusedOutput() {
outputLocInfoMap.erase(locInfo);
// Do per-patch input/output matching
- if (m_shaderStage == ShaderStageTessControl) {
+ if (m_shaderStage == ShaderStage::TessControl) {
auto &perPatchOutputLocMap = inOutUsage.perPatchOutputLocMap;
const auto &nextPerPatchInLocMap = nextResUsage->inOutUsage.perPatchInputLocMap;
unsigned availPerPatchInMapLoc = nextResUsage->inOutUsage.perPatchInputMapLocCount;
@@ -2859,7 +2855,7 @@ void PatchResourceCollect::clearUnusedOutput() {
}
// Do per-primitive input/output matching
- if (m_shaderStage == ShaderStageMesh) {
+ if (m_shaderStage == ShaderStage::Mesh) {
auto &perPrimitiveOutputLocMap = inOutUsage.perPrimitiveOutputLocMap;
const auto &nextPerPrimitiveInLocMap = nextResUsage->inOutUsage.perPrimitiveInputLocMap;
unsigned availPerPrimitiveInMapLoc = nextResUsage->inOutUsage.perPrimitiveInputMapLocCount;
@@ -2882,7 +2878,7 @@ void PatchResourceCollect::clearUnusedOutput() {
}
// Remove output of FS with invalid data format
- if (m_shaderStage == ShaderStageFragment) {
+ if (m_shaderStage == ShaderStage::Fragment) {
const bool generatingColorExportShader = m_pipelineState->isUnlinked() && !m_pipelineState->hasColorExportFormats();
for (auto locInfoMapIt = outputLocInfoMap.begin(); locInfoMapIt != outputLocInfoMap.end();) {
const unsigned origLoc = locInfoMapIt->first.getLocation();
@@ -2899,36 +2895,66 @@ void PatchResourceCollect::clearUnusedOutput() {
void PatchResourceCollect::updateOutputLocInfoMapWithUnpack() {
clearUnusedOutput();
+ const auto nextStage = m_pipelineState->getNextShaderStage(m_shaderStage);
auto &inOutUsage = m_pipelineState->getShaderResourceUsage(m_shaderStage)->inOutUsage;
- auto &outputLocInfoMap = inOutUsage.outputLocInfoMap;
- auto &perPatchOutputLocMap = inOutUsage.perPatchOutputLocMap;
- auto &perPrimitiveOutputLocMap = inOutUsage.perPrimitiveOutputLocMap;
- // Update the value of outputLocInfoMap
+ //
+ // Update per-vertex output location info
+ //
+ auto &outputLocInfoMap = inOutUsage.outputLocInfoMap;
if (!outputLocInfoMap.empty()) {
- unsigned nextAvailableLoc[MaxGsStreams] = {};
+ // If we don't have to keep the locations and the next stage is valid, try to get location map of the outputs from
+ // corresponding inputs of next stage.
+ const bool keepLocation = m_shaderStage == ShaderStage::Geometry && !canChangeOutputLocationsForGs();
+ if (!keepLocation && nextStage != ShaderStage::Invalid) {
+ auto &nextStageInputLocInfoMap = m_pipelineState->getShaderResourceUsage(nextStage)->inOutUsage.inputLocInfoMap;
+ for (auto &locInfoPair : outputLocInfoMap) {
+ const auto &locationInfo = locInfoPair.first;
+ auto &newLocationInfo = locInfoPair.second;
+
+ if (!newLocationInfo.isInvalid())
+ continue; // Skip mapped locations
+
+ // Map to the location of the input of the next stage if possible
+ if (nextStageInputLocInfoMap.count(locationInfo) > 0) {
+ auto newLocMappedTo = nextStageInputLocInfoMap[locationInfo].getLocation();
+
+ newLocationInfo.setData(0);
+ newLocationInfo.setLocation(newLocMappedTo);
+ newLocationInfo.setComponent(locationInfo.getComponent());
+
+ const unsigned streamId = m_shaderStage == ShaderStage::Geometry ? locationInfo.getStreamId() : 0;
+ newLocationInfo.setStreamId(streamId);
+
+ if (m_shaderStage == ShaderStage::Geometry)
+ inOutUsage.gs.outLocCount[streamId] = std::max(inOutUsage.gs.outLocCount[streamId], newLocMappedTo + 1);
+ }
+ }
+ }
+
+ // Collect all mapped locations before we do location mapping for those still unmapped
DenseMap<unsigned, unsigned> locMap[MaxGsStreams]; // Map from original location to new location
DenseSet<unsigned> occupiedLocs[MaxGsStreams]; // Collection of already-occupied locations in location mapping
- // Collect all mapped locations before we do location mapping for those unmapped
for (auto &locInfoPair : outputLocInfoMap) {
const auto &locationInfo = locInfoPair.first;
auto &newLocationInfo = locInfoPair.second;
- const unsigned streamId = m_shaderStage == ShaderStageGeometry ? locationInfo.getStreamId() : 0;
-
if (!newLocationInfo.isInvalid()) {
// Record mapped locations
const unsigned locAlreadyMapped = locationInfo.getLocation();
const unsigned newLocMappedTo = newLocationInfo.getLocation();
assert(newLocMappedTo != InvalidValue);
+ const unsigned streamId = m_shaderStage == ShaderStage::Geometry ? locationInfo.getStreamId() : 0;
locMap[streamId][locAlreadyMapped] = newLocMappedTo;
occupiedLocs[streamId].insert(newLocMappedTo);
}
}
- // Do location mapping
+ // Do location mapping for those still unmapped
+ unsigned nextAvailableLoc[MaxGsStreams] = {};
+
for (auto &locInfoPair : outputLocInfoMap) {
const auto &locationInfo = locInfoPair.first;
auto &newLocationInfo = locInfoPair.second;
@@ -2936,7 +2962,7 @@ void PatchResourceCollect::updateOutputLocInfoMapWithUnpack() {
if (!newLocationInfo.isInvalid())
continue; // Skip mapped locations
- const unsigned streamId = m_shaderStage == ShaderStageGeometry ? locationInfo.getStreamId() : 0;
+ const unsigned streamId = m_shaderStage == ShaderStage::Geometry ? locationInfo.getStreamId() : 0;
newLocationInfo.setData(0);
newLocationInfo.setComponent(locationInfo.getComponent());
@@ -2944,7 +2970,7 @@ void PatchResourceCollect::updateOutputLocInfoMapWithUnpack() {
const unsigned locToBeMapped = locationInfo.getLocation();
unsigned newLocMappedTo = InvalidValue;
- const bool keepLocation = m_shaderStage == ShaderStageGeometry && !canChangeOutputLocationsForGs();
+
if (keepLocation) {
// Keep location unchanged
newLocMappedTo = locToBeMapped;
@@ -2968,61 +2994,99 @@ void PatchResourceCollect::updateOutputLocInfoMapWithUnpack() {
assert(newLocMappedTo != InvalidValue);
newLocationInfo.setLocation(newLocMappedTo);
- if (m_shaderStage == ShaderStageGeometry)
+ if (m_shaderStage == ShaderStage::Geometry)
inOutUsage.gs.outLocCount[streamId] = std::max(inOutUsage.gs.outLocCount[streamId], newLocMappedTo + 1);
}
}
- // Update the value of perPatchOutputLocMap
+ //
+ // Update per-patch output location info
+ //
+ auto &perPatchOutputLocMap = inOutUsage.perPatchOutputLocMap;
if (!perPatchOutputLocMap.empty()) {
- assert(m_shaderStage == ShaderStageTessControl);
+ assert(m_shaderStage == ShaderStage::TessControl);
- unsigned nextAvailableLoc = 0;
- DenseSet<unsigned> occupiedLocs; // Collection of already-occupied locations in location mapping
+ // If the next stage is valid, try to get location map of the outputs from corresponding inputs of next stage.
+ if (nextStage != ShaderStage::Invalid) {
+ auto &nextStagePerPatchInputLocInfoMap =
+ m_pipelineState->getShaderResourceUsage(nextStage)->inOutUsage.perPatchInputLocMap;
+ for (auto &locPair : perPatchOutputLocMap) {
+ if (locPair.second != InvalidValue)
+ continue; // Skip mapped locations
- // Collect all mapped locations before we do location mapping for those unmapped
+ // Map to the location of the input of the next stage if possible
+ if (nextStagePerPatchInputLocInfoMap.count(locPair.first) > 0)
+ locPair.second = nextStagePerPatchInputLocInfoMap[locPair.first];
+ }
+ }
+
+ // Collect all mapped locations before we do location mapping for those still unmapped
+ DenseSet<unsigned> occupiedLocs; // Collection of already-occupied locations in location mapping
for (auto &locPair : perPatchOutputLocMap) {
if (locPair.second != InvalidValue)
occupiedLocs.insert(locPair.second); // Record mapped locations
}
- // Do location mapping
+ // Do location mapping for those still unmapped
+ unsigned nextAvailableLoc = 0;
for (auto &locPair : perPatchOutputLocMap) {
if (locPair.second != InvalidValue)
continue; // Skip mapped locations
+ // Map to new location
unsigned newLocMappedTo = InvalidValue;
do {
// Try to find a new location that has not been occupied
newLocMappedTo = nextAvailableLoc++;
} while (occupiedLocs.count(newLocMappedTo) > 0);
+
+ assert(newLocMappedTo != InvalidValue);
locPair.second = newLocMappedTo;
}
}
- // Update the value of perPrimitiveOutputLocMap
+ //
+ // Update per-primitive output location info
+ //
+ auto &perPrimitiveOutputLocMap = inOutUsage.perPrimitiveOutputLocMap;
if (!perPrimitiveOutputLocMap.empty()) {
- assert(m_shaderStage == ShaderStageMesh);
+ assert(m_shaderStage == ShaderStage::Mesh);
- unsigned nextAvailableLoc = 0;
- DenseSet<unsigned> occupiedLocs; // Collection of already-occupied locations in location mapping
+ // If the next stage is valid, try to get location map of the outputs from corresponding inputs of next stage.
+ if (nextStage != ShaderStage::Invalid) {
+ auto &nextStagePerPrimitiveInputLocMap =
+ m_pipelineState->getShaderResourceUsage(nextStage)->inOutUsage.perPrimitiveInputLocMap;
+ for (auto &locPair : perPrimitiveOutputLocMap) {
+ if (locPair.second != InvalidValue)
+ continue; // Skip mapped locations
+
+ // Map to the location of the input of the next stage if possible
+ if (nextStagePerPrimitiveInputLocMap.count(locPair.first) > 0)
+ locPair.second = nextStagePerPrimitiveInputLocMap[locPair.first];
+ }
+ }
// Collect all mapped locations before we do location mapping for those unmapped
+ DenseSet<unsigned> occupiedLocs; // Collection of already-occupied locations in location mapping
for (auto &locPair : perPrimitiveOutputLocMap) {
if (locPair.second != InvalidValue)
occupiedLocs.insert(locPair.second); // Record mapped locations
}
- // Do location mapping
+ // Do location mapping for those still unmapped
+ unsigned nextAvailableLoc = 0;
for (auto &locPair : perPrimitiveOutputLocMap) {
if (locPair.second != InvalidValue)
continue; // Skip mapped locations
+ // Map to new location
unsigned newLocMappedTo = InvalidValue;
do {
// Try to find a new location that has not been occupied
newLocMappedTo = nextAvailableLoc++;
} while (occupiedLocs.count(newLocMappedTo) > 0);
+
+ assert(newLocMappedTo != InvalidValue);
locPair.second = newLocMappedTo;
}
}
@@ -3039,7 +3103,7 @@ bool PatchResourceCollect::canChangeOutputLocationsForGs() {
return true;
if (m_pipelineState->getPalMetadata()->haveFsInputMappings())
return true;
- if (m_pipelineState->getNextShaderStage(ShaderStageGeometry) != ShaderStageInvalid)
+ if (m_pipelineState->getNextShaderStage(ShaderStage::Geometry) != ShaderStage::Invalid)
return true;
return false;
}
@@ -3054,9 +3118,9 @@ void PatchResourceCollect::updateInputLocInfoMapWithPack() {
if (m_inputCalls.empty())
return;
- const bool isTcs = m_shaderStage == ShaderStageTessControl;
- const bool isFs = m_shaderStage == ShaderStageFragment;
- const bool isGs = m_shaderStage == ShaderStageGeometry;
+ const bool isTcs = m_shaderStage == ShaderStage::TessControl;
+ const bool isFs = m_shaderStage == ShaderStage::Fragment;
+ const bool isGs = m_shaderStage == ShaderStage::Geometry;
assert(isTcs || isFs || isGs);
// The locations of TCS with dynamic indexing (locOffset/elemIdx) cannot be unpacked
@@ -3064,7 +3128,7 @@ void PatchResourceCollect::updateInputLocInfoMapWithPack() {
// LDS load/store copes with dword. For 8-bit/16-bit data type, we will extend them to 32-bit
bool partPipelineHasGs = m_pipelineState->isPartPipeline() && m_pipelineState->getPreRasterHasGs();
- bool isFsAndHasGs = (isFs && (m_pipelineState->hasShaderStage(ShaderStageGeometry) || partPipelineHasGs));
+ bool isFsAndHasGs = (isFs && (m_pipelineState->hasShaderStage(ShaderStage::Geometry) || partPipelineHasGs));
bool requireDword = isTcs || isGs || isFsAndHasGs;
// Create locationMap
m_locationInfoMapManager->createMap(m_inputCalls, m_shaderStage, requireDword);
@@ -3097,10 +3161,10 @@ void PatchResourceCollect::updateOutputLocInfoMapWithPack() {
if (m_outputCalls.empty())
return;
- assert(m_shaderStage == ShaderStageVertex || m_shaderStage == ShaderStageTessEval ||
- m_shaderStage == ShaderStageGeometry);
+ assert(m_shaderStage == ShaderStage::Vertex || m_shaderStage == ShaderStage::TessEval ||
+ m_shaderStage == ShaderStage::Geometry);
auto nextStage = m_pipelineState->getNextShaderStage(m_shaderStage);
- assert(nextStage != ShaderStageInvalid);
+ assert(nextStage != ShaderStage::Invalid);
auto &nextStageInputLocInfoMap = m_pipelineState->getShaderResourceUsage(nextStage)->inOutUsage.inputLocInfoMap;
// Remove unused outputs and update the output map
@@ -3117,7 +3181,7 @@ void PatchResourceCollect::updateOutputLocInfoMapWithPack() {
outputLocInfoMap = nextStageInputLocInfoMap;
} else {
// For {VS, TES, GS}-FS, the dead output is neither a XFB output or a corresponding FS' input.
- assert(nextStage == ShaderStageFragment);
+ assert(nextStage == ShaderStage::Fragment);
// Collect XFB locations
auto &xfbOutLocInfoMap = m_pipelineState->getShaderResourceUsage(m_shaderStage)->inOutUsage.locInfoXfbOutInfoMap;
@@ -3140,7 +3204,7 @@ void PatchResourceCollect::updateOutputLocInfoMapWithPack() {
const bool hasNoMappedInput = (nextStageInputLocInfoMap.find(origLocInfo) == nextStageInputLocInfoMap.end());
if (hasNoMappedInput) {
const unsigned streamId =
- m_shaderStage == ShaderStageGeometry ? cast<ConstantInt>(call->getOperand(2))->getZExtValue() : 0;
+ m_shaderStage == ShaderStage::Geometry ? cast<ConstantInt>(call->getOperand(2))->getZExtValue() : 0;
if (xfbOutputLocs[streamId].count(origLocation) == 0)
m_deadCalls.push_back(call);
@@ -3155,14 +3219,14 @@ void PatchResourceCollect::updateOutputLocInfoMapWithPack() {
InOutLocationInfo origLocInfo;
origLocInfo.setLocation(cast<ConstantInt>(call->getOperand(0))->getZExtValue());
origLocInfo.setComponent(cast<ConstantInt>(call->getOperand(1))->getZExtValue());
- if (m_shaderStage == ShaderStageGeometry)
+ if (m_shaderStage == ShaderStage::Geometry)
origLocInfo.setStreamId(cast<ConstantInt>(call->getOperand(2))->getZExtValue());
outLocInfos.push_back(origLocInfo);
}
m_locationInfoMapManager->createMap(outLocInfos, m_shaderStage);
const auto &calcOutLocInfoMap = m_locationInfoMapManager->getMap();
- if (m_shaderStage == ShaderStageGeometry) {
+ if (m_shaderStage == ShaderStage::Geometry) {
// NOTE: The output location info from next shader stage (FS) doesn't contain raster stream ID. We have to
// reconstruct it.
const auto rasterStream = m_pipelineState->getRasterizerState().rasterStream;
@@ -3192,7 +3256,7 @@ void PatchResourceCollect::updateOutputLocInfoMapWithPack() {
}
// update output count per stream for GS
- if (m_shaderStage == ShaderStageGeometry) {
+ if (m_shaderStage == ShaderStage::Geometry) {
for (auto &locInfoPair : outputLocInfoMap) {
auto &outLocCount = inOutUsage.gs.outLocCount[locInfoPair.first.getStreamId()];
outLocCount = std::max(outLocCount, locInfoPair.second.getLocation() + 1);
@@ -3349,13 +3413,13 @@ void PatchResourceCollect::scalarizeForInOutPacking(Module *module) {
Payload payload = {this, inputCalls};
static auto visitInput = [](Payload &payload, GenericLocationOp &input) {
- ShaderStage shaderStage = payload.self->m_pipelineShaders->getShaderStage(input.getFunction());
- if (payload.self->m_pipelineState->canPackInput(shaderStage)) {
+ auto shaderStage = payload.self->m_pipelineShaders->getShaderStage(input.getFunction());
+ if (payload.self->m_pipelineState->canPackInput(shaderStage.value())) {
// Collect input calls without dynamic indexing that need scalarize
const bool hasDynIndex = !isa<ConstantInt>(input.getLocOffset()) || !isa<ConstantInt>(input.getElemIdx());
if (hasDynIndex) {
// NOTE: Dynamic indexing (location offset or component) in FS is processed to be constant in lower pass.
- assert(shaderStage == ShaderStageTessControl);
+ assert(shaderStage == ShaderStage::TessControl);
// Conservatively disable all packing of the VS-TCS interface if dynamic indexing is detected.
payload.self->m_tcsInputHasDynamicIndexing = true;
@@ -3373,12 +3437,12 @@ void PatchResourceCollect::scalarizeForInOutPacking(Module *module) {
visitor.visit(payload, *module);
for (Function &func : *module) {
- if (func.getName().startswith(lgcName::OutputExportGeneric)) {
+ if (func.getName().starts_with(lgcName::OutputExportGeneric)) {
// This is a generic output. Find its uses in VS/TES/GS.
for (User *user : func.users()) {
auto call = cast<CallInst>(user);
- ShaderStage shaderStage = m_pipelineShaders->getShaderStage(call->getFunction());
- if (m_pipelineState->canPackOutput(shaderStage)) {
+ auto shaderStage = m_pipelineShaders->getShaderStage(call->getFunction());
+ if (m_pipelineState->canPackOutput(shaderStage.value())) {
// We have a use in VS/TES/GS. See if it needs scalarizing. The output value is always the final argument.
Type *valueTy = call->getArgOperand(call->arg_size() - 1)->getType();
if (isa<VectorType>(valueTy) || valueTy->getPrimitiveSizeInBits() == 64)
@@ -3391,8 +3455,8 @@ void PatchResourceCollect::scalarizeForInOutPacking(Module *module) {
for (GenericLocationOp *call : inputCalls) {
// Don't scalarize TCS inputs if dynamic indexing is used.
if (m_tcsInputHasDynamicIndexing) {
- ShaderStage shaderStage = m_pipelineShaders->getShaderStage(call->getFunction());
- if (shaderStage == ShaderStageTessControl)
+ auto shaderStage = m_pipelineShaders->getShaderStage(call->getFunction());
+ if (shaderStage == ShaderStage::TessControl)
continue;
}
scalarizeGenericInput(call);
@@ -3400,8 +3464,8 @@ void PatchResourceCollect::scalarizeForInOutPacking(Module *module) {
for (CallInst *call : outputCalls) {
// Don't scalarize VS outputs if dynamic indexing is used in TCS inputs.
if (m_tcsInputHasDynamicIndexing) {
- ShaderStage shaderStage = m_pipelineShaders->getShaderStage(call->getFunction());
- if (shaderStage == ShaderStageVertex)
+ auto shaderStage = m_pipelineShaders->getShaderStage(call->getFunction());
+ if (shaderStage == ShaderStage::Vertex)
continue;
}
scalarizeGenericOutput(call);
@@ -3590,7 +3654,7 @@ void PatchResourceCollect::scalarizeGenericOutput(CallInst *call) {
// =====================================================================================================================
// Clear non-specified output value in non-fragment shader stages
void PatchResourceCollect::clearUndefinedOutput() {
- if (m_shaderStage == ShaderStageFragment)
+ if (m_shaderStage == ShaderStage::Fragment)
return;
// NOTE: If a vector or all used channels in a location are not specified, we can safely drop it and remove the output
// export call
@@ -3605,12 +3669,12 @@ void PatchResourceCollect::clearUndefinedOutput() {
for (auto call : m_outputCalls) {
auto outputValue = call->getArgOperand(call->arg_size() - 1);
bool isUndefVal = isa<UndefValue>(outputValue) || isa<PoisonValue>(outputValue);
- unsigned index = (m_shaderStage == ShaderStageMesh || m_shaderStage == ShaderStageTessControl) ? 2 : 1;
+ unsigned index = (m_shaderStage == ShaderStage::Mesh || m_shaderStage == ShaderStage::TessControl) ? 2 : 1;
bool isDynElemIndexing = !isa<ConstantInt>(call->getArgOperand(index));
InOutLocationInfo locInfo;
locInfo.setLocation(cast<ConstantInt>(call->getArgOperand(0))->getZExtValue());
- if (m_shaderStage == ShaderStageGeometry)
+ if (m_shaderStage == ShaderStage::Geometry)
locInfo.setStreamId(cast<ConstantInt>(call->getArgOperand(2))->getZExtValue());
unsigned undefMask = 0;
@@ -3650,9 +3714,9 @@ void PatchResourceCollect::clearUndefinedOutput() {
for (auto call : candidateCalls) {
// For unlinked case, we should keep the location info map unchanged.
- if (m_pipelineState->getNextShaderStage(m_shaderStage) != ShaderStageInvalid) {
+ if (m_pipelineState->getNextShaderStage(m_shaderStage) != ShaderStage::Invalid) {
// Remove the output location info if it exists
- unsigned index = m_shaderStage == ShaderStageMesh ? 2 : 1;
+ unsigned index = m_shaderStage == ShaderStage::Mesh ? 2 : 1;
unsigned component = cast<ConstantInt>(call->getArgOperand(index))->getZExtValue();
auto outputValue = call->getArgOperand(call->arg_size() - 1);
if (outputValue->getType()->getScalarSizeInBits() == 64)
@@ -3662,7 +3726,7 @@ void PatchResourceCollect::clearUndefinedOutput() {
const unsigned location = locCandidate.first.getLocation();
outLocInfo.setLocation(location);
outLocInfo.setComponent(component);
- if (m_shaderStage == ShaderStageGeometry)
+ if (m_shaderStage == ShaderStage::Geometry)
outLocInfo.setStreamId(locCandidate.first.getStreamId());
auto &outLocInfoMap = m_resUsage->inOutUsage.outputLocInfoMap;
@@ -3697,7 +3761,7 @@ void PatchResourceCollect::clearUndefinedOutput() {
// @param call : Call to process
// @param shaderStage : Shader stage
// @param requireDword : Whether need extend 8-bit/16-bit data to dword
-void InOutLocationInfoMapManager::createMap(ArrayRef<GenericLocationOp *> calls, ShaderStage shaderStage,
+void InOutLocationInfoMapManager::createMap(ArrayRef<GenericLocationOp *> calls, ShaderStageEnum shaderStage,
bool requireDword) {
for (auto call : calls)
addSpan(call, shaderStage, requireDword);
@@ -3710,7 +3774,8 @@ void InOutLocationInfoMapManager::createMap(ArrayRef<GenericLocationOp *> calls,
//
// @param locInfos : location infos to process
// @param shaderStage : Shader stage
-void InOutLocationInfoMapManager::createMap(const std::vector<InOutLocationInfo> &locInfos, ShaderStage shaderStage) {
+void InOutLocationInfoMapManager::createMap(const std::vector<InOutLocationInfo> &locInfos,
+ ShaderStageEnum shaderStage) {
for (const auto &locInfo : locInfos) {
LocationSpan span{};
span.firstLocationInfo = locInfo;
@@ -3734,8 +3799,8 @@ void InOutLocationInfoMapManager::deserializeMap(ArrayRef<std::pair<unsigned, un
// @param call : Call to process
// @param shaderStage : Shader stage
// @param requireDword : Whether need extend to dword
-void InOutLocationInfoMapManager::addSpan(CallInst *call, ShaderStage shaderStage, bool requireDword) {
- const bool isFs = shaderStage == ShaderStageFragment;
+void InOutLocationInfoMapManager::addSpan(CallInst *call, ShaderStageEnum shaderStage, bool requireDword) {
+ const bool isFs = shaderStage == ShaderStage::Fragment;
unsigned interpMode = InOutInfo::InterpModeCustom;
bool isInterpolated = false;
unsigned location = InvalidValue;
@@ -3755,15 +3820,15 @@ void InOutLocationInfoMapManager::addSpan(CallInst *call, ShaderStage shaderStag
location = cast<ConstantInt>(call->getOperand(0))->getZExtValue();
unsigned compIdxArgIdx = 1;
- if (shaderStage == ShaderStageTessControl) {
+ if (shaderStage == ShaderStage::TessControl) {
location += cast<ConstantInt>(call->getOperand(1))->getZExtValue();
compIdxArgIdx = 2;
}
elemIdx = cast<ConstantInt>(call->getOperand(compIdxArgIdx))->getZExtValue();
- if (shaderStage == ShaderStageGeometry &&
- call->getCalledFunction()->getName().startswith(lgcName::OutputExportGeneric)) {
+ if (shaderStage == ShaderStage::Geometry &&
+ call->getCalledFunction()->getName().starts_with(lgcName::OutputExportGeneric)) {
// Set streamId and output bitWidth of a GS output export for copy shader use
streamId = cast<ConstantInt>(call->getOperand(2))->getZExtValue();
bitWidth = call->getOperand(3)->getType()->getScalarSizeInBits();
@@ -3797,7 +3862,7 @@ void InOutLocationInfoMapManager::addSpan(CallInst *call, ShaderStage shaderStag
// Build the map between original InOutLocationInfo and packed InOutLocationInfo based on sorted location spans
//
// @param shaderStage : The shader stage to determine whether to check compatibility
-void InOutLocationInfoMapManager::buildMap(ShaderStage shaderStage) {
+void InOutLocationInfoMapManager::buildMap(ShaderStageEnum shaderStage) {
m_locationInfoMap.clear();
if (m_locationSpans.empty())
return;
@@ -3806,7 +3871,7 @@ void InOutLocationInfoMapManager::buildMap(ShaderStage shaderStage) {
unsigned consecutiveLocation = 0;
unsigned compIdx = 0;
bool isHighHalf = false;
- const bool isGs = shaderStage == ShaderStageGeometry;
+ const bool isGs = shaderStage == ShaderStage::Geometry;
for (auto spanIt = m_locationSpans.begin(); spanIt != m_locationSpans.end(); ++spanIt) {
if (spanIt != m_locationSpans.begin()) {
diff --git a/lgc/patch/PatchSetupTargetFeatures.cpp b/lgc/patch/PatchSetupTargetFeatures.cpp
index 0d2ec805bc..e72e4ce984 100644
--- a/lgc/patch/PatchSetupTargetFeatures.cpp
+++ b/lgc/patch/PatchSetupTargetFeatures.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -86,15 +86,15 @@ void PatchSetupTargetFeatures::setupTargetFeatures(Module *module) {
std::string targetFeatures(globalFeatures);
AttrBuilder builder(module->getContext());
- ShaderStage shaderStage = lgc::getShaderStage(&*func);
+ auto shaderStage = lgc::getShaderStage(&*func);
- if (shaderStage == ShaderStage::ShaderStageInvalid) {
+ if (!shaderStage) {
errs() << "Invalid shader stage for function " << func->getName() << "\n";
report_fatal_error("Got invalid shader stage when setting up features for function");
}
if (isShaderEntryPoint(&*func)) {
- bool useSiScheduler = m_pipelineState->getShaderOptions(shaderStage).useSiScheduler;
+ bool useSiScheduler = m_pipelineState->getShaderOptions(shaderStage.value()).useSiScheduler;
if (useSiScheduler) {
// It was found that enabling both SIScheduler and SIFormClauses was bad on one particular
// game. So we disable the latter here. That only affects XNACK targets.
@@ -143,7 +143,7 @@ void PatchSetupTargetFeatures::setupTargetFeatures(Module *module) {
if (func->hasFnAttribute("target-features"))
targetFeatures += func->getFnAttribute("target-features").getValueAsString();
- if (m_pipelineState->getShaderWgpMode(shaderStage))
+ if (m_pipelineState->getShaderWgpMode(shaderStage.value()))
targetFeatures += ",-cumode";
else
targetFeatures += ",+cumode";
@@ -166,8 +166,8 @@ void PatchSetupTargetFeatures::setupTargetFeatures(Module *module) {
// In the backend, f32 denormals are handled by default, so request denormal flushing behavior.
builder.addAttribute("denormal-fp-math-f32", "preserve-sign");
- if (shaderStage != ShaderStageCopyShader) {
- const auto &shaderMode = m_pipelineState->getShaderModes()->getCommonShaderMode(shaderStage);
+ if (shaderStage != ShaderStage::CopyShader) {
+ const auto &shaderMode = m_pipelineState->getShaderModes()->getCommonShaderMode(shaderStage.value());
if (shaderMode.fp16DenormMode == FpDenormMode::FlushNone || shaderMode.fp16DenormMode == FpDenormMode::FlushIn ||
shaderMode.fp64DenormMode == FpDenormMode::FlushNone || shaderMode.fp64DenormMode == FpDenormMode::FlushIn) {
builder.addAttribute("denormal-fp-math", "ieee");
diff --git a/lgc/patch/PatchWorkarounds.cpp b/lgc/patch/PatchWorkarounds.cpp
index 5c4ebb049b..b070bf181d 100644
--- a/lgc/patch/PatchWorkarounds.cpp
+++ b/lgc/patch/PatchWorkarounds.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -103,7 +103,7 @@ void PatchWorkarounds::applyImageDescWorkaround(void) {
SmallVector<CallInst *, 8> useWorkListImage;
for (const Function &func : m_module->getFunctionList()) {
- bool isImage = func.getName().startswith("llvm.amdgcn.image");
+ bool isImage = func.getName().starts_with("llvm.amdgcn.image");
#if !defined(LLVM_HAVE_BRANCH_AMD_GFX)
bool isLastUse = false;
#else
@@ -166,7 +166,7 @@ void PatchWorkarounds::processImageDescWorkaround(CallInst &callInst, bool isLas
bool requiresWorkaround = false;
for (auto &use : callInst.uses()) {
if (auto *useCallInst = dyn_cast<CallInst>(use.getUser())) {
- if (useCallInst->getCalledFunction()->getName().startswith("llvm.amdgcn.image")) {
+ if (useCallInst->getCalledFunction()->getName().starts_with("llvm.amdgcn.image")) {
// We need to process this intrinsic
requiresWorkaround = true;
break;
diff --git a/lgc/patch/RegisterMetadataBuilder.cpp b/lgc/patch/RegisterMetadataBuilder.cpp
index 4652b335e4..f8b6558783 100644
--- a/lgc/patch/RegisterMetadataBuilder.cpp
+++ b/lgc/patch/RegisterMetadataBuilder.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -64,28 +64,28 @@ void RegisterMetadataBuilder::buildPalMetadata() {
if (m_hasTask || m_hasMesh) {
assert(m_pipelineState->getTargetInfo().getGfxIpVersion() >= GfxIpVersion({10, 3}));
if (m_hasMesh) {
- apiHwShaderMap[ShaderStageMesh] = Util::Abi::HwShaderGs;
+ apiHwShaderMap[ShaderStage::Mesh] = Util::Abi::HwShaderGs;
pipelineType = Util::Abi::PipelineType::Mesh;
}
if (m_hasTask) {
- apiHwShaderMap[ShaderStageTask] = Util::Abi::HwShaderCs;
+ apiHwShaderMap[ShaderStage::Task] = Util::Abi::HwShaderCs;
pipelineType = Util::Abi::PipelineType::TaskMesh;
}
} else {
if (m_hasGs) {
- auto preGsStage = m_pipelineState->getPrevShaderStage(ShaderStageGeometry);
- if (preGsStage != ShaderStageInvalid)
+ auto preGsStage = m_pipelineState->getPrevShaderStage(ShaderStage::Geometry);
+ if (preGsStage != ShaderStage::Invalid)
apiHwShaderMap[preGsStage] = Util::Abi::HwShaderGs;
}
if (m_hasTcs) {
- apiHwShaderMap[ShaderStageTessControl] = Util::Abi::HwShaderHs;
+ apiHwShaderMap[ShaderStage::TessControl] = Util::Abi::HwShaderHs;
if (m_hasVs)
- apiHwShaderMap[ShaderStageVertex] = Util::Abi::HwShaderHs;
+ apiHwShaderMap[ShaderStage::Vertex] = Util::Abi::HwShaderHs;
}
- if (lastVertexProcessingStage != ShaderStageInvalid) {
- if (lastVertexProcessingStage == ShaderStageCopyShader)
- lastVertexProcessingStage = ShaderStageGeometry;
+ if (lastVertexProcessingStage != ShaderStage::Invalid) {
+ if (lastVertexProcessingStage == ShaderStage::CopyShader)
+ lastVertexProcessingStage = ShaderStage::Geometry;
if (m_isNggMode) {
apiHwShaderMap[lastVertexProcessingStage] = Util::Abi::HwShaderGs;
pipelineType = hasTs ? Util::Abi::PipelineType::NggTess : Util::Abi::PipelineType::Ngg;
@@ -105,21 +105,21 @@ void RegisterMetadataBuilder::buildPalMetadata() {
}
}
}
- if (m_pipelineState->hasShaderStage(ShaderStageFragment))
- apiHwShaderMap[ShaderStageFragment] = Util::Abi::HwShaderPs;
+ if (m_pipelineState->hasShaderStage(ShaderStage::Fragment))
+ apiHwShaderMap[ShaderStage::Fragment] = Util::Abi::HwShaderPs;
// Set the mapping between api shader stage and hardware stage
unsigned hwStageMask = 0;
for (const auto &entry : apiHwShaderMap) {
- const auto apiStage = static_cast<ShaderStage>(entry.first);
+ const auto apiStage = static_cast<ShaderStageEnum>(entry.first);
hwStageMask |= entry.second;
addApiHwShaderMapping(apiStage, entry.second);
}
if (hwStageMask & Util::Abi::HwShaderHs) {
buildLsHsRegisters();
- ShaderStage apiStage1 = m_hasVs ? ShaderStageVertex : ShaderStageInvalid;
- ShaderStage apiStage2 = m_hasTcs ? ShaderStageTessControl : ShaderStageInvalid;
+ ShaderStageEnum apiStage1 = m_hasVs ? ShaderStage::Vertex : ShaderStage::Invalid;
+ ShaderStageEnum apiStage2 = m_hasTcs ? ShaderStage::TessControl : ShaderStage::Invalid;
buildShaderExecutionRegisters(Util::Abi::HardwareStage::Hs, apiStage1, apiStage2);
}
if (hwStageMask & Util::Abi::HwShaderGs) {
@@ -128,39 +128,39 @@ void RegisterMetadataBuilder::buildPalMetadata() {
else
buildEsGsRegisters();
- ShaderStage apiStage1 = ShaderStageInvalid;
- ShaderStage apiStage2 = ShaderStageInvalid;
+ ShaderStageEnum apiStage1 = ShaderStage::Invalid;
+ ShaderStageEnum apiStage2 = ShaderStage::Invalid;
if (m_hasMesh) {
- apiStage1 = ShaderStageMesh;
+ apiStage1 = ShaderStage::Mesh;
} else if (m_hasGs) {
- apiStage2 = ShaderStageGeometry;
+ apiStage2 = ShaderStage::Geometry;
if (m_hasTes)
- apiStage1 = ShaderStageTessEval;
+ apiStage1 = ShaderStage::TessEval;
else if (m_hasVs)
- apiStage1 = ShaderStageVertex;
+ apiStage1 = ShaderStage::Vertex;
} else if (m_hasTes) {
- apiStage1 = ShaderStageTessEval;
+ apiStage1 = ShaderStage::TessEval;
} else {
- apiStage1 = ShaderStageVertex;
+ apiStage1 = ShaderStage::Vertex;
}
buildShaderExecutionRegisters(Util::Abi::HardwareStage::Gs, apiStage1, apiStage2);
}
if (!m_isNggMode && (hwStageMask & Util::Abi::HwShaderVs)) {
buildHwVsRegisters();
- ShaderStage apiStage1 = ShaderStageVertex;
- if (m_pipelineState->hasShaderStage(ShaderStageCopyShader))
- apiStage1 = ShaderStageCopyShader;
+ ShaderStageEnum apiStage1 = ShaderStage::Vertex;
+ if (m_pipelineState->hasShaderStage(ShaderStage::CopyShader))
+ apiStage1 = ShaderStage::CopyShader;
else if (m_hasTes)
- apiStage1 = ShaderStageTessEval;
- buildShaderExecutionRegisters(Util::Abi::HardwareStage::Vs, apiStage1, ShaderStageInvalid);
+ apiStage1 = ShaderStage::TessEval;
+ buildShaderExecutionRegisters(Util::Abi::HardwareStage::Vs, apiStage1, ShaderStage::Invalid);
}
if (hwStageMask & Util::Abi::HwShaderPs) {
buildPsRegisters();
- buildShaderExecutionRegisters(Util::Abi::HardwareStage::Ps, ShaderStageFragment, ShaderStageInvalid);
+ buildShaderExecutionRegisters(Util::Abi::HardwareStage::Ps, ShaderStage::Fragment, ShaderStage::Invalid);
}
if (hwStageMask & Util::Abi::HwShaderCs) {
- buildCsRegisters(ShaderStageTask);
- buildShaderExecutionRegisters(Util::Abi::HardwareStage::Cs, ShaderStageTask, ShaderStageInvalid);
+ buildCsRegisters(ShaderStage::Task);
+ buildShaderExecutionRegisters(Util::Abi::HardwareStage::Cs, ShaderStage::Task, ShaderStage::Invalid);
}
// Set other registers if it is not a single PS or CS
@@ -173,7 +173,7 @@ void RegisterMetadataBuilder::buildPalMetadata() {
if (hwStageMask & (Util::Abi::HwShaderGs | Util::Abi::HwShaderVs))
buildPaSpecificRegisters();
- if (lastVertexProcessingStage != ShaderStageInvalid && m_pipelineState->isUnlinked()) {
+ if (lastVertexProcessingStage != ShaderStage::Invalid && m_pipelineState->isUnlinked()) {
// Fill ".preraster_output_semantic"
auto resUsage = m_pipelineState->getShaderResourceUsage(lastVertexProcessingStage);
auto &outputLocInfoMap = resUsage->inOutUsage.outputLocInfoMap;
@@ -207,10 +207,10 @@ void RegisterMetadataBuilder::buildPalMetadata() {
}
} else {
- addApiHwShaderMapping(ShaderStageCompute, Util::Abi::HwShaderCs);
+ addApiHwShaderMapping(ShaderStage::Compute, Util::Abi::HwShaderCs);
setPipelineType(Util::Abi::PipelineType::Cs);
- buildCsRegisters(ShaderStageCompute);
- buildShaderExecutionRegisters(Util::Abi::HardwareStage::Cs, ShaderStageCompute, ShaderStageInvalid);
+ buildCsRegisters(ShaderStage::Compute);
+ buildShaderExecutionRegisters(Util::Abi::HardwareStage::Cs, ShaderStage::Compute, ShaderStage::Invalid);
}
}
@@ -226,7 +226,7 @@ void RegisterMetadataBuilder::buildLsHsRegisters() {
getGraphicsRegNode()[Util::Abi::GraphicsRegisterMetadataKey::VgtHosMaxTessLevel] = maxTessFactor;
// VGT_LS_HS_CONFIG
- const auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl)->inOutUsage.tcs.calcFactor;
+ const auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl)->inOutUsage.tcs.calcFactor;
auto vgtLsHsConfig = getGraphicsRegNode()[Util::Abi::GraphicsRegisterMetadataKey::VgtLsHsConfig].getMap(true);
vgtLsHsConfig[Util::Abi::VgtLsHsConfigMetadataKey::NumPatches] = calcFactor.patchCountPerThreadGroup;
vgtLsHsConfig[Util::Abi::VgtLsHsConfigMetadataKey::HsNumInputCp] = m_pipelineState->getNumPatchControlPoints();
@@ -237,7 +237,7 @@ void RegisterMetadataBuilder::buildLsHsRegisters() {
setVgtTfParam();
// LS_VGPR_COMP_CNT in SPI_SHADER_PGM_RSRC1_HS
- const auto &vsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageVertex)->builtInUsage.vs;
+ const auto &vsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Vertex)->builtInUsage.vs;
unsigned lsVgprCompCnt = 0;
if (m_gfxIp.major <= 11) {
if (vsBuiltInUsage.instanceIndex)
@@ -265,13 +265,13 @@ void RegisterMetadataBuilder::buildLsHsRegisters() {
// =====================================================================================================================
// Builds register configuration for hardware export-geometry merged shader.
void RegisterMetadataBuilder::buildEsGsRegisters() {
- const auto vsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageVertex);
+ const auto vsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Vertex);
const auto &vsBuiltInUsage = vsResUsage->builtInUsage.vs;
- const auto gsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry);
+ const auto gsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry);
const auto &gsBuiltInUsage = gsResUsage->builtInUsage.gs;
const auto &gsInOutUsage = gsResUsage->inOutUsage;
const auto &calcFactor = gsInOutUsage.gs.calcFactor;
- const auto tesResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessEval);
+ const auto tesResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessEval);
const auto &tesBuiltInUsage = tesResUsage->builtInUsage.tes;
const bool hasTs = m_hasTcs || m_hasTes;
@@ -408,16 +408,16 @@ void RegisterMetadataBuilder::buildEsGsRegisters() {
// Builds register configuration for hardware primitive shader.
void RegisterMetadataBuilder::buildPrimShaderRegisters() {
assert(m_gfxIp.major >= 10 || (m_hasMesh && m_gfxIp >= GfxIpVersion({10, 3})));
- const auto vsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageVertex);
+ const auto vsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Vertex);
const auto &vsBuiltInUsage = vsResUsage->builtInUsage.vs;
- const auto tesResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessEval);
+ const auto tesResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessEval);
const auto &tesBuiltInUsage = tesResUsage->builtInUsage.tes;
- const auto gsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry);
+ const auto gsResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry);
const auto &gsBuiltInUsage = gsResUsage->builtInUsage.gs;
const auto &geometryMode = m_pipelineState->getShaderModes()->getGeometryShaderMode();
const auto &gsInOutUsage = gsResUsage->inOutUsage;
const auto &calcFactor = gsInOutUsage.gs.calcFactor;
- const auto meshResUsage = m_pipelineState->getShaderResourceUsage(ShaderStageMesh);
+ const auto meshResUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Mesh);
const auto &meshBuiltInUsage = meshResUsage->builtInUsage.mesh;
const auto &meshMode = m_pipelineState->getShaderModes()->getMeshShaderMode();
const bool hasTs = m_hasTcs || m_hasTes;
@@ -575,7 +575,7 @@ void RegisterMetadataBuilder::buildPrimShaderRegisters() {
bool meshLinearDispatchFromTask = false;
if (m_hasTask) {
meshLinearDispatchFromTask =
- m_pipelineState->getShaderResourceUsage(ShaderStageTask)->builtInUsage.task.meshLinearDispatch;
+ m_pipelineState->getShaderResourceUsage(ShaderStage::Task)->builtInUsage.task.meshLinearDispatch;
}
getGraphicsRegNode()[Util::Abi::GraphicsRegisterMetadataKey::MeshLinearDispatchFromTask] =
meshLinearDispatchFromTask;
@@ -677,13 +677,13 @@ void RegisterMetadataBuilder::buildPrimShaderRegisters() {
// =====================================================================================================================
// Builds register configuration for hardware vertex shader.
void RegisterMetadataBuilder::buildHwVsRegisters() {
- assert(m_hasVs || m_hasTes || m_pipelineState->hasShaderStage(ShaderStageCopyShader));
+ assert(m_hasVs || m_hasTes || m_pipelineState->hasShaderStage(ShaderStage::CopyShader));
assert(m_gfxIp.major <= 10);
- ShaderStage shaderStage = ShaderStageVertex;
- if (m_pipelineState->hasShaderStage(ShaderStageCopyShader))
- shaderStage = ShaderStageCopyShader;
+ ShaderStageEnum shaderStage = ShaderStage::Vertex;
+ if (m_pipelineState->hasShaderStage(ShaderStage::CopyShader))
+ shaderStage = ShaderStage::CopyShader;
else if (m_hasTes)
- shaderStage = ShaderStageTessEval;
+ shaderStage = ShaderStage::TessEval;
const auto resUsage = m_pipelineState->getShaderResourceUsage(shaderStage);
const auto &builtInUsage = resUsage->builtInUsage;
@@ -699,7 +699,7 @@ void RegisterMetadataBuilder::buildHwVsRegisters() {
vgtStrmoutConfig[Util::Abi::VgtStrmoutConfigMetadataKey::Streamout_1En] = enablePrimStats || streamXfbBuffers[1] > 0;
vgtStrmoutConfig[Util::Abi::VgtStrmoutConfigMetadataKey::Streamout_2En] = enablePrimStats || streamXfbBuffers[2] > 0;
vgtStrmoutConfig[Util::Abi::VgtStrmoutConfigMetadataKey::Streamout_3En] = enablePrimStats || streamXfbBuffers[3] > 0;
- if (shaderStage == ShaderStageCopyShader)
+ if (shaderStage == ShaderStage::CopyShader)
vgtStrmoutConfig[Util::Abi::VgtStrmoutConfigMetadataKey::RastStream] =
m_pipelineState->getRasterizerState().rasterStream;
@@ -728,12 +728,12 @@ void RegisterMetadataBuilder::buildHwVsRegisters() {
vgtStrmoutBufferConfig[Util::Abi::VgtStrmoutBufferConfigMetadataKey::Stream_3BufferEn] = streamXfbBuffers[3];
// VGPR_COMP_CNT
- if (shaderStage == ShaderStageVertex) {
+ if (shaderStage == ShaderStage::Vertex) {
if (builtInUsage.vs.instanceIndex)
getGraphicsRegNode()[Util::Abi::GraphicsRegisterMetadataKey::VsVgprCompCnt] = 3; // 3: Enable instance ID
else if (builtInUsage.vs.primitiveId)
getGraphicsRegNode()[Util::Abi::GraphicsRegisterMetadataKey::VsVgprCompCnt] = 2;
- } else if (shaderStage == ShaderStageTessEval) {
+ } else if (shaderStage == ShaderStage::TessEval) {
if (builtInUsage.tes.primitiveId)
getGraphicsRegNode()[Util::Abi::GraphicsRegisterMetadataKey::VsVgprCompCnt] = 3; // 3: Enable primitive ID
else
@@ -746,7 +746,7 @@ void RegisterMetadataBuilder::buildHwVsRegisters() {
// =====================================================================================================================
// Builds register configuration for hardware pixel shader.
void RegisterMetadataBuilder::buildPsRegisters() {
- ShaderStage shaderStage = ShaderStageFragment;
+ ShaderStageEnum shaderStage = ShaderStage::Fragment;
const auto &options = m_pipelineState->getOptions();
const auto &shaderOptions = m_pipelineState->getShaderOptions(shaderStage);
const auto &fragmentMode = m_pipelineState->getShaderModes()->getFragmentShaderMode();
@@ -867,7 +867,7 @@ void RegisterMetadataBuilder::buildPsRegisters() {
// PRIM_EXPORT_COUNT. When VS_EXPORT_COUNT = 0, HW assumes there is still a vertex attribute exported even
// though this is not what we want. Hence, we should reserve param0 as a dummy vertex attribute and all
// primitive attributes are moved after it.
- bool hasNoVertexAttrib = m_pipelineState->getShaderResourceUsage(ShaderStageMesh)->inOutUsage.expCount == 0;
+ bool hasNoVertexAttrib = m_pipelineState->getShaderResourceUsage(ShaderStage::Mesh)->inOutUsage.expCount == 0;
if (hasNoVertexAttrib)
++spiPsInputCntlInfo.offset;
spiPsInputCntlInfo.primAttr = true;
@@ -975,9 +975,9 @@ void RegisterMetadataBuilder::buildPsRegisters() {
// =====================================================================================================================
// Builds register configuration for compute/task shader.
-void RegisterMetadataBuilder::buildCsRegisters(ShaderStage shaderStage) {
- assert(shaderStage == ShaderStageCompute || shaderStage == ShaderStageTask);
- if (shaderStage == ShaderStageCompute) {
+void RegisterMetadataBuilder::buildCsRegisters(ShaderStageEnum shaderStage) {
+ assert(shaderStage == ShaderStage::Compute || shaderStage == ShaderStage::Task);
+ if (shaderStage == ShaderStage::Compute) {
Function *entryFunc = nullptr;
for (Function &func : *m_module) {
// Only entrypoint compute shader may have the function attribute for workgroup id optimization.
@@ -1003,7 +1003,7 @@ void RegisterMetadataBuilder::buildCsRegisters(ShaderStage shaderStage) {
const auto &computeMode = m_pipelineState->getShaderModes()->getComputeShaderMode();
unsigned workgroupSizes[3] = {};
- if (shaderStage == ShaderStageCompute) {
+ if (shaderStage == ShaderStage::Compute) {
const auto &builtInUsage = resUsage->builtInUsage.cs;
if (builtInUsage.foldWorkgroupXY) {
workgroupSizes[0] = computeMode.workgroupSizeX * computeMode.workgroupSizeY;
@@ -1015,7 +1015,7 @@ void RegisterMetadataBuilder::buildCsRegisters(ShaderStage shaderStage) {
workgroupSizes[2] = computeMode.workgroupSizeZ;
}
} else {
- assert(shaderStage == ShaderStageTask);
+ assert(shaderStage == ShaderStage::Task);
workgroupSizes[0] = computeMode.workgroupSizeX;
workgroupSizes[1] = computeMode.workgroupSizeY;
workgroupSizes[2] = computeMode.workgroupSizeZ;
@@ -1038,11 +1038,11 @@ void RegisterMetadataBuilder::buildCsRegisters(ShaderStage shaderStage) {
// @param hwStage: The hardware shader stage
// @param apiStage1: The first api shader stage
// @param apiStage2: The second api shader stage
-void RegisterMetadataBuilder::buildShaderExecutionRegisters(Util::Abi::HardwareStage hwStage, ShaderStage apiStage1,
- ShaderStage apiStage2) {
+void RegisterMetadataBuilder::buildShaderExecutionRegisters(Util::Abi::HardwareStage hwStage, ShaderStageEnum apiStage1,
+ ShaderStageEnum apiStage2) {
// Set hardware stage metadata
auto hwShaderNode = getHwShaderNode(hwStage);
- ShaderStage apiStage = apiStage2 != ShaderStageInvalid ? apiStage2 : apiStage1;
+ ShaderStageEnum apiStage = apiStage2 != ShaderStage::Invalid ? apiStage2 : apiStage1;
if (m_isNggMode || m_gfxIp.major >= 10) {
const unsigned waveSize = m_pipelineState->getShaderWaveSize(apiStage);
@@ -1050,9 +1050,9 @@ void RegisterMetadataBuilder::buildShaderExecutionRegisters(Util::Abi::HardwareS
}
unsigned checksum = 0;
- if (apiStage1 != ShaderStageInvalid && apiStage1 != ShaderStageCopyShader)
+ if (apiStage1 != ShaderStage::Invalid && apiStage1 != ShaderStage::CopyShader)
checksum = setShaderHash(apiStage1);
- if (apiStage2 != ShaderStageInvalid)
+ if (apiStage2 != ShaderStage::Invalid)
checksum ^= setShaderHash(apiStage2);
if (m_pipelineState->getTargetInfo().getGpuProperty().supportShaderPowerProfiling)
hwShaderNode[Util::Abi::HardwareStageMetadataKey::ChecksumValue] = checksum;
@@ -1062,15 +1062,15 @@ void RegisterMetadataBuilder::buildShaderExecutionRegisters(Util::Abi::HardwareS
unsigned userDataCount = 0;
unsigned sgprLimits = 0;
unsigned vgprLimits = 0;
- if (apiStage1 == ShaderStageCopyShader) {
+ if (apiStage1 == ShaderStage::CopyShader) {
userDataCount = lgc::CopyShaderUserSgprCount;
sgprLimits = m_pipelineState->getTargetInfo().getGpuProperty().maxSgprsAvailable;
vgprLimits = m_pipelineState->getTargetInfo().getGpuProperty().maxVgprsAvailable;
} else {
userDataCount = 0;
- if (apiStage1 != ShaderStageInvalid)
+ if (apiStage1 != ShaderStage::Invalid)
userDataCount = m_pipelineState->getShaderInterfaceData(apiStage1)->userDataCount;
- if (apiStage2 != ShaderStageInvalid) {
+ if (apiStage2 != ShaderStage::Invalid) {
userDataCount = std::max(userDataCount, m_pipelineState->getShaderInterfaceData(apiStage2)->userDataCount);
}
@@ -1087,9 +1087,9 @@ void RegisterMetadataBuilder::buildShaderExecutionRegisters(Util::Abi::HardwareS
hwShaderNode[Util::Abi::HardwareStageMetadataKey::MemOrdered] = true;
if (hwStage == Util::Abi::HardwareStage::Hs || hwStage == Util::Abi::HardwareStage::Gs) {
bool wgpMode = false;
- if (apiStage1 != ShaderStageInvalid)
+ if (apiStage1 != ShaderStage::Invalid)
wgpMode = m_pipelineState->getShaderWgpMode(apiStage1);
- if (apiStage2 != ShaderStageInvalid)
+ if (apiStage2 != ShaderStage::Invalid)
wgpMode = wgpMode || m_pipelineState->getShaderWgpMode(apiStage2);
hwShaderNode[Util::Abi::HardwareStageMetadataKey::WgpMode] = wgpMode;
}
@@ -1100,9 +1100,9 @@ void RegisterMetadataBuilder::buildShaderExecutionRegisters(Util::Abi::HardwareS
if (m_gfxIp.major >= 11 && hwStage != Util::Abi::HardwareStage::Vs) {
bool useImageOp = false;
- if (apiStage1 != ShaderStageInvalid)
+ if (apiStage1 != ShaderStage::Invalid)
useImageOp = m_pipelineState->getShaderResourceUsage(apiStage1)->useImageOp;
- if (apiStage2 != ShaderStageInvalid)
+ if (apiStage2 != ShaderStage::Invalid)
useImageOp |= m_pipelineState->getShaderResourceUsage(apiStage2)->useImageOp;
hwShaderNode[Util::Abi::HardwareStageMetadataKey::ImageOp] = useImageOp;
}
@@ -1122,10 +1122,10 @@ void RegisterMetadataBuilder::buildShaderExecutionRegisters(Util::Abi::HardwareS
// =====================================================================================================================
// Build PA-specific (primitive assembler) registers.
void RegisterMetadataBuilder::buildPaSpecificRegisters() {
- const bool hasTs =
- m_pipelineState->hasShaderStage(ShaderStageTessControl) || m_pipelineState->hasShaderStage(ShaderStageTessEval);
+ const bool hasTs = m_pipelineState->hasShaderStage(ShaderStage::TessControl) ||
+ m_pipelineState->hasShaderStage(ShaderStage::TessEval);
const bool meshPipeline =
- m_pipelineState->hasShaderStage(ShaderStageTask) || m_pipelineState->hasShaderStage(ShaderStageMesh);
+ m_pipelineState->hasShaderStage(ShaderStage::Task) || m_pipelineState->hasShaderStage(ShaderStage::Mesh);
// VGT_PRIMITIVEID_EN
// Stage-specific processing
@@ -1144,7 +1144,7 @@ void RegisterMetadataBuilder::buildPaSpecificRegisters() {
// Mesh pipeline
assert(m_gfxIp >= GfxIpVersion({10, 3})); // Must be GFX10.3+
- const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageMesh);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Mesh);
const auto &builtInUsage = resUsage->builtInUsage.mesh;
usePointSize = builtInUsage.pointSize;
@@ -1160,7 +1160,7 @@ void RegisterMetadataBuilder::buildPaSpecificRegisters() {
bool usePrimitiveId = false;
if (m_hasGs) {
- const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry);
const auto &builtInUsage = resUsage->builtInUsage.gs;
usePointSize = builtInUsage.pointSize;
@@ -1175,14 +1175,14 @@ void RegisterMetadataBuilder::buildPaSpecificRegisters() {
// NOTE: For ES-GS merged shader, the actual use of primitive ID should take both ES and GS into consideration.
if (hasTs) {
- const auto &tesBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessEval)->builtInUsage.tes;
+ const auto &tesBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessEval)->builtInUsage.tes;
usePrimitiveId = usePrimitiveId || tesBuiltInUsage.primitiveId;
} else {
- const auto &vsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageVertex)->builtInUsage.vs;
+ const auto &vsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Vertex)->builtInUsage.vs;
usePrimitiveId = usePrimitiveId || vsBuiltInUsage.primitiveId;
}
} else if (hasTs) {
- const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessEval);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessEval);
const auto &builtInUsage = resUsage->builtInUsage.tes;
usePointSize = builtInUsage.pointSize;
@@ -1193,7 +1193,7 @@ void RegisterMetadataBuilder::buildPaSpecificRegisters() {
expCount = resUsage->inOutUsage.expCount;
} else {
- const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStageVertex);
+ const auto resUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Vertex);
const auto &builtInUsage = resUsage->builtInUsage.vs;
usePointSize = builtInUsage.pointSize;
@@ -1410,13 +1410,13 @@ void RegisterMetadataBuilder::setVgtShaderStagesEn(unsigned hwStageMask) {
if (hwStageMask & Util::Abi::HwShaderVs) {
assert(m_gfxIp.major < 11);
- ShaderStage apiStage = ShaderStageVertex;
+ ShaderStageEnum apiStage = ShaderStage::Vertex;
unsigned vsStageEn = VS_STAGE_REAL;
- if (m_pipelineState->hasShaderStage(ShaderStageCopyShader)) {
- apiStage = ShaderStageCopyShader;
+ if (m_pipelineState->hasShaderStage(ShaderStage::CopyShader)) {
+ apiStage = ShaderStage::CopyShader;
vsStageEn = VS_STAGE_COPY_SHADER;
} else if (m_hasTes) {
- apiStage = ShaderStageTessEval;
+ apiStage = ShaderStage::TessEval;
vsStageEn = VS_STAGE_DS;
}
const auto waveSize = m_pipelineState->getShaderWaveSize(apiStage);
@@ -1426,12 +1426,12 @@ void RegisterMetadataBuilder::setVgtShaderStagesEn(unsigned hwStageMask) {
}
if (hwStageMask & Util::Abi::HwShaderGs) {
- ShaderStage apiStage = ShaderStageVertex;
+ ShaderStageEnum apiStage = ShaderStage::Vertex;
if (m_hasGs || m_hasMesh) {
- apiStage = m_hasGs ? ShaderStageGeometry : ShaderStageMesh;
+ apiStage = m_hasGs ? ShaderStage::Geometry : ShaderStage::Mesh;
vgtShaderStagesEn[Util::Abi::VgtShaderStagesEnMetadataKey::GsStageEn] = GS_STAGE_ON;
} else if (m_hasTes) {
- apiStage = ShaderStageTessEval;
+ apiStage = ShaderStage::TessEval;
}
const auto waveSize = m_pipelineState->getShaderWaveSize(apiStage);
vgtShaderStagesEn[Util::Abi::VgtShaderStagesEnMetadataKey::GsW32En] = (waveSize == 32);
@@ -1444,7 +1444,7 @@ void RegisterMetadataBuilder::setVgtShaderStagesEn(unsigned hwStageMask) {
}
if (hwStageMask & Util::Abi::HwShaderHs) {
- const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStageTessControl);
+ const auto waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::TessControl);
vgtShaderStagesEn[Util::Abi::VgtShaderStagesEnMetadataKey::HsW32En] = (waveSize == 32);
if (m_gfxIp.major <= 11)
@@ -1459,16 +1459,16 @@ void RegisterMetadataBuilder::setIaMultVgtParam() {
if (m_hasTcs || m_hasTes) {
// With tessellation, SWITCH_ON_EOI and PARTIAL_ES_WAVE_ON must be set if primitive ID is used by either the TCS,
// TES, or GS.
- const auto &tcsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl)->builtInUsage.tcs;
+ const auto &tcsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl)->builtInUsage.tcs;
bool usePrimitiveId = tcsBuiltInUsage.primitiveId;
bool needWaveOnField = false;
if (m_hasTes && !m_isNggMode) {
- const auto &tesBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageTessEval)->builtInUsage.tes;
+ const auto &tesBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::TessEval)->builtInUsage.tes;
usePrimitiveId = tesBuiltInUsage.primitiveId;
needWaveOnField = true;
}
if (m_hasGs) {
- const auto &gsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->builtInUsage.gs;
+ const auto &gsBuiltInUsage = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->builtInUsage.gs;
usePrimitiveId = gsBuiltInUsage.primitiveId;
}
diff --git a/lgc/patch/RegisterMetadataBuilder.h b/lgc/patch/RegisterMetadataBuilder.h
index e548ed63c1..b835e22837 100644
--- a/lgc/patch/RegisterMetadataBuilder.h
+++ b/lgc/patch/RegisterMetadataBuilder.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -52,9 +52,10 @@ class RegisterMetadataBuilder : public ConfigBuilderBase {
void buildPrimShaderRegisters();
void buildHwVsRegisters();
void buildPsRegisters();
- void buildCsRegisters(ShaderStage shaderStage);
+ void buildCsRegisters(ShaderStageEnum shaderStage);
- void buildShaderExecutionRegisters(Util::Abi::HardwareStage hwStage, ShaderStage apiStage1, ShaderStage apiStage2);
+ void buildShaderExecutionRegisters(Util::Abi::HardwareStage hwStage, ShaderStageEnum apiStage1,
+ ShaderStageEnum apiStage2);
void buildPaSpecificRegisters();
void setVgtShaderStagesEn(unsigned hwStageMask);
void setIaMultVgtParam();
diff --git a/lgc/patch/ShaderInputs.cpp b/lgc/patch/ShaderInputs.cpp
index 3f739340c2..634788c3b4 100644
--- a/lgc/patch/ShaderInputs.cpp
+++ b/lgc/patch/ShaderInputs.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -311,13 +311,14 @@ const char *ShaderInputs::getInputName(ShaderInput inputKind) {
// @param module : IR module
void ShaderInputs::gatherUsage(Module &module) {
for (auto &func : module) {
- if (!func.isDeclaration() || !func.getName().startswith(lgcName::ShaderInput))
+ if (!func.isDeclaration() || !func.getName().starts_with(lgcName::ShaderInput))
continue;
for (User *user : func.users()) {
CallInst *call = cast<CallInst>(user);
- ShaderStage stage = getShaderStage(call->getFunction());
- assert(stage != ShaderStageCopyShader);
- getShaderInputUsage(stage, static_cast<ShaderInput>(cast<ConstantInt>(call->getArgOperand(0))->getZExtValue()))
+ auto stage = getShaderStage(call->getFunction());
+ assert(stage != ShaderStage::CopyShader);
+ getShaderInputUsage(stage.value(),
+ static_cast<ShaderInput>(cast<ConstantInt>(call->getArgOperand(0))->getZExtValue()))
->users.push_back(call);
}
}
@@ -334,8 +335,12 @@ void ShaderInputs::fixupUses(Module &module, PipelineState *pipelineState, bool
if (func.isDeclaration())
continue;
- ShaderStage stage = getShaderStage(&func);
- ShaderInputsUsage *inputsUsage = getShaderInputsUsage(stage);
+ auto stage = getShaderStage(&func);
+
+ if (!stage)
+ continue;
+
+ ShaderInputsUsage *inputsUsage = getShaderInputsUsage(stage.value());
// Use for compute shader
bool useWorkgroupIds[3] = {false};
@@ -346,6 +351,12 @@ void ShaderInputs::fixupUses(Module &module, PipelineState *pipelineState, bool
ShaderInputUsage *inputUsage = inputsUsage->inputs[kind].get();
if (!inputUsage)
continue;
+
+ if (kind == static_cast<unsigned>(ShaderInput::LocalInvocationId) && computeWithIndirectCall &&
+ pipelineState->getShaderModes()->getComputeShaderMode().noLocalInvocationIdInCalls &&
+ !isShaderEntryPoint(&func))
+ continue;
+
Value *value = nullptr;
{
if (inputUsage->entryArgIdx != 0)
@@ -391,9 +402,9 @@ void ShaderInputs::fixupUses(Module &module, PipelineState *pipelineState, bool
// (both run later on) to tell that the input is in use. For those cases, we must keep the builtInUsage
// field, and set it here.
// Add code here as built-ins are moved from PatchInOutImportExport to InOutBuilder.
- auto &builtInUsage = pipelineState->getShaderResourceUsage(stage)->builtInUsage;
- switch (stage) {
- case ShaderStageVertex:
+ auto &builtInUsage = pipelineState->getShaderResourceUsage(stage.value())->builtInUsage;
+ switch (stage.value()) {
+ case ShaderStage::Vertex:
switch (static_cast<ShaderInput>(kind)) {
case ShaderInput::VertexId:
// Tell NggPrimShader to copy VertexId through LDS.
@@ -571,12 +582,12 @@ static const ShaderInputDesc CsVgprInputs[] = {
// @param [in/out] argTys : Argument types vector to add to
// @param [in/out] argNames : Argument names vector to add to
// @returns : Bitmap with bits set for SGPR arguments so caller can set "inreg" attribute on the args
-uint64_t ShaderInputs::getShaderArgTys(PipelineState *pipelineState, ShaderStage shaderStage, Function *origFunc,
+uint64_t ShaderInputs::getShaderArgTys(PipelineState *pipelineState, ShaderStageEnum shaderStage, Function *origFunc,
bool isComputeWithCalls, SmallVectorImpl<Type *> &argTys,
SmallVectorImpl<std::string> &argNames, unsigned argOffset) {
- bool hasTs = pipelineState->hasShaderStage(ShaderStageTessControl);
- bool hasGs = pipelineState->hasShaderStage(ShaderStageGeometry);
+ bool hasTs = pipelineState->hasShaderStage(ShaderStage::TessControl);
+ bool hasGs = pipelineState->hasShaderStage(ShaderStage::Geometry);
uint64_t inRegMask = 0;
auto intfData = pipelineState->getShaderInterfaceData(shaderStage);
@@ -588,7 +599,7 @@ uint64_t ShaderInputs::getShaderArgTys(PipelineState *pipelineState, ShaderStage
// Enable optional shader inputs as required.
switch (shaderStage) {
- case ShaderStageVertex:
+ case ShaderStage::Vertex:
if (enableHwXfb && (!hasGs && !hasTs)) {
// HW stream-out in VS as hardware VS
getShaderInputUsage(shaderStage, ShaderInput::StreamOutInfo)->enable();
@@ -605,7 +616,7 @@ uint64_t ShaderInputs::getShaderArgTys(PipelineState *pipelineState, ShaderStage
getShaderInputUsage(shaderStage, ShaderInput::InstanceId)->enable();
}
break;
- case ShaderStageTessEval:
+ case ShaderStage::TessEval:
if (!hasGs) {
// TES as hardware VS
if (!pipelineState->getNggControl()->enableNgg) {
@@ -631,7 +642,7 @@ uint64_t ShaderInputs::getShaderArgTys(PipelineState *pipelineState, ShaderStage
const unsigned id = static_cast<unsigned>(ShaderInput::WorkgroupId);
CsSgprInputs[id].always = true;
- if (shaderStage == ShaderStageCompute && !isComputeWithCalls && origFunc &&
+ if (shaderStage == ShaderStage::Compute && !isComputeWithCalls && origFunc &&
pipelineState->getTargetInfo().getGfxIpVersion().major <= 11) {
CsSgprInputs[id].always = false;
tryOptimizeWorkgroupId(pipelineState, shaderStage, origFunc);
@@ -642,11 +653,11 @@ uint64_t ShaderInputs::getShaderArgTys(PipelineState *pipelineState, ShaderStage
ArrayRef<ShaderInputDesc> vgprInputDescs;
switch (shaderStage) {
- case ShaderStageTask:
+ case ShaderStage::Task:
sgprInputDescs = TaskSgprInputs;
vgprInputDescs = TaskVgprInputs;
break;
- case ShaderStageVertex:
+ case ShaderStage::Vertex:
if (!hasTs) {
if (hasGs)
sgprInputDescs = VsAsEsSgprInputs;
@@ -655,30 +666,30 @@ uint64_t ShaderInputs::getShaderArgTys(PipelineState *pipelineState, ShaderStage
}
vgprInputDescs = VsVgprInputs;
break;
- case ShaderStageTessControl:
+ case ShaderStage::TessControl:
sgprInputDescs = TcsSgprInputs;
vgprInputDescs = TcsVgprInputs;
break;
- case ShaderStageTessEval:
+ case ShaderStage::TessEval:
if (hasGs)
sgprInputDescs = TesAsEsSgprInputs;
else
sgprInputDescs = TesAsVsSgprInputs;
vgprInputDescs = TesVgprInputs;
break;
- case ShaderStageGeometry:
+ case ShaderStage::Geometry:
sgprInputDescs = GsSgprInputs;
vgprInputDescs = GsVgprInputs;
break;
- case ShaderStageMesh:
+ case ShaderStage::Mesh:
// NOTE: Mesh shader is finally mapped to HW GS in fast launch mode. Therefore, we don't add SGPR and VGPR inputs
// here. Instead, this is deferred to mesh shader lowering in later phase.
break;
- case ShaderStageFragment:
+ case ShaderStage::Fragment:
sgprInputDescs = FsSgprInputs;
vgprInputDescs = FsVgprInputs;
break;
- case ShaderStageCompute:
+ case ShaderStage::Compute:
sgprInputDescs = CsSgprInputs;
vgprInputDescs = CsVgprInputs;
break;
@@ -721,7 +732,7 @@ uint64_t ShaderInputs::getShaderArgTys(PipelineState *pipelineState, ShaderStage
// Get ShaderInputsUsage struct for the given shader stage
//
// @param stage : Shader stage
-ShaderInputs::ShaderInputsUsage *ShaderInputs::getShaderInputsUsage(ShaderStage stage) {
+ShaderInputs::ShaderInputsUsage *ShaderInputs::getShaderInputsUsage(ShaderStageEnum stage) {
m_shaderInputsUsage.resize(std::max(m_shaderInputsUsage.size(), static_cast<size_t>(stage) + 1));
return &m_shaderInputsUsage[stage];
}
@@ -731,7 +742,7 @@ ShaderInputs::ShaderInputsUsage *ShaderInputs::getShaderInputsUsage(ShaderStage
//
// @param stage : Shader stage
// @param inputKind : ShaderInput enum value for the shader input
-ShaderInputs::ShaderInputUsage *ShaderInputs::getShaderInputUsage(ShaderStage stage, unsigned inputKind) {
+ShaderInputs::ShaderInputUsage *ShaderInputs::getShaderInputUsage(ShaderStageEnum stage, unsigned inputKind) {
ShaderInputsUsage *inputsUsage = getShaderInputsUsage(stage);
if (!inputsUsage->inputs[inputKind])
inputsUsage->inputs[inputKind] = std::make_unique<ShaderInputUsage>();
@@ -748,8 +759,9 @@ ShaderInputs::ShaderInputUsage *ShaderInputs::getShaderInputUsage(ShaderStage st
// @param pipelineState : Pipeline state
// @param shaderStage : Shader stage
// @param origFunc : The original entry point function
-void ShaderInputs::tryOptimizeWorkgroupId(PipelineState *pipelineState, ShaderStage shaderStage, Function *origFunc) {
- assert(shaderStage == ShaderStageCompute);
+void ShaderInputs::tryOptimizeWorkgroupId(PipelineState *pipelineState, ShaderStageEnum shaderStage,
+ Function *origFunc) {
+ assert(shaderStage == ShaderStage::Compute);
bool useWholeWorkgroupId = false;
SmallVector<Instruction *> extractVec3[3];
SmallVector<Instruction *> workgroupIdCallInsts;
diff --git a/lgc/patch/ShaderMerger.cpp b/lgc/patch/ShaderMerger.cpp
index bcf64cfa8a..981c7bb698 100644
--- a/lgc/patch/ShaderMerger.cpp
+++ b/lgc/patch/ShaderMerger.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -59,10 +59,10 @@ ShaderMerger::ShaderMerger(PipelineState *pipelineState, PipelineShadersResult *
assert(m_gfxIp.major >= 9);
assert(m_pipelineState->isGraphics());
- m_hasVs = m_pipelineState->hasShaderStage(ShaderStageVertex);
- m_hasTcs = m_pipelineState->hasShaderStage(ShaderStageTessControl);
- m_hasTes = m_pipelineState->hasShaderStage(ShaderStageTessEval);
- m_hasGs = m_pipelineState->hasShaderStage(ShaderStageGeometry);
+ m_hasVs = m_pipelineState->hasShaderStage(ShaderStage::Vertex);
+ m_hasTcs = m_pipelineState->hasShaderStage(ShaderStage::TessControl);
+ m_hasTes = m_pipelineState->hasShaderStage(ShaderStage::TessEval);
+ m_hasGs = m_pipelineState->hasShaderStage(ShaderStage::Geometry);
}
// =====================================================================================================================
@@ -178,7 +178,7 @@ void ShaderMerger::gatherTuningAttributes(AttrBuilder &tuningAttrs, const Functi
continue;
auto attrKind = srcAttr.getKindAsString();
- if (!(attrKind.startswith("amdgpu") || attrKind.startswith("disable")))
+ if (!(attrKind.starts_with("amdgpu") || attrKind.starts_with("disable")))
continue;
// Note: this doesn't mean attribute values match
@@ -247,18 +247,18 @@ FunctionType *ShaderMerger::generateLsHsEntryPointType(uint64_t *inRegMask) cons
// User data (SGPRs)
unsigned userDataCount = 0;
if (m_hasVs) {
- const auto intfData = m_pipelineState->getShaderInterfaceData(ShaderStageVertex);
+ const auto intfData = m_pipelineState->getShaderInterfaceData(ShaderStage::Vertex);
userDataCount = std::max(intfData->userDataCount, userDataCount);
}
if (m_hasTcs) {
- const auto intfData = m_pipelineState->getShaderInterfaceData(ShaderStageTessControl);
+ const auto intfData = m_pipelineState->getShaderInterfaceData(ShaderStage::TessControl);
userDataCount = std::max(intfData->userDataCount, userDataCount);
}
if (m_hasTcs && m_hasVs) {
- auto vsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStageVertex);
- auto tcsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStageTessControl);
+ auto vsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStage::Vertex);
+ auto tcsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStage::TessControl);
if (vsIntfData->spillTable.sizeInDwords == 0 && tcsIntfData->spillTable.sizeInDwords > 0) {
vsIntfData->userDataUsage.spillTable = userDataCount;
@@ -323,7 +323,7 @@ Function *ShaderMerger::generateLsHsEntryPoint(Function *lsEntryPoint, Function
entryPoint->addFnAttr("amdgpu-flat-work-group-size",
"128,128"); // Force s_barrier to be present (ignore optimization)
- const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStageTessControl);
+ const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::TessControl);
if (m_gfxIp.major >= 10)
entryPoint->addFnAttr("target-features", ",+wavefrontsize" + std::to_string(waveSize)); // Set wavefront size
applyTuningAttributes(entryPoint, tuningAttrs);
@@ -442,7 +442,7 @@ Function *ShaderMerger::generateLsHsEntryPoint(Function *lsEntryPoint, Function
if (m_hasVs) {
// Call LS main function
SmallVector<Value *> lsArgs;
- auto intfData = m_pipelineState->getShaderInterfaceData(ShaderStageVertex);
+ auto intfData = m_pipelineState->getShaderInterfaceData(ShaderStage::Vertex);
const auto lsArgCount = lsEntryPoint->arg_size();
@@ -488,7 +488,7 @@ Function *ShaderMerger::generateLsHsEntryPoint(Function *lsEntryPoint, Function
// it through the group.
Value *hasPatchCount = builder.CreateLShr(mergeWaveInfo, 16); // hsWaveCount = mergedWaveInfo[24:16]
hasPatchCount = builder.CreateAnd(hasPatchCount, 0xFF);
- const auto hsPatchCountStart = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl)
+ const auto hsPatchCountStart = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl)
->inOutUsage.tcs.calcFactor.onChip.hsPatchCountStart;
writeValueToLds(hasPatchCount, builder.getInt32(hsPatchCountStart), builder);
builder.CreateBr(endDistribHsPatchCountBlock);
@@ -512,11 +512,11 @@ Function *ShaderMerger::generateLsHsEntryPoint(Function *lsEntryPoint, Function
// Call HS main function
SmallVector<Value *> hsArgs;
- auto intfData = m_pipelineState->getShaderInterfaceData(ShaderStageTessControl);
+ auto intfData = m_pipelineState->getShaderInterfaceData(ShaderStage::TessControl);
SmallVector<std::pair<unsigned, unsigned>> substitutions;
if (intfData->spillTable.sizeInDwords > 0 && m_hasVs) {
- auto vsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStageVertex);
+ auto vsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStage::Vertex);
assert(vsIntfData->userDataUsage.spillTable > 0);
substitutions.emplace_back(intfData->userDataUsage.spillTable, vsIntfData->userDataUsage.spillTable);
}
@@ -566,22 +566,22 @@ FunctionType *ShaderMerger::generateEsGsEntryPointType(uint64_t *inRegMask) cons
bool hasTs = (m_hasTcs || m_hasTes);
if (hasTs) {
if (m_hasTes) {
- const auto intfData = m_pipelineState->getShaderInterfaceData(ShaderStageTessEval);
+ const auto intfData = m_pipelineState->getShaderInterfaceData(ShaderStage::TessEval);
userDataCount = std::max(intfData->userDataCount, userDataCount);
}
} else {
if (m_hasVs) {
- const auto intfData = m_pipelineState->getShaderInterfaceData(ShaderStageVertex);
+ const auto intfData = m_pipelineState->getShaderInterfaceData(ShaderStage::Vertex);
userDataCount = std::max(intfData->userDataCount, userDataCount);
}
}
- const auto intfData = m_pipelineState->getShaderInterfaceData(ShaderStageGeometry);
+ const auto intfData = m_pipelineState->getShaderInterfaceData(ShaderStage::Geometry);
userDataCount = std::max(intfData->userDataCount, userDataCount);
if (hasTs) {
if (m_hasTes) {
- const auto tesIntfData = m_pipelineState->getShaderInterfaceData(ShaderStageTessEval);
+ const auto tesIntfData = m_pipelineState->getShaderInterfaceData(ShaderStage::TessEval);
if (intfData->spillTable.sizeInDwords > 0 && tesIntfData->spillTable.sizeInDwords == 0) {
tesIntfData->userDataUsage.spillTable = userDataCount;
++userDataCount;
@@ -590,7 +590,7 @@ FunctionType *ShaderMerger::generateEsGsEntryPointType(uint64_t *inRegMask) cons
}
} else {
if (m_hasVs) {
- const auto vsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStageVertex);
+ const auto vsIntfData = m_pipelineState->getShaderInterfaceData(ShaderStage::Vertex);
if (intfData->spillTable.sizeInDwords > 0 && vsIntfData->spillTable.sizeInDwords == 0) {
vsIntfData->userDataUsage.spillTable = userDataCount;
++userDataCount;
@@ -666,7 +666,7 @@ Function *ShaderMerger::generateEsGsEntryPoint(Function *esEntryPoint, Function
entryPoint->addFnAttr("amdgpu-flat-work-group-size",
"128,128"); // Force s_barrier to be present (ignore optimization)
- const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStageGeometry);
+ const unsigned waveSize = m_pipelineState->getShaderWaveSize(ShaderStage::Geometry);
if (m_gfxIp.major >= 10)
entryPoint->addFnAttr("target-features", ",+wavefrontsize" + std::to_string(waveSize)); // Set wavefront size
applyTuningAttributes(entryPoint, tuningAttrs);
@@ -693,7 +693,7 @@ Function *ShaderMerger::generateEsGsEntryPoint(Function *esEntryPoint, Function
// Run GS
// }
//
- const auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->inOutUsage.gs.calcFactor;
+ const auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->inOutUsage.gs.calcFactor;
SmallVector<Argument *, 32> args;
for (auto &arg : entryPoint->args())
@@ -789,7 +789,7 @@ Function *ShaderMerger::generateEsGsEntryPoint(Function *esEntryPoint, Function
if ((hasTs && m_hasTes) || (!hasTs && m_hasVs)) {
// Call ES main function
SmallVector<Value *> esArgs;
- auto intfData = m_pipelineState->getShaderInterfaceData(hasTs ? ShaderStageTessEval : ShaderStageVertex);
+ auto intfData = m_pipelineState->getShaderInterfaceData(hasTs ? ShaderStage::TessEval : ShaderStage::Vertex);
spillTableIdx = intfData->userDataUsage.spillTable;
const unsigned esArgCount = esEntryPoint->arg_size();
@@ -860,7 +860,7 @@ Function *ShaderMerger::generateEsGsEntryPoint(Function *esEntryPoint, Function
// Call GS main function
SmallVector<llvm::Value *> gsArgs;
- auto intfData = m_pipelineState->getShaderInterfaceData(ShaderStageGeometry);
+ auto intfData = m_pipelineState->getShaderInterfaceData(ShaderStage::Geometry);
SmallVector<std::pair<unsigned, unsigned>> substitutions;
if (intfData->spillTable.sizeInDwords > 0 && spillTableIdx > 0)
@@ -1000,19 +1000,19 @@ void ShaderMerger::processRayQueryLdsStack(Function *entryPoint1, Function *entr
if (ldsStack) {
unsigned ldsStackBase = 0;
- ShaderStage shaderStage2 = ShaderStageInvalid;
+ std::optional<ShaderStageEnum> shaderStage2;
if (entryPoint2)
shaderStage2 = lgc::getShaderStage(entryPoint2);
- if (shaderStage2 == ShaderStageTessControl) {
+ if (shaderStage2 == ShaderStage::TessControl) {
// Must be LS-HS merged shader
const auto &calcFactor =
- m_pipelineState->getShaderResourceUsage(ShaderStageTessControl)->inOutUsage.tcs.calcFactor;
+ m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl)->inOutUsage.tcs.calcFactor;
if (calcFactor.rayQueryLdsStackSize > 0)
ldsStackBase = calcFactor.tessOnChipLdsSize;
} else {
// Must be ES-GS merged shader or NGG primitive shader
- const auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStageGeometry)->inOutUsage.gs.calcFactor;
+ const auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStage::Geometry)->inOutUsage.gs.calcFactor;
if (calcFactor.rayQueryLdsStackSize > 0)
ldsStackBase = calcFactor.gsOnChipLdsSize;
}
@@ -1089,8 +1089,8 @@ void ShaderMerger::storeTessFactorsWithOpt(Value *threadIdInWave, IRBuilder<> &b
auto entryPoint = insertBlock->getParent();
assert(entryPoint->getName() == lgcName::LsHsEntryPoint); // Must be LS-HS merged shader
- const auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStageTessControl)->inOutUsage.tcs.calcFactor;
- const unsigned waveSize = m_pipelineState->getMergedShaderWaveSize(ShaderStageTessControl);
+ const auto &calcFactor = m_pipelineState->getShaderResourceUsage(ShaderStage::TessControl)->inOutUsage.tcs.calcFactor;
+ const unsigned waveSize = m_pipelineState->getMergedShaderWaveSize(ShaderStage::TessControl);
assert(waveSize == 32 || waveSize == 64);
// Helper to create a basic block
diff --git a/lgc/patch/ShaderMerger.h b/lgc/patch/ShaderMerger.h
index 867650a2cd..1623708d0a 100644
--- a/lgc/patch/ShaderMerger.h
+++ b/lgc/patch/ShaderMerger.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/patch/SystemValues.cpp b/lgc/patch/SystemValues.cpp
index ad414781d4..7f4fda56c4 100644
--- a/lgc/patch/SystemValues.cpp
+++ b/lgc/patch/SystemValues.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -48,12 +48,12 @@ using namespace llvm;
void ShaderSystemValues::initialize(PipelineState *pipelineState, Function *entryPoint) {
if (!m_entryPoint) {
m_entryPoint = entryPoint;
- m_shaderStage = getShaderStage(entryPoint);
+ auto shaderStage = getShaderStage(entryPoint);
+ m_shaderStage = shaderStage.value();
m_context = &entryPoint->getParent()->getContext();
m_pipelineState = pipelineState;
- assert(m_shaderStage != ShaderStageInvalid);
- if (m_shaderStage != ShaderStageCopyShader) {
+ if (m_shaderStage != ShaderStage::CopyShader) {
// NOTE: For shader stages other than copy shader, make sure their entry-points are mutated with proper arguments.
// For copy shader, we don't need such check because entry-point mutation is not applied to copy shader. Copy
// shader is completely generated.
@@ -68,11 +68,11 @@ Value *ShaderSystemValues::getEsGsRingBufDesc() {
if (!m_esGsRingBufDesc) {
unsigned tableOffset = 0;
switch (m_shaderStage) {
- case ShaderStageVertex:
- case ShaderStageTessEval:
+ case ShaderStage::Vertex:
+ case ShaderStage::TessEval:
tableOffset = SiDrvTableEsRingOutOffs;
break;
- case ShaderStageGeometry:
+ case ShaderStage::Geometry:
tableOffset = SiDrvTableGsRingInOffs;
break;
default:
@@ -83,7 +83,7 @@ Value *ShaderSystemValues::getEsGsRingBufDesc() {
// Ensure we have got the global table pointer first, and insert new code after that.
BuilderBase builder(getInternalGlobalTablePtr()->getNextNode());
m_esGsRingBufDesc = loadDescFromDriverTable(tableOffset, builder);
- if (m_shaderStage != ShaderStageGeometry) {
+ if (m_shaderStage != ShaderStage::Geometry) {
// NOTE: For GFX9+, we have to explicitly set DATA_FORMAT for GS-VS ring buffer descriptor for
// VS/TES output.
m_esGsRingBufDesc = setRingBufferDataFormat(m_esGsRingBufDesc, BUF_DATA_FORMAT_32, builder);
@@ -95,7 +95,7 @@ Value *ShaderSystemValues::getEsGsRingBufDesc() {
// =====================================================================================================================
// Get the descriptor for tessellation factor (TF) buffer (TCS output)
Value *ShaderSystemValues::getTessFactorBufDesc() {
- assert(m_shaderStage == ShaderStageTessControl);
+ assert(m_shaderStage == ShaderStage::TessControl);
if (!m_tfBufDesc) {
// Ensure we have got the global table pointer first, and insert new code after that.
BuilderBase builder(getInternalGlobalTablePtr()->getNextNode());
@@ -109,8 +109,8 @@ Value *ShaderSystemValues::getTessFactorBufDesc() {
Value *ShaderSystemValues::getAttribRingBufDesc() {
// Vertex attributes through memory is for GFX11+
assert(m_pipelineState->getTargetInfo().getGfxIpVersion().major >= 11);
- assert(m_shaderStage == ShaderStageVertex || m_shaderStage == ShaderStageTessEval ||
- m_shaderStage == ShaderStageCopyShader || m_shaderStage == ShaderStageMesh);
+ assert(m_shaderStage == ShaderStage::Vertex || m_shaderStage == ShaderStage::TessEval ||
+ m_shaderStage == ShaderStage::CopyShader || m_shaderStage == ShaderStage::Mesh);
if (!m_attribRingBufDesc) {
// Ensure we have got the global table pointer first, and insert new code after that.
BuilderBase builder(getInternalGlobalTablePtr()->getNextNode());
@@ -123,7 +123,7 @@ Value *ShaderSystemValues::getAttribRingBufDesc() {
// Get the descriptor for task payload ring buffer (for task and mesh shader)
Value *ShaderSystemValues::getTaskPayloadRingBufDesc() {
assert(m_pipelineState->getTargetInfo().getGfxIpVersion() >= GfxIpVersion({10, 3})); // Must be GFX10.3+
- assert(m_shaderStage == ShaderStageTask || m_shaderStage == ShaderStageMesh);
+ assert(m_shaderStage == ShaderStage::Task || m_shaderStage == ShaderStage::Mesh);
if (!m_taskPayloadRingBufDesc) {
// Ensure we have got the global table pointer first, and insert new code after that.
BuilderBase builder(getInternalGlobalTablePtr()->getNextNode());
@@ -136,7 +136,7 @@ Value *ShaderSystemValues::getTaskPayloadRingBufDesc() {
// Get the descriptor for task draw data ring buffer (for task shader)
Value *ShaderSystemValues::getTaskDrawDataRingBufDesc() {
assert(m_pipelineState->getTargetInfo().getGfxIpVersion() >= GfxIpVersion({10, 3})); // Must be GFX10.3+
- assert(m_shaderStage == ShaderStageTask);
+ assert(m_shaderStage == ShaderStage::Task);
if (!m_taskDrawDataRingBufDesc) {
// Ensure we have got the global table pointer first, and insert new code after that.
BuilderBase builder(getInternalGlobalTablePtr()->getNextNode());
@@ -148,7 +148,7 @@ Value *ShaderSystemValues::getTaskDrawDataRingBufDesc() {
// =====================================================================================================================
// Extract value of primitive ID (TCS)
Value *ShaderSystemValues::getPrimitiveId() {
- assert(m_shaderStage == ShaderStageTessControl);
+ assert(m_shaderStage == ShaderStage::TessControl);
if (!m_primitiveId) {
auto intfData = m_pipelineState->getShaderInterfaceData(m_shaderStage);
m_primitiveId = getFunctionArgument(m_entryPoint, intfData->entryArgIdxs.tcs.patchId, "patchId");
@@ -159,7 +159,7 @@ Value *ShaderSystemValues::getPrimitiveId() {
// =====================================================================================================================
// Get invocation ID (TCS)
Value *ShaderSystemValues::getInvocationId() {
- assert(m_shaderStage == ShaderStageTessControl);
+ assert(m_shaderStage == ShaderStage::TessControl);
if (!m_invocationId) {
auto insertPos = &*m_entryPoint->front().getFirstNonPHIOrDbgOrAlloca();
auto intfData = m_pipelineState->getShaderInterfaceData(m_shaderStage);
@@ -177,7 +177,7 @@ Value *ShaderSystemValues::getInvocationId() {
// =====================================================================================================================
// Get relative patchId (TCS)
Value *ShaderSystemValues::getRelativeId() {
- assert(m_shaderStage == ShaderStageTessControl);
+ assert(m_shaderStage == ShaderStage::TessControl);
if (!m_relativeId) {
auto insertPos = &*m_entryPoint->front().getFirstNonPHIOrDbgOrAlloca();
auto intfData = m_pipelineState->getShaderInterfaceData(m_shaderStage);
@@ -193,7 +193,7 @@ Value *ShaderSystemValues::getRelativeId() {
// =====================================================================================================================
// Get offchip LDS descriptor (TCS and TES)
Value *ShaderSystemValues::getOffChipLdsDesc() {
- assert(m_shaderStage == ShaderStageTessControl || m_shaderStage == ShaderStageTessEval);
+ assert(m_shaderStage == ShaderStage::TessControl || m_shaderStage == ShaderStage::TessEval);
if (!m_offChipLdsDesc) {
// Ensure we have got the global table pointer first, and insert new code after that.
BuilderBase builder(getInternalGlobalTablePtr()->getNextNode());
@@ -205,7 +205,7 @@ Value *ShaderSystemValues::getOffChipLdsDesc() {
// =====================================================================================================================
// Get tessellated coordinate (TES)
Value *ShaderSystemValues::getTessCoord() {
- assert(m_shaderStage == ShaderStageTessEval);
+ assert(m_shaderStage == ShaderStage::TessEval);
if (!m_tessCoord) {
auto insertPos = &*m_entryPoint->front().getFirstNonPHIOrDbgOrAlloca();
auto intfData = m_pipelineState->getShaderInterfaceData(m_shaderStage);
@@ -235,7 +235,7 @@ Value *ShaderSystemValues::getTessCoord() {
// =====================================================================================================================
// Get ES -> GS offsets (GS in)
Value *ShaderSystemValues::getEsGsOffsets() {
- assert(m_shaderStage == ShaderStageGeometry);
+ assert(m_shaderStage == ShaderStage::Geometry);
if (!m_esGsOffsets) {
auto insertPos = &*m_entryPoint->front().getFirstNonPHIOrDbgOrAlloca();
auto intfData = m_pipelineState->getShaderInterfaceData(m_shaderStage);
@@ -256,14 +256,14 @@ Value *ShaderSystemValues::getEsGsOffsets() {
//
// @param streamId : Stream ID, always 0 for copy shader
Value *ShaderSystemValues::getGsVsRingBufDesc(unsigned streamId) {
- assert(m_shaderStage == ShaderStageGeometry || m_shaderStage == ShaderStageCopyShader);
+ assert(m_shaderStage == ShaderStage::Geometry || m_shaderStage == ShaderStage::CopyShader);
if (m_gsVsRingBufDescs.size() <= streamId)
m_gsVsRingBufDescs.resize(streamId + 1);
if (!m_gsVsRingBufDescs[streamId]) {
// Ensure we have got the global table pointer first, and insert new code after that.
BuilderBase builder(getInternalGlobalTablePtr()->getNextNode());
- if (m_shaderStage == ShaderStageGeometry) {
+ if (m_shaderStage == ShaderStage::Geometry) {
const auto resUsage = m_pipelineState->getShaderResourceUsage(m_shaderStage);
// Geometry shader, using GS-VS ring for output.
@@ -317,7 +317,7 @@ Value *ShaderSystemValues::getGsVsRingBufDesc(unsigned streamId) {
// =====================================================================================================================
// Get pointers to emit counters (GS)
std::pair<Type *, ArrayRef<Value *>> ShaderSystemValues::getEmitCounterPtr() {
- assert(m_shaderStage == ShaderStageGeometry);
+ assert(m_shaderStage == ShaderStage::Geometry);
auto *emitCounterTy = Type::getInt32Ty(*m_context);
if (m_emitCounterPtrs.empty()) {
// TODO: We should only insert those offsets required by the specified input primitive.
@@ -342,7 +342,7 @@ Instruction *ShaderSystemValues::getInternalGlobalTablePtr() {
// Global table is always the first function argument (separate shader) or the eighth function argument (merged
// shader). And mesh shader is actually mapped to ES-GS merged shader.
m_internalGlobalTablePtr = makePointer(
- getFunctionArgument(m_entryPoint, getShaderStage(m_entryPoint) == ShaderStageMesh ? NumSpecialSgprInputs : 0,
+ getFunctionArgument(m_entryPoint, getShaderStage(m_entryPoint) == ShaderStage::Mesh ? NumSpecialSgprInputs : 0,
"globalTable"),
ptrTy, InvalidValue);
}
@@ -353,17 +353,17 @@ Instruction *ShaderSystemValues::getInternalGlobalTablePtr() {
// Get the mesh pipeline statistics buffer pointer as pointer to i8
Value *ShaderSystemValues::getMeshPipeStatsBufPtr() {
assert(m_pipelineState->getTargetInfo().getGfxIpVersion() >= GfxIpVersion({10, 3})); // Must be GFX10.3+
- assert(m_shaderStage == ShaderStageTask || m_shaderStage == ShaderStageMesh);
+ assert(m_shaderStage == ShaderStage::Task || m_shaderStage == ShaderStage::Mesh);
if (!m_meshPipeStatsBufPtr) {
auto intfData = m_pipelineState->getShaderInterfaceData(m_shaderStage);
unsigned entryArgIdx = 0;
// Get the SGPR number of the mesh pipeline statistics buffer pointer.
switch (m_shaderStage) {
- case ShaderStageTask:
+ case ShaderStage::Task:
entryArgIdx = intfData->entryArgIdxs.task.pipeStatsBuf;
break;
- case ShaderStageMesh:
+ case ShaderStage::Mesh:
entryArgIdx = intfData->entryArgIdxs.mesh.pipeStatsBuf;
break;
default:
@@ -412,8 +412,8 @@ Value *ShaderSystemValues::getStreamOutBufDesc(unsigned xfbBuffer) {
// =====================================================================================================================
// Get stream-out buffer table pointer
std::pair<Type *, Instruction *> ShaderSystemValues::getStreamOutTablePtr() {
- assert(m_shaderStage == ShaderStageVertex || m_shaderStage == ShaderStageTessEval ||
- m_shaderStage == ShaderStageCopyShader);
+ assert(m_shaderStage == ShaderStage::Vertex || m_shaderStage == ShaderStage::TessEval ||
+ m_shaderStage == ShaderStage::CopyShader);
auto *streamOutTableTy =
ArrayType::get(FixedVectorType::get(Type::getInt32Ty(*m_context), 4), MaxTransformFeedbackBuffers);
@@ -423,13 +423,13 @@ std::pair<Type *, Instruction *> ShaderSystemValues::getStreamOutTablePtr() {
// Get the SGPR number of the stream-out table pointer.
switch (m_shaderStage) {
- case ShaderStageVertex:
+ case ShaderStage::Vertex:
entryArgIdx = intfData->entryArgIdxs.vs.streamOutData.tablePtr;
break;
- case ShaderStageTessEval:
+ case ShaderStage::TessEval:
entryArgIdx = intfData->entryArgIdxs.tes.streamOutData.tablePtr;
break;
- case ShaderStageCopyShader:
+ case ShaderStage::CopyShader:
entryArgIdx = intfData->userDataUsage.gs.copyShaderStreamOutTable;
break;
default:
diff --git a/lgc/patch/TcsPassthroughShader.cpp b/lgc/patch/TcsPassthroughShader.cpp
index 8ca65d5c8a..9b3bc12ae3 100644
--- a/lgc/patch/TcsPassthroughShader.cpp
+++ b/lgc/patch/TcsPassthroughShader.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -74,17 +74,17 @@ PreservedAnalyses TcsPassthroughShader::run(Module &module, ModuleAnalysisManage
// @param module : LLVM module to be run on
// @param pipelineState : The pipeline state read from module.
void TcsPassthroughShader::updatePipelineState(Module &module, PipelineState *pipelineState) const {
- pipelineState->setShaderStageMask(pipelineState->getShaderStageMask() | shaderStageToMask(ShaderStageTessControl));
+ pipelineState->setShaderStageMask(pipelineState->getShaderStageMask() | ShaderStageMask(ShaderStage::TessControl));
TessellationMode tessellationMode = pipelineState->getShaderModes()->getTessellationMode();
tessellationMode.outputVertices = tessellationMode.inputVertices;
- pipelineState->setTessellationMode(module, ShaderStageTessControl, tessellationMode);
+ pipelineState->setTessellationMode(module, ShaderStage::TessControl, tessellationMode);
pipelineState->readState(&module);
- ShaderOptions options = pipelineState->getShaderOptions(ShaderStageTessControl);
+ ShaderOptions options = pipelineState->getShaderOptions(ShaderStage::TessControl);
options.hash[0] = (uint64_t)-1;
options.hash[1] = (uint64_t)-1;
- pipelineState->setShaderOptions(ShaderStageTessControl, options);
+ pipelineState->setShaderOptions(ShaderStage::TessControl, options);
}
// =====================================================================================================================
@@ -112,7 +112,7 @@ Function *TcsPassthroughShader::generateTcsPassthroughEntryPoint(Module &module,
Function *entryPoint =
Function::Create(entryPointTy, GlobalValue::ExternalLinkage, lgcName::TcsPassthroughEntryPoint, &module);
entryPoint->setDLLStorageClass(GlobalValue::DLLExportStorageClass);
- setShaderStage(entryPoint, ShaderStageTessControl);
+ setShaderStage(entryPoint, ShaderStage::TessControl);
entryPoint->setCallingConv(CallingConv::SPIR_FUNC);
return entryPoint;
}
@@ -131,7 +131,7 @@ void TcsPassthroughShader::generateTcsPassthroughShaderBody(Module &module, Pipe
BuilderBase builder(module.getContext());
builder.SetInsertPoint(block);
- ResourceUsage *tcsResourceUsage = pipelineState->getShaderResourceUsage(ShaderStageTessControl);
+ ResourceUsage *tcsResourceUsage = pipelineState->getShaderResourceUsage(ShaderStage::TessControl);
auto &tcsInputLocInfoMap = tcsResourceUsage->inOutUsage.inputLocInfoMap;
auto &tcsOutputLocInfoMap = tcsResourceUsage->inOutUsage.outputLocInfoMap;
auto &tcsBuiltInInfo = tcsResourceUsage->builtInUsage.tcs;
@@ -187,9 +187,9 @@ void TcsPassthroughShader::generateTcsPassthroughShaderBody(Module &module, Pipe
// ---------------------------------------------------------------------------------------------
// copy vs generic output and built-in output to tcs output
- Function *vsEntryPoint = pipelineShaders.getEntryPoint(ShaderStageVertex);
+ Function *vsEntryPoint = pipelineShaders.getEntryPoint(ShaderStage::Vertex);
for (Function &func : *vsEntryPoint->getParent()) {
- if (func.getName().startswith(lgcName::OutputExportGeneric)) {
+ if (func.getName().starts_with(lgcName::OutputExportGeneric)) {
for (auto user : func.users()) {
CallInst *callInst = dyn_cast<CallInst>(user);
if (!callInst || callInst->getParent()->getParent() != vsEntryPoint)
@@ -228,7 +228,7 @@ void TcsPassthroughShader::generateTcsPassthroughShaderBody(Module &module, Pipe
tcsInputLocInfoMap[origLocInfo].setData(InvalidValue);
tcsOutputLocInfoMap[origLocInfo].setData(InvalidValue);
}
- } else if (func.getName().startswith(lgcName::OutputExportBuiltIn)) {
+ } else if (func.getName().starts_with(lgcName::OutputExportBuiltIn)) {
for (auto user : func.users()) {
CallInst *callInst = dyn_cast<CallInst>(user);
if (!callInst || callInst->getParent()->getParent() != vsEntryPoint)
diff --git a/lgc/patch/VertexFetch.cpp b/lgc/patch/VertexFetch.cpp
index 27741fe878..df8d6ce2ed 100644
--- a/lgc/patch/VertexFetch.cpp
+++ b/lgc/patch/VertexFetch.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -65,13 +65,6 @@ static constexpr unsigned CurrentAttributeBufferBinding = 1; // Descriptor bi
static constexpr unsigned GenericVertexFetchShaderBinding = 0; // Descriptor binding for generic vertex fetch shader
static constexpr unsigned VertexInputBindingCurrent = 64; // Vertex input binding for current attribute
-// Represents vertex format info corresponding to vertex attribute format (VkFormat).
-struct VertexFormatInfo {
- BufNumFormat nfmt; // Numeric format of vertex buffer
- BufDataFormat dfmt; // Data format of vertex buffer
- unsigned numChannels; // Valid number of channels
-};
-
// Represents vertex component info corresponding to vertex data format (BufDataFormat).
//
// NOTE: This info is used by vertex fetch instructions. We split vertex fetch into its per-component fetches when
@@ -81,14 +74,24 @@ struct VertexCompFormatInfo {
unsigned vertexByteSize; // Byte size of the vertex
unsigned compByteSize; // Byte size of each individual component
unsigned compCount; // Component count
- BufDataFmt compDfmt; // Equivalent data format of each component
+ BufDataFmt fetchDfmt; // Equivalent data format of each fetch intrinsic
+};
+
+// Represents vertex format data results info corresponding to vertex numerical format (BufNumFormat).
+//
+// This info will be used to determine property of each format, corresponding to final result emulation including
+// packed formats and when do fetch in Byte.
+struct VertexNumFormatInfo {
+ bool isSigned; // Load result is signed, do SExt when needed.
+ bool isScaled; // Load result is scaled.
+ bool isNorm; // Load result is normarlized.
};
// =====================================================================================================================
// Vertex fetch manager
class VertexFetchImpl : public VertexFetch {
public:
- VertexFetchImpl(LgcContext *lgcContext, bool useSoftwareVertexBufferDescriptors);
+ VertexFetchImpl(LgcContext *lgcContext, bool useSoftwareVertexBufferDescriptors, bool vbAddressLowBitsKnown);
VertexFetchImpl(const VertexFetchImpl &) = delete;
VertexFetchImpl &operator=(const VertexFetchImpl &) = delete;
@@ -97,11 +100,10 @@ class VertexFetchImpl : public VertexFetch {
BuilderImpl &builderImpl) override;
// Generate code to fetch a vertex value for uber shader
- Value *fetchVertex(InputImportGenericOp *inst, Value *descPtr, Value *locMasks, BuilderBase &builder) override;
+ Value *fetchVertex(InputImportGenericOp *inst, Value *descPtr, Value *locMasks, BuilderBase &builder,
+ bool disablePerCompFetch) override;
private:
- static VertexFormatInfo getVertexFormatInfo(const VertexInputDescription *description);
-
// Gets variable corresponding to vertex index
Value *getVertexIndex() { return m_vertexIndex; }
@@ -110,21 +112,29 @@ class VertexFetchImpl : public VertexFetch {
static const VertexCompFormatInfo *getVertexComponentFormatInfo(unsigned dfmt);
+ static const VertexNumFormatInfo *getVertexNumericFormatInfo(unsigned nfmt);
+
unsigned mapVertexFormat(unsigned dfmt, unsigned nfmt) const;
Value *loadVertexBufferDescriptor(unsigned binding, BuilderImpl &builderImpl);
- void addVertexFetchInst(Value *vbDesc, unsigned numChannels, bool is16bitFetch, Value *vbIndex, Value *srdStride,
- unsigned offset, unsigned stride, unsigned dfmt, unsigned nfmt, Instruction *insertPos,
- Value **ppFetch) const;
+ void addVertexFetchInst(Value *vbDesc, Value *vbIndex, Value *srdStride, unsigned numChannels, unsigned offset,
+ unsigned dfmt, unsigned nfmt, unsigned inputCompBytes, unsigned fetchCompBytes, bool isSigned,
+ bool isPacked, bool fetchInByte, BuilderImpl &builderImpl, Value **ppFetch) const;
bool needPostShuffle(const VertexInputDescription *inputDesc, std::vector<Constant *> &shuffleMask) const;
- bool needSecondVertexFetch(const VertexInputDescription *inputDesc) const;
-
bool needPatch32(const VertexInputDescription *inputDesc) const;
- std::pair<Value *, Value *> convertSrdToOffsetMode(Value *vbDesc, BuilderBase &builder);
+ bool needPackFormatEmulation(const VertexInputDescription *inputDesc, std::vector<unsigned> &extractMask) const;
+
+ void postFetchEmulation(const VertexInputDescription *description, bool fetchInByte, unsigned inputCompBytes,
+ unsigned numChannels, const VertexNumFormatInfo *numFormatInfo,
+ const VertexCompFormatInfo *descFormatInfo, BuilderImpl &builderImpl, Value **ppFetch) const;
+
+ std::pair<Value *, Value *> convertSrdToOffsetMode(Value *vbDesc, BuilderImpl &builder);
+
+ Type *getVertexFetchType(bool isFloat, unsigned byteSize, BuilderImpl &builderImpl) const;
LgcContext *m_lgcContext = nullptr; // LGC context
LLVMContext *m_context = nullptr; // LLVM context
@@ -134,8 +144,10 @@ class VertexFetchImpl : public VertexFetch {
Value *m_instanceIndex = nullptr; // Instance index
bool m_useSoftwareVertexBufferDescriptors = false; // Use software vertex buffer descriptors to structure SRD.
+ bool m_vbAddressLowBitsKnown = false; // Use vertex buffer offset low bits from driver.
static const VertexCompFormatInfo m_vertexCompFormatInfo[]; // Info table of vertex component format
+ static const VertexNumFormatInfo m_vertexNumFormatInfo[]; // Info table of vertex num format
static const unsigned char m_vertexFormatMapGfx10[][9]; // Info table of vertex format mapping for GFX10
static const unsigned char m_vertexFormatMapGfx11[][9]; // Info table of vertex format mapping for GFX11
@@ -155,6 +167,20 @@ class VertexFetchImpl : public VertexFetch {
// =====================================================================================================================
// Internal tables
+// Initializes info table of vertex numerical format map
+// <isSigned, isScaled, isNorm>
+const VertexNumFormatInfo VertexFetchImpl::m_vertexNumFormatInfo[] = {
+ {false, false, true}, // BUF_NUM_FORMAT_UNORM
+ {true, false, true}, // BUF_NUM_FORMAT_SNORM
+ {false, true, false}, // BUF_NUM_FORMAT_USCALED
+ {true, true, false}, // BUF_NUM_FORMAT_SSCALED
+ {false, false, false}, // BUF_NUM_FORMAT_UINT
+ {true, false, false}, // BUF_NUM_FORMAT_SINT
+ {true, false, false}, // BUF_NUM_FORMAT_SNORM_OGL
+ {true, false, false}, // BUF_NUM_FORMAT_FLOAT
+ {true, false, false}, // BUF_NUM_FORMAT_FIXED
+};
+
#define VERTEX_FORMAT_UNDEFINED(_format) \
{ _format, BUF_NUM_FORMAT_FLOAT, BUF_DATA_FORMAT_INVALID, 0, }
@@ -166,24 +192,24 @@ const VertexCompFormatInfo VertexFetchImpl::m_vertexCompFormatInfo[] = {
{2, 1, 2, BUF_DATA_FORMAT_8}, // BUF_DATA_FORMAT_8_8
{4, 4, 1, BUF_DATA_FORMAT_32}, // BUF_DATA_FORMAT_32
{4, 2, 2, BUF_DATA_FORMAT_16}, // BUF_DATA_FORMAT_16_16
- {4, 0, 0, BUF_DATA_FORMAT_10_11_11}, // BUF_DATA_FORMAT_10_11_11 (Packed)
- {4, 0, 0, BUF_DATA_FORMAT_11_11_10}, // BUF_DATA_FORMAT_11_11_10 (Packed)
- {4, 0, 0, BUF_DATA_FORMAT_10_10_10_2}, // BUF_DATA_FORMAT_10_10_10_2 (Packed)
- {4, 0, 0, BUF_DATA_FORMAT_2_10_10_10}, // BUF_DATA_FORMAT_2_10_10_10 (Packed)
+ {4, 0, 3, BUF_DATA_FORMAT_10_11_11}, // BUF_DATA_FORMAT_10_11_11 (Packed)
+ {4, 0, 3, BUF_DATA_FORMAT_11_11_10}, // BUF_DATA_FORMAT_11_11_10 (Packed)
+ {4, 0, 4, BUF_DATA_FORMAT_10_10_10_2}, // BUF_DATA_FORMAT_10_10_10_2 (Packed)
+ {4, 0, 4, BUF_DATA_FORMAT_2_10_10_10}, // BUF_DATA_FORMAT_2_10_10_10 (Packed)
{4, 1, 4, BUF_DATA_FORMAT_8}, // BUF_DATA_FORMAT_8_8_8_8
{8, 4, 2, BUF_DATA_FORMAT_32}, // BUF_DATA_FORMAT_32_32
{8, 2, 4, BUF_DATA_FORMAT_16}, // BUF_DATA_FORMAT_16_16_16_16
{12, 4, 3, BUF_DATA_FORMAT_32}, // BUF_DATA_FORMAT_32_32_32
{16, 4, 4, BUF_DATA_FORMAT_32}, // BUF_DATA_FORMAT_32_32_32_32
{0, 0, 0, BUF_DATA_FORMAT_INVALID}, // BufDataFormatReserved
- {0, 0, 0, BUF_DATA_FORMAT_INVALID}, // BufDataFormat8_8_8_8_Bgra
+ {4, 1, 4, BUF_DATA_FORMAT_8}, // BufDataFormat8_8_8_8_Bgra
{3, 1, 3, BUF_DATA_FORMAT_8}, // BufDataFormat8_8_8
- {0, 0, 0, BUF_DATA_FORMAT_INVALID}, // BufDataFormat8_8_8_Bgr,
- {0, 0, 0, BUF_DATA_FORMAT_INVALID}, // BufDataFormat2_10_10_10_Bgra,
- {0, 0, 0, BUF_DATA_FORMAT_INVALID}, // BufDataFormat64,
- {0, 0, 0, BUF_DATA_FORMAT_INVALID}, // BufDataFormat64_64,
- {0, 0, 0, BUF_DATA_FORMAT_INVALID}, // BufDataFormat64_64_64,
- {0, 0, 0, BUF_DATA_FORMAT_INVALID}, // BufDataFormat64_64_64_64,
+ {3, 0, 3, BUF_DATA_FORMAT_8}, // BufDataFormat8_8_8_Bgr,
+ {4, 0, 4, BUF_DATA_FORMAT_2_10_10_10}, // BufDataFormat2_10_10_10_Bgra,
+ {8, 8, 1, BUF_DATA_FORMAT_32}, // BufDataFormat64,
+ {16, 8, 2, BUF_DATA_FORMAT_32}, // BufDataFormat64_64,
+ {24, 8, 3, BUF_DATA_FORMAT_32}, // BufDataFormat64_64_64,
+ {32, 8, 4, BUF_DATA_FORMAT_32}, // BufDataFormat64_64_64_64,
{0, 0, 0, BUF_DATA_FORMAT_INVALID}, // BufDataFormat4_4,
{0, 0, 0, BUF_DATA_FORMAT_INVALID}, // BufDataFormat4_4_4_4,
{0, 0, 0, BUF_DATA_FORMAT_INVALID}, // BufDataFormat4_4_4_4_Bgra,
@@ -605,7 +631,7 @@ bool LowerVertexFetch::runImpl(Module &module, PipelineState *pipelineState) {
static const auto fetchVisitor = llvm_dialects::VisitorBuilder<SmallVectorImpl<InputImportGenericOp *>>()
.setStrategy(llvm_dialects::VisitorStrategy::ByFunctionDeclaration)
.add<InputImportGenericOp>([](auto &fetches, InputImportGenericOp &op) {
- if (lgc::getShaderStage(op.getFunction()) == ShaderStageVertex)
+ if (lgc::getShaderStage(op.getFunction()) == ShaderStage::Vertex)
fetches.push_back(&op);
})
.build();
@@ -614,16 +640,17 @@ bool LowerVertexFetch::runImpl(Module &module, PipelineState *pipelineState) {
return false;
std::unique_ptr<VertexFetch> vertexFetch(VertexFetch::create(
- pipelineState->getLgcContext(), pipelineState->getOptions().useSoftwareVertexBufferDescriptors));
+ pipelineState->getLgcContext(), pipelineState->getOptions().useSoftwareVertexBufferDescriptors,
+ pipelineState->getOptions().vbAddressLowBitsKnown));
BuilderImpl builder(pipelineState);
if (pipelineState->getOptions().enableUberFetchShader) {
// NOTE: The 10_10_10_2 formats are not supported by the uber fetch shader on gfx9 and older.
// We rely on the driver to fallback to not using the uber fetch shader when those formats are used.
- builder.setShaderStage(ShaderStageVertex);
+ builder.setShaderStage(ShaderStage::Vertex);
builder.SetInsertPointPastAllocas(vertexFetches[0]->getFunction());
- auto desc = builder.CreateLoadBufferDesc(InternalDescriptorSetId, FetchShaderInternalBufferBinding,
- builder.getInt32(0), Builder::BufferFlagAddress);
+ auto desc = builder.CreateBufferDesc(InternalDescriptorSetId, FetchShaderInternalBufferBinding, builder.getInt32(0),
+ Builder::BufferFlagAddress);
auto descPtr = builder.CreateIntToPtr(desc, builder.getPtrTy(ADDR_SPACE_CONST));
@@ -633,7 +660,8 @@ bool LowerVertexFetch::runImpl(Module &module, PipelineState *pipelineState) {
for (InputImportGenericOp *inst : vertexFetches) {
builder.SetInsertPoint(inst);
- Value *vertex = vertexFetch->fetchVertex(inst, descPtr, locationMasks, BuilderBase::get(builder));
+ Value *vertex = vertexFetch->fetchVertex(inst, descPtr, locationMasks, BuilderBase::get(builder),
+ pipelineState->getOptions().disablePerCompFetch);
// Replace and erase this instruction.
inst->replaceAllUsesWith(vertex);
inst->eraseFromParent();
@@ -662,7 +690,7 @@ bool LowerVertexFetch::runImpl(Module &module, PipelineState *pipelineState) {
} else {
// Fetch the vertex.
builder.SetInsertPoint(fetch);
- builder.setShaderStage(ShaderStageVertex);
+ builder.setShaderStage(ShaderStage::Vertex);
vertex = vertexFetch->fetchVertex(fetch->getType(), description, location, component, builder);
}
@@ -743,8 +771,10 @@ bool LowerVertexFetch::runImpl(Module &module, PipelineState *pipelineState) {
// @param descPtr : 64bit address of buffer
// @param locMasks : determine if the attribute data is valid.
// @param builder : Builder to use to insert vertex fetch instructions
+// @param disablePerCompFetch : disable per component fetch
// @returns : vertex
-Value *VertexFetchImpl::fetchVertex(InputImportGenericOp *inst, Value *descPtr, Value *locMasks, BuilderBase &builder) {
+Value *VertexFetchImpl::fetchVertex(InputImportGenericOp *inst, Value *descPtr, Value *locMasks, BuilderBase &builder,
+ bool disablePerCompFetch) {
if (!m_vertexIndex) {
IRBuilderBase::InsertPointGuard ipg(builder);
builder.SetInsertPointPastAllocas(inst->getFunction());
@@ -774,15 +804,22 @@ Value *VertexFetchImpl::fetchVertex(InputImportGenericOp *inst, Value *descPtr,
auto currentBlock = inst->getParent();
auto fetchEndBlock = currentBlock->splitBasicBlock(inst);
- auto fetchUberEndBlock = createBlock(".fetchUberEndBlock", fetchEndBlock);
- auto perCompEndBlock = createBlock(".perCompEnd", fetchUberEndBlock);
- auto comp3Block = createBlock(".comp3Block", perCompEndBlock);
- auto comp2Block = createBlock(".comp2Block", comp3Block);
- auto comp1Block = createBlock(".comp1Block", comp2Block);
- auto comp0Block = createBlock(".comp0Block", comp1Block);
- auto wholeVertexBlock = createBlock(".wholeVertex", comp0Block);
- auto fetchUberStartBlock = createBlock(".fetchUberStartBlock", wholeVertexBlock);
- auto fetchStartBlock = createBlock(".fetchStart", fetchUberStartBlock);
+ BasicBlock *fetchUberEndBlock = createBlock(".fetchUberEndBlock", fetchEndBlock);
+ BasicBlock *perCompEndBlock = nullptr;
+ BasicBlock *comp3Block = nullptr;
+ BasicBlock *comp2Block = nullptr;
+ BasicBlock *comp1Block = nullptr;
+ BasicBlock *comp0Block = nullptr;
+ if (!disablePerCompFetch) {
+ perCompEndBlock = createBlock(".perCompEnd", fetchUberEndBlock);
+ comp3Block = createBlock(".comp3Block", perCompEndBlock);
+ comp2Block = createBlock(".comp2Block", comp3Block);
+ comp1Block = createBlock(".comp1Block", comp2Block);
+ comp0Block = createBlock(".comp0Block", comp1Block);
+ }
+ BasicBlock *wholeVertexBlock = createBlock(".wholeVertex", comp0Block);
+ BasicBlock *fetchUberStartBlock = createBlock(".fetchUberStartBlock", wholeVertexBlock);
+ BasicBlock *fetchStartBlock = createBlock(".fetchStart", fetchUberStartBlock);
unsigned location = inst->getLocation();
auto zero = builder.getInt32(0);
@@ -887,8 +924,12 @@ Value *VertexFetchImpl::fetchVertex(InputImportGenericOp *inst, Value *descPtr,
args.push_back(builder.getInt32(0));
args.push_back(builder.getInt32(0));
- // If ispacked is false, we require per-component fetch
- builder.CreateCondBr(isPacked, wholeVertexBlock, comp0Block);
+ if (disablePerCompFetch) {
+ builder.CreateBr(wholeVertexBlock);
+ } else {
+ // If ispacked is false, we require per-component fetch
+ builder.CreateCondBr(isPacked, wholeVertexBlock, comp0Block);
+ }
// 8-bit vertex fetches use the 16-bit path as well.
bool is16bitFetch = bitWidth <= 16;
@@ -911,147 +952,153 @@ Value *VertexFetchImpl::fetchVertex(InputImportGenericOp *inst, Value *descPtr,
builder.CreateBr(fetchUberEndBlock);
}
- fetchType = FixedVectorType::get(builder.getInt32Ty(), is64bitFetch ? 8 : 4);
- if (is16bitFetch)
- fetchType = FixedVectorType::get(builder.getInt16Ty(), 4);
-
- // Initialize the default values
Value *lastVert = nullptr;
- if (basicTy->isIntegerTy()) {
- if (bitWidth <= 16)
- lastVert = m_fetchDefaults.int16;
- else if (bitWidth == 32)
- lastVert = m_fetchDefaults.int32;
- else {
- assert(bitWidth == 64);
- lastVert = m_fetchDefaults.int64;
- }
- } else if (basicTy->isFloatingPointTy()) {
- if (bitWidth == 16)
- lastVert = m_fetchDefaults.float16;
- else if (bitWidth == 32)
- lastVert = m_fetchDefaults.float32;
- else {
- assert(bitWidth == 64);
- lastVert = m_fetchDefaults.double64;
+ if (!disablePerCompFetch) {
+ fetchType = FixedVectorType::get(builder.getInt32Ty(), is64bitFetch ? 8 : 4);
+ if (is16bitFetch)
+ fetchType = FixedVectorType::get(builder.getInt16Ty(), 4);
+
+ // Initialize the default values
+ if (basicTy->isIntegerTy()) {
+ if (bitWidth <= 16)
+ lastVert = m_fetchDefaults.int16;
+ else if (bitWidth == 32)
+ lastVert = m_fetchDefaults.int32;
+ else {
+ assert(bitWidth == 64);
+ lastVert = m_fetchDefaults.int64;
+ }
+ } else if (basicTy->isFloatingPointTy()) {
+ if (bitWidth == 16)
+ lastVert = m_fetchDefaults.float16;
+ else if (bitWidth == 32)
+ lastVert = m_fetchDefaults.float32;
+ else {
+ assert(bitWidth == 64);
+ lastVert = m_fetchDefaults.double64;
+ }
+ } else
+ llvm_unreachable("Should never be called!");
+
+ Value *comp0 = nullptr;
+ Value *comp1 = nullptr;
+ Value *comp2 = nullptr;
+ Value *comp3 = nullptr;
+ auto compType = is16bitFetch ? builder.getInt16Ty() : builder.getInt32Ty();
+
+ // Per-component fetch
+ // X channel
+ // .comp0Block
+ {
+ builder.SetInsertPoint(comp0Block);
+
+ args[offsetIdx] = byteOffset;
+ if (is64bitFetch) {
+ Value *comp = builder.CreateIntrinsic(instId, fetch64Type, args, {});
+ Value *elem = builder.CreateExtractElement(comp, uint64_t(0));
+ lastVert = builder.CreateInsertElement(lastVert, elem, uint64_t(0));
+ elem = builder.CreateExtractElement(comp, 1);
+ lastVert = builder.CreateInsertElement(lastVert, elem, 1);
+ comp0 = lastVert;
+ } else {
+ comp0 = builder.CreateIntrinsic(instId, compType, args, {});
+ lastVert = builder.CreateInsertElement(lastVert, comp0, uint64_t(0));
+ comp0 = lastVert;
+ }
+ // If Y channel is 0, we will fetch the second component.
+ builder.CreateCondBr(yMask, comp1Block, perCompEndBlock);
}
- } else
- llvm_unreachable("Should never be called!");
-
- Value *comp0 = nullptr;
- Value *comp1 = nullptr;
- Value *comp2 = nullptr;
- Value *comp3 = nullptr;
- auto compType = is16bitFetch ? builder.getInt16Ty() : builder.getInt32Ty();
-
- // Per-component fetch
- // X channel
- // .comp0Block
- {
- builder.SetInsertPoint(comp0Block);
- args[offsetIdx] = byteOffset;
- if (is64bitFetch) {
- Value *comp = builder.CreateIntrinsic(instId, fetch64Type, args, {});
- Value *elem = builder.CreateExtractElement(comp, uint64_t(0));
- lastVert = builder.CreateInsertElement(lastVert, elem, uint64_t(0));
- elem = builder.CreateExtractElement(comp, 1);
- lastVert = builder.CreateInsertElement(lastVert, elem, 1);
- comp0 = lastVert;
- } else {
- comp0 = builder.CreateIntrinsic(instId, compType, args, {});
- lastVert = builder.CreateInsertElement(lastVert, comp0, uint64_t(0));
- comp0 = lastVert;
+ // Y channel
+ // .comp1Block
+ {
+ builder.SetInsertPoint(comp1Block);
+ // Add offset. offset = offset + componentSize
+ args[offsetIdx] = builder.CreateAdd(args[offsetIdx], componentSize);
+ if (is64bitFetch) {
+ Value *comp = builder.CreateIntrinsic(instId, fetch64Type, args, {});
+ Value *elem = builder.CreateExtractElement(comp, uint64_t(0));
+ lastVert = builder.CreateInsertElement(lastVert, elem, 2);
+ elem = builder.CreateExtractElement(comp, 1);
+ lastVert = builder.CreateInsertElement(lastVert, elem, 3);
+ comp1 = lastVert;
+ } else {
+ comp1 = builder.CreateIntrinsic(instId, compType, args, {});
+ lastVert = builder.CreateInsertElement(lastVert, comp1, 1);
+ comp1 = lastVert;
+ }
+ builder.CreateCondBr(zMask, comp2Block, perCompEndBlock);
}
- // If Y channel is 0, we will fetch the second component.
- builder.CreateCondBr(yMask, comp1Block, perCompEndBlock);
- }
- // Y channel
- // .comp1Block
- {
- builder.SetInsertPoint(comp1Block);
- // Add offset. offset = offset + componentSize
- args[offsetIdx] = builder.CreateAdd(args[offsetIdx], componentSize);
- if (is64bitFetch) {
- Value *comp = builder.CreateIntrinsic(instId, fetch64Type, args, {});
- Value *elem = builder.CreateExtractElement(comp, uint64_t(0));
- lastVert = builder.CreateInsertElement(lastVert, elem, 2);
- elem = builder.CreateExtractElement(comp, 1);
- lastVert = builder.CreateInsertElement(lastVert, elem, 3);
- comp1 = lastVert;
- } else {
- comp1 = builder.CreateIntrinsic(instId, compType, args, {});
- lastVert = builder.CreateInsertElement(lastVert, comp1, 1);
- comp1 = lastVert;
+ // Z channel
+ // .comp2Block
+ {
+ builder.SetInsertPoint(comp2Block);
+ args[offsetIdx] = builder.CreateAdd(args[offsetIdx], componentSize);
+ if (is64bitFetch) {
+ Value *comp = builder.CreateIntrinsic(instId, fetch64Type, args, {});
+ Value *elem = builder.CreateExtractElement(comp, uint64_t(0));
+ lastVert = builder.CreateInsertElement(lastVert, elem, 4);
+ elem = builder.CreateExtractElement(comp, 1);
+ lastVert = builder.CreateInsertElement(lastVert, elem, 5);
+ comp2 = lastVert;
+ } else {
+ comp2 = builder.CreateIntrinsic(instId, compType, args, {});
+ lastVert = builder.CreateInsertElement(lastVert, comp2, 2);
+ comp2 = lastVert;
+ }
+ builder.CreateCondBr(wMask, comp3Block, perCompEndBlock);
}
- builder.CreateCondBr(zMask, comp2Block, perCompEndBlock);
- }
- // Z channel
- // .comp2Block
- {
- builder.SetInsertPoint(comp2Block);
- args[offsetIdx] = builder.CreateAdd(args[offsetIdx], componentSize);
- if (is64bitFetch) {
- Value *comp = builder.CreateIntrinsic(instId, fetch64Type, args, {});
- Value *elem = builder.CreateExtractElement(comp, uint64_t(0));
- lastVert = builder.CreateInsertElement(lastVert, elem, 4);
- elem = builder.CreateExtractElement(comp, 1);
- lastVert = builder.CreateInsertElement(lastVert, elem, 5);
- comp2 = lastVert;
- } else {
- comp2 = builder.CreateIntrinsic(instId, compType, args, {});
- lastVert = builder.CreateInsertElement(lastVert, comp2, 2);
- comp2 = lastVert;
+ // W channel
+ // .comp3Block
+ {
+ builder.SetInsertPoint(comp3Block);
+ args[offsetIdx] = builder.CreateAdd(args[offsetIdx], componentSize);
+ if (is64bitFetch) {
+ Value *comp = builder.CreateIntrinsic(instId, fetch64Type, args, {});
+ Value *elem = builder.CreateExtractElement(comp, uint64_t(0));
+ lastVert = builder.CreateInsertElement(lastVert, elem, 6);
+ elem = builder.CreateExtractElement(comp, 1);
+ lastVert = builder.CreateInsertElement(lastVert, elem, 7);
+ comp3 = lastVert;
+ } else {
+ comp3 = builder.CreateIntrinsic(instId, compType, args, {});
+ lastVert = builder.CreateInsertElement(lastVert, comp3, 3);
+ comp3 = lastVert;
+ }
+ builder.CreateBr(perCompEndBlock);
}
- builder.CreateCondBr(wMask, comp3Block, perCompEndBlock);
- }
- // W channel
- // .comp3Block
- {
- builder.SetInsertPoint(comp3Block);
- args[offsetIdx] = builder.CreateAdd(args[offsetIdx], componentSize);
- if (is64bitFetch) {
- Value *comp = builder.CreateIntrinsic(instId, fetch64Type, args, {});
- Value *elem = builder.CreateExtractElement(comp, uint64_t(0));
- lastVert = builder.CreateInsertElement(lastVert, elem, 6);
- elem = builder.CreateExtractElement(comp, 1);
- lastVert = builder.CreateInsertElement(lastVert, elem, 7);
- comp3 = lastVert;
- } else {
- comp3 = builder.CreateIntrinsic(instId, compType, args, {});
- lastVert = builder.CreateInsertElement(lastVert, comp3, 3);
- comp3 = lastVert;
+ // .perCompEnd
+ {
+ builder.SetInsertPoint(perCompEndBlock);
+ auto phiInst = builder.CreatePHI(lastVert->getType(), 4);
+ phiInst->addIncoming(comp0, comp0Block);
+ phiInst->addIncoming(comp1, comp1Block);
+ phiInst->addIncoming(comp2, comp2Block);
+ phiInst->addIncoming(comp3, comp3Block);
+ lastVert = phiInst;
+ // If the format is bgr, fix the order. It only is included in 32-bit format.
+ if (!is64bitFetch) {
+ auto fixedVertex = builder.CreateShuffleVector(lastVert, lastVert, ArrayRef<int>{2, 1, 0, 3});
+ lastVert = builder.CreateSelect(isBgr, fixedVertex, lastVert);
+ }
+ builder.CreateBr(fetchUberEndBlock);
}
- builder.CreateBr(perCompEndBlock);
- }
- // .perCompEnd
- {
- builder.SetInsertPoint(perCompEndBlock);
- auto phiInst = builder.CreatePHI(lastVert->getType(), 4);
- phiInst->addIncoming(comp0, comp0Block);
- phiInst->addIncoming(comp1, comp1Block);
- phiInst->addIncoming(comp2, comp2Block);
- phiInst->addIncoming(comp3, comp3Block);
+ // .fetchUberEndBlock
+ builder.SetInsertPoint(fetchUberEndBlock);
+ auto phiInst = builder.CreatePHI(lastVert->getType(), 2);
+ phiInst->addIncoming(wholeVertex, wholeVertexBlock);
+ phiInst->addIncoming(lastVert, perCompEndBlock);
lastVert = phiInst;
- // If the format is bgr, fix the order. It only is included in 32-bit format.
- if (!is64bitFetch) {
- auto fixedVertex = builder.CreateShuffleVector(lastVert, lastVert, ArrayRef<int>{2, 1, 0, 3});
- lastVert = builder.CreateSelect(isBgr, fixedVertex, lastVert);
- }
- builder.CreateBr(fetchUberEndBlock);
+ } else {
+ // .fetchUberEndBlock
+ builder.SetInsertPoint(fetchUberEndBlock);
+ lastVert = wholeVertex;
}
- // .fetchUberEndBlock
- builder.SetInsertPoint(fetchUberEndBlock);
- auto phiInst = builder.CreatePHI(lastVert->getType(), 2);
- phiInst->addIncoming(wholeVertex, wholeVertexBlock);
- phiInst->addIncoming(lastVert, perCompEndBlock);
- lastVert = phiInst;
-
// Get vertex fetch values
const unsigned fetchCompCount = cast<FixedVectorType>(lastVert->getType())->getNumElements();
std::vector<Value *> fetchValues(fetchCompCount);
@@ -1125,17 +1172,20 @@ Value *VertexFetchImpl::fetchVertex(InputImportGenericOp *inst, Value *descPtr,
// =====================================================================================================================
// Create a VertexFetch
-VertexFetch *VertexFetch::create(LgcContext *lgcContext, bool useSoftwareVertexBufferDescriptors) {
- return new VertexFetchImpl(lgcContext, useSoftwareVertexBufferDescriptors);
+VertexFetch *VertexFetch::create(LgcContext *lgcContext, bool useSoftwareVertexBufferDescriptors,
+ bool vbAddressLowBitsKnown) {
+ return new VertexFetchImpl(lgcContext, useSoftwareVertexBufferDescriptors, vbAddressLowBitsKnown);
}
// =====================================================================================================================
// Constructor
//
// @param context : LLVM context
-VertexFetchImpl::VertexFetchImpl(LgcContext *lgcContext, bool useSoftwareVertexBufferDescriptors)
+VertexFetchImpl::VertexFetchImpl(LgcContext *lgcContext, bool useSoftwareVertexBufferDescriptors,
+ bool vbAddressLowBitsKnown)
: m_lgcContext(lgcContext), m_context(&lgcContext->getContext()),
- m_useSoftwareVertexBufferDescriptors(useSoftwareVertexBufferDescriptors) {
+ m_useSoftwareVertexBufferDescriptors(useSoftwareVertexBufferDescriptors),
+ m_vbAddressLowBitsKnown(vbAddressLowBitsKnown) {
// Initialize default fetch values
auto zero = ConstantInt::get(Type::getInt32Ty(*m_context), 0);
@@ -1175,6 +1225,25 @@ VertexFetchImpl::VertexFetchImpl(LgcContext *lgcContext, bool useSoftwareVertexB
m_fetchDefaults.double64 = ConstantVector::get({zero, zero, zero, zero, zero, zero, doubleOne0, doubleOne1});
}
+// =====================================================================================================================
+// Get vertex fetch related types referred to their type bit width. For 64 bit type, we do 32 bit fetch instead.
+//
+// @param isFloat : Whether target type is a float point type.
+// @param byteSize : Byte (8 bit) size of target Type.
+// @param builderImpl : BuilderImpl to use to insert vertex fetch instructions.
+Type *VertexFetchImpl::getVertexFetchType(bool isFloat, unsigned byteSize, BuilderImpl &builderImpl) const {
+ assert(byteSize == 1 || byteSize == 2 || byteSize == 4 || byteSize == 8);
+ if (byteSize == 1) {
+ assert(!isFloat);
+ return builderImpl.getInt8Ty();
+ } else if (byteSize == 2) {
+ return isFloat ? builderImpl.getHalfTy() : builderImpl.getInt16Ty();
+ } else {
+ // HW doesn't support 64bit fetch intrinsics, hence we will use 32bit fetch for double times.
+ return isFloat ? builderImpl.getFloatTy() : builderImpl.getInt32Ty();
+ }
+}
+
// =====================================================================================================================
// Executes vertex fetch operations based on the specified vertex input type and its location.
//
@@ -1191,8 +1260,7 @@ Value *VertexFetchImpl::fetchVertex(Type *inputTy, const VertexInputDescription
auto vbDesc = loadVertexBufferDescriptor(description->binding, builderImpl);
Value *srdStride = nullptr;
if (m_useSoftwareVertexBufferDescriptors)
- std::tie(vbDesc, srdStride) = convertSrdToOffsetMode(vbDesc, builder);
-
+ std::tie(vbDesc, srdStride) = convertSrdToOffsetMode(vbDesc, builderImpl);
Value *vbIndex = nullptr;
if (description->inputRate == VertexInputRateVertex) {
// Use vertex index
@@ -1221,302 +1289,120 @@ Value *VertexFetchImpl::fetchVertex(Type *inputTy, const VertexInputDescription
}
}
- Value *vertexFetches[2] = {}; // Two vertex fetch operations might be required
- Value *vertexFetch = nullptr; // Coalesced vector by combining the results of two vertex fetch operations
+ Value *vertexFetch = nullptr;
- VertexFormatInfo formatInfo = getVertexFormatInfo(description);
+ // Conponent format and numeric format info.
+ const VertexCompFormatInfo *compFormatInfo = getVertexComponentFormatInfo(description->dfmt);
+ const VertexNumFormatInfo *numFormatInfo = getVertexNumericFormatInfo(description->nfmt);
- const bool is16bitFetch = (inputTy->getScalarSizeInBits() <= 16);
+ // Input components' type
+ Type *inputCompTy = inputTy->isVectorTy() ? cast<VectorType>(inputTy)->getElementType() : inputTy;
+ unsigned inputCompBytes = std::max(inputCompTy->getScalarSizeInBits() / 8, compFormatInfo->compByteSize);
- // Do the first vertex fetch operation
- addVertexFetchInst(vbDesc, formatInfo.numChannels, is16bitFetch, vbIndex, srdStride, description->offset,
- description->stride, formatInfo.dfmt, formatInfo.nfmt, insertPos, &vertexFetches[0]);
+ // Location size of components. If its type is Double, each component consumes 2 locations.
+ const unsigned compLocationSize = (inputCompBytes + 3) / 4;
+ compIdx *= compLocationSize;
- // Do post-processing in certain cases
- std::vector<Constant *> shuffleMask;
- bool postShuffle = needPostShuffle(description, shuffleMask);
- bool patch32 = needPatch32(description);
- if (postShuffle || patch32) {
- if (postShuffle) {
- // NOTE: If we are fetching a swizzled format, we have to add an extra "shufflevector" instruction to
- // get the components in the right order.
- assert(shuffleMask.empty() == false);
- vertexFetches[0] =
- new ShuffleVectorInst(vertexFetches[0], vertexFetches[0], ConstantVector::get(shuffleMask), "", insertPos);
- }
+ // For Double type, we still do 32 bit fetch.
+ inputCompBytes /= compLocationSize;
- if (patch32) {
- bool isSigned = (description->nfmt == BufNumFormatSscaled || description->nfmt == BufNumFormatSnorm ||
- description->nfmt == BufNumFormatFixed);
-
- // Whether need to do normalization emulation.
- bool isNorm = (description->nfmt == BufNumFormatSnorm || description->nfmt == BufNumFormatUnorm);
-
- // Whether need to do fixed point emulation
- bool isFixed = (description->nfmt == BufNumFormatFixed);
-
- // Whether need to translate from int bits to float bits.
- bool needTransToFp = (description->nfmt == BufNumFormatSscaled || description->nfmt == BufNumFormatSnorm ||
- description->nfmt == BufNumFormatUscaled || description->nfmt == BufNumFormatUnorm);
-
- // Only for 32 bits format patch and emulation.
- for (unsigned i = 0; i < formatInfo.numChannels; ++i) {
- Value *elemInstr = ExtractElementInst::Create(vertexFetches[0],
- ConstantInt::get(Type::getInt32Ty(*m_context), i), "", insertPos);
- if (needTransToFp) {
- // A constant divisor for normalization emulation.
- float normDiv = 2.14748365e+09f;
- if (isSigned) {
- // Signed int to float
- elemInstr = new SIToFPInst(elemInstr, Type::getFloatTy(*m_context), "", insertPos);
- } else {
- // Unsigned int to float
- elemInstr = new UIToFPInst(elemInstr, Type::getFloatTy(*m_context), "", insertPos);
- normDiv = 4.29496730e+09f;
- }
- if (isNorm) {
- // Normalization emulation.
- elemInstr = BinaryOperator::CreateFDiv(elemInstr, ConstantFP::get(Type::getFloatTy(*m_context), normDiv),
- "", insertPos);
- }
- } else if (isFixed) {
- // A constant divisor to translate loaded float bits to fixed point format.
- float fixedPointMul = 1.0f / 65536.0f;
- elemInstr = new SIToFPInst(elemInstr, Type::getFloatTy(*m_context), "", insertPos);
- elemInstr = BinaryOperator::CreateFMul(
- elemInstr, ConstantFP::get(Type::getFloatTy(*m_context), fixedPointMul), "", insertPos);
- } else {
- llvm_unreachable("Should never be called!");
- }
+ // Whether it is fetching with a packed format.
+ bool isPacked = (compFormatInfo->compByteSize == 0);
- elemInstr = new BitCastInst(elemInstr, Type::getInt32Ty(*m_context), "", insertPos);
- vertexFetches[0] = InsertElementInst::Create(vertexFetches[0], elemInstr,
- ConstantInt::get(Type::getInt32Ty(*m_context), i), "", insertPos);
- }
- }
- }
+ // If its a packed format, fetch in i32Vec4 type.
+ uint32_t fetchCompBytes = isPacked ? 4 : compFormatInfo->compByteSize / compLocationSize;
+ unsigned numChannels = compLocationSize * compFormatInfo->compCount;
- // Do the second vertex fetch operation
- const bool secondFetch = needSecondVertexFetch(description);
- if (secondFetch) {
- unsigned numChannels = formatInfo.numChannels;
- unsigned dfmt = formatInfo.dfmt;
-
- if (description->dfmt == BufDataFormat64_64_64) {
- // Valid number of channels and data format have to be revised
- numChannels = 2;
- dfmt = BUF_DATA_FORMAT_32_32;
- }
-
- addVertexFetchInst(vbDesc, numChannels, is16bitFetch, vbIndex, srdStride, description->offset + SizeOfVec4,
- description->stride, dfmt, formatInfo.nfmt, insertPos, &vertexFetches[1]);
+ // Basically, do fetch in component, and in some special cases, we do fetch in Byte for alignment purpose.
+ bool fetchInByte = false;
+ if (m_vbAddressLowBitsKnown) {
+ const uint32_t firstInstanceOffset = description->vbAddrLowBits + description->offset;
+ const uint32_t alignStride = (description->stride == 0) ? fetchCompBytes : description->stride;
+ fetchInByte =
+ (firstInstanceOffset % fetchCompBytes != 0 || (firstInstanceOffset + alignStride) % fetchCompBytes != 0);
}
- if (secondFetch) {
- // NOTE: If we performs vertex fetch operations twice, we have to coalesce result values of the two
- // fetch operations and generate a combined one.
- assert(vertexFetches[0] && vertexFetches[1]);
- assert(cast<FixedVectorType>(vertexFetches[0]->getType())->getNumElements() == 4);
-
- unsigned compCount = cast<FixedVectorType>(vertexFetches[1]->getType())->getNumElements();
- assert(compCount == 2 || compCount == 4); // Should be <2 x i32> or <4 x i32>
-
- if (compCount == 2) {
- // NOTE: We have to enlarge the second vertex fetch, from <2 x i32> to <4 x i32>. Otherwise,
- // vector shuffle operation could not be performed in that it requires the two vectors have
- // the same types.
-
- // %vf1 = shufflevector %vf1, %vf1, <0, 1, undef, undef>
- Constant *shuffleMask[] = {
- ConstantInt::get(Type::getInt32Ty(*m_context), 0), ConstantInt::get(Type::getInt32Ty(*m_context), 1),
- PoisonValue::get(Type::getInt32Ty(*m_context)), PoisonValue::get(Type::getInt32Ty(*m_context))};
- vertexFetches[1] =
- new ShuffleVectorInst(vertexFetches[1], vertexFetches[1], ConstantVector::get(shuffleMask), "", insertPos);
- }
+ // After back-end optimization, intrinsics may be combined to fetch the whole vertex in generated ISA codes.
+ // To make sure combination works, we need to keep tbuffer_load formats as same as possible when visit this function.
+ // To avoid redundant extract and insert operation, we need to keep component bit width as same as input component.
+ addVertexFetchInst(vbDesc, vbIndex, srdStride, numChannels, description->offset, compFormatInfo->fetchDfmt,
+ description->nfmt, inputCompBytes, fetchCompBytes, numFormatInfo->isSigned, isPacked, fetchInByte,
+ builderImpl, &vertexFetch);
- // %vf = shufflevector %vf0, %vf1, <0, 1, 2, 3, 4, 5, ...>
- shuffleMask.clear();
- for (unsigned i = 0; i < 4 + compCount; ++i)
- shuffleMask.push_back(ConstantInt::get(Type::getInt32Ty(*m_context), i));
- vertexFetch =
- new ShuffleVectorInst(vertexFetches[0], vertexFetches[1], ConstantVector::get(shuffleMask), "", insertPos);
- } else
- vertexFetch = vertexFetches[0];
+ // When do fetch in Byte, we need to emulate final results manually.
+ postFetchEmulation(description, fetchInByte, inputCompBytes, numChannels, numFormatInfo, compFormatInfo, builderImpl,
+ &vertexFetch);
// Finalize vertex fetch
- Type *basicTy = inputTy->isVectorTy() ? cast<VectorType>(inputTy)->getElementType() : inputTy;
- bool needDoubleEmulation =
- description->dfmt >= BufDataFormat64 && description->dfmt <= BufDataFormat64_64_64_64 && basicTy->isFloatTy();
- if (needDoubleEmulation)
- basicTy = Type::getDoubleTy(*m_context);
- const unsigned bitWidth = basicTy->getScalarSizeInBits();
- assert(bitWidth == 8 || bitWidth == 16 || bitWidth == 32 || bitWidth == 64);
-
- // Get default fetch values
- Constant *defaults = nullptr;
-
- if (basicTy->isIntegerTy()) {
- if (bitWidth <= 16)
- defaults = m_fetchDefaults.int16;
- else if (bitWidth == 32)
- defaults = m_fetchDefaults.int32;
- else {
- assert(bitWidth == 64);
- defaults = m_fetchDefaults.int64;
- }
- } else if (basicTy->isFloatingPointTy()) {
- if (bitWidth == 16)
- defaults = m_fetchDefaults.float16;
- else if (bitWidth == 32)
- defaults = m_fetchDefaults.float32;
- else {
- assert(bitWidth == 64);
- defaults = m_fetchDefaults.double64;
- }
- } else
- llvm_unreachable("Should never be called!");
+ Type *vertexCompTy = getVertexFetchType(false, inputCompBytes, builderImpl);
- const unsigned defaultCompCount = cast<FixedVectorType>(defaults->getType())->getNumElements();
- std::vector<Value *> defaultValues(defaultCompCount);
-
- for (unsigned i = 0; i < defaultValues.size(); ++i) {
- defaultValues[i] =
- ExtractElementInst::Create(defaults, ConstantInt::get(Type::getInt32Ty(*m_context), i), "", insertPos);
- }
-
- // Get vertex fetch values
- const unsigned fetchCompCount =
+ unsigned fetchCompCount =
vertexFetch->getType()->isVectorTy() ? cast<FixedVectorType>(vertexFetch->getType())->getNumElements() : 1;
- std::vector<Value *> fetchValues(fetchCompCount);
-
- if (fetchCompCount == 1)
- fetchValues[0] = vertexFetch;
- else {
- for (unsigned i = 0; i < fetchCompCount; ++i) {
- fetchValues[i] =
- ExtractElementInst::Create(vertexFetch, ConstantInt::get(Type::getInt32Ty(*m_context), i), "", insertPos);
- }
- }
-
- // Construct vertex fetch results
const unsigned inputCompCount = inputTy->isVectorTy() ? cast<FixedVectorType>(inputTy)->getNumElements() : 1;
- const unsigned vertexCompCount = inputCompCount * (bitWidth == 64 ? 2 : 1);
-
- std::vector<Value *> vertexValues(vertexCompCount);
-
- // NOTE: Original component index is based on the basic scalar type.
- compIdx *= (bitWidth == 64 ? 2 : 1);
-
- // Vertex input might take values from vertex fetch values or default fetch values
- for (unsigned i = 0; i < vertexCompCount; i++) {
- if (compIdx + i < fetchCompCount)
- vertexValues[i] = fetchValues[compIdx + i];
- else if (compIdx + i < defaultCompCount)
- vertexValues[i] = defaultValues[compIdx + i];
- else {
- llvm_unreachable("Should never be called!");
- vertexValues[i] = PoisonValue::get(Type::getInt32Ty(*m_context));
+ unsigned vertexCompCount = inputCompCount * compLocationSize;
+ unsigned insertCompCount = std::min(vertexCompCount, fetchCompCount - compIdx);
+
+ // Final fetch results may be constructed by fetched values and default values.
+ unsigned elemIdx = 0;
+ vertex = PoisonValue::get(FixedVectorType::get(vertexCompTy, vertexCompCount));
+ if (vertexCompCount == 1) {
+ // If compIdx is larger than fetchCompCount, assign a default value to it later (depending on compIdx).
+ if (compIdx < fetchCompCount) {
+ vertex = fetchCompCount > 1 ? builderImpl.CreateExtractElement(vertexFetch, builderImpl.getInt32(compIdx))
+ : vertexFetch;
+ elemIdx++;
}
- }
-
- if (vertexCompCount == 1)
- vertex = vertexValues[0];
- else {
- Type *vertexTy = is16bitFetch ? FixedVectorType::get(Type::getInt16Ty(*m_context), vertexCompCount)
- : FixedVectorType::get(Type::getInt32Ty(*m_context), vertexCompCount);
- vertex = PoisonValue::get(vertexTy);
-
- for (unsigned i = 0; i < vertexCompCount; ++i) {
- vertex = InsertElementInst::Create(vertex, vertexValues[i], ConstantInt::get(Type::getInt32Ty(*m_context), i), "",
- insertPos);
+ } else {
+ if (numChannels > 1) {
+ for (; elemIdx < insertCompCount; ++elemIdx) {
+ Value *elemVal = builderImpl.CreateExtractElement(vertexFetch, builderImpl.getInt32(elemIdx + compIdx));
+ vertex = builderImpl.CreateInsertElement(vertex, elemVal, builderImpl.getInt32(elemIdx));
+ }
+ } else {
+ vertex = builderImpl.CreateInsertElement(vertex, vertexFetch, builderImpl.getInt32(elemIdx));
+ elemIdx++;
}
}
- const bool is8bitFetch = (inputTy->getScalarSizeInBits() == 8);
- if (is8bitFetch) {
- // NOTE: The vertex fetch results are represented as <n x i16> now. For 8-bit vertex fetch, we have to
- // convert them to <n x i8> and the 8 high bits is truncated.
- assert(inputTy->isIntOrIntVectorTy()); // Must be integer type
-
- Type *vertexTy = vertex->getType();
- Type *truncTy = Type::getInt8Ty(*m_context);
- truncTy = vertexTy->isVectorTy()
- ? cast<Type>(FixedVectorType::get(truncTy, cast<FixedVectorType>(vertexTy)->getNumElements()))
- : truncTy;
- vertex = new TruncInst(vertex, truncTy, "", insertPos);
+ // Append default zero to unused channels.
+ Value *defaultZero = ConstantInt::get(vertexCompTy, 0);
+ for (; elemIdx < vertexCompCount - compLocationSize; ++elemIdx) {
+ vertex = builderImpl.CreateInsertElement(vertex, defaultZero, builderImpl.getInt32(elemIdx));
}
- if (needDoubleEmulation) {
+ if (compLocationSize == 2 && inputCompTy->isFloatTy()) {
// SPIR-V extended format emulation
// If input type is float32 but vertex attribute data format is float64, we need another float point trunc step.
- int vecSize = cast<FixedVectorType>(vertex->getType())->getNumElements() / 2;
- vertex = new BitCastInst(vertex, FixedVectorType::get(Type::getDoubleTy(*m_context), vecSize), "", insertPos);
- vertex = new FPTruncInst(vertex, FixedVectorType::get(Type::getFloatTy(*m_context), vecSize), "", insertPos);
+ vertex = builderImpl.CreateBitCast(vertex, FixedVectorType::get(builderImpl.getDoubleTy(), vertexCompCount / 2));
+ vertex = builderImpl.CreateFPTrunc(vertex, FixedVectorType::get(builderImpl.getFloatTy(), vertexCompCount / 2));
}
if (vertex->getType() != inputTy)
- vertex = new BitCastInst(vertex, inputTy, "", insertPos);
+ vertex = builderImpl.CreateBitCast(vertex, inputTy);
+
+ // Last default value may be zero or one, depending on component index and result channel number.
+ if (elemIdx == vertexCompCount - compLocationSize) {
+ elemIdx = elemIdx / compLocationSize;
+ bool isOne = (elemIdx + compIdx == 3);
+ Value *lastDefaultVal = nullptr;
+ if (inputCompTy->isIntegerTy()) {
+ lastDefaultVal = ConstantInt::get(inputCompTy, isOne ? 1 : 0);
+ } else if (inputCompTy->isFloatingPointTy()) {
+ lastDefaultVal = ConstantFP::get(inputCompTy, isOne ? 1.0 : 0);
+ } else
+ llvm_unreachable("Should never be called!");
+
+ if (vertexCompCount > 1)
+ vertex = builderImpl.CreateInsertElement(vertex, lastDefaultVal, builderImpl.getInt32(elemIdx));
+ else
+ vertex = lastDefaultVal;
+ }
+
vertex->setName("vertex" + Twine(location) + "." + Twine(compIdx));
return vertex;
}
-// =====================================================================================================================
-// Gets info from table according to vertex attribute format.
-//
-// @param inputDesc : Vertex input description
-VertexFormatInfo VertexFetchImpl::getVertexFormatInfo(const VertexInputDescription *inputDesc) {
- VertexFormatInfo info = {static_cast<BufNumFormat>(inputDesc->nfmt), static_cast<BufDataFormat>(inputDesc->dfmt), 1};
- switch (inputDesc->dfmt) {
- case BufDataFormat8_8:
- case BufDataFormat16_16:
- case BufDataFormat32_32:
- info.numChannels = 2;
- break;
- case BufDataFormat32_32_32:
- case BufDataFormat10_11_11:
- case BufDataFormat11_11_10:
- info.numChannels = 3;
- break;
- case BufDataFormat8_8_8_8:
- case BufDataFormat16_16_16_16:
- case BufDataFormat32_32_32_32:
- case BufDataFormat10_10_10_2:
- case BufDataFormat2_10_10_10:
- info.numChannels = 4;
- break;
- case BufDataFormat8_8_8_8_Bgra:
- info.numChannels = 4;
- info.dfmt = BufDataFormat8_8_8_8;
- break;
- case BufDataFormat2_10_10_10_Bgra:
- info.numChannels = 4;
- info.dfmt = BufDataFormat2_10_10_10;
- break;
- case BufDataFormat64:
- info.numChannels = 2;
- info.dfmt = BufDataFormat32_32;
- break;
- case BufDataFormat64_64:
- case BufDataFormat64_64_64:
- case BufDataFormat64_64_64_64:
- info.numChannels = 4;
- info.dfmt = BufDataFormat32_32_32_32;
- break;
- case BufDataFormat8_8_8:
- info.dfmt = BufDataFormat8_8_8;
- info.numChannels = 3;
- break;
- case BufDataFormat16_16_16:
- info.dfmt = BufDataFormat16_16_16;
- info.numChannels = 3;
- break;
- default:
- break;
- }
- return info;
-}
-
// =====================================================================================================================
// Gets component info from table according to vertex buffer data format.
//
@@ -1526,6 +1412,15 @@ const VertexCompFormatInfo *VertexFetchImpl::getVertexComponentFormatInfo(unsign
return &m_vertexCompFormatInfo[dfmt];
}
+// =====================================================================================================================
+// Gets format property info from table according to vertex buffer num format.
+//
+// @param nfmt : Numeric format of vertex buffer
+const VertexNumFormatInfo *VertexFetchImpl::getVertexNumericFormatInfo(unsigned nfmt) {
+ assert(nfmt < sizeof(m_vertexNumFormatInfo) / sizeof(m_vertexNumFormatInfo[0]));
+ return &m_vertexNumFormatInfo[nfmt];
+}
+
// =====================================================================================================================
// Maps separate buffer data and numeric formats to the combined buffer format
//
@@ -1559,6 +1454,43 @@ unsigned VertexFetchImpl::mapVertexFormat(unsigned dfmt, unsigned nfmt) const {
return format;
}
+// =====================================================================================================================
+// Checks whether bit extraction is required for packed format when do fetch in Byte.
+//
+// @param inputDesc : Vertex input description.
+// @param [out] extractMask : Bits extract mask.
+bool VertexFetchImpl::needPackFormatEmulation(const VertexInputDescription *inputDesc,
+ std::vector<unsigned> &extractMask) const {
+ switch (inputDesc->dfmt) {
+ case BufDataFormat10_11_11:
+ extractMask.push_back(11);
+ extractMask.push_back(10);
+ extractMask.push_back(10);
+ return true;
+ case BufDataFormat11_11_10:
+ extractMask.push_back(10);
+ extractMask.push_back(11);
+ extractMask.push_back(11);
+ return true;
+ case BufDataFormat10_10_10_2:
+ extractMask.push_back(2);
+ extractMask.push_back(10);
+ extractMask.push_back(10);
+ extractMask.push_back(10);
+ return true;
+ case BufDataFormat2_10_10_10:
+ extractMask.push_back(10);
+ extractMask.push_back(10);
+ extractMask.push_back(10);
+ extractMask.push_back(2);
+ return true;
+ default:
+ break;
+ }
+
+ return false;
+}
+
// =====================================================================================================================
// Loads vertex descriptor based on the specified vertex input location.
//
@@ -1605,159 +1537,229 @@ Value *VertexFetchImpl::loadVertexBufferDescriptor(unsigned binding, BuilderImpl
return vbDesc;
}
+// =====================================================================================================================
+// Post-process for final fetch emulation, including for post shuffle, scaled/norm format emulation and packed format.
+//
+// @param description : Vertex input description.
+// @param fetchInByte : Whether is doing fetch in Byte.
+// @param inputCompBytes : Component Byte size of input type.
+// @param numChannels : Valid number of channels.
+// @param numFormatInfo : vertex format data results info corresponding to vertex numerical format (BufNumFormat).
+// @param descFormatInfo : Vertex component info corresponding to vertex data format (BufDataFormat).
+// @param builderImpl : BuilderImpl to use to insert vertex fetch instructions.
+// @param [out] ppFetch : Destination of vertex fetch.
+void VertexFetchImpl::postFetchEmulation(const VertexInputDescription *description, bool fetchInByte,
+ unsigned inputCompBytes, unsigned numChannels,
+ const VertexNumFormatInfo *numFormatInfo,
+ const VertexCompFormatInfo *descFormatInfo, BuilderImpl &builderImpl,
+ Value **ppFetch) const {
+ Type *compIntTy = getVertexFetchType(false, inputCompBytes, builderImpl);
+ // Do post-processing in certain cases
+ std::vector<Constant *> shuffleMask;
+ std::vector<unsigned> extractMask;
+ // Emulation for packed formats.
+ if (fetchInByte && needPackFormatEmulation(description, extractMask)) {
+ // Must be 8 bit fetch in Byte.
+ Value *packedVertex =
+ PoisonValue::get(FixedVectorType::get(builderImpl.getInt8Ty(), descFormatInfo->vertexByteSize));
+ for (unsigned i = 0; i < descFormatInfo->vertexByteSize; i++) {
+ Value *oneByteVal = builderImpl.CreateExtractElement(*ppFetch, i);
+ oneByteVal = builderImpl.CreateTrunc(oneByteVal, builderImpl.getInt8Ty());
+ packedVertex = builderImpl.CreateInsertElement(packedVertex, oneByteVal, i);
+ }
+
+ // Cast fetched data from i8Vec4 to a i32 for bit extract and vector re-construction.
+ packedVertex = builderImpl.CreateBitCast(packedVertex, builderImpl.getInt32Ty());
+ Value *emulateVertex = PoisonValue::get(FixedVectorType::get(compIntTy, descFormatInfo->compCount));
+
+ // Re-construct final results.
+ unsigned offset = 0;
+ for (unsigned i = 0; i < descFormatInfo->compCount; i++) {
+ Value *bitExtractVal = builderImpl.CreateExtractBitField(
+ packedVertex, builderImpl.getInt32(offset), builderImpl.getInt32(extractMask[i]), numFormatInfo->isSigned);
+ emulateVertex = builderImpl.CreateInsertElement(emulateVertex, bitExtractVal, builderImpl.getInt32(i));
+ offset += extractMask[i];
+ }
+
+ *ppFetch = emulateVertex;
+ }
+ if (needPostShuffle(description, shuffleMask)) {
+ // NOTE: If we are fetching a swizzled format, we have to add an extra "shufflevector" instruction to
+ // get the components in the right order.
+ assert(shuffleMask.empty() == false);
+ *ppFetch = builderImpl.CreateShuffleVector(*ppFetch, *ppFetch, ConstantVector::get(shuffleMask));
+ }
+ if (fetchInByte || needPatch32(description)) {
+ Type *compFloatTy = getVertexFetchType(true, inputCompBytes, builderImpl);
+ for (unsigned i = 0; i < numChannels; ++i) {
+ Value *elemInstr = nullptr;
+ if (numChannels == 1)
+ elemInstr = *ppFetch;
+ else
+ elemInstr = builderImpl.CreateExtractElement(*ppFetch, builderImpl.getInt32(i));
+ if (numFormatInfo->isNorm || numFormatInfo->isScaled) {
+ // A constant divisor for normalization emulation.
+ float normDiv = 2.14748365e+09f;
+ if (numFormatInfo->isSigned) {
+ // Signed int to float
+ elemInstr = builderImpl.CreateSIToFP(elemInstr, compFloatTy);
+ } else {
+ // Unsigned int to float
+ elemInstr = builderImpl.CreateUIToFP(elemInstr, compFloatTy);
+ normDiv = 4.29496730e+09f;
+ }
+ if (numFormatInfo->isNorm) {
+ // Normalization emulation.
+ elemInstr = builderImpl.CreateFDiv(elemInstr, ConstantFP::get(compFloatTy, normDiv));
+ }
+ } else if (description->nfmt == BufNumFormatFixed) {
+ // A constant divisor to translate loaded float bits to fixed point format.
+ double fixedPointMul = 1.0f / 65536.0f;
+ elemInstr = builderImpl.CreateSIToFP(elemInstr, compFloatTy);
+ elemInstr = builderImpl.CreateFMul(elemInstr, ConstantFP::get(compFloatTy, fixedPointMul));
+ }
+
+ elemInstr = builderImpl.CreateBitCast(elemInstr, compIntTy);
+ if (numChannels > 1)
+ *ppFetch = builderImpl.CreateInsertElement(*ppFetch, elemInstr, builderImpl.getInt32(i));
+ else
+ *ppFetch = elemInstr;
+ }
+ }
+}
+
// =====================================================================================================================
// Inserts instructions to do vertex fetch operations.
//
-// The stride is passed only to ensure that a valid load is used, not to actually calculate the load address.
-// Instead, we use the index as the index in a structured tbuffer load instruction, and rely on the driver
-// setting up the descriptor with the correct stride.
+// When do vertex fetch, the construction order is : single fetch -> component -> fetch results.
+// In most of cases, we do fetch in component granularity to make sure alignment is correct. After later optimization,
+// if several tbuffer_load intrinsics with same load format are observed continuous on buffer by checking their offsets,
+// they will be combined and generate a vector fetch in final ISA codes.
+// There are two special cases:
+// 1. For packed formats, we just do a single fetch with a vector result type, which is supported from HW.
+// 2. If we know address low bits of vertex buffer and found current data is not aligned, we do fetch in Byte and
+// emulate results later.
//
// @param vbDesc : Vertex buffer descriptor
-// @param numChannels : Valid number of channels
-// @param is16bitFetch : Whether it is 16-bit vertex fetch
// @param vbIndex : Index of vertex fetch in buffer
-// @param offset : Vertex attribute offset (in bytes)
// @param srdStride: Stride from SRD. Only for offset mode.
-// @param stride : Vertex attribute stride (in bytes)
+// @param numChannels : Valid number of channels
+// @param offset : Vertex attribute offset (in bytes)
// @param dfmt : Date format of vertex buffer
// @param nfmt : Numeric format of vertex buffer
-// @param insertPos : Where to insert instructions
+// @param inputCompBytes : Number of Bytes of input component type.
+// @param fetchCompBytes : Number of Bytes of fetch results' component type.
+// @param isSigned: Whether current format is signed.
+// @param isPacked: Whether current format is packed.
+// @param fetchInByte: Do fetch in Byte if the vertex attribute offset and stride are not aligned.
+// @param builderImpl : BuilderImpl to use to insert vertex fetch instructions
// @param [out] ppFetch : Destination of vertex fetch
-void VertexFetchImpl::addVertexFetchInst(Value *vbDesc, unsigned numChannels, bool is16bitFetch, Value *vbIndex,
- Value *srdStride, unsigned offset, unsigned stride, unsigned dfmt,
- unsigned nfmt, Instruction *insertPos, Value **ppFetch) const {
-
- const VertexCompFormatInfo *formatInfo = getVertexComponentFormatInfo(dfmt);
-
+void VertexFetchImpl::addVertexFetchInst(Value *vbDesc, Value *vbIndex, Value *srdStride, unsigned numChannels,
+ unsigned offset, unsigned dfmt, unsigned nfmt, unsigned inputCompBytes,
+ unsigned fetchCompBytes, bool isSigned, bool isPacked, bool fetchInByte,
+ BuilderImpl &builderImpl, Value **ppFetch) const {
Intrinsic::ID instId = Intrinsic::amdgcn_struct_tbuffer_load;
- BuilderBase builder(insertPos);
- Value *instOffset = builder.getInt32(offset);
+ Value *instOffset = builderImpl.getInt32(offset);
if (m_useSoftwareVertexBufferDescriptors) {
+ // Generated offset delta will always be aligned.
instId = Intrinsic::amdgcn_raw_tbuffer_load;
- auto index2Offset = builder.CreateMul(vbIndex, srdStride);
- instOffset = builder.CreateAdd(index2Offset, instOffset);
+ auto index2Offset = builderImpl.CreateMul(vbIndex, srdStride);
+ instOffset = builderImpl.CreateAdd(index2Offset, instOffset);
}
- // NOTE: If the vertex attribute offset and stride are aligned on data format boundaries, we can do a vertex fetch
- // operation to read the whole vertex. Otherwise, we have to do vertex per-component fetch operations.
- if (((offset % formatInfo->vertexByteSize) == 0 && (stride % formatInfo->vertexByteSize) == 0 &&
- // NOTE: For the vertex data format 8_8, 8_8_8_8, 16_16, and 16_16_16_16, tbuffer_load has a HW defect when
- // vertex buffer is unaligned. Therefore, we have to split the vertex fetch to component-based ones
- dfmt != BufDataFormat8_8 && dfmt != BufDataFormat8_8_8_8 && dfmt != BufDataFormat16_16 &&
- dfmt != BufDataFormat16_16_16_16 && dfmt != BufDataFormat8_8_8 && dfmt != BufDataFormat16_16_16) ||
- formatInfo->compDfmt == dfmt) {
-
- SmallVector<Value *, 6> args;
- args.push_back(vbDesc);
- if (!m_useSoftwareVertexBufferDescriptors)
- args.push_back(vbIndex);
- args.push_back(instOffset);
- args.push_back(builder.getInt32(0));
- args.push_back(builder.getInt32(mapVertexFormat(dfmt, nfmt)));
- args.push_back(builder.getInt32(0));
-
- // Do vertex fetch
- Type *fetchTy = nullptr;
-
- if (is16bitFetch) {
- switch (numChannels) {
- case 1:
- fetchTy = Type::getHalfTy(*m_context);
- break;
- case 2:
- fetchTy = FixedVectorType::get(Type::getHalfTy(*m_context), 2);
- break;
- case 3:
- case 4:
- fetchTy = FixedVectorType::get(Type::getHalfTy(*m_context), 4);
- break;
- default:
- llvm_unreachable("Should never be called!");
- break;
- }
- } else {
- switch (numChannels) {
- case 1:
- fetchTy = Type::getInt32Ty(*m_context);
- break;
- case 2:
- fetchTy = FixedVectorType::get(Type::getInt32Ty(*m_context), 2);
- break;
- case 3:
- case 4:
- fetchTy = FixedVectorType::get(Type::getInt32Ty(*m_context), 4);
- break;
- default:
- llvm_unreachable("Should never be called!");
- break;
- }
- }
-
- Value *fetch = builder.CreateIntrinsic(instId, fetchTy, args, {});
-
- if (is16bitFetch) {
- // NOTE: The fetch values are represented by <n x i16>, so we will bitcast the float16 values to
- // int16 eventually.
- Type *bitCastTy = Type::getInt16Ty(*m_context);
- bitCastTy = numChannels == 1 ? bitCastTy : FixedVectorType::get(bitCastTy, numChannels >= 3 ? 4 : numChannels);
- fetch = new BitCastInst(fetch, bitCastTy, "", insertPos);
+ // For tbuffer_load, only support two types (could be vector) of fetch : d16 or i32, depending on input type.
+ unsigned tbufLoadBytes = inputCompBytes <= 2 ? 2 : 4;
+ unsigned fetchLoadBytes = fetchInByte ? 1 : fetchCompBytes;
+
+ Type *tbufLoadTy = inputCompBytes <= 2 ? builderImpl.getHalfTy() : builderImpl.getInt32Ty();
+ Type *fetchLoadTy = getVertexFetchType(false, fetchLoadBytes, builderImpl);
+ Type *fetchCompTy = getVertexFetchType(false, fetchCompBytes, builderImpl);
+ Type *inputCompTy = getVertexFetchType(false, inputCompBytes, builderImpl);
+
+ auto resultChannels = numChannels;
+ unsigned compChannels = fetchCompBytes / fetchLoadBytes;
+
+ // Special fetch mode for packed data format like 2_10_10_10.
+ if (isPacked) {
+ // If process fetch packed vertex in Byte, fetch type should be <4 x i8> and do emulation later.
+ compChannels = 1;
+ if (!fetchInByte) {
+ // For packed format, if not fetch in Byte, directly use this data format in tbuffer_load intrinsic call.
+ // HW supports to do 4 dwords fetch with format conversion, intrinsic result type should be <4 x i32>.
+ // (or <4 x d16> if it is a d16 fetch).
+ resultChannels = 1;
+ tbufLoadTy = FixedVectorType::get(tbufLoadTy, numChannels);
}
+ }
- if (numChannels == 3) {
- // NOTE: If valid number of channels is 3, the actual fetch type should be revised from <4 x i32>
- // to <3 x i32>.
- *ppFetch = new ShuffleVectorInst(fetch, fetch, ArrayRef<int>{0, 1, 2}, "", insertPos);
- } else
- *ppFetch = fetch;
- } else {
- // NOTE: Here, we split the vertex into its components and do per-component fetches. The expectation
- // is that the vertex per-component fetches always match the hardware requirements.
- assert(numChannels == formatInfo->compCount);
-
- Value *compVbIndices[4] = {};
- unsigned compOffsets[4] = {};
-
- for (unsigned i = 0; i < formatInfo->compCount; ++i) {
- unsigned compOffset = offset + i * formatInfo->compByteSize;
- compVbIndices[i] = vbIndex;
- compOffsets[i] = compOffset;
- }
+ // As 64 bit floating type will be emulated by i32 fetch, max loaded size will be 32 Bytes.
+ int compOffsets[32] = {};
+ for (unsigned i = 0; i < compChannels * resultChannels; ++i) {
+ compOffsets[i] = offset + i * fetchLoadBytes;
+ }
- Type *fetchTy = is16bitFetch ? FixedVectorType::get(Type::getInt16Ty(*m_context), numChannels)
- : FixedVectorType::get(Type::getInt32Ty(*m_context), numChannels);
- Value *fetch = PoisonValue::get(fetchTy);
-
- SmallVector<Value *, 6> args;
- args.push_back(vbDesc);
- if (!m_useSoftwareVertexBufferDescriptors)
- args.push_back(vbIndex);
- unsigned offsetIdx = args.size();
- args.push_back(instOffset);
- args.push_back(builder.getInt32(0));
- args.push_back(builder.getInt32(mapVertexFormat(formatInfo->compDfmt, nfmt)));
- args.push_back(builder.getInt32(0));
-
- // Do vertex per-component fetches
- for (unsigned i = 0; i < formatInfo->compCount; ++i) {
- Value *compOffset = builder.getInt32(compOffsets[i]);
+ SmallVector<Value *, 6> args;
+ args.push_back(vbDesc);
+ if (!m_useSoftwareVertexBufferDescriptors)
+ args.push_back(vbIndex);
+ unsigned offsetIdx = args.size();
+ args.push_back(instOffset);
+ args.push_back(builderImpl.getInt32(0));
+ if (fetchInByte)
+ args.push_back(builderImpl.getInt32(mapVertexFormat(BUF_DATA_FORMAT_8, BufNumFormatUint)));
+ else
+ args.push_back(builderImpl.getInt32(mapVertexFormat(dfmt, nfmt)));
+ args.push_back(builderImpl.getInt32(0));
+
+ Value *fetchVal = resultChannels > 1 ? PoisonValue::get(FixedVectorType::get(inputCompTy, resultChannels)) : nullptr;
+ for (unsigned i = 0; i < resultChannels; ++i) {
+ Value *compVal = compChannels > 1 ? PoisonValue::get(FixedVectorType::get(fetchLoadTy, compChannels)) : nullptr;
+ unsigned compBytes = compChannels > 1 ? fetchCompBytes : tbufLoadBytes;
+ for (unsigned j = 0; j < compChannels; ++j) {
+ unsigned idx = i * compChannels + j;
+ Value *compOffset = builderImpl.getInt32(compOffsets[idx]);
if (m_useSoftwareVertexBufferDescriptors)
- args[offsetIdx] = builder.CreateAdd(instOffset, compOffset);
+ args[offsetIdx] = builderImpl.CreateAdd(instOffset, compOffset);
else
args[offsetIdx] = compOffset;
- Value *compFetch = nullptr;
- if (is16bitFetch) {
- compFetch = builder.CreateIntrinsic(instId, builder.getHalfTy(), args, {});
- compFetch = builder.CreateBitCast(compFetch, builder.getInt16Ty());
+ Value *tbufLoad = builderImpl.CreateIntrinsic(tbufLoadTy, instId, args);
+
+ // Keep intermediate component type as integer before final casting.
+ if (inputCompBytes <= 2) {
+ tbufLoad = builderImpl.CreateBitCast(tbufLoad, builderImpl.getInt16Ty());
+ }
+
+ if (compChannels > 1) {
+ tbufLoad = builderImpl.CreateTrunc(tbufLoad, fetchLoadTy);
+ compVal = builderImpl.CreateInsertElement(compVal, tbufLoad, j);
} else {
- compFetch = builder.CreateIntrinsic(instId, builder.getInt32Ty(), args, {});
+ // Avoid do wasted Trunc here and Ext back.
+ compVal = tbufLoad;
}
+ }
+
+ // When do fetch in Byte, we finally cast fetch array to a component with expected type.
+ if (compChannels > 1)
+ compVal = builderImpl.CreateBitCast(compVal, fetchCompTy);
- fetch = builder.CreateInsertElement(fetch, compFetch, i);
+ // Let each component here have same bit width as final expected fetch results.
+ if (inputCompBytes < compBytes)
+ compVal = builderImpl.CreateTrunc(compVal, inputCompTy);
+ else if (inputCompBytes > compBytes) {
+ if (isSigned)
+ compVal = builderImpl.CreateSExt(compVal, inputCompTy);
+ else
+ compVal = builderImpl.CreateZExt(compVal, inputCompTy);
}
- *ppFetch = fetch;
+ if (resultChannels > 1)
+ fetchVal = builderImpl.CreateInsertElement(fetchVal, compVal, i);
+ else
+ fetchVal = compVal;
}
+
+ *ppFetch = fetchVal;
}
// =====================================================================================================================
@@ -1809,21 +1811,13 @@ bool VertexFetchImpl::needPatch32(const VertexInputDescription *inputDesc) const
return needPatch;
}
-// =====================================================================================================================
-// Checks whether the second vertex fetch operation is required (particularly for certain 64-bit typed formats).
-//
-// @param inputDesc : Vertex input description
-bool VertexFetchImpl::needSecondVertexFetch(const VertexInputDescription *inputDesc) const {
- return inputDesc->dfmt == BufDataFormat64_64_64 || inputDesc->dfmt == BufDataFormat64_64_64_64;
-}
-
// =====================================================================================================================
// Convert D3D12_VERTEX_BUFFER_VIEW SRD to offset mode. Stride will be used to calculate offset.
//
// @param vbDesc : Original SRD
// @param builder : Builder to use to insert vertex fetch instructions
// @returns : {New SRD,stride}
-std::pair<Value *, Value *> VertexFetchImpl::convertSrdToOffsetMode(Value *vbDesc, BuilderBase &builder) {
+std::pair<Value *, Value *> VertexFetchImpl::convertSrdToOffsetMode(Value *vbDesc, BuilderImpl &builder) {
assert(m_useSoftwareVertexBufferDescriptors);
// NOTE: Vertex buffer SRD is D3D12_VERTEX_BUFFER_VIEW
// struct VertexBufferView
diff --git a/lgc/state/Compiler.cpp b/lgc/state/Compiler.cpp
index e988b12efe..03bd2a948a 100644
--- a/lgc/state/Compiler.cpp
+++ b/lgc/state/Compiler.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -64,13 +64,13 @@ ElfLinker *createElfLinkerImpl(PipelineState *pipelineState, llvm::ArrayRef<llvm
// in the front-end before a shader is associated with a pipeline.
//
// @param func : Shader entry-point function
-// @param stage : Shader stage or ShaderStageInvalid
-void Pipeline::markShaderEntryPoint(Function *func, ShaderStage stage) {
+// @param stage : Shader stage or ShaderStage::Invalid
+void Pipeline::markShaderEntryPoint(Function *func, ShaderStageEnum stage) {
// We mark the shader entry-point function by
// 1. marking it external linkage and DLLExportStorageClass; and
// 2. adding the shader stage metadata.
// The shader stage metadata for any other non-inlined functions in the module is added in irLink().
- if (stage != ShaderStageInvalid) {
+ if (stage != ShaderStage::Invalid) {
func->setLinkage(GlobalValue::ExternalLinkage);
func->setDLLStorageClass(GlobalValue::DLLExportStorageClass);
} else
@@ -82,79 +82,89 @@ void Pipeline::markShaderEntryPoint(Function *func, ShaderStage stage) {
// Get a function's shader stage.
//
// @param func : Function to check
-// @returns stage : Shader stage, or ShaderStageInvalid if none
-ShaderStage Pipeline::getShaderStage(llvm::Function *func) {
+// @returns stage : Shader stage, or nullopt if none
+std::optional<ShaderStageEnum> Pipeline::getShaderStage(llvm::Function *func) {
return lgc::getShaderStage(func);
}
+// =====================================================================================================================
+// Find the shader entry-point from shader module, and set pipeline stage.
+//
+// @param module : Shader module to attach
+void PipelineState::attachModule(llvm::Module *module) {
+ if (!module)
+ return;
+
+ // Find the shader entry-point (marked with irLink()), and get the shader stage from that.
+ std::optional<ShaderStageEnum> stage;
+ for (Function &func : *module) {
+ if (!isShaderEntryPoint(&func))
+ continue;
+ // We have the entry-point (marked as DLLExportStorageClass).
+ stage = getShaderStage(&func);
+ m_stageMask |= ShaderStageMask(stage.value());
+
+ // Rename the entry-point to ensure there is no clash on linking.
+ func.setName(Twine(lgcName::EntryPointPrefix) + getShaderStageAbbreviation(stage.value()) + "." + func.getName());
+ }
+
+ // Check if this is a compute library with no shader entry-point; if so, mark functions as compute.
+ if (!stage) {
+ stage = ShaderStage::Compute;
+ m_computeLibrary = true;
+ }
+
+ // Mark all other function definitions in the module with the same shader stage.
+ for (Function &func : *module) {
+ if (!func.isDeclaration() && !isShaderEntryPoint(&func))
+ setShaderStage(&func, stage);
+ }
+}
+
// =====================================================================================================================
// Link shader IR modules into a pipeline module.
//
-// @param modules : Array of modules. Modules are freed
+// @param modules : Array of modules unique pointers. Modules are freed
// @param pipelineLink : Enum saying whether this is a pipeline, unlinked or part-pipeline compile.
-Module *PipelineState::irLink(ArrayRef<Module *> modules, PipelineLink pipelineLink) {
+std::unique_ptr<Module> PipelineState::irLink(MutableArrayRef<std::unique_ptr<Module>> modules,
+ PipelineLink pipelineLink) {
m_pipelineLink = pipelineLink;
// Processing for each shader module before linking.
IRBuilder<> builder(getContext());
- for (Module *module : modules) {
+ for (auto &module : modules) {
if (!module)
continue;
- // Find the shader entry-point (marked with irLink()), and get the shader stage from that.
- ShaderStage stage = ShaderStageInvalid;
- for (Function &func : *module) {
- if (!isShaderEntryPoint(&func))
- continue;
- // We have the entry-point (marked as DLLExportStorageClass).
- stage = getShaderStage(&func);
- m_stageMask |= 1U << stage;
-
- // Rename the entry-point to ensure there is no clash on linking.
- func.setName(Twine(lgcName::EntryPointPrefix) + getShaderStageAbbreviation(static_cast<ShaderStage>(stage)) +
- "." + func.getName());
- }
-
- // Check if this is a compute library with no shader entry-point; if so, mark functions as compute.
- if (stage == ShaderStageInvalid) {
- stage = ShaderStageCompute;
- m_computeLibrary = true;
- }
-
- // Mark all other function definitions in the module with the same shader stage.
- for (Function &func : *module) {
- if (!func.isDeclaration() && !isShaderEntryPoint(&func))
- setShaderStage(&func, stage);
- }
+ attachModule(module.get());
}
// The front-end was using a BuilderRecorder; record pipeline state into IR metadata.
- record(modules[0]);
+ record(modules[0].get());
// If there is only one shader, just change the name on its module and return it.
- Module *pipelineModule = nullptr;
+ std::unique_ptr<Module> pipelineModule;
if (modules.size() == 1) {
- pipelineModule = modules[0];
+ pipelineModule = std::move(modules[0]);
pipelineModule->setModuleIdentifier("lgcPipeline");
} else {
// Create an empty module then link each shader module into it.
bool result = true;
- pipelineModule = new Module("lgcPipeline", getContext());
+ pipelineModule = std::unique_ptr<Module>(new Module("lgcPipeline", getContext()));
TargetMachine *targetMachine = getLgcContext()->getTargetMachine();
pipelineModule->setTargetTriple(targetMachine->getTargetTriple().getTriple());
pipelineModule->setDataLayout(modules.front()->getDataLayout());
Linker linker(*pipelineModule);
- for (Module *module : modules) {
+ for (auto &module : modules) {
// NOTE: We use unique_ptr here. The shader module will be destroyed after it is
// linked into pipeline module.
- if (linker.linkInModule(std::unique_ptr<Module>(module)))
+ if (linker.linkInModule(std::move(module)))
result = false;
}
if (!result) {
- delete pipelineModule;
- pipelineModule = nullptr;
+ pipelineModule.release();
}
}
return pipelineModule;
diff --git a/lgc/state/LgcContext.cpp b/lgc/state/LgcContext.cpp
index bf0c4705bf..547e971dc3 100644
--- a/lgc/state/LgcContext.cpp
+++ b/lgc/state/LgcContext.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/state/LgcDialect.cpp b/lgc/state/LgcDialect.cpp
index b13af8bc6d..47fb1eb109 100644
--- a/lgc/state/LgcDialect.cpp
+++ b/lgc/state/LgcDialect.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/state/PalMetadata.cpp b/lgc/state/PalMetadata.cpp
index b6ce24ad12..0c6a2e0451 100644
--- a/lgc/state/PalMetadata.cpp
+++ b/lgc/state/PalMetadata.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -213,9 +213,9 @@ void PalMetadata::mergeFromBlob(llvm::StringRef blob, bool isGlueCode) {
if (destNode->isString() && srcNode.isString()) {
if (destNode->getString() == srcNode.getString())
return 0;
- if (srcNode.getString().endswith("_fetchless"))
+ if (srcNode.getString().ends_with("_fetchless"))
return 0;
- if (destNode->getString().endswith("_fetchless")) {
+ if (destNode->getString().ends_with("_fetchless")) {
*destNode = srcNode;
return 0;
}
@@ -307,9 +307,9 @@ void PalMetadata::mergeFromBlob(llvm::StringRef blob, bool isGlueCode) {
if (destNode->isString() && srcNode.isString()) {
if (destNode->getString() == srcNode.getString())
return 0;
- if (srcNode.getString().endswith("_fetchless"))
+ if (srcNode.getString().ends_with("_fetchless"))
return 0;
- if (destNode->getString().endswith("_fetchless")) {
+ if (destNode->getString().ends_with("_fetchless")) {
*destNode = srcNode;
return 0;
}
@@ -404,60 +404,60 @@ void PalMetadata::mergeFromBlob(llvm::StringRef blob, bool isGlueCode) {
// stages are present in the pipeline, and whether NGG is enabled. The first time this is called must be
// after PatchResourceCollect has run.
//
-// @param stage : ShaderStage
-unsigned PalMetadata::getUserDataReg0(ShaderStage stage) {
+// @param stage : ShaderStageEnum
+unsigned PalMetadata::getUserDataReg0(ShaderStageEnum stage) {
assert(!m_useRegisterFieldFormat);
if (m_userDataRegMapping[stage] != 0)
return m_userDataRegMapping[stage];
// Mapping not yet initialized.
- // Set up ShaderStage -> user data register mapping.
- m_userDataRegMapping[ShaderStageCompute] = mmCOMPUTE_USER_DATA_0;
- m_userDataRegMapping[ShaderStageFragment] = mmSPI_SHADER_USER_DATA_PS_0;
- m_userDataRegMapping[ShaderStageTask] = mmCOMPUTE_USER_DATA_0;
- m_userDataRegMapping[ShaderStageMesh] = mmSPI_SHADER_USER_DATA_GS_0;
+ // Set up ShaderStageEnum -> user data register mapping.
+ m_userDataRegMapping[ShaderStage::Compute] = mmCOMPUTE_USER_DATA_0;
+ m_userDataRegMapping[ShaderStage::Fragment] = mmSPI_SHADER_USER_DATA_PS_0;
+ m_userDataRegMapping[ShaderStage::Task] = mmCOMPUTE_USER_DATA_0;
+ m_userDataRegMapping[ShaderStage::Mesh] = mmSPI_SHADER_USER_DATA_GS_0;
if (m_pipelineState->getTargetInfo().getGfxIpVersion().major == 9) {
// GFX9: Merged shaders, and merged ES-GS user data goes into ES registers.
- m_userDataRegMapping[ShaderStageCopyShader] = mmSPI_SHADER_USER_DATA_VS_0;
- m_userDataRegMapping[ShaderStageGeometry] = mmSPI_SHADER_USER_DATA_ES_0;
- if (m_pipelineState->hasShaderStage(ShaderStageGeometry))
- m_userDataRegMapping[ShaderStageTessEval] = m_userDataRegMapping[ShaderStageGeometry];
+ m_userDataRegMapping[ShaderStage::CopyShader] = mmSPI_SHADER_USER_DATA_VS_0;
+ m_userDataRegMapping[ShaderStage::Geometry] = mmSPI_SHADER_USER_DATA_ES_0;
+ if (m_pipelineState->hasShaderStage(ShaderStage::Geometry))
+ m_userDataRegMapping[ShaderStage::TessEval] = m_userDataRegMapping[ShaderStage::Geometry];
else
- m_userDataRegMapping[ShaderStageTessEval] = mmSPI_SHADER_USER_DATA_VS_0;
- m_userDataRegMapping[ShaderStageTessControl] = mmSPI_SHADER_USER_DATA_HS_0;
- if (m_pipelineState->hasShaderStage(ShaderStageTessControl))
- m_userDataRegMapping[ShaderStageVertex] = m_userDataRegMapping[ShaderStageTessControl];
- else if (m_pipelineState->hasShaderStage(ShaderStageGeometry))
- m_userDataRegMapping[ShaderStageVertex] = m_userDataRegMapping[ShaderStageGeometry];
+ m_userDataRegMapping[ShaderStage::TessEval] = mmSPI_SHADER_USER_DATA_VS_0;
+ m_userDataRegMapping[ShaderStage::TessControl] = mmSPI_SHADER_USER_DATA_HS_0;
+ if (m_pipelineState->hasShaderStage(ShaderStage::TessControl))
+ m_userDataRegMapping[ShaderStage::Vertex] = m_userDataRegMapping[ShaderStage::TessControl];
+ else if (m_pipelineState->hasShaderStage(ShaderStage::Geometry))
+ m_userDataRegMapping[ShaderStage::Vertex] = m_userDataRegMapping[ShaderStage::Geometry];
else
- m_userDataRegMapping[ShaderStageVertex] = mmSPI_SHADER_USER_DATA_VS_0;
+ m_userDataRegMapping[ShaderStage::Vertex] = mmSPI_SHADER_USER_DATA_VS_0;
} else if (!m_pipelineState->getNggControl()->enableNgg) {
// GFX10+ not NGG: Same as GFX9, except ES-GS user data goes into GS registers.
- m_userDataRegMapping[ShaderStageCopyShader] = mmSPI_SHADER_USER_DATA_VS_0;
- m_userDataRegMapping[ShaderStageGeometry] = mmSPI_SHADER_USER_DATA_GS_0;
- if (m_pipelineState->hasShaderStage(ShaderStageGeometry))
- m_userDataRegMapping[ShaderStageTessEval] = m_userDataRegMapping[ShaderStageGeometry];
+ m_userDataRegMapping[ShaderStage::CopyShader] = mmSPI_SHADER_USER_DATA_VS_0;
+ m_userDataRegMapping[ShaderStage::Geometry] = mmSPI_SHADER_USER_DATA_GS_0;
+ if (m_pipelineState->hasShaderStage(ShaderStage::Geometry))
+ m_userDataRegMapping[ShaderStage::TessEval] = m_userDataRegMapping[ShaderStage::Geometry];
else
- m_userDataRegMapping[ShaderStageTessEval] = mmSPI_SHADER_USER_DATA_VS_0;
- m_userDataRegMapping[ShaderStageTessControl] = mmSPI_SHADER_USER_DATA_HS_0;
- if (m_pipelineState->hasShaderStage(ShaderStageTessControl))
- m_userDataRegMapping[ShaderStageVertex] = m_userDataRegMapping[ShaderStageTessControl];
- else if (m_pipelineState->hasShaderStage(ShaderStageGeometry))
- m_userDataRegMapping[ShaderStageVertex] = m_userDataRegMapping[ShaderStageGeometry];
+ m_userDataRegMapping[ShaderStage::TessEval] = mmSPI_SHADER_USER_DATA_VS_0;
+ m_userDataRegMapping[ShaderStage::TessControl] = mmSPI_SHADER_USER_DATA_HS_0;
+ if (m_pipelineState->hasShaderStage(ShaderStage::TessControl))
+ m_userDataRegMapping[ShaderStage::Vertex] = m_userDataRegMapping[ShaderStage::TessControl];
+ else if (m_pipelineState->hasShaderStage(ShaderStage::Geometry))
+ m_userDataRegMapping[ShaderStage::Vertex] = m_userDataRegMapping[ShaderStage::Geometry];
else
- m_userDataRegMapping[ShaderStageVertex] = mmSPI_SHADER_USER_DATA_VS_0;
+ m_userDataRegMapping[ShaderStage::Vertex] = mmSPI_SHADER_USER_DATA_VS_0;
} else {
// GFX10+ NGG
- m_userDataRegMapping[ShaderStageGeometry] = mmSPI_SHADER_USER_DATA_GS_0;
- m_userDataRegMapping[ShaderStageTessEval] = m_userDataRegMapping[ShaderStageGeometry];
- m_userDataRegMapping[ShaderStageTessControl] = mmSPI_SHADER_USER_DATA_HS_0;
- if (m_pipelineState->hasShaderStage(ShaderStageTessControl))
- m_userDataRegMapping[ShaderStageVertex] = m_userDataRegMapping[ShaderStageTessControl];
+ m_userDataRegMapping[ShaderStage::Geometry] = mmSPI_SHADER_USER_DATA_GS_0;
+ m_userDataRegMapping[ShaderStage::TessEval] = m_userDataRegMapping[ShaderStage::Geometry];
+ m_userDataRegMapping[ShaderStage::TessControl] = mmSPI_SHADER_USER_DATA_HS_0;
+ if (m_pipelineState->hasShaderStage(ShaderStage::TessControl))
+ m_userDataRegMapping[ShaderStage::Vertex] = m_userDataRegMapping[ShaderStage::TessControl];
else
- m_userDataRegMapping[ShaderStageVertex] = m_userDataRegMapping[ShaderStageGeometry];
+ m_userDataRegMapping[ShaderStage::Vertex] = m_userDataRegMapping[ShaderStage::Geometry];
}
return m_userDataRegMapping[stage];
@@ -466,13 +466,13 @@ unsigned PalMetadata::getUserDataReg0(ShaderStage stage) {
// =====================================================================================================================
// Set the PAL metadata SPI register for a number of consecutive user data entries
//
-// @param stage : ShaderStage
+// @param stage : ShaderStageEnum
// @param userDataIndex : User data index 0-15 or 0-31 depending on HW and shader stage
// @param userDataValue : Value to store in that entry, one of:
// - a 0-based integer for the root user data dword offset
// - one of the UserDataMapping values, e.g. UserDataMapping::GlobalTable
// @param dwordCount : Number of user data entries to set
-void PalMetadata::setUserDataEntry(ShaderStage stage, unsigned userDataIndex, unsigned userDataValue,
+void PalMetadata::setUserDataEntry(ShaderStageEnum stage, unsigned userDataIndex, unsigned userDataValue,
unsigned dwordCount) {
assert(!m_useRegisterFieldFormat);
// Get the start register number of SPI user data registers for this shader stage.
@@ -480,8 +480,8 @@ void PalMetadata::setUserDataEntry(ShaderStage stage, unsigned userDataIndex, un
// Assert that the supplied user data index is not too big.
bool inRange = userDataIndex + dwordCount <= 16;
- if (m_pipelineState->getTargetInfo().getGfxIpVersion().major >= 9 && stage != ShaderStageCompute &&
- stage != ShaderStageTask)
+ if (m_pipelineState->getTargetInfo().getGfxIpVersion().major >= 9 && stage != ShaderStage::Compute &&
+ stage != ShaderStage::Task)
inRange = userDataIndex + dwordCount <= 32;
assert(inRange && "Out of range user data index");
(void(inRange)); // Unused
@@ -515,10 +515,10 @@ void PalMetadata::fixUpRegisters() {
// If pipeline includes GS or TS, the type is from shader, we don't need to fix it. We only must fix a case
// which includes VS + FS + NGG.
if (m_pipelineState->isGraphics()) {
- const bool hasTs =
- m_pipelineState->hasShaderStage(ShaderStageTessControl) || m_pipelineState->hasShaderStage(ShaderStageTessEval);
- const bool hasGs = m_pipelineState->hasShaderStage(ShaderStageGeometry);
- const bool hasMesh = m_pipelineState->hasShaderStage(ShaderStageMesh);
+ const bool hasTs = m_pipelineState->hasShaderStage(ShaderStage::TessControl) ||
+ m_pipelineState->hasShaderStage(ShaderStage::TessEval);
+ const bool hasGs = m_pipelineState->hasShaderStage(ShaderStage::Geometry);
+ const bool hasMesh = m_pipelineState->hasShaderStage(ShaderStage::Mesh);
if (!hasTs && !hasGs && !hasMesh) {
auto getPrimType = [&]() {
const auto primType = m_pipelineState->getInputAssemblyState().primitiveType;
@@ -573,24 +573,24 @@ void PalMetadata::fixUpRegisters() {
// =====================================================================================================================
// Get shader stage mask (only called for a link-only pipeline whose shader stage mask has not been set yet).
-unsigned PalMetadata::getShaderStageMask() {
+ShaderStageMask PalMetadata::getShaderStageMask() {
msgpack::MapDocNode shaderStages = m_pipelineNode[Util::Abi::PipelineMetadataKey::Shaders].getMap(true);
static const struct TableEntry {
const char *key;
- unsigned maskBit;
- } table[] = {{".compute", 1U << ShaderStageCompute}, {".pixel", 1U << ShaderStageFragment},
- {".mesh", 1U << ShaderStageMesh}, {".geometry", 1U << ShaderStageGeometry},
- {".domain", 1U << ShaderStageTessEval}, {".hull", 1U << ShaderStageTessControl},
- {".vertex", 1U << ShaderStageVertex}, {".task", 1U << ShaderStageTask}};
- unsigned stageMask = 0;
+ ShaderStageEnum stage;
+ } table[] = {{".compute", ShaderStage::Compute}, {".pixel", ShaderStage::Fragment},
+ {".mesh", ShaderStage::Mesh}, {".geometry", ShaderStage::Geometry},
+ {".domain", ShaderStage::TessEval}, {".hull", ShaderStage::TessControl},
+ {".vertex", ShaderStage::Vertex}, {".task", ShaderStage::Task}};
+ ShaderStageMask stageMask;
for (const auto &entry : ArrayRef<TableEntry>(table)) {
if (shaderStages.find(m_document->getNode(entry.key)) != shaderStages.end()) {
msgpack::MapDocNode stageNode = shaderStages[entry.key].getMap(true);
if (stageNode.find(m_document->getNode(Util::Abi::ShaderMetadataKey::ApiShaderHash)) != stageNode.end())
- stageMask |= entry.maskBit;
+ stageMask |= ShaderStageMask(entry.stage);
}
}
- assert(stageMask != 0);
+ assert(!stageMask.empty());
return stageMask;
}
@@ -627,7 +627,7 @@ void PalMetadata::finalizeRegisterSettings(bool isWholePipeline) {
}
if (m_pipelineState->getTargetInfo().getGfxIpVersion().major == 10) {
- WaveBreak waveBreakSize = m_pipelineState->getShaderOptions(ShaderStageFragment).waveBreakSize;
+ WaveBreak waveBreakSize = m_pipelineState->getShaderOptions(ShaderStage::Fragment).waveBreakSize;
auto paScShaderControl = graphicsRegNode[Util::Abi::GraphicsRegisterMetadataKey::PaScShaderControl].getMap(true);
paScShaderControl[Util::Abi::PaScShaderControlMetadataKey::WaveBreakRegionSize] =
static_cast<unsigned>(waveBreakSize);
@@ -660,7 +660,7 @@ void PalMetadata::finalizeRegisterSettings(bool isWholePipeline) {
}
if (m_pipelineState->getTargetInfo().getGfxIpVersion().major == 10) {
- WaveBreak waveBreakSize = m_pipelineState->getShaderOptions(ShaderStageFragment).waveBreakSize;
+ WaveBreak waveBreakSize = m_pipelineState->getShaderOptions(ShaderStage::Fragment).waveBreakSize;
PA_SC_SHADER_CONTROL paScShaderControl = {};
paScShaderControl.gfx10.WAVE_BREAK_REGION_SIZE = static_cast<unsigned>(waveBreakSize);
setRegister(mmPA_SC_SHADER_CONTROL, paScShaderControl.u32All);
@@ -683,11 +683,12 @@ void PalMetadata::finalizeRegisterSettings(bool isWholePipeline) {
//
// Adjust the value if gl_ViewportIndex is not used in the pre-rasterizer stages.
void PalMetadata::finalizeInputControlRegisterSetting() {
- assert(isShaderStageInMask(ShaderStageFragment, m_pipelineState->getShaderStageMask()));
+ assert(m_pipelineState->getShaderStageMask().contains(ShaderStage::Fragment));
unsigned viewportIndexLoc = getFragmentShaderBuiltInLoc(BuiltInViewportIndex);
if (viewportIndexLoc == InvalidValue) {
- auto &builtInInLocMap = m_pipelineState->getShaderResourceUsage(ShaderStageFragment)->inOutUsage.builtInInputLocMap;
+ auto &builtInInLocMap =
+ m_pipelineState->getShaderResourceUsage(ShaderStage::Fragment)->inOutUsage.builtInInputLocMap;
auto builtInInputLocMapIt = builtInInLocMap.find(BuiltInViewportIndex);
if (builtInInputLocMapIt == builtInInLocMap.end())
return;
@@ -752,7 +753,7 @@ void PalMetadata::finalizePipeline(bool isWholePipeline) {
return;
// In the part-pipeline compilation only at ELF link stage do we know how gl_ViewportIndex was used in all stages.
- if (isShaderStageInMask(ShaderStageFragment, m_pipelineState->getShaderStageMask()))
+ if (m_pipelineState->getShaderStageMask().contains(ShaderStage::Fragment))
finalizeInputControlRegisterSetting();
// Erase the PAL metadata for FS input mappings.
diff --git a/lgc/state/PassManagerCache.cpp b/lgc/state/PassManagerCache.cpp
index a00dfa84dd..32f8f8425c 100644
--- a/lgc/state/PassManagerCache.cpp
+++ b/lgc/state/PassManagerCache.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/state/PipelineShaders.cpp b/lgc/state/PipelineShaders.cpp
index 57b6182098..0e7368dfb3 100644
--- a/lgc/state/PipelineShaders.cpp
+++ b/lgc/state/PipelineShaders.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -75,9 +75,9 @@ PipelineShadersResult PipelineShaders::runImpl(Module &module) {
if (isShaderEntryPoint(&func)) {
auto shaderStage = lgc::getShaderStage(&func);
- if (shaderStage != ShaderStageInvalid) {
- result.m_entryPoints[shaderStage] = &func;
- result.m_entryPointMap[&func] = shaderStage;
+ if (shaderStage) {
+ result.m_entryPoints[shaderStage.value()] = &func;
+ result.m_entryPointMap[&func] = shaderStage.value();
}
}
}
@@ -88,18 +88,18 @@ PipelineShadersResult PipelineShaders::runImpl(Module &module) {
// Get the shader for a particular API shader stage, or nullptr if none
//
// @param shaderStage : Shader stage
-Function *PipelineShadersResult::getEntryPoint(ShaderStage shaderStage) const {
- assert((unsigned)shaderStage < ShaderStageCountInternal);
+Function *PipelineShadersResult::getEntryPoint(ShaderStageEnum shaderStage) const {
+ assert((unsigned)shaderStage < ShaderStage::CountInternal);
return m_entryPoints[shaderStage];
}
// =====================================================================================================================
-// Get the ABI shader stage for a particular function, or ShaderStageInvalid if not a shader entrypoint.
+// Get the ABI shader stage for a particular function, or ShaderStage::Invalid if not a shader entrypoint.
//
// @param func : Function to look up
-ShaderStage PipelineShadersResult::getShaderStage(const Function *func) const {
+std::optional<ShaderStageEnum> PipelineShadersResult::getShaderStage(const Function *func) const {
auto entryMapIt = m_entryPointMap.find(func);
- if (entryMapIt == m_entryPointMap.end())
- return ShaderStageInvalid;
- return entryMapIt->second;
+ if (entryMapIt != m_entryPointMap.end())
+ return entryMapIt->second;
+ return std::nullopt;
}
diff --git a/lgc/state/PipelineState.cpp b/lgc/state/PipelineState.cpp
index a1d9b57a0c..c428b90e71 100644
--- a/lgc/state/PipelineState.cpp
+++ b/lgc/state/PipelineState.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -229,7 +229,8 @@ static CompSetting computeCompSetting(BufDataFormat dfmt) {
// @param module : Module to record in
// @param shaderStage : Shader stage to set modes for
// @param commonShaderMode : FP round and denorm modes
-void Pipeline::setCommonShaderMode(Module &module, ShaderStage shaderStage, const CommonShaderMode &commonShaderMode) {
+void Pipeline::setCommonShaderMode(Module &module, ShaderStageEnum shaderStage,
+ const CommonShaderMode &commonShaderMode) {
ShaderModes::setCommonShaderMode(module, shaderStage, commonShaderMode);
}
@@ -239,7 +240,7 @@ void Pipeline::setCommonShaderMode(Module &module, ShaderStage shaderStage, cons
//
// @param module : Module to read from
// @param shaderStage : Shader stage to get modes for
-CommonShaderMode Pipeline::getCommonShaderMode(Module &module, ShaderStage shaderStage) {
+CommonShaderMode Pipeline::getCommonShaderMode(Module &module, ShaderStageEnum shaderStage) {
return ShaderModes::getCommonShaderMode(module, shaderStage);
}
@@ -251,14 +252,15 @@ CommonShaderMode Pipeline::getCommonShaderMode(Module &module, ShaderStage shade
// @param module : Module to record in
// @param shaderStage : Shader stage to set modes for (TCS or TES)
// @param tessellationMode : Tessellation mode
-void Pipeline::setTessellationMode(Module &module, ShaderStage shaderStage, const TessellationMode &tessellationMode) {
+void Pipeline::setTessellationMode(Module &module, ShaderStageEnum shaderStage,
+ const TessellationMode &tessellationMode) {
ShaderModes::setTessellationMode(module, shaderStage, tessellationMode);
}
// =====================================================================================================================
// Get the tessellation mode for the given shader stage.
// This reads the mode from IR metadata in the given module.
-TessellationMode Pipeline::getTessellationMode(Module &module, ShaderStage shaderStage) {
+TessellationMode Pipeline::getTessellationMode(Module &module, ShaderStageEnum shaderStage) {
return ShaderModes::getTessellationMode(module, shaderStage);
}
@@ -309,7 +311,7 @@ void Pipeline::setComputeShaderMode(Module &module, const ComputeShaderMode &com
// @param module : Module to record in
// @param stage : Shader stage
// @param usage : Subgroup size usage
-void Pipeline::setSubgroupSizeUsage(Module &module, ShaderStage stage, bool usage) {
+void Pipeline::setSubgroupSizeUsage(Module &module, ShaderStageEnum stage, bool usage) {
ShaderModes::setSubgroupSizeUsage(module, stage, usage);
}
@@ -482,54 +484,54 @@ void PipelineState::readState(Module *module) {
//
// @param module : LLVM module
void PipelineState::readShaderStageMask(Module *module) {
- m_stageMask = 0;
+ m_stageMask = {};
for (auto &func : *module) {
if (isShaderEntryPoint(&func)) {
auto shaderStage = getShaderStage(&func);
- if (shaderStage != ShaderStageInvalid)
- m_stageMask |= 1 << shaderStage;
+ if (shaderStage)
+ m_stageMask |= ShaderStageMask(shaderStage.value());
}
}
- if (m_stageMask == 0) {
- m_stageMask = 1 << ShaderStageCompute;
+ if (m_stageMask.empty()) {
+ m_stageMask = ShaderStageMask(ShaderStage::Compute);
m_computeLibrary = true;
}
}
// =====================================================================================================================
-// Get the last vertex processing shader stage in this pipeline, or ShaderStageInvalid if none.
-ShaderStage PipelineState::getLastVertexProcessingStage() const {
- if (m_stageMask & shaderStageToMask(ShaderStageCopyShader))
- return ShaderStageCopyShader;
- if (m_stageMask & shaderStageToMask(ShaderStageGeometry))
- return ShaderStageGeometry;
- if (m_stageMask & shaderStageToMask(ShaderStageTessEval))
- return ShaderStageTessEval;
- if (m_stageMask & shaderStageToMask(ShaderStageVertex))
- return ShaderStageVertex;
- return ShaderStageInvalid;
+// Get the last vertex processing shader stage in this pipeline, or ShaderStage::Invalid if none.
+ShaderStageEnum PipelineState::getLastVertexProcessingStage() const {
+ if (m_stageMask.contains(ShaderStage::CopyShader))
+ return ShaderStage::CopyShader;
+ if (m_stageMask.contains(ShaderStage::Geometry))
+ return ShaderStage::Geometry;
+ if (m_stageMask.contains(ShaderStage::TessEval))
+ return ShaderStage::TessEval;
+ if (m_stageMask.contains(ShaderStage::Vertex))
+ return ShaderStage::Vertex;
+ return ShaderStage::Invalid;
}
// =====================================================================================================================
// Gets the previous active shader stage in this pipeline
//
// @param shaderStage : Current shader stage
-ShaderStage PipelineState::getPrevShaderStage(ShaderStage shaderStage) const {
- if (shaderStage == ShaderStageCompute)
- return ShaderStageInvalid;
+ShaderStageEnum PipelineState::getPrevShaderStage(ShaderStageEnum shaderStage) const {
+ if (shaderStage == ShaderStage::Compute)
+ return ShaderStage::Invalid;
- if (shaderStage == ShaderStageCopyShader) {
+ if (shaderStage == ShaderStage::CopyShader) {
// Treat copy shader as part of geometry shader
- shaderStage = ShaderStageGeometry;
+ shaderStage = ShaderStage::Geometry;
}
- assert(shaderStage < ShaderStageGfxCount);
+ assert(shaderStage < ShaderStage::GfxCount);
- ShaderStage prevStage = ShaderStageInvalid;
+ ShaderStageEnum prevStage = ShaderStage::Invalid;
for (int stage = shaderStage - 1; stage >= 0; --stage) {
- if ((m_stageMask & shaderStageToMask(static_cast<ShaderStage>(stage))) != 0) {
- prevStage = static_cast<ShaderStage>(stage);
+ if (m_stageMask.contains(static_cast<ShaderStageEnum>(stage))) {
+ prevStage = static_cast<ShaderStageEnum>(stage);
break;
}
}
@@ -541,25 +543,25 @@ ShaderStage PipelineState::getPrevShaderStage(ShaderStage shaderStage) const {
// Gets the next active shader stage in this pipeline
//
// @param shaderStage : Current shader stage
-ShaderStage PipelineState::getNextShaderStage(ShaderStage shaderStage) const {
- if (shaderStage == ShaderStageCompute)
- return ShaderStageInvalid;
+ShaderStageEnum PipelineState::getNextShaderStage(ShaderStageEnum shaderStage) const {
+ if (shaderStage == ShaderStage::Compute)
+ return ShaderStage::Invalid;
- if (shaderStage == ShaderStageCopyShader) {
+ if (shaderStage == ShaderStage::CopyShader) {
// Treat copy shader as part of geometry shader
- shaderStage = ShaderStageGeometry;
+ shaderStage = ShaderStage::Geometry;
}
- assert(shaderStage < ShaderStageGfxCount);
+ assert(shaderStage < ShaderStage::GfxCount);
- ShaderStage nextStage = ShaderStageInvalid;
- unsigned stageMask = m_stageMask;
+ ShaderStageEnum nextStage = ShaderStage::Invalid;
+ auto stageMask = m_stageMask;
if (isPartPipeline())
- stageMask |= shaderStageToMask(ShaderStageFragment);
+ stageMask |= ShaderStageMask(ShaderStage::Fragment);
- for (unsigned stage = shaderStage + 1; stage < ShaderStageGfxCount; ++stage) {
- if ((stageMask & shaderStageToMask(static_cast<ShaderStage>(stage))) != 0) {
- nextStage = static_cast<ShaderStage>(stage);
+ for (unsigned stage = shaderStage + 1; stage < ShaderStage::GfxCount; ++stage) {
+ if (stageMask.contains(static_cast<ShaderStageEnum>(stage))) {
+ nextStage = static_cast<ShaderStageEnum>(stage);
break;
}
}
@@ -569,8 +571,8 @@ ShaderStage PipelineState::getNextShaderStage(ShaderStage shaderStage) const {
// =====================================================================================================================
// Get the shader stage mask.
-unsigned PipelineState::getShaderStageMask() {
- if (!m_stageMask && !m_computeLibrary) {
+ShaderStageMask PipelineState::getShaderStageMask() {
+ if (m_stageMask.empty() && !m_computeLibrary) {
// No shader stage mask set (and it isn't a compute library). We must be in ElfLinker; get the shader stage
// mask from PAL metadata.
m_stageMask = getPalMetadata()->getShaderStageMask();
@@ -581,9 +583,9 @@ unsigned PipelineState::getShaderStageMask() {
// =====================================================================================================================
// Check whether the pipeline is a graphics pipeline
bool PipelineState::isGraphics() {
- return (getShaderStageMask() & ((1U << ShaderStageTask) | (1U << ShaderStageVertex) | (1U << ShaderStageTessControl) |
- (1U << ShaderStageTessEval) | (1U << ShaderStageGeometry) | (1U << ShaderStageMesh) |
- (1U << ShaderStageFragment))) != 0;
+ return getShaderStageMask().contains_any({ShaderStage::Task, ShaderStage::Vertex, ShaderStage::TessControl,
+ ShaderStage::TessEval, ShaderStage::Geometry, ShaderStage::Mesh,
+ ShaderStage::Fragment});
}
// =====================================================================================================================
@@ -591,7 +593,7 @@ bool PipelineState::isGraphics() {
//
// @param stage : Shader stage
// @param options : Shader options
-void PipelineState::setShaderOptions(ShaderStage stage, const ShaderOptions &options) {
+void PipelineState::setShaderOptions(ShaderStageEnum stage, const ShaderOptions &options) {
if (m_shaderOptions.size() <= stage)
m_shaderOptions.resize(stage + 1);
m_shaderOptions[stage] = options;
@@ -601,7 +603,7 @@ void PipelineState::setShaderOptions(ShaderStage stage, const ShaderOptions &opt
// Get per-shader options
//
// @param stage : Shader stage
-const ShaderOptions &PipelineState::getShaderOptions(ShaderStage stage) {
+const ShaderOptions &PipelineState::getShaderOptions(ShaderStageEnum stage) {
if (m_shaderOptions.size() <= stage)
m_shaderOptions.resize(stage + 1);
return m_shaderOptions[stage];
@@ -626,7 +628,7 @@ void PipelineState::recordOptions(Module *module) {
setNamedMetadataToArrayOfInt32(module, m_options, OptionsMetadataName);
for (unsigned stage = 0; stage != m_shaderOptions.size(); ++stage) {
std::string metadataName =
- (Twine(OptionsMetadataName) + "." + getShaderStageAbbreviation(static_cast<ShaderStage>(stage))).str();
+ (Twine(OptionsMetadataName) + "." + getShaderStageAbbreviation(static_cast<ShaderStageEnum>(stage))).str();
setNamedMetadataToArrayOfInt32(module, m_shaderOptions[stage], metadataName);
}
}
@@ -656,9 +658,9 @@ void PipelineState::readOptions(Module *module) {
m_preRasterHasGs = preRasterHasGsAsInt;
readNamedMetadataArrayOfInt32(module, OptionsMetadataName, m_options);
- for (unsigned stage = 0; stage != ShaderStageCompute + 1; ++stage) {
+ for (unsigned stage = 0; stage != ShaderStage::Compute + 1; ++stage) {
std::string metadataName =
- (Twine(OptionsMetadataName) + "." + getShaderStageAbbreviation(static_cast<ShaderStage>(stage))).str();
+ (Twine(OptionsMetadataName) + "." + getShaderStageAbbreviation(static_cast<ShaderStageEnum>(stage))).str();
auto namedMetaNode = module->getNamedMetadata(metadataName);
if (!namedMetaNode || namedMetaNode->getNumOperands() == 0)
continue;
@@ -890,11 +892,11 @@ void PipelineState::readUserDataNodes(Module *module) {
// =====================================================================================================================
// Returns the resource node for the push constant.
//
-// @param stage : Shader stage to check against nodes' visibility field, or ShaderStageInvalid for any
-const ResourceNode *PipelineState::findPushConstantResourceNode(ShaderStage stage) const {
+// @param stage : Shader stage to check against nodes' visibility field, or ShaderStage::Invalid for any
+const ResourceNode *PipelineState::findPushConstantResourceNode(std::optional<ShaderStageEnum> stage) const {
unsigned visibilityMask = UINT_MAX;
- if (stage != ShaderStageInvalid)
- visibilityMask = 1 << std::min(unsigned(stage), unsigned(ShaderStageCompute));
+ if (stage)
+ visibilityMask = 1 << std::min(unsigned(stage.value()), unsigned(ShaderStage::Compute));
for (const ResourceNode &node : getUserDataNodes()) {
if (node.visibility != 0 && (node.visibility & visibilityMask) == 0)
@@ -1014,17 +1016,19 @@ bool PipelineState::matchResourceNode(const ResourceNode &node, ResourceNodeType
// If the node is not found and nodeType == Fmask, then a search will be done for a DescriptorResource at the given
// descriptor set and binding.
//
+// If pipeline option useResourceBindingRange is set, then a node matches a range of bindings of size
+// sizeInDwords/stride.
+//
// @param nodeType : Type of the resource mapping node
// @param descSet : ID of descriptor set
// @param binding : ID of descriptor binding
-// @param stage : Shader stage to check against nodes' visibility field, or ShaderStageInvalid for any
-std::pair<const ResourceNode *, const ResourceNode *> PipelineState::findResourceNode(ResourceNodeType nodeType,
- uint64_t descSet,
- unsigned binding,
- ShaderStage stage) const {
+// @param stage : Shader stage to check against nodes' visibility field, or ShaderStage::Invalid for any
+std::pair<const ResourceNode *, const ResourceNode *>
+PipelineState::findResourceNode(ResourceNodeType nodeType, uint64_t descSet, unsigned binding,
+ std::optional<ShaderStageEnum> stage) const {
unsigned visibilityMask = UINT_MAX;
- if (stage != ShaderStageInvalid)
- visibilityMask = 1 << std::min(unsigned(stage), unsigned(ShaderStageCompute));
+ if (stage)
+ visibilityMask = 1 << std::min(unsigned(stage.value()), unsigned(ShaderStage::Compute));
for (const ResourceNode &node : getUserDataNodes()) {
if (!nodeTypeHasBinding(node.concreteType))
@@ -1070,11 +1074,11 @@ std::pair<const ResourceNode *, const ResourceNode *> PipelineState::findResourc
// Find the single root resource node of the given type
//
// @param nodeType : Type of the resource mapping node
-// @param stage : Shader stage to check against nodes' visibility field, or ShaderStageInvalid for any
-const ResourceNode *PipelineState::findSingleRootResourceNode(ResourceNodeType nodeType, ShaderStage stage) const {
+// @param stage : Shader stage to check against nodes' visibility field, or ShaderStage::Invalid for any
+const ResourceNode *PipelineState::findSingleRootResourceNode(ResourceNodeType nodeType, ShaderStageEnum stage) const {
unsigned visibilityMask = UINT_MAX;
- if (stage != ShaderStageInvalid)
- visibilityMask = 1 << std::min(unsigned(stage), unsigned(ShaderStageCompute));
+ if (stage != ShaderStage::Invalid)
+ visibilityMask = 1 << std::min(unsigned(stage), unsigned(ShaderStage::Compute));
for (const ResourceNode &node : getUserDataNodes()) {
if (node.visibility != 0 && (node.visibility & visibilityMask) == 0)
@@ -1340,13 +1344,13 @@ unsigned PipelineState::getNumPatchControlPoints() const {
// NOTE: Need to be called after PatchResourceCollect pass, so usage of subgroupSize is confirmed.
//
// @param stage : Shader stage
-unsigned PipelineState::getShaderWaveSize(ShaderStage stage) {
- if (stage == ShaderStageCopyShader) {
+unsigned PipelineState::getShaderWaveSize(ShaderStageEnum stage) {
+ if (stage == ShaderStage::CopyShader) {
// Treat copy shader as part of geometry shader
- stage = ShaderStageGeometry;
+ stage = ShaderStage::Geometry;
}
- assert(stage <= ShaderStageCompute);
+ assert(stage <= ShaderStage::Compute);
if (!m_waveSize[stage])
setShaderDefaultWaveSize(stage);
@@ -1363,7 +1367,7 @@ unsigned PipelineState::getShaderWaveSize(ShaderStage stage) {
// NOTE: For GFX9+, two shaders are merged as a shader pair. The wave size is determined by the larger one.
//
// @param stage : Shader stage
-unsigned PipelineState::getMergedShaderWaveSize(ShaderStage stage) {
+unsigned PipelineState::getMergedShaderWaveSize(ShaderStageEnum stage) {
assert(getTargetInfo().getGfxIpVersion().major >= 9);
unsigned waveSize = m_waveSize[stage];
@@ -1374,34 +1378,34 @@ unsigned PipelineState::getMergedShaderWaveSize(ShaderStage stage) {
// - TES + GS -> HW GS
// - VS/TES -> HW GS (NGG, no geometry)
switch (stage) {
- case ShaderStageVertex:
- if (hasShaderStage(ShaderStageTessControl)) {
- return std::max(waveSize, m_waveSize[ShaderStageTessControl]);
+ case ShaderStage::Vertex:
+ if (hasShaderStage(ShaderStage::TessControl)) {
+ return std::max(waveSize, m_waveSize[ShaderStage::TessControl]);
}
- if (hasShaderStage(ShaderStageGeometry)) {
- return std::max(waveSize, m_waveSize[ShaderStageGeometry]);
+ if (hasShaderStage(ShaderStage::Geometry)) {
+ return std::max(waveSize, m_waveSize[ShaderStage::Geometry]);
}
return waveSize;
- case ShaderStageTessControl:
- return std::max(waveSize, m_waveSize[ShaderStageVertex]);
+ case ShaderStage::TessControl:
+ return std::max(waveSize, m_waveSize[ShaderStage::Vertex]);
- case ShaderStageTessEval:
- if (hasShaderStage(ShaderStageGeometry)) {
- return std::max(waveSize, m_waveSize[ShaderStageGeometry]);
+ case ShaderStage::TessEval:
+ if (hasShaderStage(ShaderStage::Geometry)) {
+ return std::max(waveSize, m_waveSize[ShaderStage::Geometry]);
}
return waveSize;
- case ShaderStageGeometry:
- if (!hasShaderStage(ShaderStageGeometry)) {
+ case ShaderStage::Geometry:
+ if (!hasShaderStage(ShaderStage::Geometry)) {
// NGG, no geometry
return std::max(waveSize,
- m_waveSize[hasShaderStage(ShaderStageTessEval) ? ShaderStageTessEval : ShaderStageVertex]);
+ m_waveSize[hasShaderStage(ShaderStage::TessEval) ? ShaderStage::TessEval : ShaderStage::Vertex]);
}
- if (hasShaderStage(ShaderStageTessEval)) {
- return std::max(waveSize, m_waveSize[ShaderStageTessEval]);
+ if (hasShaderStage(ShaderStage::TessEval)) {
+ return std::max(waveSize, m_waveSize[ShaderStage::TessEval]);
}
- return std::max(waveSize, m_waveSize[ShaderStageVertex]);
+ return std::max(waveSize, m_waveSize[ShaderStage::Vertex]);
default:
return waveSize;
@@ -1413,13 +1417,13 @@ unsigned PipelineState::getMergedShaderWaveSize(ShaderStage stage) {
//
// @param stage : Shader stage
// @returns : Subgroup size of the specified shader stage
-unsigned PipelineState::getShaderSubgroupSize(ShaderStage stage) {
- if (stage == ShaderStageCopyShader) {
+unsigned PipelineState::getShaderSubgroupSize(ShaderStageEnum stage) {
+ if (stage == ShaderStage::CopyShader) {
// Treat copy shader as part of geometry shader
- stage = ShaderStageGeometry;
+ stage = ShaderStage::Geometry;
}
- assert(stage <= ShaderStageCompute);
+ assert(stage <= ShaderStage::Compute);
if (!m_subgroupSize[stage])
setShaderDefaultWaveSize(stage);
@@ -1430,16 +1434,16 @@ unsigned PipelineState::getShaderSubgroupSize(ShaderStage stage) {
// Set the default wave size for the specified shader stage
//
// @param stage : Shader stage
-void PipelineState::setShaderDefaultWaveSize(ShaderStage stage) {
- ShaderStage checkingStage = stage;
+void PipelineState::setShaderDefaultWaveSize(ShaderStageEnum stage) {
+ ShaderStageEnum checkingStage = stage;
const bool isGfx10Plus = getTargetInfo().getGfxIpVersion().major >= 10;
- if (isGfx10Plus && stage == ShaderStageGeometry && !hasShaderStage(ShaderStageGeometry)) {
+ if (isGfx10Plus && stage == ShaderStage::Geometry && !hasShaderStage(ShaderStage::Geometry)) {
// NOTE: For NGG, GS could be absent and VS/TES acts as part of it in the merged shader.
// In such cases, we check the property of VS or TES.
- checkingStage = hasShaderStage(ShaderStageTessEval) ? ShaderStageTessEval : ShaderStageVertex;
+ checkingStage = hasShaderStage(ShaderStage::TessEval) ? ShaderStage::TessEval : ShaderStage::Vertex;
}
- if (checkingStage == ShaderStageCompute)
+ if (checkingStage == ShaderStage::Compute)
m_waveSize[checkingStage] = m_shaderModes.getComputeShaderMode().subgroupSize;
if (!m_waveSize[checkingStage]) {
@@ -1454,10 +1458,10 @@ void PipelineState::setShaderDefaultWaveSize(ShaderStage stage) {
// 4) If gl_SubgroupSize is not used in the (mesh/task/compute) shader, and the workgroup size is
// not larger than 32, use wave size 32.
- if (checkingStage == ShaderStageFragment) {
+ if (checkingStage == ShaderStage::Fragment) {
// Per programming guide, it's recommended to use wave64 for fragment shader.
waveSize = 64;
- } else if (hasShaderStage(ShaderStageGeometry)) {
+ } else if (hasShaderStage(ShaderStage::Geometry)) {
// Legacy (non-NGG) hardware path for GS does not support wave32.
waveSize = 64;
if (getTargetInfo().getGfxIpVersion().major >= 11)
@@ -1466,7 +1470,7 @@ void PipelineState::setShaderDefaultWaveSize(ShaderStage stage) {
// Experimental data from performance tuning show that wave64 is more efficient than wave32 in most cases for CS
// on post-GFX10.3. Hence, set the wave size to wave64 by default.
- if (getTargetInfo().getGfxIpVersion() >= GfxIpVersion({10, 3}) && stage == ShaderStageCompute)
+ if (getTargetInfo().getGfxIpVersion() >= GfxIpVersion({10, 3}) && stage == ShaderStage::Compute)
waveSize = 64;
// Prefer wave64 on GFX11+
@@ -1479,13 +1483,14 @@ void PipelineState::setShaderDefaultWaveSize(ShaderStage stage) {
// Note: the conditions below override the tuning option.
// If workgroup size is not larger than 32, use wave size 32.
- if (checkingStage == ShaderStageMesh || checkingStage == ShaderStageTask || checkingStage == ShaderStageCompute) {
+ if (checkingStage == ShaderStage::Mesh || checkingStage == ShaderStage::Task ||
+ checkingStage == ShaderStage::Compute) {
unsigned workGroupSize;
- if (checkingStage == ShaderStageMesh) {
+ if (checkingStage == ShaderStage::Mesh) {
auto &mode = m_shaderModes.getMeshShaderMode();
workGroupSize = mode.workgroupSizeX * mode.workgroupSizeY * mode.workgroupSizeZ;
} else {
- assert(checkingStage == ShaderStageTask || checkingStage == ShaderStageCompute);
+ assert(checkingStage == ShaderStage::Task || checkingStage == ShaderStage::Compute);
auto &mode = m_shaderModes.getComputeShaderMode();
workGroupSize = mode.workgroupSizeX * mode.workgroupSizeY * mode.workgroupSizeZ;
}
@@ -1528,13 +1533,13 @@ void PipelineState::setShaderDefaultWaveSize(ShaderStage stage) {
// Whether WGP mode is enabled for the given shader stage
//
// @param stage : Shader stage
-bool PipelineState::getShaderWgpMode(ShaderStage stage) const {
- if (stage == ShaderStageCopyShader) {
+bool PipelineState::getShaderWgpMode(ShaderStageEnum stage) const {
+ if (stage == ShaderStage::CopyShader) {
// Treat copy shader as part of geometry shader
- stage = ShaderStageGeometry;
+ stage = ShaderStage::Geometry;
}
- assert(stage <= ShaderStageCompute);
+ assert(stage <= ShaderStage::Compute);
assert(stage < m_shaderOptions.size());
return m_shaderOptions[stage].wgpMode;
@@ -1567,13 +1572,13 @@ bool PipelineState::enableSwXfb() {
return false;
// Mesh pipeline doesn't support stream-out
- if (hasShaderStage(ShaderStageTask) || hasShaderStage(ShaderStageMesh))
+ if (hasShaderStage(ShaderStage::Task) || hasShaderStage(ShaderStage::Mesh))
return false;
auto lastVertexStage = getLastVertexProcessingStage();
- lastVertexStage = lastVertexStage == ShaderStageCopyShader ? ShaderStageGeometry : lastVertexStage;
+ lastVertexStage = lastVertexStage == ShaderStage::CopyShader ? ShaderStage::Geometry : lastVertexStage;
- if (lastVertexStage == ShaderStageInvalid) {
+ if (lastVertexStage == ShaderStage::Invalid) {
assert(isUnlinked()); // Unlinked pipeline only having fragment shader.
return false;
}
@@ -1585,9 +1590,9 @@ bool PipelineState::enableSwXfb() {
// Gets resource usage of the specified shader stage
//
// @param shaderStage : Shader stage
-ResourceUsage *PipelineState::getShaderResourceUsage(ShaderStage shaderStage) {
- if (shaderStage == ShaderStageCopyShader)
- shaderStage = ShaderStageGeometry;
+ResourceUsage *PipelineState::getShaderResourceUsage(ShaderStageEnum shaderStage) {
+ if (shaderStage == ShaderStage::CopyShader)
+ shaderStage = ShaderStage::Geometry;
auto &resUsage = MutableArrayRef<std::unique_ptr<ResourceUsage>>(m_resourceUsage)[shaderStage];
if (!resUsage) {
@@ -1600,9 +1605,9 @@ ResourceUsage *PipelineState::getShaderResourceUsage(ShaderStage shaderStage) {
// Gets interface data of the specified shader stage
//
// @param shaderStage : Shader stage
-InterfaceData *PipelineState::getShaderInterfaceData(ShaderStage shaderStage) {
- if (shaderStage == ShaderStageCopyShader)
- shaderStage = ShaderStageGeometry;
+InterfaceData *PipelineState::getShaderInterfaceData(ShaderStageEnum shaderStage) {
+ if (shaderStage == ShaderStage::CopyShader)
+ shaderStage = ShaderStage::Geometry;
auto &intfData = MutableArrayRef<std::unique_ptr<InterfaceData>>(m_interfaceData)[shaderStage];
if (!intfData) {
@@ -1760,7 +1765,7 @@ StringRef PipelineState::getBuiltInName(BuiltInKind builtIn) {
bool PipelineState::canOptimizeTessFactor() {
if (getTargetInfo().getGfxIpVersion().major < 11)
return false;
- auto resUsage = getShaderResourceUsage(ShaderStageTessControl);
+ auto resUsage = getShaderResourceUsage(ShaderStage::TessControl);
auto &perPatchBuiltInOutLocMap = resUsage->inOutUsage.perPatchBuiltInOutputLocMap;
// Disable tessellation factor optimization if TFs are read in TES or TCS
if (perPatchBuiltInOutLocMap.count(BuiltInTessLevelOuter) || perPatchBuiltInOutLocMap.count(BuiltInTessLevelInner))
@@ -1775,33 +1780,33 @@ void PipelineState::initializeInOutPackState() {
// If the pipeline is not unlinked, the state of input/output pack in specified shader stages is enabled
if (!isUnlinked()) {
// The generic input imports of {TCS, GS, FS} are packed by default
- m_inputPackState[ShaderStageTessControl] = true;
- m_inputPackState[ShaderStageGeometry] = true;
- m_inputPackState[ShaderStageFragment] = true;
+ m_inputPackState[ShaderStage::TessControl] = true;
+ m_inputPackState[ShaderStage::Geometry] = true;
+ m_inputPackState[ShaderStage::Fragment] = true;
// The generic output exports of {VS, TES, GS} are packed by default
- m_outputPackState[ShaderStageVertex] = true;
- m_outputPackState[ShaderStageTessEval] = true;
- m_outputPackState[ShaderStageGeometry] = true;
+ m_outputPackState[ShaderStage::Vertex] = true;
+ m_outputPackState[ShaderStage::TessEval] = true;
+ m_outputPackState[ShaderStage::Geometry] = true;
// NOTE: For mesh shader, we don't do in-out packing currently in that mesh shader could emit per-vertex outputs
// and per-primitive outputs, which introduces additional complexity and this complexity increases with the
// involvement of dynamic indexing.
- if (hasShaderStage(ShaderStageMesh)) {
- m_outputPackState[ShaderStageMesh] = false;
- m_inputPackState[ShaderStageFragment] = false;
+ if (hasShaderStage(ShaderStage::Mesh)) {
+ m_outputPackState[ShaderStage::Mesh] = false;
+ m_inputPackState[ShaderStage::Fragment] = false;
}
} else {
// For unlinked shaders, we can do in-out packing if the pipeline has two adjacent shaders.
// We are assuming that if any of the vertex processing, then the vertex processing stages are complete. For
// example, if we see a vertex shader and geometry shader with no tessellation shaders, then we will assume we can
// pack the vertex outputs and geometry inputs because no tessellation shader will be added later.
- for (ShaderStage stage : lgc::enumRange(ShaderStage::ShaderStageGfxCount)) {
- if ((m_stageMask & shaderStageToMask(stage)) == 0)
+ for (ShaderStageEnum stage : lgc::enumRange(ShaderStage::GfxCount)) {
+ if (!m_stageMask.contains(stage))
continue;
- if (stage == ShaderStageTessEval)
+ if (stage == ShaderStage::TessEval)
continue;
- ShaderStage preStage = getPrevShaderStage(stage);
- if (preStage == ShaderStageInvalid)
+ ShaderStageEnum preStage = getPrevShaderStage(stage);
+ if (preStage == ShaderStage::Invalid)
continue;
m_inputPackState[stage] = true;
m_outputPackState[preStage] = true;
@@ -1813,12 +1818,12 @@ void PipelineState::initializeInOutPackState() {
// Get whether the input locations of the specified shader stage can be packed
//
// @param shaderStage : The given shader stage
-bool PipelineState::canPackInput(ShaderStage shaderStage) {
- ShaderStage preStage = getPrevShaderStage(shaderStage);
+bool PipelineState::canPackInput(ShaderStageEnum shaderStage) {
+ ShaderStageEnum preStage = getPrevShaderStage(shaderStage);
// The input packable state of the current stage should match the output packable state of the previous stage, except
// that the current stage has no previous and it is a null FS.
- if (preStage != ShaderStageInvalid &&
- !(shaderStage == ShaderStageFragment && getShaderResourceUsage(shaderStage)->inOutUsage.fs.isNullFs))
+ if (preStage != ShaderStage::Invalid &&
+ !(shaderStage == ShaderStage::Fragment && getShaderResourceUsage(shaderStage)->inOutUsage.fs.isNullFs))
assert(m_inputPackState[shaderStage] == m_outputPackState[preStage]);
return m_inputPackState[shaderStage];
}
@@ -1827,12 +1832,12 @@ bool PipelineState::canPackInput(ShaderStage shaderStage) {
// Get whether the output locations of the specified shader stage can be packed
//
// @param shaderStage : The given shader stage
-bool PipelineState::canPackOutput(ShaderStage shaderStage) {
- ShaderStage nextStage = getNextShaderStage(shaderStage);
+bool PipelineState::canPackOutput(ShaderStageEnum shaderStage) {
+ ShaderStageEnum nextStage = getNextShaderStage(shaderStage);
// The output packable state of the current stage should match the input packable state of the next stage, except that
// the current stage has no next stage or a null FS.
- if (nextStage != ShaderStageInvalid &&
- !(nextStage == ShaderStageFragment && getShaderResourceUsage(nextStage)->inOutUsage.fs.isNullFs))
+ if (nextStage != ShaderStage::Invalid &&
+ !(nextStage == ShaderStage::Fragment && getShaderResourceUsage(nextStage)->inOutUsage.fs.isNullFs))
assert(m_outputPackState[shaderStage] == m_inputPackState[nextStage]);
return m_outputPackState[shaderStage];
}
@@ -1840,7 +1845,7 @@ bool PipelineState::canPackOutput(ShaderStage shaderStage) {
// =====================================================================================================================
// Get the count of vertices per primitive. For GS, the count is for output primitive.
unsigned PipelineState::getVerticesPerPrimitive() {
- if (hasShaderStage(ShaderStageGeometry)) {
+ if (hasShaderStage(ShaderStage::Geometry)) {
const auto &geometryMode = getShaderModes()->getGeometryShaderMode();
switch (geometryMode.outputPrimitive) {
case OutputPrimitives::Points:
@@ -1853,7 +1858,7 @@ unsigned PipelineState::getVerticesPerPrimitive() {
llvm_unreachable("Unexpected output primitive type!");
return 0;
}
- } else if (hasShaderStage(ShaderStageTessControl) || hasShaderStage(ShaderStageTessEval)) {
+ } else if (hasShaderStage(ShaderStage::TessControl) || hasShaderStage(ShaderStage::TessEval)) {
assert(getInputAssemblyState().primitiveType == PrimitiveType::Patch);
const auto &tessMode = getShaderModes()->getTessellationMode();
if (tessMode.pointMode)
@@ -1888,7 +1893,7 @@ unsigned PipelineState::getVerticesPerPrimitive() {
// =====================================================================================================================
// Get the primitive type. For GS, the type is for output primitive.
PrimitiveType PipelineState::getPrimitiveType() {
- if (hasShaderStage(ShaderStageGeometry)) {
+ if (hasShaderStage(ShaderStage::Geometry)) {
const auto &geometryMode = getShaderModes()->getGeometryShaderMode();
switch (geometryMode.outputPrimitive) {
case OutputPrimitives::Points:
@@ -1900,7 +1905,7 @@ PrimitiveType PipelineState::getPrimitiveType() {
default:
llvm_unreachable("Unexpected output primitive type!");
}
- } else if (hasShaderStage(ShaderStageTessControl) || hasShaderStage(ShaderStageTessEval)) {
+ } else if (hasShaderStage(ShaderStage::TessControl) || hasShaderStage(ShaderStage::TessEval)) {
assert(getInputAssemblyState().primitiveType == PrimitiveType::Patch);
const auto &tessMode = getShaderModes()->getTessellationMode();
if (tessMode.pointMode)
diff --git a/lgc/state/RayTracingLibrarySummary.cpp b/lgc/state/RayTracingLibrarySummary.cpp
new file mode 100644
index 0000000000..fe38599edf
--- /dev/null
+++ b/lgc/state/RayTracingLibrarySummary.cpp
@@ -0,0 +1,121 @@
+/*
+ ***********************************************************************************************************************
+ *
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ **********************************************************************************************************************/
+/**
+ ***********************************************************************************************************************
+ * @file RayTracingLibrarySummary.cpp
+ * @brief Implementation of helpers for raytracing library summaries
+ ***********************************************************************************************************************
+ */
+
+#include "lgc/RayTracingLibrarySummary.h"
+#include "llvm/BinaryFormat/MsgPackDocument.h"
+
+using namespace llvm;
+using namespace lgc;
+
+namespace {
+namespace RtLibSummary {
+
+constexpr unsigned MajorVersion = 1;
+
+static constexpr char Version[] = "version";
+static constexpr char UsesTraceRay[] = "uses_trace_ray";
+static constexpr char KnownSetRayFlags[] = "ray_flags_known_set";
+static constexpr char KnownUnsetRayFlags[] = "ray_flags_known_unset";
+static constexpr char MaxRayPayloadSize[] = "max_ray_payload_size";
+static constexpr char MaxHitAttributeSize[] = "max_hit_attribute_size";
+static constexpr char HasKernelEntry[] = "has_kernel_entry";
+static constexpr char HasTraceRayModule[] = "has_trace_ray_module";
+
+} // namespace RtLibSummary
+} // anonymous namespace
+
+Expected<RayTracingLibrarySummary> RayTracingLibrarySummary::decodeMsgpack(StringRef data) {
+ RayTracingLibrarySummary rls = {};
+ msgpack::Document doc;
+
+ if (!doc.readFromBlob(data, false))
+ return make_error<StringError>("failed to parse msgpack", inconvertibleErrorCode());
+
+ auto &root = doc.getRoot().getMap();
+
+ auto getBool = [](msgpack::DocNode &node, bool &out) {
+ if (!node.isEmpty())
+ out = node.getBool();
+ };
+ auto getUInt = [](msgpack::DocNode &node, auto &out) {
+ if (!node.isEmpty())
+ out = node.getUInt();
+ };
+
+ uint64_t version = 0;
+ getUInt(root[RtLibSummary::Version], version);
+ if (version != RtLibSummary::MajorVersion)
+ return make_error<StringError>("bad/missing RtLibSummary version", inconvertibleErrorCode());
+
+ getBool(root[RtLibSummary::UsesTraceRay], rls.usesTraceRay);
+ getUInt(root[RtLibSummary::KnownSetRayFlags], rls.knownSetRayFlags);
+ getUInt(root[RtLibSummary::KnownUnsetRayFlags], rls.knownUnsetRayFlags);
+ getUInt(root[RtLibSummary::MaxRayPayloadSize], rls.maxRayPayloadSize);
+ getUInt(root[RtLibSummary::MaxHitAttributeSize], rls.maxHitAttributeSize);
+ getBool(root[RtLibSummary::HasKernelEntry], rls.hasKernelEntry);
+ getBool(root[RtLibSummary::HasTraceRayModule], rls.hasTraceRayModule);
+
+ return rls;
+}
+
+std::string RayTracingLibrarySummary::encodeMsgpack() const {
+ msgpack::Document doc;
+
+ auto &root = doc.getRoot().getMap(true);
+
+ root[RtLibSummary::Version] = RtLibSummary::MajorVersion;
+
+ root[RtLibSummary::UsesTraceRay] = usesTraceRay;
+ root[RtLibSummary::KnownSetRayFlags] = knownSetRayFlags;
+ root[RtLibSummary::KnownUnsetRayFlags] = knownUnsetRayFlags;
+ root[RtLibSummary::MaxRayPayloadSize] = maxRayPayloadSize;
+ root[RtLibSummary::MaxHitAttributeSize] = maxHitAttributeSize;
+ root[RtLibSummary::HasKernelEntry] = hasKernelEntry;
+ root[RtLibSummary::HasTraceRayModule] = hasTraceRayModule;
+
+ std::string out;
+ doc.writeToBlob(out);
+ return out;
+}
+
+void RayTracingLibrarySummary::merge(const RayTracingLibrarySummary &other) {
+ usesTraceRay |= other.usesTraceRay;
+ if (other.usesTraceRay) {
+ knownSetRayFlags &= other.knownSetRayFlags;
+ knownUnsetRayFlags &= other.knownUnsetRayFlags;
+ }
+ maxRayPayloadSize = std::max(maxRayPayloadSize, other.maxRayPayloadSize);
+ maxHitAttributeSize = std::max(maxHitAttributeSize, other.maxHitAttributeSize);
+
+ // TODO: Inherit kernel entry and trace ray module if possible and avoid recompile?
+ hasKernelEntry = false;
+ hasTraceRayModule = false;
+}
diff --git a/lgc/state/ResourceUsage.cpp b/lgc/state/ResourceUsage.cpp
index ddc17dd478..2e09897e4d 100644
--- a/lgc/state/ResourceUsage.cpp
+++ b/lgc/state/ResourceUsage.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -33,20 +33,20 @@
using namespace lgc;
// =====================================================================================================================
-ResourceUsage::ResourceUsage(ShaderStage shaderStage) {
+ResourceUsage::ResourceUsage(ShaderStageEnum shaderStage) {
// NOTE: We use memset to explicitly zero builtInUsage since it has unions inside.
memset(&builtInUsage, 0, sizeof(builtInUsage));
- if (shaderStage == ShaderStageVertex) {
+ if (shaderStage == ShaderStage::Vertex) {
// NOTE: For vertex shader, PAL expects base vertex and base instance in user data,
// even if they are not used in shader.
builtInUsage.vs.baseVertex = true;
builtInUsage.vs.baseInstance = true;
- } else if (shaderStage == ShaderStageTessControl) {
+ } else if (shaderStage == ShaderStage::TessControl) {
inOutUsage.tcs.calcFactor = {};
- } else if (shaderStage == ShaderStageGeometry) {
+ } else if (shaderStage == ShaderStage::Geometry) {
inOutUsage.gs.calcFactor = {};
- } else if (shaderStage == ShaderStageFragment) {
+ } else if (shaderStage == ShaderStage::Fragment) {
for (uint32_t i = 0; i < MaxColorTargets; ++i) {
inOutUsage.fs.outputTypes[i] = BasicType::Unknown;
}
diff --git a/lgc/state/ShaderModes.cpp b/lgc/state/ShaderModes.cpp
index 479e27c665..aec7d7699c 100644
--- a/lgc/state/ShaderModes.cpp
+++ b/lgc/state/ShaderModes.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -60,18 +60,18 @@ void ShaderModes::clear() {
// @param module : Module to record in
// @param stage : Shader stage
// @param commonShaderMode : Common shader mode
-void ShaderModes::setCommonShaderMode(Module &module, ShaderStage stage, const CommonShaderMode &commonShaderMode) {
+void ShaderModes::setCommonShaderMode(Module &module, ShaderStageEnum stage, const CommonShaderMode &commonShaderMode) {
SmallString<64> metadataName(CommonShaderModeMetadataPrefix);
- metadataName += getShaderStageAbbreviation(static_cast<ShaderStage>(stage));
+ metadataName += getShaderStageAbbreviation(static_cast<ShaderStageEnum>(stage));
// Or the mode into any existing recorded mode, in case the front-end has already called setSubgroupSizeUsage.
PipelineState::orNamedMetadataToArrayOfInt32(&module, commonShaderMode, metadataName);
}
// =====================================================================================================================
// Get the common shader modes for the given shader stage: static edition that reads directly from IR.
-CommonShaderMode ShaderModes::getCommonShaderMode(Module &module, ShaderStage stage) {
+CommonShaderMode ShaderModes::getCommonShaderMode(Module &module, ShaderStageEnum stage) {
SmallString<64> metadataName(CommonShaderModeMetadataPrefix);
- metadataName += getShaderStageAbbreviation(static_cast<ShaderStage>(stage));
+ metadataName += getShaderStageAbbreviation(static_cast<ShaderStageEnum>(stage));
CommonShaderMode mode = {};
PipelineState::readNamedMetadataArrayOfInt32(&module, metadataName, mode);
return mode;
@@ -81,7 +81,7 @@ CommonShaderMode ShaderModes::getCommonShaderMode(Module &module, ShaderStage st
// Get the common shader mode (FP mode) for the given shader stage
//
// @param stage : Shader stage
-const CommonShaderMode &ShaderModes::getCommonShaderMode(ShaderStage stage) const {
+const CommonShaderMode &ShaderModes::getCommonShaderMode(ShaderStageEnum stage) const {
return ArrayRef<CommonShaderMode>(m_commonShaderModes)[stage];
}
@@ -103,19 +103,19 @@ bool ShaderModes::getAnyUseSubgroupSize() const {
// @param module : Module to record in
// @param stage : Shader stage
// @param inMode : Tessellation mode
-void ShaderModes::setTessellationMode(Module &module, ShaderStage stage, const TessellationMode &inMode) {
- assert(stage == ShaderStageTessControl || stage == ShaderStageTessEval);
+void ShaderModes::setTessellationMode(Module &module, ShaderStageEnum stage, const TessellationMode &inMode) {
+ assert(stage == ShaderStage::TessControl || stage == ShaderStage::TessEval);
PipelineState::setNamedMetadataToArrayOfInt32(
- &module, inMode, stage == ShaderStageTessControl ? TcsModeMetadataName : TesModeMetadataName);
+ &module, inMode, stage == ShaderStage::TessControl ? TcsModeMetadataName : TesModeMetadataName);
}
// =====================================================================================================================
// Get the tessellation mode for the given shader stage (TCS or TES): static edition that reads directly from IR.
-TessellationMode ShaderModes::getTessellationMode(Module &module, ShaderStage stage) {
- assert(stage == ShaderStageTessControl || stage == ShaderStageTessEval);
+TessellationMode ShaderModes::getTessellationMode(Module &module, ShaderStageEnum stage) {
+ assert(stage == ShaderStage::TessControl || stage == ShaderStage::TessEval);
TessellationMode mode = {};
PipelineState::readNamedMetadataArrayOfInt32(
- &module, stage == ShaderStageTessControl ? TcsModeMetadataName : TesModeMetadataName, mode);
+ &module, stage == ShaderStage::TessControl ? TcsModeMetadataName : TesModeMetadataName, mode);
return mode;
}
@@ -207,11 +207,11 @@ const ComputeShaderMode &ShaderModes::getComputeShaderMode() const {
// @param module : Module to record in
// @param stage : Shader stage
// @param usage : Subgroup size usage
-void ShaderModes::setSubgroupSizeUsage(Module &module, ShaderStage stage, bool usage) {
+void ShaderModes::setSubgroupSizeUsage(Module &module, ShaderStageEnum stage, bool usage) {
CommonShaderMode mode = {};
mode.useSubgroupSize = usage;
SmallString<64> metadataName(CommonShaderModeMetadataPrefix);
- metadataName += getShaderStageAbbreviation(static_cast<ShaderStage>(stage));
+ metadataName += getShaderStageAbbreviation(static_cast<ShaderStageEnum>(stage));
// Or the mode into any existing recorded mode, in case the front-end has already called setCommonShaderMode.
PipelineState::orNamedMetadataToArrayOfInt32(&module, mode, metadataName);
}
@@ -223,7 +223,7 @@ void ShaderModes::setSubgroupSizeUsage(Module &module, ShaderStage stage, bool u
void ShaderModes::readModesFromPipeline(Module *module) {
// First the common state.
for (unsigned stage = 0; stage < ArrayRef<CommonShaderMode>(m_commonShaderModes).size(); ++stage)
- m_commonShaderModes[stage] = getCommonShaderMode(*module, ShaderStage(stage));
+ m_commonShaderModes[stage] = getCommonShaderMode(*module, ShaderStageEnum(stage));
// Then the specific shader modes except tessellation.
PipelineState::readNamedMetadataArrayOfInt32(module, GeometryShaderModeMetadataName, m_geometryShaderMode);
diff --git a/lgc/state/ShaderStage.cpp b/lgc/state/ShaderStage.cpp
index 77d3417951..e97961b48d 100644
--- a/lgc/state/ShaderStage.cpp
+++ b/lgc/state/ShaderStage.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,14 +17,14 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
***********************************************************************************************************************
- * @file ShaderStage.cpp
+ * @file ShaderStageEnum.cpp
* @brief LLPC source file: utility functions for shader stage
***********************************************************************************************************************
*/
@@ -50,13 +50,16 @@ const static char ShaderStageMetadata[] = "lgc.shaderstage";
//
// @param [in/out] module : Module to set shader stage on
// @param stage : Shader stage to set
-void lgc::setShaderStage(Module *module, ShaderStage stage) {
+void lgc::setShaderStage(Module *module, std::optional<ShaderStageEnum> stage) {
unsigned mdKindId = module->getContext().getMDKindID(ShaderStageMetadata);
- auto stageMetaNode = MDNode::get(
- module->getContext(), {ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(module->getContext()), stage))});
+ auto stageMetaNode =
+ stage ? MDNode::get(
+ module->getContext(),
+ {ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(module->getContext()), stage.value()))})
+ : nullptr;
for (Function &func : *module) {
if (!func.isDeclaration()) {
- if (stage != ShaderStageInvalid)
+ if (stage)
func.setMetadata(mdKindId, stageMetaNode);
else
func.eraseMetadata(mdKindId);
@@ -68,27 +71,28 @@ void lgc::setShaderStage(Module *module, ShaderStage stage) {
// Set shader stage metadata on a function
//
// @param [in/out] func : Function to set shader stage on
-// @param stage : Shader stage to set or ShaderStageInvalid
-void lgc::setShaderStage(Function *func, ShaderStage stage) {
+// @param stage : Shader stage to set or ShaderStage::Invalid
+void lgc::setShaderStage(Function *func, std::optional<ShaderStageEnum> stage) {
unsigned mdKindId = func->getContext().getMDKindID(ShaderStageMetadata);
- if (stage != ShaderStageInvalid) {
- auto stageMetaNode = MDNode::get(
- func->getContext(), {ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(func->getContext()), stage))});
+ if (stage) {
+ auto stageMetaNode =
+ MDNode::get(func->getContext(),
+ {ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(func->getContext()), stage.value()))});
func->setMetadata(mdKindId, stageMetaNode);
} else
func->eraseMetadata(mdKindId);
}
// =====================================================================================================================
-// Gets the shader stage from the specified LLVM function. Returns ShaderStageInvalid if metadata not found.
+// Gets the shader stage from the specified LLVM function. Returns ShaderStage::Invalid if metadata not found.
//
// @param func : LLVM function
-ShaderStage lgc::getShaderStage(const Function *func) {
+std::optional<ShaderStageEnum> lgc::getShaderStage(const Function *func) {
// Check for the metadata that is added by PipelineState::link.
MDNode *stageMetaNode = func->getMetadata(ShaderStageMetadata);
if (stageMetaNode)
- return ShaderStage(mdconst::dyn_extract<ConstantInt>(stageMetaNode->getOperand(0))->getZExtValue());
- return ShaderStageInvalid;
+ return ShaderStageEnum(mdconst::dyn_extract<ConstantInt>(stageMetaNode->getOperand(0))->getZExtValue());
+ return std::nullopt;
}
// =====================================================================================================================
@@ -105,10 +109,10 @@ bool lgc::isShaderEntryPoint(const Function *func) {
// Gets name string of the abbreviation for the specified shader stage
//
// @param shaderStage : Shader stage
-const char *lgc::getShaderStageAbbreviation(ShaderStage shaderStage) {
- if (shaderStage == ShaderStageCopyShader)
+const char *lgc::getShaderStageAbbreviation(ShaderStageEnum shaderStage) {
+ if (shaderStage == ShaderStage::CopyShader)
return "COPY";
- if (shaderStage > ShaderStageCompute)
+ if (shaderStage > ShaderStage::Compute)
return "Bad";
static const char *ShaderStageAbbrs[] = {"TASK", "VS", "TCS", "TES", "GS", "MESH", "FS", "CS"};
diff --git a/lgc/state/TargetInfo.cpp b/lgc/state/TargetInfo.cpp
index e9f1b2a9d6..d73857ba2f 100644
--- a/lgc/state/TargetInfo.cpp
+++ b/lgc/state/TargetInfo.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/test/BuiltIns/cs-deviceindex.lgc b/lgc/test/BuiltIns/cs-deviceindex.lgc
index 5864885362..6beeaef4aa 100644
--- a/lgc/test/BuiltIns/cs-deviceindex.lgc
+++ b/lgc/test/BuiltIns/cs-deviceindex.lgc
@@ -3,7 +3,7 @@
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
- %0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
%1 = call i32 (...) @lgc.create.read.builtin.input.i32(i32 4438, i32 0, i32 poison, i32 poison)
%2 = bitcast i8 addrspace(7)* %0 to i32 addrspace(7)*
store i32 %1, i32 addrspace(7)* %2, align 4
@@ -11,14 +11,14 @@ define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc
}
declare i32 @lgc.create.read.builtin.input.i32(...) local_unnamed_addr #0
-declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
!lgc.device.index = !{!3}
-; ShaderStageCompute
+; ShaderStage::Compute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 0, i32 0, i32 2, i32 1, i32 1}
diff --git a/lgc/test/BuiltIns/cs-globalinvocationid.lgc b/lgc/test/BuiltIns/cs-globalinvocationid.lgc
index 74e54d9ecc..c7224aec6c 100644
--- a/lgc/test/BuiltIns/cs-globalinvocationid.lgc
+++ b/lgc/test/BuiltIns/cs-globalinvocationid.lgc
@@ -4,7 +4,7 @@
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
- %0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
%1 = call <3 x i32> (...) @lgc.create.read.builtin.input.v3i32(i32 28, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to <3 x i32> addrspace(7)*
store <3 x i32> %1, <3 x i32> addrspace(7)* %2, align 4
@@ -12,14 +12,14 @@ define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc
}
declare <3 x i32> @lgc.create.read.builtin.input.v3i32(...) local_unnamed_addr #0
-declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
!llpc.compute.mode = !{!3}
-; ShaderStageCompute
+; ShaderStage::Compute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 0, i32 0, i32 2, i32 1, i32 1}
diff --git a/lgc/test/BuiltIns/cs-localinvocationid.lgc b/lgc/test/BuiltIns/cs-localinvocationid.lgc
index 5aa0bd298f..46c43aea2b 100644
--- a/lgc/test/BuiltIns/cs-localinvocationid.lgc
+++ b/lgc/test/BuiltIns/cs-localinvocationid.lgc
@@ -4,7 +4,7 @@
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
- %0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
%1 = call <3 x i32> (...) @lgc.create.read.builtin.input.v3i32(i32 27, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to <3 x i32> addrspace(7)*
store <3 x i32> %1, <3 x i32> addrspace(7)* %2, align 4
@@ -12,14 +12,14 @@ define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc
}
declare <3 x i32> @lgc.create.read.builtin.input.v3i32(...) local_unnamed_addr #0
-declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
!llpc.compute.mode = !{!3}
-; ShaderStageCompute
+; ShaderStage::Compute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 0, i32 0, i32 2, i32 1, i32 1}
diff --git a/lgc/test/BuiltIns/cs-localinvocationindex.lgc b/lgc/test/BuiltIns/cs-localinvocationindex.lgc
index 8ac5af96a9..8fa75c3ca0 100644
--- a/lgc/test/BuiltIns/cs-localinvocationindex.lgc
+++ b/lgc/test/BuiltIns/cs-localinvocationindex.lgc
@@ -4,7 +4,7 @@
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
- %0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
%1 = call i32 (...) @lgc.create.read.builtin.input.i32(i32 29, i32 0, i32 poison, i32 poison)
%2 = bitcast i8 addrspace(7)* %0 to i32 addrspace(7)*
store i32 %1, i32 addrspace(7)* %2, align 4
@@ -12,14 +12,14 @@ define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc
}
declare i32 @lgc.create.read.builtin.input.i32(...) local_unnamed_addr #0
-declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
!llpc.compute.mode = !{!3}
-; ShaderStageCompute
+; ShaderStage::Compute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 0, i32 0, i32 2, i32 1, i32 1}
diff --git a/lgc/test/BuiltIns/cs-numsubgroups.lgc b/lgc/test/BuiltIns/cs-numsubgroups.lgc
index 0b41f89cc3..2395bfd755 100644
--- a/lgc/test/BuiltIns/cs-numsubgroups.lgc
+++ b/lgc/test/BuiltIns/cs-numsubgroups.lgc
@@ -4,7 +4,7 @@
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
- %0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
%1 = call i32 (...) @lgc.create.read.builtin.input.i32(i32 38, i32 0, i32 poison, i32 poison)
%2 = bitcast i8 addrspace(7)* %0 to i32 addrspace(7)*
store i32 %1, i32 addrspace(7)* %2, align 4
@@ -12,14 +12,14 @@ define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc
}
declare i32 @lgc.create.read.builtin.input.i32(...) local_unnamed_addr #0
-declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
!llpc.compute.mode = !{!3}
-; ShaderStageCompute
+; ShaderStage::Compute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 0, i32 0, i32 2, i32 1, i32 1}
diff --git a/lgc/test/BuiltIns/cs-numworkgroups.lgc b/lgc/test/BuiltIns/cs-numworkgroups.lgc
index 6327b0bd6a..553a5a8a6c 100644
--- a/lgc/test/BuiltIns/cs-numworkgroups.lgc
+++ b/lgc/test/BuiltIns/cs-numworkgroups.lgc
@@ -3,7 +3,7 @@
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
- %0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
%1 = call <3 x i32> (...) @lgc.create.read.builtin.input.v3i32(i32 24, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to <3 x i32> addrspace(7)*
store <3 x i32> %1, <3 x i32> addrspace(7)* %2, align 4
@@ -11,13 +11,13 @@ define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc
}
declare <3 x i32> @lgc.create.read.builtin.input.v3i32(...) local_unnamed_addr #0
-declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
-; ShaderStageCompute
+; ShaderStage::Compute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 0, i32 0, i32 2, i32 1, i32 1}
diff --git a/lgc/test/BuiltIns/cs-subgroupid.lgc b/lgc/test/BuiltIns/cs-subgroupid.lgc
index f41b1f3718..316fa2fc9a 100644
--- a/lgc/test/BuiltIns/cs-subgroupid.lgc
+++ b/lgc/test/BuiltIns/cs-subgroupid.lgc
@@ -4,7 +4,7 @@
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
- %0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
%1 = call i32 (...) @lgc.create.read.builtin.input.i32(i32 40, i32 0, i32 poison, i32 poison)
%2 = bitcast i8 addrspace(7)* %0 to i32 addrspace(7)*
store i32 %1, i32 addrspace(7)* %2, align 4
@@ -12,14 +12,14 @@ define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc
}
declare i32 @lgc.create.read.builtin.input.i32(...) local_unnamed_addr #0
-declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
!llpc.compute.mode = !{!3}
-; ShaderStageCompute
+; ShaderStage::Compute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 0, i32 0, i32 2, i32 1, i32 1}
diff --git a/lgc/test/BuiltIns/cs-subgrouplocalinvocationid.lgc b/lgc/test/BuiltIns/cs-subgrouplocalinvocationid.lgc
index 81686f4469..756a62ce63 100644
--- a/lgc/test/BuiltIns/cs-subgrouplocalinvocationid.lgc
+++ b/lgc/test/BuiltIns/cs-subgrouplocalinvocationid.lgc
@@ -3,7 +3,7 @@
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
- %0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
%1 = call i32 (...) @lgc.create.read.builtin.input.i32(i32 41, i32 0, i32 poison, i32 poison)
%2 = bitcast i8 addrspace(7)* %0 to i32 addrspace(7)*
store i32 %1, i32 addrspace(7)* %2, align 4
@@ -11,13 +11,13 @@ define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc
}
declare i32 @lgc.create.read.builtin.input.i32(...) local_unnamed_addr #0
-declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
-; ShaderStageCompute
+; ShaderStage::Compute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 0, i32 0, i32 2, i32 1, i32 1}
diff --git a/lgc/test/BuiltIns/cs-subgroupsize.lgc b/lgc/test/BuiltIns/cs-subgroupsize.lgc
index 77e0344996..e01e5964bd 100644
--- a/lgc/test/BuiltIns/cs-subgroupsize.lgc
+++ b/lgc/test/BuiltIns/cs-subgroupsize.lgc
@@ -3,7 +3,7 @@
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
- %0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
%1 = call i32 (...) @lgc.create.read.builtin.input.i32(i32 36, i32 0, i32 poison, i32 poison)
%2 = bitcast i8 addrspace(7)* %0 to i32 addrspace(7)*
store i32 %1, i32 addrspace(7)* %2, align 4
@@ -11,13 +11,13 @@ define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc
}
declare i32 @lgc.create.read.builtin.input.i32(...) local_unnamed_addr #0
-declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
-; ShaderStageCompute
+; ShaderStage::Compute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 0, i32 0, i32 2, i32 1, i32 1}
diff --git a/lgc/test/BuiltIns/cs-workgroupid.lgc b/lgc/test/BuiltIns/cs-workgroupid.lgc
index abcbc4ba71..fc1154a056 100644
--- a/lgc/test/BuiltIns/cs-workgroupid.lgc
+++ b/lgc/test/BuiltIns/cs-workgroupid.lgc
@@ -3,7 +3,7 @@
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
- %0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
%1 = call <3 x i32> (...) @lgc.create.read.builtin.input.v3i32(i32 26, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to <3 x i32> addrspace(7)*
store <3 x i32> %1, <3 x i32> addrspace(7)* %2, align 4
@@ -11,13 +11,13 @@ define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc
}
declare <3 x i32> @lgc.create.read.builtin.input.v3i32(...) local_unnamed_addr #0
-declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
-; ShaderStageCompute
+; ShaderStage::Compute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 0, i32 0, i32 2, i32 1, i32 1}
diff --git a/lgc/test/BuiltIns/cs-workgroupsize.lgc b/lgc/test/BuiltIns/cs-workgroupsize.lgc
index d79a928435..247bd2223f 100644
--- a/lgc/test/BuiltIns/cs-workgroupsize.lgc
+++ b/lgc/test/BuiltIns/cs-workgroupsize.lgc
@@ -3,7 +3,7 @@
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
- %0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
%1 = call <3 x i32> (...) @lgc.create.read.builtin.input.v3i32(i32 25, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to <3 x i32> addrspace(7)*
store <3 x i32> %1, <3 x i32> addrspace(7)* %2, align 4
@@ -11,14 +11,14 @@ define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc
}
declare <3 x i32> @lgc.create.read.builtin.input.v3i32(...) local_unnamed_addr #0
-declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
!llpc.compute.mode = !{!3}
-; ShaderStageCompute
+; ShaderStage::Compute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 0, i32 0, i32 2, i32 1, i32 1}
diff --git a/lgc/test/CMakeLists.txt b/lgc/test/CMakeLists.txt
index ddc9ea08e4..3669aa8019 100644
--- a/lgc/test/CMakeLists.txt
+++ b/lgc/test/CMakeLists.txt
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/lgc/test/CallLibFromCs-indirect.lgc b/lgc/test/CallLibFromCs-indirect.lgc
index 6c1e564ff7..4c5f4a82a8 100644
--- a/lgc/test/CallLibFromCs-indirect.lgc
+++ b/lgc/test/CallLibFromCs-indirect.lgc
@@ -13,18 +13,18 @@ target triple = "amdgcn--amdpal"
; Function Attrs: nounwind
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !7 {
.entry:
- %0 = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i32 0, i32 2, i32 0, i32 2)
- %1 = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i32 0, i32 0, i32 0, i32 2)
- %2 = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i32 0, i32 1, i32 0, i32 2)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 2, i32 0, i32 2)
+ %1 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
+ %2 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 1, i32 0, i32 2)
%3 = bitcast i8 addrspace(7)* %2 to <4 x i32> addrspace(7)*
%4 = load <4 x i32>, ptr addrspace(7) %2, align 16
- %5 = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i32 0, i32 1, i32 1, i32 2)
+ %5 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 1, i32 1, i32 2)
%6 = load <4 x i32>, ptr addrspace(7) %5, align 16
%7 = add <4 x i32> %4, %6
- %8 = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i32 0, i32 1, i32 2, i32 2)
+ %8 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 1, i32 2, i32 2)
%9 = load <4 x i32>, ptr addrspace(7) %8, align 16
%10 = add <4 x i32> %7, %9
- %11 = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i32 0, i32 1, i32 3, i32 2)
+ %11 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 1, i32 3, i32 2)
%12 = load <4 x i32>, ptr addrspace(7) %11, align 16
%13 = add <4 x i32> %10, %12
%14 = load <4 x i32>, ptr addrspace(7) %0, align 16
@@ -38,7 +38,7 @@ define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc
}
; Function Attrs: nounwind readonly
-declare ptr addrspace(7) @lgc.create.load.buffer.desc.p7(...) local_unnamed_addr #1
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #1
attributes #0 = { nounwind }
attributes #1 = { nounwind readonly }
diff --git a/lgc/test/CallLibFromCs.lgc b/lgc/test/CallLibFromCs.lgc
index e19d181170..3f68d40e8f 100644
--- a/lgc/test/CallLibFromCs.lgc
+++ b/lgc/test/CallLibFromCs.lgc
@@ -16,20 +16,20 @@ declare spir_func i32 @compute_library_func() #0
; Function Attrs: nounwind
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !7 {
.entry:
- %0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 2, i32 0, i32 2)
- %1 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
- %2 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 1, i32 0, i32 2)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 2, i32 0, i32 2)
+ %1 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
+ %2 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 1, i32 0, i32 2)
%3 = bitcast i8 addrspace(7)* %2 to <4 x i32> addrspace(7)*
%4 = load <4 x i32>, <4 x i32> addrspace(7)* %3, align 16
- %5 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 1, i32 1, i32 2)
+ %5 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 1, i32 1, i32 2)
%6 = bitcast i8 addrspace(7)* %5 to <4 x i32> addrspace(7)*
%7 = load <4 x i32>, <4 x i32> addrspace(7)* %6, align 16
%8 = add <4 x i32> %4, %7
- %9 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 1, i32 2, i32 2)
+ %9 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 1, i32 2, i32 2)
%10 = bitcast i8 addrspace(7)* %9 to <4 x i32> addrspace(7)*
%11 = load <4 x i32>, <4 x i32> addrspace(7)* %10, align 16
%12 = add <4 x i32> %8, %11
- %13 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 1, i32 3, i32 2)
+ %13 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 1, i32 3, i32 2)
%14 = bitcast i8 addrspace(7)* %13 to <4 x i32> addrspace(7)*
%15 = load <4 x i32>, <4 x i32> addrspace(7)* %14, align 16
%16 = add <4 x i32> %12, %15
@@ -44,7 +44,7 @@ define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc
}
; Function Attrs: nounwind readonly
-declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #1
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #1
attributes #0 = { nounwind }
attributes #1 = { nounwind readonly }
diff --git a/lgc/test/CallLibFromCsPayload.lgc b/lgc/test/CallLibFromCsPayload.lgc
index cdca6ac9a0..1ef4c46bf4 100644
--- a/lgc/test/CallLibFromCsPayload.lgc
+++ b/lgc/test/CallLibFromCsPayload.lgc
@@ -16,20 +16,20 @@ define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc
; CHECK-NEXT: v_mov_b32_e32 v40, v0
; CHECK-NEXT: buffer_store_dwordx4 v[{{[0-9]+:[0-9]+}}], off, s[{{[0-9]+:[0-9]+}}], 0
.entry:
- %0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 2, i32 0, i32 2)
- %1 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
- %2 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 1, i32 0, i32 2)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 2, i32 0, i32 2)
+ %1 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
+ %2 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 1, i32 0, i32 2)
%3 = bitcast i8 addrspace(7)* %2 to <4 x i32> addrspace(7)*
%4 = load <4 x i32>, <4 x i32> addrspace(7)* %3, align 16
- %5 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 1, i32 1, i32 2)
+ %5 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 1, i32 1, i32 2)
%6 = bitcast i8 addrspace(7)* %5 to <4 x i32> addrspace(7)*
%7 = load <4 x i32>, <4 x i32> addrspace(7)* %6, align 16
%8 = add <4 x i32> %4, %7
- %9 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 1, i32 2, i32 2)
+ %9 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 1, i32 2, i32 2)
%10 = bitcast i8 addrspace(7)* %9 to <4 x i32> addrspace(7)*
%11 = load <4 x i32>, <4 x i32> addrspace(7)* %10, align 16
%12 = add <4 x i32> %8, %11
- %13 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 1, i32 3, i32 2)
+ %13 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 1, i32 3, i32 2)
%14 = bitcast i8 addrspace(7)* %13 to <4 x i32> addrspace(7)*
%15 = load <4 x i32>, <4 x i32> addrspace(7)* %14, align 16
%16 = add <4 x i32> %12, %15
@@ -46,7 +46,7 @@ define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc
}
; Function Attrs: nounwind readonly
-declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #1
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #1
attributes #0 = { nounwind }
attributes #1 = { nounwind readonly }
diff --git a/lgc/test/CsBPermuteWave64.lgc b/lgc/test/CsBPermuteWave64.lgc
index cdc90ba356..ed2e99d54e 100644
--- a/lgc/test/CsBPermuteWave64.lgc
+++ b/lgc/test/CsBPermuteWave64.lgc
@@ -9,7 +9,7 @@ define spir_func float @fn(float %value, i32 %index) !lgc.shaderstage !0 {
declare float @lgc.create.subgroup.shuffle.f32(...)
-; ShaderStageCompute
+; ShaderStage::Compute
!0 = !{i32 7}
; Setting Threadgroup Dimensions to 64 x 1 x 1
diff --git a/lgc/test/CsComputeLibrary.lgc b/lgc/test/CsComputeLibrary.lgc
index 7d81b2f06c..1368e78100 100644
--- a/lgc/test/CsComputeLibrary.lgc
+++ b/lgc/test/CsComputeLibrary.lgc
@@ -17,17 +17,17 @@ target triple = "amdgcn--amdpal"
; Function Attrs: nounwind
define spir_func void @func() local_unnamed_addr #0 !lgc.shaderstage !7 {
.entry:
- %0 = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i32 0, i32 2, i32 0, i32 2)
- %1 = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i32 0, i32 0, i32 0, i32 2)
- %2 = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i32 0, i32 1, i32 0, i32 2)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 2, i32 0, i32 2)
+ %1 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
+ %2 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 1, i32 0, i32 2)
%3 = load <4 x i32>, ptr addrspace(7) %2, align 16
- %4 = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i32 0, i32 1, i32 1, i32 2)
+ %4 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 1, i32 1, i32 2)
%5 = load <4 x i32>, ptr addrspace(7) %4, align 16
%6 = add <4 x i32> %3, %5
- %7 = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i32 0, i32 1, i32 2, i32 2)
+ %7 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 1, i32 2, i32 2)
%8 = load <4 x i32>, ptr addrspace(7) %7, align 16
%9 = add <4 x i32> %6, %8
- %10 = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i32 0, i32 1, i32 3, i32 2)
+ %10 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 1, i32 3, i32 2)
%11 = load <4 x i32>, ptr addrspace(7) %10, align 16
%12 = add <4 x i32> %9, %11
%13 = load <4 x i32>, ptr addrspace(7) %0, align 16
@@ -37,7 +37,7 @@ define spir_func void @func() local_unnamed_addr #0 !lgc.shaderstage !7 {
}
; Function Attrs: nounwind readonly
-declare ptr addrspace(7) @lgc.create.load.buffer.desc.p7(...) local_unnamed_addr #1
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #1
attributes #0 = { nounwind }
attributes #1 = { nounwind readonly }
diff --git a/lgc/test/CsComputeLibraryPayload.lgc b/lgc/test/CsComputeLibraryPayload.lgc
index 09c8a0e164..f9441f5b17 100644
--- a/lgc/test/CsComputeLibraryPayload.lgc
+++ b/lgc/test/CsComputeLibraryPayload.lgc
@@ -17,9 +17,6 @@ define spir_func <10 x i32> @func(<10 x i32> %arg) local_unnamed_addr #0 !lgc.sh
declare <3 x i32> @lgc.shader.input.LocalInvocationId(i32) #1
-; Function Attrs: nounwind readonly
-declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #1
-
attributes #0 = { nounwind }
attributes #1 = { nounwind readonly }
diff --git a/lgc/test/CsReconfigWorkgroup.lgc b/lgc/test/CsReconfigWorkgroup.lgc
index f4f44976ce..0ef36e6515 100644
--- a/lgc/test/CsReconfigWorkgroup.lgc
+++ b/lgc/test/CsReconfigWorkgroup.lgc
@@ -10,7 +10,7 @@
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
- %0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
%1 = call <3 x i32> (...) @lgc.create.read.builtin.input.v3i32(i32 27, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to <3 x i32> addrspace(7)*
store <3 x i32> %1, <3 x i32> addrspace(7)* %2, align 4
@@ -18,14 +18,14 @@ define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc
}
declare <3 x i32> @lgc.create.read.builtin.input.v3i32(...) local_unnamed_addr #0
-declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
!llpc.compute.mode = !{!3}
-; ShaderStageCompute
+; ShaderStage::Compute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 0, i32 0, i32 2, i32 1, i32 1}
@@ -46,7 +46,7 @@ attributes #0 = { nounwind }
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
- %0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
%1 = call <3 x i32> (...) @lgc.create.read.builtin.input.v3i32(i32 27, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to <3 x i32> addrspace(7)*
store <3 x i32> %1, <3 x i32> addrspace(7)* %2, align 4
@@ -60,7 +60,7 @@ define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc
}
declare <3 x i32> @lgc.create.read.builtin.input.v3i32(...) local_unnamed_addr #0
-declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #0
declare <8 x i32> addrspace(4)* @lgc.create.get.desc.ptr.v8i32(...) local_unnamed_addr #0
declare <2 x float> @lgc.create.image.load.v2f32(...) local_unnamed_addr #0
@@ -70,7 +70,7 @@ attributes #0 = { nounwind }
!llpc.compute.mode = !{!4}
!lgc.options = !{!5}
-; ShaderStageCompute
+; ShaderStage::Compute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 0, i32 0, i32 2, i32 1, i32 1}
@@ -94,7 +94,7 @@ attributes #0 = { nounwind }
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
- %0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
%1 = call <3 x i32> (...) @lgc.create.read.builtin.input.v3i32(i32 27, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to <3 x i32> addrspace(7)*
store <3 x i32> %1, <3 x i32> addrspace(7)* %2, align 4
@@ -108,7 +108,7 @@ define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc
}
declare <3 x i32> @lgc.create.read.builtin.input.v3i32(...) local_unnamed_addr #0
-declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #0
declare <8 x i32> addrspace(4)* @lgc.create.get.desc.ptr.v8i32(...) local_unnamed_addr #0
declare <2 x float> @lgc.create.image.load.v2f32(...) local_unnamed_addr #0
@@ -118,7 +118,7 @@ attributes #0 = { nounwind }
!llpc.compute.mode = !{!4}
!lgc.options = !{!5}
-; ShaderStageCompute
+; ShaderStage::Compute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 0, i32 0, i32 2, i32 1, i32 1}
diff --git a/lgc/test/FetchShaderSingleInput.lgc b/lgc/test/FetchShaderSingleInput.lgc
index 27c279cafe..b731ce15fc 100644
--- a/lgc/test/FetchShaderSingleInput.lgc
+++ b/lgc/test/FetchShaderSingleInput.lgc
@@ -64,7 +64,7 @@ target triple = "amdgcn--amdpal"
define dllexport spir_func void @lgc.shader.VS.main() local_unnamed_addr #0 !lgc.shaderstage !5 {
.entry:
- %0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 0)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
%1 = call {}* @llvm.invariant.start.p7i8(i64 -1, i8 addrspace(7)* %0)
%2 = call <4 x float> (...) @lgc.create.read.generic.input.v4f32(i32 0, i32 0, i32 0, i32 0, i32 0, i32 poison)
%3 = bitcast i8 addrspace(7)* %0 to <4 x float> addrspace(7)*
@@ -98,7 +98,7 @@ declare <4 x float> @lgc.create.read.generic.input.v4f32(...) local_unnamed_addr
declare void @lgc.create.write.builtin.output(...) local_unnamed_addr #0
; Function Attrs: nounwind
-declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #0
; Function Attrs: argmemonly nounwind willreturn
declare {}* @llvm.invariant.start.p7i8(i64 immarg, i8 addrspace(7)* nocapture) #2
diff --git a/lgc/test/InOutPackingNonZeroBase.lgc b/lgc/test/InOutPackingNonZeroBase.lgc
index 3d9776afdf..eb2f673b07 100644
--- a/lgc/test/InOutPackingNonZeroBase.lgc
+++ b/lgc/test/InOutPackingNonZeroBase.lgc
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --tool lgc
-; RUN: lgc -mcpu=gfx900 --print-after=lgc-patch-resource-collect --verify-ir %s -o=/dev/null 2>&1 | FileCheck --check-prefixes=IR %s
+; RUN: lgc -mcpu=gfx1010 --print-after=lgc-patch-resource-collect --verify-ir %s -o=/dev/null 2>&1 | FileCheck --check-prefixes=IR %s
; Throw in 'cat' as a hack to prevent update_test_checks from touching the "MAPPING" lines
-; RUN: lgc -mcpu=gfx900 -v --verify-ir %s -o=/dev/null 2>&1 > %t.out
+; RUN: lgc -mcpu=gfx1010 -v --verify-ir %s -o=/dev/null 2>&1 > %t.out
; RUN: cat %t.out | FileCheck --check-prefixes=MAPPING %s
; Check that input-output packing works with non-zero-based vector components.
@@ -11,26 +11,26 @@ source_filename = "lgcPipeline"
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7"
target triple = "amdgcn--amdpal"
-; MAPPING-LABEL: {{^//}} LLPC location input/output mapping results (FS shader)
+; MAPPING-LABEL: {{^//}} LLPC location input/output mapping results (FS)
;
-; MAPPING: (FS) Input: loc = 0, comp = 0 => Mapped = 0, 0
-; MAPPING-NEXT: (FS) Input: loc = 1, comp = 0 => Mapped = 0, 1
-; MAPPING-NEXT: (FS) Input: loc = 2, comp = 0 => Mapped = 0, 2
-; MAPPING-NEXT: (FS) Input: loc = 3, comp = 0 => Mapped = 0, 3
-; MAPPING-NEXT: (FS) Input: loc = 4, comp = 0 => Mapped = 1, 0
-; MAPPING-NEXT: (FS) Input: loc = 5, comp = 0 => Mapped = 1, 1
-; MAPPING-NEXT: (FS) Input: loc = 6, comp = 0 => Mapped = 1, 2
-; MAPPING-NEXT: (FS) Input: loc = 7, comp = 0 => Mapped = 1, 3
-; MAPPING-NEXT: (FS) Input: loc = 8, comp = 0 => Mapped = 2, 0
-; MAPPING-NEXT: (FS) Input: loc = 9, comp = 0 => Mapped = 2, 1
-
-; MAPPING-LABEL: {{^//}} LLPC location input/output mapping results (VS shader)
+; MAPPING: (FS) Input: [location, component] = [0, 0] => Mapped = [0, 0]
+; MAPPING-NEXT: (FS) Input: [location, component] = [1, 0] => Mapped = [0, 1]
+; MAPPING-NEXT: (FS) Input: [location, component] = [2, 0] => Mapped = [0, 2]
+; MAPPING-NEXT: (FS) Input: [location, component] = [3, 0] => Mapped = [0, 3]
+; MAPPING-NEXT: (FS) Input: [location, component] = [4, 0] => Mapped = [1, 0]
+; MAPPING-NEXT: (FS) Input: [location, component] = [5, 0] => Mapped = [1, 1]
+; MAPPING-NEXT: (FS) Input: [location, component] = [6, 0] => Mapped = [1, 2]
+; MAPPING-NEXT: (FS) Input: [location, component] = [7, 0] => Mapped = [1, 3]
+; MAPPING-NEXT: (FS) Input: [location, component] = [8, 0] => Mapped = [2, 0]
+; MAPPING-NEXT: (FS) Input: [location, component] = [9, 0] => Mapped = [2, 1]
+
+; MAPPING-LABEL: {{^//}} LLPC location input/output mapping results (VS)
;
-; MAPPING: (VS) Input: loc = 1, comp = 0 => Mapped = 1, 0
+; MAPPING: (VS) Input: [location, component] = [1, 0] => Mapped = [1, 0]
;
-; MAPPING: (VS) Output: loc = 7, comp = 0 => Mapped = 1, 3
-; MAPPING-NEXT: (VS) Output: loc = 8, comp = 0 => Mapped = 2, 0
-; MAPPING-NEXT: (VS) Output: loc = 9, comp = 0 => Mapped = 2, 1
+; MAPPING: (VS) Output: [location, component] = [7, 0] => Mapped = [1, 3]
+; MAPPING-NEXT: (VS) Output: [location, component] = [8, 0] => Mapped = [2, 0]
+; MAPPING-NEXT: (VS) Output: [location, component] = [9, 0] => Mapped = [2, 1]
; ModuleID = 'lgcPipeline'
source_filename = "lgcPipeline"
@@ -49,12 +49,12 @@ define dllexport spir_func void @lgc.shader.VS.main() local_unnamed_addr #0 !spi
; IR-NEXT: [[TMP5:%.*]] = bitcast float [[TMP2]] to i32
; IR-NEXT: [[TMP6:%.*]] = bitcast float [[TMP3]] to i32
; IR-NEXT: [[TMP7:%.*]] = bitcast i32 [[TMP4]] to float
-; IR-NEXT: call void @lgc.output.export.generic.i32.i32.f32(i32 7, i32 0, float [[TMP7]]) #[[ATTR0:[0-9]+]]
+; IR-NEXT: call void @lgc.output.export.generic.i32.i32.f32(i32 7, i32 0, float [[TMP7]]) #[[ATTR3:[0-9]+]]
; IR-NEXT: [[TMP8:%.*]] = bitcast i32 [[TMP5]] to float
; IR-NEXT: [[TMP9:%.*]] = insertelement <2 x float> poison, float [[TMP8]], i64 0
; IR-NEXT: [[TMP10:%.*]] = bitcast i32 [[TMP6]] to float
; IR-NEXT: [[TMP11:%.*]] = insertelement <2 x float> [[TMP9]], float [[TMP10]], i64 1
-; IR-NEXT: call void @lgc.output.export.generic.i32.i32.v2f32(i32 8, i32 0, <2 x float> [[TMP11]]) #[[ATTR0]]
+; IR-NEXT: call void @lgc.output.export.generic.i32.i32.v2f32(i32 8, i32 0, <2 x float> [[TMP11]]) #[[ATTR3]]
; IR-NEXT: ret void
;
.entry:
@@ -81,25 +81,25 @@ declare void @lgc.create.write.generic.output(...) local_unnamed_addr #0
define dllexport spir_func void @lgc.shader.FS.main() local_unnamed_addr #0 !spirv.ExecutionModel !11 !lgc.shaderstage !12 {
; IR-LABEL: @lgc.shader.FS.main(
; IR-NEXT: .entry:
-; IR-NEXT: [[INTERPPERSPCENTER:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR2:[0-9]+]]
+; IR-NEXT: [[INTERPPERSPCENTER:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR4:[0-9]+]]
; IR-NEXT: [[TMP0:%.*]] = call float (...) @lgc.input.import.interpolated.f32(i1 false, i32 9, i32 0, i32 0, i32 poison, i32 0, <2 x float> [[INTERPPERSPCENTER]])
-; IR-NEXT: [[INTERPPERSPCENTER1:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR2]]
+; IR-NEXT: [[INTERPPERSPCENTER1:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR4]]
; IR-NEXT: [[TMP1:%.*]] = call float (...) @lgc.input.import.interpolated.f32(i1 false, i32 8, i32 0, i32 0, i32 poison, i32 0, <2 x float> [[INTERPPERSPCENTER1]])
-; IR-NEXT: [[INTERPPERSPCENTER2:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR2]]
+; IR-NEXT: [[INTERPPERSPCENTER2:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR4]]
; IR-NEXT: [[TMP2:%.*]] = call float (...) @lgc.input.import.interpolated.f32(i1 false, i32 7, i32 0, i32 0, i32 poison, i32 0, <2 x float> [[INTERPPERSPCENTER2]])
-; IR-NEXT: [[INTERPPERSPCENTER3:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR2]]
+; IR-NEXT: [[INTERPPERSPCENTER3:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR4]]
; IR-NEXT: [[TMP3:%.*]] = call float (...) @lgc.input.import.interpolated.f32(i1 false, i32 6, i32 0, i32 0, i32 poison, i32 0, <2 x float> [[INTERPPERSPCENTER3]])
-; IR-NEXT: [[INTERPPERSPCENTER4:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR2]]
+; IR-NEXT: [[INTERPPERSPCENTER4:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR4]]
; IR-NEXT: [[TMP4:%.*]] = call float (...) @lgc.input.import.interpolated.f32(i1 false, i32 5, i32 0, i32 0, i32 poison, i32 0, <2 x float> [[INTERPPERSPCENTER4]])
-; IR-NEXT: [[INTERPPERSPCENTER5:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR2]]
+; IR-NEXT: [[INTERPPERSPCENTER5:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR4]]
; IR-NEXT: [[TMP5:%.*]] = call float (...) @lgc.input.import.interpolated.f32(i1 false, i32 4, i32 0, i32 0, i32 poison, i32 0, <2 x float> [[INTERPPERSPCENTER5]])
-; IR-NEXT: [[INTERPPERSPCENTER6:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR2]]
+; IR-NEXT: [[INTERPPERSPCENTER6:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR4]]
; IR-NEXT: [[TMP6:%.*]] = call float (...) @lgc.input.import.interpolated.f32(i1 false, i32 3, i32 0, i32 0, i32 poison, i32 0, <2 x float> [[INTERPPERSPCENTER6]])
-; IR-NEXT: [[INTERPPERSPCENTER7:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR2]]
+; IR-NEXT: [[INTERPPERSPCENTER7:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR4]]
; IR-NEXT: [[TMP7:%.*]] = call float (...) @lgc.input.import.interpolated.f32(i1 false, i32 2, i32 0, i32 0, i32 poison, i32 0, <2 x float> [[INTERPPERSPCENTER7]])
-; IR-NEXT: [[INTERPPERSPCENTER8:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR2]]
+; IR-NEXT: [[INTERPPERSPCENTER8:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR4]]
; IR-NEXT: [[TMP8:%.*]] = call float (...) @lgc.input.import.interpolated.f32(i1 false, i32 1, i32 0, i32 0, i32 poison, i32 0, <2 x float> [[INTERPPERSPCENTER8]])
-; IR-NEXT: [[INTERPPERSPCENTER9:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR2]]
+; IR-NEXT: [[INTERPPERSPCENTER9:%.*]] = call <2 x float> @lgc.input.import.builtin.InterpPerspCenter.v2f32.i32(i32 268435457) #[[ATTR4]]
; IR-NEXT: [[TMP9:%.*]] = call float (...) @lgc.input.import.interpolated.f32(i1 false, i32 0, i32 0, i32 0, i32 poison, i32 0, <2 x float> [[INTERPPERSPCENTER9]])
; IR-NEXT: [[TMP10:%.*]] = fadd reassoc nnan nsz arcp contract afn float [[TMP9]], [[TMP8]]
; IR-NEXT: [[TMP11:%.*]] = fadd reassoc nnan nsz arcp contract afn float [[TMP10]], [[TMP7]]
@@ -112,7 +112,7 @@ define dllexport spir_func void @lgc.shader.FS.main() local_unnamed_addr #0 !spi
; IR-NEXT: [[TMP18:%.*]] = fadd reassoc nnan nsz arcp contract afn float [[TMP17]], [[TMP0]]
; IR-NEXT: [[TMP19:%.*]] = insertelement <4 x float> poison, float [[TMP18]], i64 0
; IR-NEXT: [[TMP20:%.*]] = shufflevector <4 x float> [[TMP19]], <4 x float> poison, <4 x i32> zeroinitializer
-; IR-NEXT: call void @lgc.output.export.generic.i32.i32.v4f32(i32 0, i32 0, <4 x float> [[TMP20]]) #[[ATTR0]]
+; IR-NEXT: call void @lgc.output.export.generic.i32.i32.v4f32(i32 0, i32 0, <4 x float> [[TMP20]]) #[[ATTR3]]
; IR-NEXT: ret void
;
.entry:
diff --git a/lgc/test/IntToPtrWithAdd.lgc b/lgc/test/IntToPtrWithAdd.lgc
index b4b9219397..3193ceee02 100644
--- a/lgc/test/IntToPtrWithAdd.lgc
+++ b/lgc/test/IntToPtrWithAdd.lgc
@@ -1,16 +1,16 @@
; Change inttoptr ( add x, const ) -> gep ( inttoptr x, const )
-; RUN: lgc -mcpu=gfx900 -print-after=lgc-patch-peephole-opt -o /dev/null 2>&1 - <%s | FileCheck --check-prefixes=CHECK %s
+; RUN: lgc -mcpu=gfx1010 -print-after=lgc-patch-peephole-opt -o - 2>&1 - <%s | FileCheck --check-prefixes=CHECK %s
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-ni:7"
target triple = "amdgcn--amdpal"
; Function Attrs: nounwind
-define dllexport spir_func void @lgc.shader.VS.main(i64 %0, <4 x i32> addrspace(1)* %1) local_unnamed_addr #0 !lgc.shaderstage !10 {
+define dllexport spir_func void @lgc.shader.CS.main(i64 %0, <4 x i32> addrspace(1)* %1) local_unnamed_addr #0 !lgc.shaderstage !10 {
; CHECK: IR Dump After Patch LLVM for peephole optimizations
; CHECK: [[INTTOPTR:%[0-9]+]] = inttoptr i64 %[[#]] to ptr addrspace(1)
; CHECK: [[LOAD:%[0-9]+]] = load i32, ptr addrspace(1) [[INTTOPTR]], align 4
-; CHECK: [[INSERTELEMENT:%[0-9]+]] = insertelement <4 x i32> undef, i32 [[LOAD]], i{{32|64}} 0
+; CHECK: [[INSERTELEMENT:%[0-9]+]] = insertelement <4 x i32> {{poison|undef}}, i32 [[LOAD]], i{{32|64}} 0
; CHECK: [[INTTOPTR1:%[0-9]+]] = inttoptr i64 %[[#]] to ptr addrspace(1)
; CHECK: [[GEP1:%[0-9]+]] = getelementptr i32, ptr addrspace(1) [[INTTOPTR1]], i64 1
@@ -62,8 +62,8 @@ attributes #1 = { nounwind readonly }
!lgc.unlinked = !{!10}
!lgc.options = !{!0}
-!lgc.options.VS = !{!1}
+!lgc.options.CS = !{!1}
!0 = !{i32 739459867, i32 836497279, i32 -1935591037, i32 -652075177, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 2}
!1 = !{i32 801932830, i32 600683540, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 64, i32 0, i32 15, i32 3}
-!10 = !{i32 1}
+!10 = !{i32 7}
diff --git a/lgc/test/PatchInvalidImageDescriptor.lgc b/lgc/test/PatchInvalidImageDescriptor.lgc
index be099ba691..32a48a7f9f 100644
--- a/lgc/test/PatchInvalidImageDescriptor.lgc
+++ b/lgc/test/PatchInvalidImageDescriptor.lgc
@@ -1,14 +1,8 @@
; Test that invalid image descriptor patching is applied where required.
-; RUN: lgc -mcpu=gfx900 -print-after=lgc-patch-workarounds -o - - <%s 2>&1 | FileCheck --check-prefixes=CHECK,GFX900 %s
; RUN: lgc -mcpu=gfx1010 -print-after=lgc-patch-workarounds -o - - <%s 2>&1 | FileCheck --check-prefixes=CHECK,GFX1010 %s
; CHECK-LABEL: IR Dump After Patch LLVM for workarounds
-
-; GFX900: extractelement <8 x i32> %.desc, i64 7
-; GFX900: call i32 @llvm.amdgcn.readfirstlane(i32 %{{[0-9]+}})
-; GFX900: insertelement <8 x i32> %{{[0-9]+}}, i32 %{{[0-9]+}}, i64 7
-; GFX900: %.load = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 1, i32 0, <8 x i32> %{{[0-9]+}}, i32 0, i32 0)
; GFX1010: extractelement <8 x i32> %{{[0-9]+}}, i64 3
; GFX1010-NEXT: icmp sge i32
; GFX1010-NEXT: and i32
@@ -16,24 +10,17 @@
; GFX1010-NEXT: [[PATCHED_DESC0:%[.a-zA-Z0-9]+]] = insertelement <8 x i32> %{{[0-9]+}}
; GFX1010: %.load = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 1, <8 x i32> [[PATCHED_DESC0]], i32 0, i32 0)
-; GFX900: call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> zeroinitializer, i32 15, i32 0, i32 0, <8 x i32> %{{[0-9]+}}, i32 0, i32 0)
; GFX1010: call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> zeroinitializer, i32 15, i32 0, i32 0, <8 x i32> %{{[0-9]+}}, i32 0, i32 0)
-; GFX900: %.sample = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 0.000000e+00, float 0.000000e+00, <8 x i32> %{{[0-9]+}}, <4 x i32> %.sampler, i1 false, i32 0, i32 0)
; GFX1010: %.sample = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 0.000000e+00, float 0.000000e+00, <8 x i32> %{{[0-9]+}}, <4 x i32> %.sampler, i1 false, i32 0, i32 0)
-; GFX900: %.gather = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, <8 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, i1 false, i32 0, i32 0)
; GFX1010: %.gather = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, <8 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, i1 false, i32 0, i32 0)
-; GFX900: %.atomic = call i32 @llvm.amdgcn.image.atomic.add.2d.i32.i32(i32 1, i32 0, i32 0, <8 x i32> %{{[0-9]+}}, i32 0, i32 0)
; GFX1010: %.atomic = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i32(i32 1, i32 0, <8 x i32> %{{[0-9]+}}, i32 0, i32 0)
-; GFX900: %.lod = call <2 x float> @llvm.amdgcn.image.getlod.2d.v2f32.f32(i32 3, float 0.000000e+00, float 0.000000e+00, <8 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, i1 false, i32 0, i32 0)
; GFX1010: %.lod = call <2 x float> @llvm.amdgcn.image.getlod.2d.v2f32.f32(i32 3, float 0.000000e+00, float 0.000000e+00, <8 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, i1 false, i32 0, i32 0)
; CHECK: [[WFDESC:%[0-9]+]] = call <8 x i32> @llvm.amdgcn.waterfall.readfirstlane
-; GFX900: [[WFDESC1:%[0-9]+]] = call <8 x i32> @llvm.amdgcn.waterfall.last.use.v8i32(i32 %{{[0-9]+}}, <8 x i32> [[WFDESC]])
-; GFX900: call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> zeroinitializer, i32 15, i32 0, i32 0, <8 x i32> [[WFDESC1]], i32 0, i32 0)
; GFX1010: extractelement <8 x i32> [[WFDESC]], i64 3
; GFX1010-NEXT: icmp sge i32
; GFX1010-NEXT: and i32
diff --git a/lgc/test/PhiWithArgument.lgc b/lgc/test/PhiWithArgument.lgc
index 9df43d1e5f..d81b058b83 100644
--- a/lgc/test/PhiWithArgument.lgc
+++ b/lgc/test/PhiWithArgument.lgc
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by tool/update_llpc_test_checks.py UTC_ARGS: --tool lgc
-; RUN: lgc -mcpu=gfx900 - <%s | FileCheck --check-prefixes=VS-ISA %s
+; RUN: lgc -mcpu=gfx1010 - <%s | FileCheck --check-prefixes=VS-ISA %s
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-ni:7"
target triple = "amdgcn--amdpal"
@@ -47,16 +47,37 @@ attributes #1 = { nounwind readonly }
!2 = !{!"PushConst", i32 9, i32 0, i32 0, i32 18, i32 0, i32 0, i32 0}
!10 = !{i32 1}
-; VS-ISA-LABEL: amdgpu_vs_main_fetchless:
-; VS-ISA: v_mov_b32_e32 v1, s1
-; VS-ISA-NEXT: v_cmp_eq_f32_e32 vcc, 1.0, v4
+; VS-ISA-LABEL: amdgpu_gs_main_fetchless:
+; VS-ISA: s_mov_b32 exec_lo, -1
+; VS-ISA-NEXT: s_bfe_u32 s3, s3, 0x40018
+; VS-ISA-NEXT: s_bfe_u32 s1, s2, 0x90016
+; VS-ISA-NEXT: s_bfe_u32 s0, s2, 0x9000c
+; VS-ISA-NEXT: s_cmp_lg_u32 s3, 0
+; VS-ISA-NEXT: s_barrier
+; VS-ISA-NEXT: s_cbranch_scc1 .LBB0_2
+; VS-ISA-NEXT: s_lshl_b32 s2, s1, 12
+; VS-ISA-NEXT: s_or_b32 m0, s2, s0
+; VS-ISA-NEXT: s_sendmsg sendmsg(MSG_GS_ALLOC_REQ)
+; VS-ISA-NEXT: .LBB0_2:
+; VS-ISA-NEXT: v_mbcnt_lo_u32_b32 v1, -1, 0
+; VS-ISA-NEXT: v_lshl_or_b32 v1, s3, 5, v1
+; VS-ISA-NEXT: v_cmp_gt_u32_e32 vcc_lo, s1, v1
+; VS-ISA-NEXT: s_and_saveexec_b32 s1, vcc_lo
+; VS-ISA-NEXT: s_cbranch_execz .LBB0_4
+; VS-ISA-NEXT: exp prim v0, off, off, off done
+; VS-ISA-NEXT: .LBB0_4:
+; VS-ISA-NEXT: s_waitcnt expcnt(0)
+; VS-ISA-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; VS-ISA-NEXT: v_cmp_gt_u32_e32 vcc_lo, s0, v1
+; VS-ISA-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; VS-ISA-NEXT: s_cbranch_execz .LBB0_6
; VS-ISA-NEXT: v_mov_b32_e32 v0, 1.0
-; VS-ISA-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
-; VS-ISA-NEXT: v_mov_b32_e32 v4, 0
-; VS-ISA-NEXT: exp pos0 v4, v4, v4, v0 done
-; VS-ISA-NEXT: v_mov_b32_e32 v2, s2
-; VS-ISA-NEXT: v_mov_b32_e32 v3, s3
-; VS-ISA-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; VS-ISA-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
-; VS-ISA-NEXT: exp param1 v1, v2, v3, off
+; VS-ISA-NEXT: v_mov_b32_e32 v1, 0
+; VS-ISA-NEXT: v_cmp_eq_f32_e32 vcc_lo, 1.0, v9
+; VS-ISA-NEXT: exp pos0 v1, v1, v1, v0 done
+; VS-ISA-NEXT: v_cndmask_b32_e64 v2, v9, s9, vcc_lo
+; VS-ISA-NEXT: v_cndmask_b32_e64 v3, v10, s10, vcc_lo
+; VS-ISA-NEXT: v_cndmask_b32_e64 v4, v11, s11, vcc_lo
+; VS-ISA-NEXT: exp param1 v2, v3, v4, off
+; VS-ISA-NEXT: .LBB0_6:
; VS-ISA-NEXT: s_endpgm
diff --git a/lgc/test/ScalarizeInputWithDynamicIndexUser.lgc b/lgc/test/ScalarizeInputWithDynamicIndexUser.lgc
index 82d70384e9..35a1a10e71 100644
--- a/lgc/test/ScalarizeInputWithDynamicIndexUser.lgc
+++ b/lgc/test/ScalarizeInputWithDynamicIndexUser.lgc
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --tool lgc --function lgc.shader.FS.main
; Check that if the generic input has an extract instruction user whose index is dynamic, the input should be scalarized for each component.
-; RUN: lgc -mcpu=gfx900 -stop-after=lgc-patch-resource-collect %s -o=- | FileCheck %s
+; RUN: lgc -mcpu=gfx1010 -stop-after=lgc-patch-resource-collect %s -o=- | FileCheck %s
; ModuleID = 'lgcPipeline'
source_filename = "lgcPipeline"
diff --git a/lgc/test/ShaderStages.lgc b/lgc/test/ShaderStages.lgc
index 799c65286f..2e58f2bf43 100644
--- a/lgc/test/ShaderStages.lgc
+++ b/lgc/test/ShaderStages.lgc
@@ -1,9 +1,7 @@
; ----------------------------------------------------------------------
; Extract 1: CS
-; RUN: lgc -extract=1 -print-after=lgc-patch-setup-target-features -mcpu=gfx900 %s -o /dev/null 2>&1 | FileCheck --check-prefixes=CHECK1,CHECK-NO-NGG1 %s
; RUN: lgc -extract=1 -print-after=lgc-patch-setup-target-features -mcpu=gfx1010 %s -o /dev/null 2>&1 | FileCheck --check-prefixes=CHECK1,CHECK-NGG1 %s
-; CHECK-NO-NGG1: define dllexport amdgpu_cs void @_amdgpu_cs_main{{.*}} !lgc.shaderstage !3 {
; CHECK-NGG1: define dllexport amdgpu_cs void @_amdgpu_cs_main{{.*}} !lgc.shaderstage !3 {
; CHECK1: !3 = !{i32 7}
@@ -17,7 +15,7 @@ attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
!lgc.device.index = !{!3}
-; ShaderStageCompute
+; ShaderStage::Compute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 0, i32 0, i32 2, i32 1, i32 1}
@@ -29,12 +27,7 @@ attributes #0 = { nounwind }
; ----------------------------------------------------------------------
; Extract 2: VS/FS
-; RUN: lgc -extract=2 -print-after=lgc-patch-setup-target-features -mcpu=gfx900 %s -o /dev/null 2>&1 | FileCheck --check-prefixes=CHECK-NO-NGG2 %s
; RUN: lgc -extract=2 -print-after=lgc-patch-setup-target-features -mcpu=gfx1010 %s -o /dev/null 2>&1 | FileCheck --check-prefixes=CHECK-NGG2 %s
-; CHECK-NO-NGG2: define dllexport amdgpu_vs void @_amdgpu_vs_main{{.*}} !lgc.shaderstage !3 {
-; CHECK-NO-NGG2: define dllexport amdgpu_ps void @_amdgpu_ps_main{{.*}} !lgc.shaderstage !4 {
-; CHECK-NO-NGG2: !3 = !{i32 1}
-; CHECK-NO-NGG2: !4 = !{i32 6}
; CHECK-NGG2: define dllexport amdgpu_gs void @_amdgpu_gs_main{{.*}} !lgc.shaderstage !3 {
; CHECK-NGG2: define dllexport amdgpu_ps void @_amdgpu_ps_main{{.*}} !lgc.shaderstage !4 {
@@ -56,9 +49,9 @@ attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
!lgc.device.index = !{!3}
-; ShaderStageVertex
+; ShaderStage::Vertex
!0 = !{i32 1}
-; ShaderStageFragment
+; ShaderStage::Fragment
!4 = !{i32 6}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 0, i32 0, i32 2, i32 1, i32 1}
@@ -70,7 +63,6 @@ attributes #0 = { nounwind }
; ----------------------------------------------------------------------
; Extract 3: GS/VS
-; RUN: lgc -extract=3 -print-after=lgc-patch-setup-target-features -mcpu=gfx900 %s -o /dev/null 2>&1 | FileCheck --check-prefixes=CHECK-NGG3 %s
; RUN: lgc -extract=3 -print-after=lgc-patch-setup-target-features -mcpu=gfx1010 %s -o /dev/null 2>&1 | FileCheck --check-prefixes=CHECK-NGG3 %s
; _amdgpu_gs_main must be first, so it can be linked with a potential vertex fetch shader.
@@ -148,26 +140,17 @@ attributes #0 = { nounwind }
!3 = !{i32 -2101593, i32 1179029646, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 64, i32 0, i32 0, i32 3}
!4 = !{i32 16}
!5 = !{i32 0, i32 3}
-; ShaderStageVertex
+; ShaderStage::Vertex
!6 = !{i32 1}
-; ShaderStageGeometry
+; ShaderStage::Geometry
!7 = !{i32 4}
!8 = distinct !{!8}
; ----------------------------------------------------------------------
; Extract 4: TCS/TES
-; RUN: lgc -extract=4 -print-after=lgc-patch-setup-target-features -mcpu=gfx900 %s -o /dev/null 2>&1 | FileCheck --check-prefixes=CHECK-GFX94 %s
; RUN: lgc -extract=4 -print-after=lgc-patch-setup-target-features -mcpu=gfx1010 %s -o /dev/null 2>&1 | FileCheck --check-prefixes=CHECK-NGG4 %s
-; CHECK-GFX94: define dllexport amdgpu_hs void @_amdgpu_hs_main{{.*}} !lgc.shaderstage !5 {
-; CHECK-GFX94: define internal{{.*}} amdgpu_hs void @_amdgpu_hs_main.1{{.*}} !lgc.shaderstage !5 {
-; CHECK-GFX94: define dllexport amdgpu_vs void @_amdgpu_vs_main{{.*}} !lgc.shaderstage !6 {
-; CHECK-GFX94: define dllexport amdgpu_ps void @_amdgpu_ps_main{{.*}} !lgc.shaderstage !7 {
-; CHECK-GFX94: !5 = !{i32 2}
-; CHECK-GFX94: !6 = !{i32 3}
-; CHECK-GFX94: !7 = !{i32 6}
-
; CHECK-NGG4: define dllexport amdgpu_gs void @_amdgpu_gs_main{{.*}} !lgc.shaderstage !5 {
; CHECK-NGG4: define dllexport amdgpu_hs void @_amdgpu_hs_main{{.*}} !lgc.shaderstage !6 {
; CHECK-NGG4: define dllexport amdgpu_ps void @_amdgpu_ps_main{{.*}} !lgc.shaderstage !7 {
@@ -237,7 +220,6 @@ attributes #1 = { nounwind readonly }
; ----------------------------------------------------------------------
; Extract 5: TCS
-; RUN: lgc -extract=5 -print-after=lgc-patch-setup-target-features -mcpu=gfx900 %s -o /dev/null 2>&1 | FileCheck --check-prefixes=CHECK-NGG5 %s
; RUN: lgc -extract=5 -print-after=lgc-patch-setup-target-features -mcpu=gfx1010 %s -o /dev/null 2>&1 | FileCheck --check-prefixes=CHECK-NGG5 %s
; CHECK-NGG5: define dllexport amdgpu_hs void @_amdgpu_hs_main{{.*}} !lgc.shaderstage !5 {
@@ -291,14 +273,8 @@ attributes #1 = { nounwind readonly }
; ----------------------------------------------------------------------
; Extract 6: TES
-; RUN: lgc -extract=6 -print-after=lgc-patch-setup-target-features -mcpu=gfx900 %s -o /dev/null 2>&1 | FileCheck --check-prefixes=CHECK-GFX96 %s
; RUN: lgc -extract=6 -print-after=lgc-patch-setup-target-features -mcpu=gfx1010 %s -o /dev/null 2>&1 | FileCheck --check-prefixes=CHECK-NGG6 %s
-; CHECK-GFX96: define dllexport amdgpu_vs void @_amdgpu_vs_main{{.*}} !lgc.shaderstage !5 {
-; CHECK-GFX96: define dllexport amdgpu_ps void @_amdgpu_ps_main{{.*}} !lgc.shaderstage !6 {
-; CHECK-GFX96: !5 = !{i32 3}
-; CHECK-GFX96: !6 = !{i32 6}
-
; CHECK-NGG6: define dllexport amdgpu_gs void @_amdgpu_gs_main{{.*}} !lgc.shaderstage !5 {
; CHECK-NGG6: define dllexport amdgpu_ps void @_amdgpu_ps_main{{.*}} !lgc.shaderstage !6 {
; CHECK-NGG6: !5 = !{i32 3}
@@ -351,7 +327,6 @@ attributes #1 = { nounwind readonly }
; ----------------------------------------------------------------------
; Extract 7: TCS/TES/GS
-; RUN: lgc -extract=7 -print-after=lgc-patch-setup-target-features -mcpu=gfx900 %s -o /dev/null 2>&1 | FileCheck --check-prefixes=CHECK-NGG7 %s
; RUN: lgc -extract=7 -print-after=lgc-patch-setup-target-features -mcpu=gfx1010 %s -o /dev/null 2>&1 | FileCheck --check-prefixes=CHECK-NGG7 %s
; When there is are tes and geom shader, _amdgpu_hs_main must be first, so it can be linked with a potential
diff --git a/lgc/test/TextureRange.lgc b/lgc/test/TextureRange.lgc
index f45129a8f1..3cc0b9881a 100644
--- a/lgc/test/TextureRange.lgc
+++ b/lgc/test/TextureRange.lgc
@@ -1,5 +1,5 @@
-; RUN: lgc %s -print-after=lgc-builder-replayer -o /dev/null 2>&1 - <%s | FileCheck --check-prefixes=CHECK %s
+; RUN: lgc %s -print-after=lgc-lower-desc -o /dev/null 2>&1 - <%s | FileCheck --check-prefixes=CHECK %s
; CHECK: call <2 x i32> @lgc.load.user.data.v2i32(i32 24)
; CHECK: call ptr addrspace(7) @lgc.buffer.desc.to.ptr(<4 x i32>
@@ -71,11 +71,11 @@ define dllexport spir_func void @lgc.shader.VS.VSMain() local_unnamed_addr #0 !s
; Function Attrs: nounwind
define dllexport spir_func void @lgc.shader.FS.PSMain() local_unnamed_addr #0 !spirv.ExecutionModel !18 !lgc.shaderstage !19 {
.entry:
- %0 = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i32 -1610612736, i32 1, i32 0, i32 0)
+ %0 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 2684354560, i32 1, i32 0, i32 0)
%1 = call {}* @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) %0)
- %2 = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i32 -536870912, i32 1, i32 0, i32 2)
+ %2 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 3758096384, i32 1, i32 0, i32 2)
%3 = bitcast i8 addrspace(7)* %2 to <{ [4294967295 x float] }> addrspace(7)*
- %4 = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i32 -1610612736, i32 3, i32 0, i32 0)
+ %4 = call ptr addrspace(7) @lgc.load.buffer.desc(i64 2684354560, i32 3, i32 0, i32 0)
%5 = call {}* @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) %4)
%6 = call <2 x float> (...) @lgc.create.read.generic.input.v2f32(i32 0, i32 0, i32 0, i32 0, i32 16, i32 poison)
%7 = load i32, ptr addrspace(7) %4, align 4
@@ -85,11 +85,11 @@ define dllexport spir_func void @lgc.shader.FS.PSMain() local_unnamed_addr #0 !s
%11 = getelementptr inbounds i8, ptr addrspace(7) %0, i64 64
%12 = load float, ptr addrspace(7) %11, align 4
%13 = fmul reassoc nnan nsz arcp contract afn float %10, %12
- %14 = call ptr addrspace(4) (...) @lgc.create.get.desc.ptr.p4(i32 1, i32 1, i32 -1073741824, i32 1)
- %15 = call i32 (...) @lgc.create.get.desc.stride.i32(i32 1, i32 1, i32 -1073741824, i32 1)
+ %14 = call ptr addrspace(4) (...) @lgc.create.get.desc.ptr.p4(i32 1, i32 1, i64 3221225472, i32 1)
+ %15 = call i32 (...) @lgc.create.get.desc.stride.i32(i32 1, i32 1, i64 3221225472, i32 1)
%16 = load <8 x i32>, ptr addrspace(4) %14, align 32
- %17 = call ptr addrspace(4) (...) @lgc.create.get.desc.ptr.p4(i32 2, i32 2, i32 -2147483648, i32 0)
- %18 = call i32 (...) @lgc.create.get.desc.stride.i32(i32 2, i32 2, i32 -2147483648, i32 0)
+ %17 = call ptr addrspace(4) (...) @lgc.create.get.desc.ptr.p4(i32 2, i32 2, i64 2147483648, i32 0)
+ %18 = call i32 (...) @lgc.create.get.desc.stride.i32(i32 2, i32 2, i64 2147483648, i32 0)
%19 = load <4 x i32>, ptr addrspace(4) %17, align 16
%20 = call reassoc nnan nsz arcp contract afn <4 x float> (...) @lgc.create.image.sample.v4f32(i32 1, i32 512, <8 x i32> %16, <4 x i32> %19, i32 1, <2 x float> %6)
%.splatinsert = insertelement <4 x float> poison, float %13, i64 0
@@ -100,7 +100,7 @@ define dllexport spir_func void @lgc.shader.FS.PSMain() local_unnamed_addr #0 !s
}
; Function Attrs: nounwind readonly willreturn
-declare ptr addrspace(7) @lgc.create.load.buffer.desc.p7(...) local_unnamed_addr #1
+declare ptr addrspace(7) @lgc.load.buffer.desc(i64, i32, i32, i32) local_unnamed_addr #1
; Function Attrs: argmemonly nocallback nofree nosync nounwind willreturn
declare {}* @llvm.invariant.start.p7(i64 immarg, ptr addrspace(7) nocapture) #2
@@ -139,13 +139,13 @@ attributes #3 = { nounwind readnone }
!2 = !{i32 -64684466, i32 1801624907, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 64, i32 0, i32 0, i32 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 20, i32 1800}
!3 = !{i32 -1829766609, i32 -657263028, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 64, i32 0, i32 0, i32 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 20, i32 1800}
!4 = !{!"DescriptorTableVaPtr", i32 0, i32 0, i32 0, i32 1, i32 1}
-!5 = !{!"DescriptorBuffer", i32 6, i32 0, i32 0, i32 8, i32 -1610612736, i32 0, i32 4}
+!5 = !{!"DescriptorBuffer", i32 6, i32 0, i32 0, i32 8, i64 2684354560, i32 0, i32 4}
!6 = !{!"DescriptorTableVaPtr", i32 0, i32 0, i32 1, i32 1, i32 2}
-!7 = !{!"DescriptorResource", i32 1, i32 0, i32 0, i32 16, i32 -1073741824, i32 0, i32 8}
-!8 = !{!"DescriptorSampler", i32 2, i32 0, i32 16, i32 4, i32 -2147483648, i32 0, i32 4}
-!9 = !{!"InlineBuffer", i32 14, i32 0, i32 2, i32 1, i32 -1610612736, i32 3, i32 4}
-!10 = !{!"InlineBuffer", i32 14, i32 0, i32 3, i32 1, i32 -1610612736, i32 4, i32 4}
-!11 = !{!"DescriptorBufferCompact", i32 10, i32 0, i32 4, i32 4, i32 -536870912, i32 0, i32 2}
+!7 = !{!"DescriptorResource", i32 1, i32 0, i32 0, i32 16, i64 3221225472, i32 0, i32 8}
+!8 = !{!"DescriptorSampler", i32 2, i32 0, i32 16, i32 4, i64 2147483648, i32 0, i32 4}
+!9 = !{!"InlineBuffer", i32 14, i32 0, i32 2, i32 1, i64 2684354560, i32 3, i32 4}
+!10 = !{!"InlineBuffer", i32 14, i32 0, i32 3, i32 1, i64 2684354560, i32 4, i32 4}
+!11 = !{!"DescriptorBufferCompact", i32 10, i32 0, i32 4, i32 4, i64 3758096384, i32 0, i32 2}
!12 = !{!"IndirectUserDataVaPtr", i32 0, i32 0, i32 7, i32 1, i32 0}
!13 = !{i32 16, i32 0, i32 0, i32 0, i32 15}
!14 = !{i32 3, i32 3}
diff --git a/lgc/test/Transforms/Continufy/simple.lgc b/lgc/test/Transforms/Continufy/simple.lgc
index 81eaa6bd5a..0d7e4cef86 100644
--- a/lgc/test/Transforms/Continufy/simple.lgc
+++ b/lgc/test/Transforms/Continufy/simple.lgc
@@ -40,7 +40,7 @@ exit:
declare ptr addrspace(4) @lgc.user.data(i32)
declare i32 @lgc.shader.input.LocalInvocationId(i32)
; CHECK-LABEL: define {{[^@]+}}@raygen
-; CHECK-SAME: ({} [[STATE:%.*]], i32 [[RCR:%.*]]) !lgc.shaderstage !2 !continufy.stage !3 !lgc.cps !3 {
+; CHECK-SAME: ({} [[STATE:%.*]], i32 [[RCR:%.*]], i32 [[SHADER_INDEX:%.*]]) !lgc.shaderstage !2 !continufy.stage !3 !lgc.cps !3 {
; CHECK-NEXT: [[PUSHCONST:%.*]] = call ptr addrspace(4) @lgc.user.data(i32 0)
; CHECK-NEXT: [[FN:%.*]] = load ptr, ptr addrspace(4) [[PUSHCONST]], align 8
; CHECK-NEXT: [[P8:%.*]] = getelementptr i8, ptr addrspace(4) [[PUSHCONST]], i32 8
@@ -49,19 +49,19 @@ declare i32 @lgc.shader.input.LocalInvocationId(i32)
; CHECK-NEXT: [[DST:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[P16]], align 8
; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[FN]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 2
-; CHECK-NEXT: [[TMP3:%.*]] = call [2 x i32] (...) @lgc.cps.await.a2i32(i32 [[TMP2]], i32 4, i32 [[X]], ptr addrspace(1) [[DST]])
+; CHECK-NEXT: [[TMP3:%.*]] = call [2 x i32] (...) @lgc.cps.await.a2i32(i32 [[TMP2]], i32 4, i32 poison, i32 [[X]], ptr addrspace(1) [[DST]])
; CHECK-NEXT: store [2 x i32] [[TMP3]], ptr addrspace(1) [[DST]], align 4
; CHECK-NEXT: ret void
;
;
; CHECK-LABEL: define {{[^@]+}}@chs
-; CHECK-SAME: ({} [[STATE:%.*]], i32 [[RCR:%.*]], i32 [[X:%.*]]) !lgc.shaderstage !2 !continufy.stage !4 !lgc.cps !5 {
+; CHECK-SAME: ({} [[STATE:%.*]], i32 [[RCR:%.*]], i32 [[SHADER_INDEX:%.*]], i32 [[X:%.*]]) !lgc.shaderstage !2 !continufy.stage !4 !lgc.cps !5 {
; CHECK-NEXT: [[PUSHCONST:%.*]] = call ptr addrspace(4) @lgc.user.data(i32 24)
; CHECK-NEXT: [[FN:%.*]] = load ptr, ptr addrspace(4) [[PUSHCONST]], align 8
; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[FN]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 1
-; CHECK-NEXT: [[TMP3:%.*]] = call i32 (...) @lgc.cps.await.i32(i32 [[TMP2]], i32 2, i32 [[X]])
-; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[RCR]], i32 4, {} poison, i32 poison, i32 [[TMP3]])
+; CHECK-NEXT: [[TMP3:%.*]] = call i32 (...) @lgc.cps.await.i32(i32 [[TMP2]], i32 2, i32 poison, i32 [[X]])
+; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[RCR]], i32 4, {} poison, i32 poison, i32 poison, i32 [[TMP3]])
; CHECK-NEXT: unreachable
;
;
@@ -74,7 +74,7 @@ declare i32 @lgc.shader.input.LocalInvocationId(i32)
; CHECK-NEXT: [[PUSHCONST:%.*]] = call ptr addrspace(4) @lgc.user.data(i32 32)
; CHECK-NEXT: [[FN:%.*]] = load ptr, ptr addrspace(4) [[PUSHCONST]], align 8
; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[FN]] to i32
-; CHECK-NEXT: call void (...) @lgc.cps.await.isVoid(i32 [[TMP0]], i32 1)
+; CHECK-NEXT: call void (...) @lgc.cps.await.isVoid(i32 [[TMP0]], i32 1, i32 poison)
; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
; CHECK-NEXT: ret void
diff --git a/lgc/test/Transforms/CpsLowering/continuation-basic.lgc b/lgc/test/Transforms/CpsLowering/continuation-basic.lgc
index 2b06d4351f..e0faa36e92 100644
--- a/lgc/test/Transforms/CpsLowering/continuation-basic.lgc
+++ b/lgc/test/Transforms/CpsLowering/continuation-basic.lgc
@@ -17,9 +17,9 @@ entry:
!0 = !{i32 1} ; level 1
; CHECK-LABEL: define {{[^@]+}}@test
-; CHECK-SAME: (i32 inreg [[GLOBALTABLE:%.*]], ptr addrspace(4) inreg [[NUMWORKGROUPSPTR:%.*]], i32 inreg [[PAD0:%.*]], i32 inreg [[PAD1:%.*]], i32 inreg [[PAD2:%.*]], i32 inreg [[PAD3:%.*]], i32 inreg [[PAD4:%.*]], i32 inreg [[PAD5:%.*]], i32 inreg [[PAD6:%.*]], i32 inreg [[PAD7:%.*]], i32 inreg [[PAD8:%.*]], i32 inreg [[PAD9:%.*]], i32 inreg [[PAD10:%.*]], i32 inreg [[PAD11:%.*]], i32 inreg [[SPILLTABLE:%.*]], i32 [[VCR:%.*]], ptr addrspace(5) [[VSP:%.*]], i32 [[ARG:%.*]], ptr [[TABLE:%.*]]) #[[ATTR1:[0-9]+]] align 64 !lgc.cps !2 !lgc.shaderstage !3 {
+; CHECK-SAME: (i32 inreg [[GLOBALTABLE:%.*]], ptr addrspace(4) inreg [[NUMWORKGROUPSPTR:%.*]], i32 inreg [[PAD0:%.*]], i32 inreg [[PAD1:%.*]], i32 inreg [[PAD2:%.*]], i32 inreg [[PAD3:%.*]], i32 inreg [[PAD4:%.*]], i32 inreg [[PAD5:%.*]], i32 inreg [[PAD6:%.*]], i32 inreg [[PAD7:%.*]], i32 inreg [[PAD8:%.*]], i32 inreg [[PAD9:%.*]], i32 inreg [[PAD10:%.*]], i32 inreg [[PAD11:%.*]], i32 inreg [[SPILLTABLE:%.*]], <3 x i32> inreg [[WORKGROUPID:%.*]], i32 inreg [[MULTIDISPATCHINFO:%.*]], <3 x i32> [[LOCALINVOCATIONID:%.*]], i32 [[VCR:%.*]], ptr addrspace(5) [[VSP:%.*]], i32 [[ARG:%.*]], ptr [[TABLE:%.*]]) #[[ATTR1:[0-9]+]] align 64 !lgc.cps !2 !lgc.shaderstage !3 {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+; CHECK-NEXT: [[TMP0:%.*]] = alloca i32, align 4, addrspace(5)
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.amdgcn.s.getpc()
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[TMP1]] to <2 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[SPILLTABLE]], i64 0
@@ -29,55 +29,65 @@ entry:
; CHECK-NEXT: [[TMP7:%.*]] = bitcast i64 [[TMP6]] to <2 x i32>
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr addrspace(5) [[VSP]], i32 -4
; CHECK-NEXT: [[CPS_STATE:%.*]] = load { i32 }, ptr addrspace(5) [[TMP8]], align 4
-; CHECK-NEXT: store ptr addrspace(5) [[TMP8]], ptr addrspace(5) [[TMP0]], align 4
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr addrspace(5) [[TMP8]] to i32
+; CHECK-NEXT: store i32 [[TMP9]], ptr addrspace(5) [[TMP0]], align 4
; CHECK-NEXT: [[V:%.*]] = extractvalue { i32 } [[CPS_STATE]], 0
; CHECK-NEXT: [[TABLE_0:%.*]] = getelementptr i32, ptr [[TABLE]], i32 0
; CHECK-NEXT: [[CR_THEN:%.*]] = load i32, ptr [[TABLE_0]], align 4
; CHECK-NEXT: [[THEN_ARG:%.*]] = add i32 [[ARG]], 1
; CHECK-NEXT: [[V_THEN:%.*]] = mul i32 [[V]], 2
; CHECK-NEXT: [[STATE_THEN:%.*]] = insertvalue { i32 } poison, i32 [[V_THEN]], 0
-; CHECK-NEXT: [[TMP9:%.*]] = load ptr addrspace(5), ptr addrspace(5) [[TMP0]], align 4
-; CHECK-NEXT: store { i32 } [[STATE_THEN]], ptr addrspace(5) [[TMP9]], align 4
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr addrspace(5) [[TMP9]], i32 4
+; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(5) [[TMP0]], align 4
+; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP10]] to ptr addrspace(5)
+; CHECK-NEXT: store { i32 } [[STATE_THEN]], ptr addrspace(5) [[TMP11]], align 4
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr addrspace(5) [[TMP11]], i32 4
; CHECK-NEXT: br label [[TAIL_BLOCK:%.*]]
; CHECK: tail.block:
-; CHECK-NEXT: [[TMP11:%.*]] = insertvalue { i32, ptr addrspace(5), i32 } poison, i32 [[CR_THEN]], 0
-; CHECK-NEXT: [[TMP12:%.*]] = insertvalue { i32, ptr addrspace(5), i32 } [[TMP11]], ptr addrspace(5) [[TMP10]], 1
-; CHECK-NEXT: [[TMP13:%.*]] = insertvalue { i32, ptr addrspace(5), i32 } [[TMP12]], i32 [[THEN_ARG]], 2
-; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
-; CHECK-NEXT: [[TMP15:%.*]] = bitcast i64 [[TMP14]] to <2 x i32>
-; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x i32> [[TMP15]], i64 0
-; CHECK-NEXT: [[TMP17:%.*]] = extractelement <2 x i32> [[TMP15]], i64 1
-; CHECK-NEXT: [[TMP18:%.*]] = insertelement <16 x i32> poison, i32 [[GLOBALTABLE]], i64 0
-; CHECK-NEXT: [[TMP19:%.*]] = insertelement <16 x i32> [[TMP18]], i32 [[TMP16]], i64 1
-; CHECK-NEXT: [[TMP20:%.*]] = insertelement <16 x i32> [[TMP19]], i32 [[TMP17]], i64 2
-; CHECK-NEXT: [[TMP21:%.*]] = insertelement <16 x i32> [[TMP20]], i32 [[PAD0]], i64 3
-; CHECK-NEXT: [[TMP22:%.*]] = insertelement <16 x i32> [[TMP21]], i32 [[PAD1]], i64 4
-; CHECK-NEXT: [[TMP23:%.*]] = insertelement <16 x i32> [[TMP22]], i32 [[PAD2]], i64 5
-; CHECK-NEXT: [[TMP24:%.*]] = insertelement <16 x i32> [[TMP23]], i32 [[PAD3]], i64 6
-; CHECK-NEXT: [[TMP25:%.*]] = insertelement <16 x i32> [[TMP24]], i32 [[PAD4]], i64 7
-; CHECK-NEXT: [[TMP26:%.*]] = insertelement <16 x i32> [[TMP25]], i32 [[PAD5]], i64 8
-; CHECK-NEXT: [[TMP27:%.*]] = insertelement <16 x i32> [[TMP26]], i32 [[PAD6]], i64 9
-; CHECK-NEXT: [[TMP28:%.*]] = insertelement <16 x i32> [[TMP27]], i32 [[PAD7]], i64 10
-; CHECK-NEXT: [[TMP29:%.*]] = insertelement <16 x i32> [[TMP28]], i32 [[PAD8]], i64 11
-; CHECK-NEXT: [[TMP30:%.*]] = insertelement <16 x i32> [[TMP29]], i32 [[PAD9]], i64 12
-; CHECK-NEXT: [[TMP31:%.*]] = insertelement <16 x i32> [[TMP30]], i32 [[PAD10]], i64 13
-; CHECK-NEXT: [[TMP32:%.*]] = insertelement <16 x i32> [[TMP31]], i32 [[PAD11]], i64 14
-; CHECK-NEXT: [[TMP33:%.*]] = insertelement <16 x i32> [[TMP32]], i32 [[SPILLTABLE]], i64 15
-; CHECK-NEXT: [[TMP34:%.*]] = extractvalue { i32, ptr addrspace(5), i32 } [[TMP13]], 0
-; CHECK-NEXT: [[TMP35:%.*]] = call i32 @llvm.amdgcn.set.inactive.{{(chain.arg.)?}}i32(i32 [[TMP34]], i32 [[VCR]])
-; CHECK-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
-; CHECK-NEXT: [[TMP37:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP36]])
-; CHECK-NEXT: [[TMP38:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP37]], i1 true)
-; CHECK-NEXT: [[TMP39:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP35]], i32 [[TMP38]])
-; CHECK-NEXT: [[TMP40:%.*]] = icmp eq i32 [[TMP35]], [[TMP39]]
-; CHECK-NEXT: [[TMP41:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP40]])
-; CHECK-NEXT: [[TMP42:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP39]])
-; CHECK-NEXT: [[TMP43:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP41]])
-; CHECK-NEXT: [[TMP44:%.*]] = and i32 [[TMP42]], -64
-; CHECK-NEXT: [[TMP45:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP44]], i64 0
-; CHECK-NEXT: [[TMP46:%.*]] = bitcast <2 x i32> [[TMP45]] to i64
-; CHECK-NEXT: [[TMP47:%.*]] = inttoptr i64 [[TMP46]] to ptr
-; CHECK-NEXT: call void (ptr, i32, <16 x i32>, { i32, ptr addrspace(5), i32 }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v16i32.sl_i32p5i32s(ptr inreg [[TMP47]], i32 inreg [[TMP43]], <16 x i32> inreg [[TMP33]], { i32, ptr addrspace(5), i32 } [[TMP13]], i32 0)
+; CHECK-NEXT: [[TMP13:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32 } poison, <3 x i32> [[LOCALINVOCATIONID]], 0
+; CHECK-NEXT: [[TMP14:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32 } [[TMP13]], i32 [[CR_THEN]], 1
+; CHECK-NEXT: [[TMP15:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32 } [[TMP14]], ptr addrspace(5) [[TMP12]], 2
+; CHECK-NEXT: [[TMP16:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32 } [[TMP15]], i32 [[THEN_ARG]], 3
+; CHECK-NEXT: [[TMP17:%.*]] = extractvalue { <3 x i32>, i32, ptr addrspace(5), i32 } [[TMP16]], 1
+; CHECK-NEXT: [[TMP18:%.*]] = call i32 @llvm.amdgcn.set.inactive.chain.arg.i32(i32 [[TMP17]], i32 [[VCR]])
+; CHECK-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
+; CHECK-NEXT: [[TMP20:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP19]])
+; CHECK-NEXT: [[TMP21:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP20]], i1 true)
+; CHECK-NEXT: [[TMP22:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP18]], i32 [[TMP21]])
+; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i32 [[TMP18]], [[TMP22]]
+; CHECK-NEXT: [[TMP24:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP23]])
+; CHECK-NEXT: [[TMP25:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP22]])
+; CHECK-NEXT: [[TMP26:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP24]])
+; CHECK-NEXT: [[TMP27:%.*]] = and i32 [[TMP25]], -64
+; CHECK-NEXT: [[TMP28:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP27]], i64 0
+; CHECK-NEXT: [[TMP29:%.*]] = bitcast <2 x i32> [[TMP28]] to i64
+; CHECK-NEXT: [[TMP30:%.*]] = inttoptr i64 [[TMP29]] to ptr
+; CHECK-NEXT: [[TMP31:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
+; CHECK-NEXT: [[TMP32:%.*]] = bitcast i64 [[TMP31]] to <2 x i32>
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <2 x i32> [[TMP32]], i64 0
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <2 x i32> [[TMP32]], i64 1
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 0
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 1
+; CHECK-NEXT: [[TMP37:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 2
+; CHECK-NEXT: [[TMP38:%.*]] = insertelement <20 x i32> poison, i32 [[GLOBALTABLE]], i64 0
+; CHECK-NEXT: [[TMP39:%.*]] = insertelement <20 x i32> [[TMP38]], i32 [[TMP33]], i64 1
+; CHECK-NEXT: [[TMP40:%.*]] = insertelement <20 x i32> [[TMP39]], i32 [[TMP34]], i64 2
+; CHECK-NEXT: [[TMP41:%.*]] = insertelement <20 x i32> [[TMP40]], i32 [[PAD0]], i64 3
+; CHECK-NEXT: [[TMP42:%.*]] = insertelement <20 x i32> [[TMP41]], i32 [[PAD1]], i64 4
+; CHECK-NEXT: [[TMP43:%.*]] = insertelement <20 x i32> [[TMP42]], i32 [[PAD2]], i64 5
+; CHECK-NEXT: [[TMP44:%.*]] = insertelement <20 x i32> [[TMP43]], i32 [[PAD3]], i64 6
+; CHECK-NEXT: [[TMP45:%.*]] = insertelement <20 x i32> [[TMP44]], i32 [[PAD4]], i64 7
+; CHECK-NEXT: [[TMP46:%.*]] = insertelement <20 x i32> [[TMP45]], i32 [[PAD5]], i64 8
+; CHECK-NEXT: [[TMP47:%.*]] = insertelement <20 x i32> [[TMP46]], i32 [[PAD6]], i64 9
+; CHECK-NEXT: [[TMP48:%.*]] = insertelement <20 x i32> [[TMP47]], i32 [[PAD7]], i64 10
+; CHECK-NEXT: [[TMP49:%.*]] = insertelement <20 x i32> [[TMP48]], i32 [[PAD8]], i64 11
+; CHECK-NEXT: [[TMP50:%.*]] = insertelement <20 x i32> [[TMP49]], i32 [[PAD9]], i64 12
+; CHECK-NEXT: [[TMP51:%.*]] = insertelement <20 x i32> [[TMP50]], i32 [[PAD10]], i64 13
+; CHECK-NEXT: [[TMP52:%.*]] = insertelement <20 x i32> [[TMP51]], i32 [[PAD11]], i64 14
+; CHECK-NEXT: [[TMP53:%.*]] = insertelement <20 x i32> [[TMP52]], i32 [[SPILLTABLE]], i64 15
+; CHECK-NEXT: [[TMP54:%.*]] = insertelement <20 x i32> [[TMP53]], i32 [[TMP35]], i64 16
+; CHECK-NEXT: [[TMP55:%.*]] = insertelement <20 x i32> [[TMP54]], i32 [[TMP36]], i64 17
+; CHECK-NEXT: [[TMP56:%.*]] = insertelement <20 x i32> [[TMP55]], i32 [[TMP37]], i64 18
+; CHECK-NEXT: [[TMP57:%.*]] = insertelement <20 x i32> [[TMP56]], i32 [[MULTIDISPATCHINFO]], i64 19
+; CHECK-NEXT: call void (ptr, i32, <20 x i32>, { <3 x i32>, i32, ptr addrspace(5), i32 }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v20i32.sl_v3i32i32p5i32s(ptr inreg [[TMP30]], i32 inreg [[TMP26]], <20 x i32> inreg [[TMP57]], { <3 x i32>, i32, ptr addrspace(5), i32 } [[TMP16]], i32 0)
; CHECK-NEXT: unreachable
;
diff --git a/lgc/test/Transforms/CpsLowering/cps-entry-point.lgc b/lgc/test/Transforms/CpsLowering/cps-entry-point.lgc
index 8ff0f669f8..f1824f7734 100644
--- a/lgc/test/Transforms/CpsLowering/cps-entry-point.lgc
+++ b/lgc/test/Transforms/CpsLowering/cps-entry-point.lgc
@@ -44,12 +44,13 @@ attributes #5 = { nounwind willreturn memory(none) }
!llpc.compute.mode = !{!2}
!1 = !{!"DescriptorBuffer", i32 6, i32 6, i32 0, i32 4, i64 0, i32 0, i32 4}
-!2 = !{i32 8, i32 4, i32 1}
+!2 = !{i32 8, i32 4, i32 1, i32 0, i32 0, i32 1}
!3 = !{i32 7}
+
; CHECK-LABEL: define {{[^@]+}}@lgc.shader.CS.main
; CHECK-SAME: (i32 inreg noundef [[GLOBALTABLE:%.*]], ptr addrspace(4) inreg noundef [[NUMWORKGROUPSPTR:%.*]], i32 inreg noundef [[USERDATA0:%.*]], i32 inreg noundef [[USERDATA1:%.*]], i32 inreg noundef [[USERDATA2:%.*]], i32 inreg noundef [[USERDATA3:%.*]], i32 inreg noundef [[PAD4:%.*]], i32 inreg noundef [[PAD5:%.*]], i32 inreg noundef [[PAD6:%.*]], i32 inreg noundef [[PAD7:%.*]], i32 inreg noundef [[PAD8:%.*]], i32 inreg noundef [[PAD9:%.*]], i32 inreg noundef [[PAD10:%.*]], i32 inreg noundef [[PAD11:%.*]], i32 inreg noundef [[SPILLTABLE:%.*]], <3 x i32> inreg noundef [[WORKGROUPID:%.*]], i32 inreg noundef [[MULTIDISPATCHINFO:%.*]], <3 x i32> noundef [[LOCALINVOCATIONID:%.*]]) #[[ATTR3:[0-9]+]] !lgc.shaderstage !4 {
; CHECK-NEXT: .entry:
-; CHECK-NEXT: [[TMP0:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+; CHECK-NEXT: [[TMP0:%.*]] = alloca i32, align 4, addrspace(5)
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.amdgcn.s.getpc()
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[TMP1]] to <2 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[SPILLTABLE]], i64 0
@@ -64,55 +65,61 @@ attributes #5 = { nounwind willreturn memory(none) }
; CHECK-NEXT: [[PTR:%.*]] = call ptr addrspace(7) @lgc.buffer.desc.to.ptr(<4 x i32> [[TMP11]])
; CHECK-NEXT: [[P0:%.*]] = getelementptr i32, ptr addrspace(7) [[PTR]], i32 0
; CHECK-NEXT: [[I_VSP:%.*]] = load i32, ptr addrspace(7) [[P0]], align 4
-; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i32 [[I_VSP]] to ptr addrspace(5)
-; CHECK-NEXT: store ptr addrspace(5) [[TMP12]], ptr addrspace(5) [[TMP0]], align 4
+; CHECK-NEXT: store i32 [[I_VSP]], ptr addrspace(5) [[TMP0]], align 4
; CHECK-NEXT: [[P1:%.*]] = getelementptr i32, ptr addrspace(7) [[PTR]], i32 1
; CHECK-NEXT: [[CR:%.*]] = load i32, ptr addrspace(7) [[P1]], align 4
; CHECK-NEXT: [[P2:%.*]] = getelementptr i32, ptr addrspace(7) [[PTR]], i32 2
; CHECK-NEXT: [[ARG:%.*]] = load i32, ptr addrspace(7) [[P2]], align 4
; CHECK-NEXT: [[STATE:%.*]] = insertvalue { i32 } poison, i32 [[ARG]], 0
-; CHECK-NEXT: [[TMP13:%.*]] = load ptr addrspace(5), ptr addrspace(5) [[TMP0]], align 4
-; CHECK-NEXT: [[TMP14:%.*]] = load ptr addrspace(5), ptr addrspace(5) [[TMP0]], align 4
+; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(5) [[TMP0]], align 4
+; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(5) [[TMP0]], align 4
+; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i32 [[TMP13]] to ptr addrspace(5)
; CHECK-NEXT: store { i32 } [[STATE]], ptr addrspace(5) [[TMP14]], align 4
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr addrspace(5) [[TMP14]], i32 4
-; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr addrspace(5) [[TMP13]] to i32
; CHECK-NEXT: br label [[TAIL_BLOCK:%.*]]
; CHECK: tail.block:
-; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { i32, ptr addrspace(5), i32, i32 } poison, i32 [[CR]], 0
-; CHECK-NEXT: [[TMP18:%.*]] = insertvalue { i32, ptr addrspace(5), i32, i32 } [[TMP17]], ptr addrspace(5) [[TMP15]], 1
-; CHECK-NEXT: [[TMP19:%.*]] = insertvalue { i32, ptr addrspace(5), i32, i32 } [[TMP18]], i32 [[ARG]], 2
-; CHECK-NEXT: [[TMP20:%.*]] = insertvalue { i32, ptr addrspace(5), i32, i32 } [[TMP19]], i32 [[TMP16]], 3
-; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
-; CHECK-NEXT: [[TMP22:%.*]] = bitcast i64 [[TMP21]] to <2 x i32>
-; CHECK-NEXT: [[TMP23:%.*]] = extractelement <2 x i32> [[TMP22]], i64 0
-; CHECK-NEXT: [[TMP24:%.*]] = extractelement <2 x i32> [[TMP22]], i64 1
-; CHECK-NEXT: [[TMP25:%.*]] = insertelement <16 x i32> poison, i32 [[GLOBALTABLE]], i64 0
-; CHECK-NEXT: [[TMP26:%.*]] = insertelement <16 x i32> [[TMP25]], i32 [[TMP23]], i64 1
-; CHECK-NEXT: [[TMP27:%.*]] = insertelement <16 x i32> [[TMP26]], i32 [[TMP24]], i64 2
-; CHECK-NEXT: [[TMP28:%.*]] = insertelement <16 x i32> [[TMP27]], i32 [[USERDATA0]], i64 3
-; CHECK-NEXT: [[TMP29:%.*]] = insertelement <16 x i32> [[TMP28]], i32 [[USERDATA1]], i64 4
-; CHECK-NEXT: [[TMP30:%.*]] = insertelement <16 x i32> [[TMP29]], i32 [[USERDATA2]], i64 5
-; CHECK-NEXT: [[TMP31:%.*]] = insertelement <16 x i32> [[TMP30]], i32 [[USERDATA3]], i64 6
-; CHECK-NEXT: [[TMP32:%.*]] = insertelement <16 x i32> [[TMP31]], i32 [[PAD4]], i64 7
-; CHECK-NEXT: [[TMP33:%.*]] = insertelement <16 x i32> [[TMP32]], i32 [[PAD5]], i64 8
-; CHECK-NEXT: [[TMP34:%.*]] = insertelement <16 x i32> [[TMP33]], i32 [[PAD6]], i64 9
-; CHECK-NEXT: [[TMP35:%.*]] = insertelement <16 x i32> [[TMP34]], i32 [[PAD7]], i64 10
-; CHECK-NEXT: [[TMP36:%.*]] = insertelement <16 x i32> [[TMP35]], i32 [[PAD8]], i64 11
-; CHECK-NEXT: [[TMP37:%.*]] = insertelement <16 x i32> [[TMP36]], i32 [[PAD9]], i64 12
-; CHECK-NEXT: [[TMP38:%.*]] = insertelement <16 x i32> [[TMP37]], i32 [[PAD10]], i64 13
-; CHECK-NEXT: [[TMP39:%.*]] = insertelement <16 x i32> [[TMP38]], i32 [[PAD11]], i64 14
-; CHECK-NEXT: [[TMP40:%.*]] = insertelement <16 x i32> [[TMP39]], i32 [[SPILLTABLE]], i64 15
-; CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i32, ptr addrspace(5), i32, i32 } [[TMP20]], 0
-; CHECK-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0
-; CHECK-NEXT: [[TMP43:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP42]])
-; CHECK-NEXT: [[TMP44:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP43]], i1 true)
-; CHECK-NEXT: [[TMP45:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP41]], i32 [[TMP44]])
-; CHECK-NEXT: [[TMP46:%.*]] = icmp eq i32 [[TMP41]], [[TMP45]]
-; CHECK-NEXT: [[TMP47:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP46]])
-; CHECK-NEXT: [[TMP48:%.*]] = and i32 [[TMP45]], -64
-; CHECK-NEXT: [[TMP49:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP48]], i64 0
-; CHECK-NEXT: [[TMP50:%.*]] = bitcast <2 x i32> [[TMP49]] to i64
-; CHECK-NEXT: [[TMP51:%.*]] = inttoptr i64 [[TMP50]] to ptr
-; CHECK-NEXT: call void (ptr, i32, <16 x i32>, { i32, ptr addrspace(5), i32, i32 }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v16i32.sl_i32p5i32i32s(ptr inreg [[TMP51]], i32 inreg [[TMP47]], <16 x i32> inreg [[TMP40]], { i32, ptr addrspace(5), i32, i32 } [[TMP20]], i32 0)
+; CHECK-NEXT: [[TMP16:%.*]] = insertvalue { i32, ptr addrspace(5), i32, i32 } poison, i32 [[CR]], 0
+; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { i32, ptr addrspace(5), i32, i32 } [[TMP16]], ptr addrspace(5) [[TMP15]], 1
+; CHECK-NEXT: [[TMP18:%.*]] = insertvalue { i32, ptr addrspace(5), i32, i32 } [[TMP17]], i32 [[ARG]], 2
+; CHECK-NEXT: [[TMP19:%.*]] = insertvalue { i32, ptr addrspace(5), i32, i32 } [[TMP18]], i32 [[TMP12]], 3
+; CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i32, ptr addrspace(5), i32, i32 } [[TMP19]], 0
+; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
+; CHECK-NEXT: [[TMP22:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP21]])
+; CHECK-NEXT: [[TMP23:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP22]], i1 true)
+; CHECK-NEXT: [[TMP24:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP20]], i32 [[TMP23]])
+; CHECK-NEXT: [[TMP25:%.*]] = icmp eq i32 [[TMP20]], [[TMP24]]
+; CHECK-NEXT: [[TMP26:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP25]])
+; CHECK-NEXT: [[TMP27:%.*]] = and i32 [[TMP24]], -64
+; CHECK-NEXT: [[TMP28:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP27]], i64 0
+; CHECK-NEXT: [[TMP29:%.*]] = bitcast <2 x i32> [[TMP28]] to i64
+; CHECK-NEXT: [[TMP30:%.*]] = inttoptr i64 [[TMP29]] to ptr
+; CHECK-NEXT: [[TMP31:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
+; CHECK-NEXT: [[TMP32:%.*]] = bitcast i64 [[TMP31]] to <2 x i32>
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <2 x i32> [[TMP32]], i64 0
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <2 x i32> [[TMP32]], i64 1
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 0
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 1
+; CHECK-NEXT: [[TMP37:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 2
+; CHECK-NEXT: [[TMP38:%.*]] = insertelement <20 x i32> poison, i32 [[GLOBALTABLE]], i64 0
+; CHECK-NEXT: [[TMP39:%.*]] = insertelement <20 x i32> [[TMP38]], i32 [[TMP33]], i64 1
+; CHECK-NEXT: [[TMP40:%.*]] = insertelement <20 x i32> [[TMP39]], i32 [[TMP34]], i64 2
+; CHECK-NEXT: [[TMP41:%.*]] = insertelement <20 x i32> [[TMP40]], i32 [[USERDATA0]], i64 3
+; CHECK-NEXT: [[TMP42:%.*]] = insertelement <20 x i32> [[TMP41]], i32 [[USERDATA1]], i64 4
+; CHECK-NEXT: [[TMP43:%.*]] = insertelement <20 x i32> [[TMP42]], i32 [[USERDATA2]], i64 5
+; CHECK-NEXT: [[TMP44:%.*]] = insertelement <20 x i32> [[TMP43]], i32 [[USERDATA3]], i64 6
+; CHECK-NEXT: [[TMP45:%.*]] = insertelement <20 x i32> [[TMP44]], i32 [[PAD4]], i64 7
+; CHECK-NEXT: [[TMP46:%.*]] = insertelement <20 x i32> [[TMP45]], i32 [[PAD5]], i64 8
+; CHECK-NEXT: [[TMP47:%.*]] = insertelement <20 x i32> [[TMP46]], i32 [[PAD6]], i64 9
+; CHECK-NEXT: [[TMP48:%.*]] = insertelement <20 x i32> [[TMP47]], i32 [[PAD7]], i64 10
+; CHECK-NEXT: [[TMP49:%.*]] = insertelement <20 x i32> [[TMP48]], i32 [[PAD8]], i64 11
+; CHECK-NEXT: [[TMP50:%.*]] = insertelement <20 x i32> [[TMP49]], i32 [[PAD9]], i64 12
+; CHECK-NEXT: [[TMP51:%.*]] = insertelement <20 x i32> [[TMP50]], i32 [[PAD10]], i64 13
+; CHECK-NEXT: [[TMP52:%.*]] = insertelement <20 x i32> [[TMP51]], i32 [[PAD11]], i64 14
+; CHECK-NEXT: [[TMP53:%.*]] = insertelement <20 x i32> [[TMP52]], i32 [[SPILLTABLE]], i64 15
+; CHECK-NEXT: [[TMP54:%.*]] = insertelement <20 x i32> [[TMP53]], i32 [[TMP35]], i64 16
+; CHECK-NEXT: [[TMP55:%.*]] = insertelement <20 x i32> [[TMP54]], i32 [[TMP36]], i64 17
+; CHECK-NEXT: [[TMP56:%.*]] = insertelement <20 x i32> [[TMP55]], i32 [[TMP37]], i64 18
+; CHECK-NEXT: [[TMP57:%.*]] = insertelement <20 x i32> [[TMP56]], i32 [[MULTIDISPATCHINFO]], i64 19
+; CHECK-NEXT: call void (ptr, i32, <20 x i32>, { i32, ptr addrspace(5), i32, i32 }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v20i32.sl_i32p5i32i32s(ptr inreg [[TMP30]], i32 inreg [[TMP26]], <20 x i32> inreg [[TMP57]], { i32, ptr addrspace(5), i32, i32 } [[TMP19]], i32 0)
; CHECK-NEXT: unreachable
;
diff --git a/lgc/test/Transforms/CpsLowering/cps-from-continufy.lgc b/lgc/test/Transforms/CpsLowering/cps-from-continufy.lgc
index 880e354825..6282fab94a 100644
--- a/lgc/test/Transforms/CpsLowering/cps-from-continufy.lgc
+++ b/lgc/test/Transforms/CpsLowering/cps-from-continufy.lgc
@@ -76,6 +76,9 @@ entryresume.0:
%.reload3 = load ptr addrspace(7), ptr addrspace(32) %5, align 32
%6 = getelementptr inbounds %_rgen_1.Frame, ptr addrspace(32) %3, i32 0, i32 0
%.reload = load ptr addrspace(7), ptr addrspace(32) %6, align 32
+ %dummy.udata = call i32 @lgc.load.user.data.i32(i32 20)
+ %dummy.gep = getelementptr inbounds %_rgen_1.Frame, ptr addrspace(32) %3, i32 %dummy.udata, i32 0
+ %dummy.reload = load ptr addrspace(7), ptr addrspace(32) %dummy.gep, align 32
%7 = load volatile i32, ptr addrspace(7) %.reload3, align 4
%8 = icmp eq i32 %.reload6, %7
%9 = zext i1 %8 to i32
@@ -143,7 +146,7 @@ attributes #7 = { nounwind willreturn memory(inaccessiblemem: read) }
; CHECK-LABEL: define {{[^@]+}}@_rgen_1
; CHECK-SAME: (i32 inreg [[GLOBALTABLE:%.*]], ptr addrspace(4) inreg [[NUMWORKGROUPSPTR:%.*]], i32 inreg [[USERDATA0:%.*]], i32 inreg [[USERDATA1:%.*]], i32 inreg [[USERDATA2:%.*]], i32 inreg [[USERDATA3:%.*]], i32 inreg [[USERDATA4:%.*]], i32 inreg [[USERDATA5:%.*]], i32 inreg [[PAD6:%.*]], i32 inreg [[PAD7:%.*]], i32 inreg [[PAD8:%.*]], i32 inreg [[PAD9:%.*]], i32 inreg [[PAD10:%.*]], i32 inreg [[PAD11:%.*]], i32 inreg [[SPILLTABLE:%.*]], <3 x i32> inreg [[WORKGROUPID:%.*]], i32 inreg [[MULTIDISPATCHINFO:%.*]], <3 x i32> [[LOCALINVOCATIONID:%.*]], i32 [[VCR:%.*]], ptr addrspace(5) [[VSP:%.*]], i32 [[RCR:%.*]]) #[[ATTR0:[0-9]+]] align 64 !spirv.ExecutionModel !15 !lgc.shaderstage !16 !continufy.stage !17 !continuation !18 !lgc.cps !17 {
; CHECK-NEXT: .entry:
-; CHECK-NEXT: [[TMP0:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+; CHECK-NEXT: [[TMP0:%.*]] = alloca i32, align 4, addrspace(5)
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.amdgcn.s.getpc()
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[TMP1]] to <2 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[SPILLTABLE]], i64 0
@@ -151,120 +154,124 @@ attributes #7 = { nounwind willreturn memory(inaccessiblemem: read) }
; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr addrspace(4)
; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.amdgcn.s.getpc()
; CHECK-NEXT: [[TMP7:%.*]] = bitcast i64 [[TMP6]] to <2 x i32>
-; CHECK-NEXT: store ptr addrspace(5) [[VSP]], ptr addrspace(5) [[TMP0]], align 4
-; CHECK-NEXT: [[TMP8:%.*]] = load ptr addrspace(5), ptr addrspace(5) [[TMP0]], align 4
-; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr addrspace(5) [[TMP8]], i32 96
-; CHECK-NEXT: store ptr addrspace(5) [[TMP9]], ptr addrspace(5) [[TMP0]], align 4
-; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.amdgcn.s.getpc()
-; CHECK-NEXT: [[TMP11:%.*]] = bitcast i64 [[TMP10]] to <2 x i32>
-; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.amdgcn.s.getpc()
-; CHECK-NEXT: [[TMP13:%.*]] = bitcast i64 [[TMP12]] to <2 x i32>
-; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.amdgcn.s.getpc()
-; CHECK-NEXT: [[TMP15:%.*]] = bitcast i64 [[TMP14]] to <2 x i32>
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <2 x i32> [[TMP15]], i32 [[USERDATA5]], i64 0
-; CHECK-NEXT: [[TMP17:%.*]] = bitcast <2 x i32> [[TMP16]] to i64
-; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr addrspace(4)
-; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP18]], i32 0
-; CHECK-NEXT: [[TMP20:%.*]] = load <2 x i32>, ptr addrspace(4) [[TMP19]], align 8
-; CHECK-NEXT: [[TMP21:%.*]] = extractelement <2 x i32> [[TMP20]], i64 0
-; CHECK-NEXT: [[TMP22:%.*]] = extractelement <2 x i32> [[TMP20]], i64 1
-; CHECK-NEXT: [[TMP23:%.*]] = insertelement <4 x i32> poison, i32 [[TMP21]], i64 0
-; CHECK-NEXT: [[TMP24:%.*]] = and i32 [[TMP22]], 65535
-; CHECK-NEXT: [[TMP25:%.*]] = insertelement <4 x i32> [[TMP23]], i32 [[TMP24]], i64 1
-; CHECK-NEXT: [[TMP26:%.*]] = insertelement <4 x i32> [[TMP25]], i32 -1, i64 2
-; CHECK-NEXT: [[TMP27:%.*]] = insertelement <4 x i32> [[TMP26]], i32 553734060, i64 3
-; CHECK-NEXT: [[TMP28:%.*]] = call ptr addrspace(7) @lgc.buffer.desc.to.ptr(<4 x i32> [[TMP27]])
-; CHECK-NEXT: [[TMP29:%.*]] = insertelement <2 x i32> [[TMP13]], i32 [[USERDATA0]], i64 0
-; CHECK-NEXT: [[TMP30:%.*]] = bitcast <2 x i32> [[TMP29]] to i64
-; CHECK-NEXT: [[TMP31:%.*]] = inttoptr i64 [[TMP30]] to ptr addrspace(4)
-; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP31]], i32 32
-; CHECK-NEXT: [[TMP33:%.*]] = load <4 x i32>, ptr addrspace(4) [[TMP32]], align 16
-; CHECK-NEXT: [[TMP34:%.*]] = call ptr addrspace(7) @lgc.buffer.desc.to.ptr(<4 x i32> [[TMP33]])
-; CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[_RGEN_1_FRAME:%.*]], ptr addrspace(5) [[TMP8]], i32 0, i32 0
-; CHECK-NEXT: store ptr addrspace(7) [[TMP34]], ptr addrspace(5) [[TMP35]], align 32
-; CHECK-NEXT: [[TMP36:%.*]] = insertelement <2 x i32> [[TMP11]], i32 [[USERDATA0]], i64 0
-; CHECK-NEXT: [[TMP37:%.*]] = bitcast <2 x i32> [[TMP36]] to i64
-; CHECK-NEXT: [[TMP38:%.*]] = inttoptr i64 [[TMP37]] to ptr addrspace(4)
-; CHECK-NEXT: [[TMP39:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP38]], i32 48
-; CHECK-NEXT: [[TMP40:%.*]] = load <4 x i32>, ptr addrspace(4) [[TMP39]], align 16
-; CHECK-NEXT: [[TMP41:%.*]] = call ptr addrspace(7) @lgc.buffer.desc.to.ptr(<4 x i32> [[TMP40]])
-; CHECK-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[_RGEN_1_FRAME]], ptr addrspace(5) [[TMP8]], i32 0, i32 1
-; CHECK-NEXT: store ptr addrspace(7) [[TMP41]], ptr addrspace(5) [[TMP42]], align 32
-; CHECK-NEXT: [[TMP43:%.*]] = load volatile i32, ptr addrspace(7) [[TMP41]], align 4
-; CHECK-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[_RGEN_1_FRAME]], ptr addrspace(5) [[TMP8]], i32 0, i32 2
-; CHECK-NEXT: store i32 [[TMP43]], ptr addrspace(5) [[TMP44]], align 4
-; CHECK-NEXT: [[TMP45:%.*]] = add i32 [[TMP43]], -37
-; CHECK-NEXT: [[TMP46:%.*]] = getelementptr inbounds i8, ptr addrspace(7) [[TMP28]], i32 52
-; CHECK-NEXT: [[TMP47:%.*]] = load i64, ptr addrspace(7) [[TMP46]], align 8
-; CHECK-NEXT: [[TMP48:%.*]] = getelementptr inbounds i8, ptr addrspace(7) [[TMP28]], i32 60
-; CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr addrspace(7) [[TMP48]], align 4
-; CHECK-NEXT: [[TMP50:%.*]] = mul i32 [[TMP45]], [[TMP49]]
-; CHECK-NEXT: [[TMP51:%.*]] = inttoptr i64 [[TMP47]] to ptr addrspace(1)
-; CHECK-NEXT: [[TMP52:%.*]] = sext i32 [[TMP50]] to i64
-; CHECK-NEXT: [[TMP53:%.*]] = getelementptr i8, ptr addrspace(1) [[TMP51]], i64 [[TMP52]]
-; CHECK-NEXT: [[TMP54:%.*]] = load i64, ptr addrspace(1) [[TMP53]], align 8
-; CHECK-NEXT: [[TMP55:%.*]] = inttoptr i64 [[TMP54]] to ptr
-; CHECK-NEXT: [[TMP56:%.*]] = ptrtoint ptr [[TMP55]] to i32
-; CHECK-NEXT: [[TMP57:%.*]] = or i32 [[TMP56]], 1
-; CHECK-NEXT: [[TMP58:%.*]] = inttoptr i32 [[TMP57]] to ptr
-; CHECK-NEXT: [[TMP59:%.*]] = load ptr addrspace(5), ptr addrspace(5) [[TMP0]], align 4
+; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr addrspace(5) [[VSP]] to i32
+; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(5) [[TMP0]], align 4
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(5) [[TMP0]], align 4
+; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], 96
+; CHECK-NEXT: store i32 [[TMP10]], ptr addrspace(5) [[TMP0]], align 4
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.amdgcn.s.getpc()
+; CHECK-NEXT: [[TMP12:%.*]] = bitcast i64 [[TMP11]] to <2 x i32>
+; CHECK-NEXT: [[TMP13:%.*]] = call i64 @llvm.amdgcn.s.getpc()
+; CHECK-NEXT: [[TMP14:%.*]] = bitcast i64 [[TMP13]] to <2 x i32>
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.amdgcn.s.getpc()
+; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <2 x i32>
+; CHECK-NEXT: [[TMP17:%.*]] = insertelement <2 x i32> [[TMP16]], i32 [[USERDATA5]], i64 0
+; CHECK-NEXT: [[TMP18:%.*]] = bitcast <2 x i32> [[TMP17]] to i64
+; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to ptr addrspace(4)
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP19]], i32 0
+; CHECK-NEXT: [[TMP21:%.*]] = load <2 x i32>, ptr addrspace(4) [[TMP20]], align 8
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <2 x i32> [[TMP21]], i64 0
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <2 x i32> [[TMP21]], i64 1
+; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x i32> poison, i32 [[TMP22]], i64 0
+; CHECK-NEXT: [[TMP25:%.*]] = and i32 [[TMP23]], 65535
+; CHECK-NEXT: [[TMP26:%.*]] = insertelement <4 x i32> [[TMP24]], i32 [[TMP25]], i64 1
+; CHECK-NEXT: [[TMP27:%.*]] = insertelement <4 x i32> [[TMP26]], i32 -1, i64 2
+; CHECK-NEXT: [[TMP28:%.*]] = insertelement <4 x i32> [[TMP27]], i32 553734060, i64 3
+; CHECK-NEXT: [[TMP29:%.*]] = call ptr addrspace(7) @lgc.buffer.desc.to.ptr(<4 x i32> [[TMP28]])
+; CHECK-NEXT: [[TMP30:%.*]] = insertelement <2 x i32> [[TMP14]], i32 [[USERDATA0]], i64 0
+; CHECK-NEXT: [[TMP31:%.*]] = bitcast <2 x i32> [[TMP30]] to i64
+; CHECK-NEXT: [[TMP32:%.*]] = inttoptr i64 [[TMP31]] to ptr addrspace(4)
+; CHECK-NEXT: [[TMP33:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP32]], i32 32
+; CHECK-NEXT: [[TMP34:%.*]] = load <4 x i32>, ptr addrspace(4) [[TMP33]], align 16
+; CHECK-NEXT: [[TMP35:%.*]] = call ptr addrspace(7) @lgc.buffer.desc.to.ptr(<4 x i32> [[TMP34]])
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr addrspace(5) null, i32 [[TMP9]]
+; CHECK-NEXT: store ptr addrspace(7) [[TMP35]], ptr addrspace(5) [[TMP36]], align 32
+; CHECK-NEXT: [[TMP37:%.*]] = insertelement <2 x i32> [[TMP12]], i32 [[USERDATA0]], i64 0
+; CHECK-NEXT: [[TMP38:%.*]] = bitcast <2 x i32> [[TMP37]] to i64
+; CHECK-NEXT: [[TMP39:%.*]] = inttoptr i64 [[TMP38]] to ptr addrspace(4)
+; CHECK-NEXT: [[TMP40:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP39]], i32 48
+; CHECK-NEXT: [[TMP41:%.*]] = load <4 x i32>, ptr addrspace(4) [[TMP40]], align 16
+; CHECK-NEXT: [[TMP42:%.*]] = call ptr addrspace(7) @lgc.buffer.desc.to.ptr(<4 x i32> [[TMP41]])
+; CHECK-NEXT: [[TMP43:%.*]] = add i32 [[TMP9]], 32
+; CHECK-NEXT: [[TMP44:%.*]] = getelementptr i8, ptr addrspace(5) null, i32 [[TMP43]]
+; CHECK-NEXT: store ptr addrspace(7) [[TMP42]], ptr addrspace(5) [[TMP44]], align 32
+; CHECK-NEXT: [[TMP45:%.*]] = load volatile i32, ptr addrspace(7) [[TMP42]], align 4
+; CHECK-NEXT: [[TMP46:%.*]] = add i32 [[TMP9]], 64
+; CHECK-NEXT: [[TMP47:%.*]] = getelementptr i8, ptr addrspace(5) null, i32 [[TMP46]]
+; CHECK-NEXT: store i32 [[TMP45]], ptr addrspace(5) [[TMP47]], align 4
+; CHECK-NEXT: [[TMP48:%.*]] = add i32 [[TMP45]], -37
+; CHECK-NEXT: [[TMP49:%.*]] = getelementptr inbounds i8, ptr addrspace(7) [[TMP29]], i32 52
+; CHECK-NEXT: [[TMP50:%.*]] = load i64, ptr addrspace(7) [[TMP49]], align 8
+; CHECK-NEXT: [[TMP51:%.*]] = getelementptr inbounds i8, ptr addrspace(7) [[TMP29]], i32 60
+; CHECK-NEXT: [[TMP52:%.*]] = load i32, ptr addrspace(7) [[TMP51]], align 4
+; CHECK-NEXT: [[TMP53:%.*]] = mul i32 [[TMP48]], [[TMP52]]
+; CHECK-NEXT: [[TMP54:%.*]] = inttoptr i64 [[TMP50]] to ptr addrspace(1)
+; CHECK-NEXT: [[TMP55:%.*]] = sext i32 [[TMP53]] to i64
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr addrspace(1) [[TMP54]], i64 [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = load i64, ptr addrspace(1) [[TMP56]], align 8
+; CHECK-NEXT: [[TMP58:%.*]] = inttoptr i64 [[TMP57]] to ptr
+; CHECK-NEXT: [[TMP59:%.*]] = ptrtoint ptr [[TMP58]] to i32
+; CHECK-NEXT: [[TMP60:%.*]] = or i32 [[TMP59]], 1
+; CHECK-NEXT: [[TMP61:%.*]] = inttoptr i32 [[TMP60]] to ptr
+; CHECK-NEXT: [[TMP62:%.*]] = load i32, ptr addrspace(5) [[TMP0]], align 4
+; CHECK-NEXT: [[TMP63:%.*]] = inttoptr i32 [[TMP62]] to ptr addrspace(5)
; CHECK-NEXT: br label [[TAIL_BLOCK:%.*]]
; CHECK: tail.block:
-; CHECK-NEXT: [[TMP60:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32, i32 } poison, <3 x i32> [[LOCALINVOCATIONID]], 0
-; CHECK-NEXT: [[TMP61:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32, i32 } [[TMP60]], i32 [[TMP57]], 1
-; CHECK-NEXT: [[TMP62:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32, i32 } [[TMP61]], ptr addrspace(5) [[TMP59]], 2
-; CHECK-NEXT: [[TMP63:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32, i32 } [[TMP62]], i32 ptrtoint (ptr @_rgen_1.resume.0 to i32), 3
-; CHECK-NEXT: [[TMP64:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32, i32 } [[TMP63]], i32 undef, 4
-; CHECK-NEXT: [[TMP65:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32, i32 } [[TMP64]], i32 [[TMP45]], 5
-; CHECK-NEXT: [[TMP66:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
-; CHECK-NEXT: [[TMP67:%.*]] = bitcast i64 [[TMP66]] to <2 x i32>
-; CHECK-NEXT: [[TMP68:%.*]] = extractelement <2 x i32> [[TMP67]], i64 0
-; CHECK-NEXT: [[TMP69:%.*]] = extractelement <2 x i32> [[TMP67]], i64 1
-; CHECK-NEXT: [[TMP70:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 0
-; CHECK-NEXT: [[TMP71:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 1
-; CHECK-NEXT: [[TMP72:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 2
-; CHECK-NEXT: [[TMP73:%.*]] = insertelement <20 x i32> poison, i32 [[GLOBALTABLE]], i64 0
-; CHECK-NEXT: [[TMP74:%.*]] = insertelement <20 x i32> [[TMP73]], i32 [[TMP68]], i64 1
-; CHECK-NEXT: [[TMP75:%.*]] = insertelement <20 x i32> [[TMP74]], i32 [[TMP69]], i64 2
-; CHECK-NEXT: [[TMP76:%.*]] = insertelement <20 x i32> [[TMP75]], i32 [[USERDATA0]], i64 3
-; CHECK-NEXT: [[TMP77:%.*]] = insertelement <20 x i32> [[TMP76]], i32 [[USERDATA1]], i64 4
-; CHECK-NEXT: [[TMP78:%.*]] = insertelement <20 x i32> [[TMP77]], i32 [[USERDATA2]], i64 5
-; CHECK-NEXT: [[TMP79:%.*]] = insertelement <20 x i32> [[TMP78]], i32 [[USERDATA3]], i64 6
-; CHECK-NEXT: [[TMP80:%.*]] = insertelement <20 x i32> [[TMP79]], i32 [[USERDATA4]], i64 7
-; CHECK-NEXT: [[TMP81:%.*]] = insertelement <20 x i32> [[TMP80]], i32 [[USERDATA5]], i64 8
-; CHECK-NEXT: [[TMP82:%.*]] = insertelement <20 x i32> [[TMP81]], i32 [[PAD6]], i64 9
-; CHECK-NEXT: [[TMP83:%.*]] = insertelement <20 x i32> [[TMP82]], i32 [[PAD7]], i64 10
-; CHECK-NEXT: [[TMP84:%.*]] = insertelement <20 x i32> [[TMP83]], i32 [[PAD8]], i64 11
-; CHECK-NEXT: [[TMP85:%.*]] = insertelement <20 x i32> [[TMP84]], i32 [[PAD9]], i64 12
-; CHECK-NEXT: [[TMP86:%.*]] = insertelement <20 x i32> [[TMP85]], i32 [[PAD10]], i64 13
-; CHECK-NEXT: [[TMP87:%.*]] = insertelement <20 x i32> [[TMP86]], i32 [[PAD11]], i64 14
-; CHECK-NEXT: [[TMP88:%.*]] = insertelement <20 x i32> [[TMP87]], i32 [[SPILLTABLE]], i64 15
-; CHECK-NEXT: [[TMP89:%.*]] = insertelement <20 x i32> [[TMP88]], i32 [[TMP70]], i64 16
-; CHECK-NEXT: [[TMP90:%.*]] = insertelement <20 x i32> [[TMP89]], i32 [[TMP71]], i64 17
-; CHECK-NEXT: [[TMP91:%.*]] = insertelement <20 x i32> [[TMP90]], i32 [[TMP72]], i64 18
-; CHECK-NEXT: [[TMP92:%.*]] = insertelement <20 x i32> [[TMP91]], i32 [[MULTIDISPATCHINFO]], i64 19
-; CHECK-NEXT: [[TMP93:%.*]] = extractvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32, i32 } [[TMP65]], 1
-; CHECK-NEXT: [[TMP94:%.*]] = call i32 @llvm.amdgcn.set.inactive.{{(chain.arg.)?}}i32(i32 [[TMP93]], i32 [[VCR]])
-; CHECK-NEXT: [[TMP95:%.*]] = icmp ne i32 [[TMP94]], 0
-; CHECK-NEXT: [[TMP96:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP95]])
-; CHECK-NEXT: [[TMP97:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP96]], i1 true)
-; CHECK-NEXT: [[TMP98:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP94]], i32 [[TMP97]])
-; CHECK-NEXT: [[TMP99:%.*]] = icmp eq i32 [[TMP94]], [[TMP98]]
-; CHECK-NEXT: [[TMP100:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP99]])
-; CHECK-NEXT: [[TMP101:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP98]])
-; CHECK-NEXT: [[TMP102:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP100]])
-; CHECK-NEXT: [[TMP103:%.*]] = and i32 [[TMP101]], -64
-; CHECK-NEXT: [[TMP104:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP103]], i64 0
-; CHECK-NEXT: [[TMP105:%.*]] = bitcast <2 x i32> [[TMP104]] to i64
-; CHECK-NEXT: [[TMP106:%.*]] = inttoptr i64 [[TMP105]] to ptr
-; CHECK-NEXT: call void (ptr, i32, <20 x i32>, { <3 x i32>, i32, ptr addrspace(5), i32, i32, i32 }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v20i32.sl_v3i32i32p5i32i32i32s(ptr inreg [[TMP106]], i32 inreg [[TMP102]], <20 x i32> inreg [[TMP92]], { <3 x i32>, i32, ptr addrspace(5), i32, i32, i32 } [[TMP65]], i32 0)
+; CHECK-NEXT: [[TMP64:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32, i32 } poison, <3 x i32> [[LOCALINVOCATIONID]], 0
+; CHECK-NEXT: [[TMP65:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32, i32 } [[TMP64]], i32 [[TMP60]], 1
+; CHECK-NEXT: [[TMP66:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32, i32 } [[TMP65]], ptr addrspace(5) [[TMP63]], 2
+; CHECK-NEXT: [[TMP67:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32, i32 } [[TMP66]], i32 ptrtoint (ptr @_rgen_1.resume.0 to i32), 3
+; CHECK-NEXT: [[TMP68:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32, i32 } [[TMP67]], i32 undef, 4
+; CHECK-NEXT: [[TMP69:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32, i32 } [[TMP68]], i32 [[TMP48]], 5
+; CHECK-NEXT: [[TMP70:%.*]] = extractvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32, i32 } [[TMP69]], 1
+; CHECK-NEXT: [[TMP71:%.*]] = call i32 @llvm.amdgcn.set.inactive.chain.arg.i32(i32 [[TMP70]], i32 [[VCR]])
+; CHECK-NEXT: [[TMP72:%.*]] = icmp ne i32 [[TMP71]], 0
+; CHECK-NEXT: [[TMP73:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP72]])
+; CHECK-NEXT: [[TMP74:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP73]], i1 true)
+; CHECK-NEXT: [[TMP75:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP71]], i32 [[TMP74]])
+; CHECK-NEXT: [[TMP76:%.*]] = icmp eq i32 [[TMP71]], [[TMP75]]
+; CHECK-NEXT: [[TMP77:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP76]])
+; CHECK-NEXT: [[TMP78:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP75]])
+; CHECK-NEXT: [[TMP79:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP77]])
+; CHECK-NEXT: [[TMP80:%.*]] = and i32 [[TMP78]], -64
+; CHECK-NEXT: [[TMP81:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP80]], i64 0
+; CHECK-NEXT: [[TMP82:%.*]] = bitcast <2 x i32> [[TMP81]] to i64
+; CHECK-NEXT: [[TMP83:%.*]] = inttoptr i64 [[TMP82]] to ptr
+; CHECK-NEXT: [[TMP84:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
+; CHECK-NEXT: [[TMP85:%.*]] = bitcast i64 [[TMP84]] to <2 x i32>
+; CHECK-NEXT: [[TMP86:%.*]] = extractelement <2 x i32> [[TMP85]], i64 0
+; CHECK-NEXT: [[TMP87:%.*]] = extractelement <2 x i32> [[TMP85]], i64 1
+; CHECK-NEXT: [[TMP88:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 0
+; CHECK-NEXT: [[TMP89:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 1
+; CHECK-NEXT: [[TMP90:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 2
+; CHECK-NEXT: [[TMP91:%.*]] = insertelement <20 x i32> poison, i32 [[GLOBALTABLE]], i64 0
+; CHECK-NEXT: [[TMP92:%.*]] = insertelement <20 x i32> [[TMP91]], i32 [[TMP86]], i64 1
+; CHECK-NEXT: [[TMP93:%.*]] = insertelement <20 x i32> [[TMP92]], i32 [[TMP87]], i64 2
+; CHECK-NEXT: [[TMP94:%.*]] = insertelement <20 x i32> [[TMP93]], i32 [[USERDATA0]], i64 3
+; CHECK-NEXT: [[TMP95:%.*]] = insertelement <20 x i32> [[TMP94]], i32 [[USERDATA1]], i64 4
+; CHECK-NEXT: [[TMP96:%.*]] = insertelement <20 x i32> [[TMP95]], i32 [[USERDATA2]], i64 5
+; CHECK-NEXT: [[TMP97:%.*]] = insertelement <20 x i32> [[TMP96]], i32 [[USERDATA3]], i64 6
+; CHECK-NEXT: [[TMP98:%.*]] = insertelement <20 x i32> [[TMP97]], i32 [[USERDATA4]], i64 7
+; CHECK-NEXT: [[TMP99:%.*]] = insertelement <20 x i32> [[TMP98]], i32 [[USERDATA5]], i64 8
+; CHECK-NEXT: [[TMP100:%.*]] = insertelement <20 x i32> [[TMP99]], i32 [[PAD6]], i64 9
+; CHECK-NEXT: [[TMP101:%.*]] = insertelement <20 x i32> [[TMP100]], i32 [[PAD7]], i64 10
+; CHECK-NEXT: [[TMP102:%.*]] = insertelement <20 x i32> [[TMP101]], i32 [[PAD8]], i64 11
+; CHECK-NEXT: [[TMP103:%.*]] = insertelement <20 x i32> [[TMP102]], i32 [[PAD9]], i64 12
+; CHECK-NEXT: [[TMP104:%.*]] = insertelement <20 x i32> [[TMP103]], i32 [[PAD10]], i64 13
+; CHECK-NEXT: [[TMP105:%.*]] = insertelement <20 x i32> [[TMP104]], i32 [[PAD11]], i64 14
+; CHECK-NEXT: [[TMP106:%.*]] = insertelement <20 x i32> [[TMP105]], i32 [[SPILLTABLE]], i64 15
+; CHECK-NEXT: [[TMP107:%.*]] = insertelement <20 x i32> [[TMP106]], i32 [[TMP88]], i64 16
+; CHECK-NEXT: [[TMP108:%.*]] = insertelement <20 x i32> [[TMP107]], i32 [[TMP89]], i64 17
+; CHECK-NEXT: [[TMP109:%.*]] = insertelement <20 x i32> [[TMP108]], i32 [[TMP90]], i64 18
+; CHECK-NEXT: [[TMP110:%.*]] = insertelement <20 x i32> [[TMP109]], i32 [[MULTIDISPATCHINFO]], i64 19
+; CHECK-NEXT: call void (ptr, i32, <20 x i32>, { <3 x i32>, i32, ptr addrspace(5), i32, i32, i32 }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v20i32.sl_v3i32i32p5i32i32i32s(ptr inreg [[TMP83]], i32 inreg [[TMP79]], <20 x i32> inreg [[TMP110]], { <3 x i32>, i32, ptr addrspace(5), i32, i32, i32 } [[TMP69]], i32 0)
; CHECK-NEXT: unreachable
;
;
; CHECK-LABEL: define {{[^@]+}}@_rgen_1.resume.0
; CHECK-SAME: (i32 inreg [[GLOBALTABLE:%.*]], ptr addrspace(4) inreg [[NUMWORKGROUPSPTR:%.*]], i32 inreg [[USERDATA0:%.*]], i32 inreg [[USERDATA1:%.*]], i32 inreg [[USERDATA2:%.*]], i32 inreg [[USERDATA3:%.*]], i32 inreg [[USERDATA4:%.*]], i32 inreg [[USERDATA5:%.*]], i32 inreg [[PAD6:%.*]], i32 inreg [[PAD7:%.*]], i32 inreg [[PAD8:%.*]], i32 inreg [[PAD9:%.*]], i32 inreg [[PAD10:%.*]], i32 inreg [[PAD11:%.*]], i32 inreg [[SPILLTABLE:%.*]], <3 x i32> inreg [[WORKGROUPID:%.*]], i32 inreg [[MULTIDISPATCHINFO:%.*]], <3 x i32> [[LOCALINVOCATIONID:%.*]], i32 [[VCR:%.*]], ptr addrspace(5) [[VSP:%.*]], i32 [[TMP0:%.*]], [1 x i32] [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] align 64 !spirv.ExecutionModel !15 !lgc.shaderstage !16 !continufy.stage !17 !continuation !18 !lgc.cps !17 {
; CHECK-NEXT: entryresume.0:
-; CHECK-NEXT: [[TMP2:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+; CHECK-NEXT: [[TMP2:%.*]] = alloca i32, align 4, addrspace(5)
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.s.getpc()
; CHECK-NEXT: [[TMP4:%.*]] = bitcast i64 [[TMP3]] to <2 x i32>
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> [[TMP4]], i32 [[SPILLTABLE]], i64 0
@@ -272,69 +279,76 @@ attributes #7 = { nounwind willreturn memory(inaccessiblemem: read) }
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr addrspace(4)
; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.amdgcn.s.getpc()
; CHECK-NEXT: [[TMP9:%.*]] = bitcast i64 [[TMP8]] to <2 x i32>
-; CHECK-NEXT: store ptr addrspace(5) [[VSP]], ptr addrspace(5) [[TMP2]], align 4
-; CHECK-NEXT: [[TMP10:%.*]] = load ptr addrspace(5), ptr addrspace(5) [[TMP2]], align 4
-; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr addrspace(5) [[TMP10]], i32 -96
-; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[_RGEN_1_FRAME:%.*]], ptr addrspace(5) [[TMP11]], i32 0, i32 2
-; CHECK-NEXT: [[DOTRELOAD6:%.*]] = load i32, ptr addrspace(5) [[TMP12]], align 4
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[_RGEN_1_FRAME]], ptr addrspace(5) [[TMP11]], i32 0, i32 1
-; CHECK-NEXT: [[DOTRELOAD3:%.*]] = load ptr addrspace(7), ptr addrspace(5) [[TMP13]], align 32
-; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[_RGEN_1_FRAME]], ptr addrspace(5) [[TMP11]], i32 0, i32 0
-; CHECK-NEXT: [[DOTRELOAD:%.*]] = load ptr addrspace(7), ptr addrspace(5) [[TMP14]], align 32
-; CHECK-NEXT: [[TMP15:%.*]] = load volatile i32, ptr addrspace(7) [[DOTRELOAD3]], align 4
-; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[DOTRELOAD6]], [[TMP15]]
-; CHECK-NEXT: [[TMP17:%.*]] = zext i1 [[TMP16]] to i32
-; CHECK-NEXT: store i32 [[TMP17]], ptr addrspace(7) [[DOTRELOAD]], align 4
+; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr addrspace(5) [[VSP]] to i32
+; CHECK-NEXT: store i32 [[TMP10]], ptr addrspace(5) [[TMP2]], align 4
+; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(5) [[TMP2]], align 4
+; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], -96
+; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[TMP12]], 64
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr addrspace(5) null, i32 [[TMP13]]
+; CHECK-NEXT: [[DOTRELOAD6:%.*]] = load i32, ptr addrspace(5) [[TMP14]], align 4
+; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP12]], 32
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr addrspace(5) null, i32 [[TMP15]]
+; CHECK-NEXT: [[DOTRELOAD3:%.*]] = load ptr addrspace(7), ptr addrspace(5) [[TMP16]], align 32
+; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr addrspace(5) null, i32 [[TMP12]]
+; CHECK-NEXT: [[DOTRELOAD:%.*]] = load ptr addrspace(7), ptr addrspace(5) [[TMP17]], align 32
+; CHECK-NEXT: [[TMP18:%.*]] = mul i32 [[USERDATA5]], 96
+; CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP12]], [[TMP18]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr addrspace(5) null, i32 [[TMP19]]
+; CHECK-NEXT: [[DUMMY_RELOAD:%.*]] = load ptr addrspace(7), ptr addrspace(5) [[TMP20]], align 32
+; CHECK-NEXT: [[TMP21:%.*]] = load volatile i32, ptr addrspace(7) [[DOTRELOAD3]], align 4
+; CHECK-NEXT: [[TMP22:%.*]] = icmp eq i32 [[DOTRELOAD6]], [[TMP21]]
+; CHECK-NEXT: [[TMP23:%.*]] = zext i1 [[TMP22]] to i32
+; CHECK-NEXT: store i32 [[TMP23]], ptr addrspace(7) [[DOTRELOAD]], align 4
; CHECK-NEXT: br label [[TAIL_BLOCK:%.*]]
; CHECK: tail.block:
-; CHECK-NEXT: [[TMP18:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5) } poison, <3 x i32> [[LOCALINVOCATIONID]], 0
-; CHECK-NEXT: [[TMP19:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5) } [[TMP18]], i32 0, 1
-; CHECK-NEXT: [[TMP20:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5) } [[TMP19]], ptr addrspace(5) poison, 2
-; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
-; CHECK-NEXT: [[TMP22:%.*]] = bitcast i64 [[TMP21]] to <2 x i32>
-; CHECK-NEXT: [[TMP23:%.*]] = extractelement <2 x i32> [[TMP22]], i64 0
-; CHECK-NEXT: [[TMP24:%.*]] = extractelement <2 x i32> [[TMP22]], i64 1
-; CHECK-NEXT: [[TMP25:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 0
-; CHECK-NEXT: [[TMP26:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 1
-; CHECK-NEXT: [[TMP27:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 2
-; CHECK-NEXT: [[TMP28:%.*]] = insertelement <20 x i32> poison, i32 [[GLOBALTABLE]], i64 0
-; CHECK-NEXT: [[TMP29:%.*]] = insertelement <20 x i32> [[TMP28]], i32 [[TMP23]], i64 1
-; CHECK-NEXT: [[TMP30:%.*]] = insertelement <20 x i32> [[TMP29]], i32 [[TMP24]], i64 2
-; CHECK-NEXT: [[TMP31:%.*]] = insertelement <20 x i32> [[TMP30]], i32 [[USERDATA0]], i64 3
-; CHECK-NEXT: [[TMP32:%.*]] = insertelement <20 x i32> [[TMP31]], i32 [[USERDATA1]], i64 4
-; CHECK-NEXT: [[TMP33:%.*]] = insertelement <20 x i32> [[TMP32]], i32 [[USERDATA2]], i64 5
-; CHECK-NEXT: [[TMP34:%.*]] = insertelement <20 x i32> [[TMP33]], i32 [[USERDATA3]], i64 6
-; CHECK-NEXT: [[TMP35:%.*]] = insertelement <20 x i32> [[TMP34]], i32 [[USERDATA4]], i64 7
-; CHECK-NEXT: [[TMP36:%.*]] = insertelement <20 x i32> [[TMP35]], i32 [[USERDATA5]], i64 8
-; CHECK-NEXT: [[TMP37:%.*]] = insertelement <20 x i32> [[TMP36]], i32 [[PAD6]], i64 9
-; CHECK-NEXT: [[TMP38:%.*]] = insertelement <20 x i32> [[TMP37]], i32 [[PAD7]], i64 10
-; CHECK-NEXT: [[TMP39:%.*]] = insertelement <20 x i32> [[TMP38]], i32 [[PAD8]], i64 11
-; CHECK-NEXT: [[TMP40:%.*]] = insertelement <20 x i32> [[TMP39]], i32 [[PAD9]], i64 12
-; CHECK-NEXT: [[TMP41:%.*]] = insertelement <20 x i32> [[TMP40]], i32 [[PAD10]], i64 13
-; CHECK-NEXT: [[TMP42:%.*]] = insertelement <20 x i32> [[TMP41]], i32 [[PAD11]], i64 14
-; CHECK-NEXT: [[TMP43:%.*]] = insertelement <20 x i32> [[TMP42]], i32 [[SPILLTABLE]], i64 15
-; CHECK-NEXT: [[TMP44:%.*]] = insertelement <20 x i32> [[TMP43]], i32 [[TMP25]], i64 16
-; CHECK-NEXT: [[TMP45:%.*]] = insertelement <20 x i32> [[TMP44]], i32 [[TMP26]], i64 17
-; CHECK-NEXT: [[TMP46:%.*]] = insertelement <20 x i32> [[TMP45]], i32 [[TMP27]], i64 18
-; CHECK-NEXT: [[TMP47:%.*]] = insertelement <20 x i32> [[TMP46]], i32 [[MULTIDISPATCHINFO]], i64 19
-; CHECK-NEXT: [[TMP48:%.*]] = extractvalue { <3 x i32>, i32, ptr addrspace(5) } [[TMP20]], 1
-; CHECK-NEXT: [[TMP49:%.*]] = call i32 @llvm.amdgcn.set.inactive.{{(chain.arg.)?}}i32(i32 [[TMP48]], i32 [[VCR]])
-; CHECK-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0
-; CHECK-NEXT: [[TMP51:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP50]])
-; CHECK-NEXT: [[TMP52:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP51]], i1 true)
-; CHECK-NEXT: [[TMP53:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP49]], i32 [[TMP52]])
-; CHECK-NEXT: [[TMP54:%.*]] = icmp eq i32 [[TMP49]], [[TMP53]]
-; CHECK-NEXT: [[TMP55:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP54]])
-; CHECK-NEXT: [[TMP56:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP53]])
-; CHECK-NEXT: [[TMP57:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP55]])
-; CHECK-NEXT: [[TMP58:%.*]] = icmp eq i32 [[TMP56]], 0
-; CHECK-NEXT: br i1 [[TMP58]], label [[RET_BLOCK:%.*]], label [[CHAIN_BLOCK:%.*]]
+; CHECK-NEXT: [[TMP24:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5) } poison, <3 x i32> [[LOCALINVOCATIONID]], 0
+; CHECK-NEXT: [[TMP25:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5) } [[TMP24]], i32 0, 1
+; CHECK-NEXT: [[TMP26:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5) } [[TMP25]], ptr addrspace(5) poison, 2
+; CHECK-NEXT: [[TMP27:%.*]] = extractvalue { <3 x i32>, i32, ptr addrspace(5) } [[TMP26]], 1
+; CHECK-NEXT: [[TMP28:%.*]] = call i32 @llvm.amdgcn.set.inactive.chain.arg.i32(i32 [[TMP27]], i32 [[VCR]])
+; CHECK-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
+; CHECK-NEXT: [[TMP30:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP29]])
+; CHECK-NEXT: [[TMP31:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP30]], i1 true)
+; CHECK-NEXT: [[TMP32:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP28]], i32 [[TMP31]])
+; CHECK-NEXT: [[TMP33:%.*]] = icmp eq i32 [[TMP28]], [[TMP32]]
+; CHECK-NEXT: [[TMP34:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP33]])
+; CHECK-NEXT: [[TMP35:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP32]])
+; CHECK-NEXT: [[TMP36:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP34]])
+; CHECK-NEXT: [[TMP37:%.*]] = icmp eq i32 [[TMP35]], 0
+; CHECK-NEXT: br i1 [[TMP37]], label [[RET_BLOCK:%.*]], label [[CHAIN_BLOCK:%.*]]
; CHECK: chain.block:
-; CHECK-NEXT: [[TMP59:%.*]] = and i32 [[TMP56]], -64
-; CHECK-NEXT: [[TMP60:%.*]] = insertelement <2 x i32> [[TMP9]], i32 [[TMP59]], i64 0
-; CHECK-NEXT: [[TMP61:%.*]] = bitcast <2 x i32> [[TMP60]] to i64
-; CHECK-NEXT: [[TMP62:%.*]] = inttoptr i64 [[TMP61]] to ptr
-; CHECK-NEXT: call void (ptr, i32, <20 x i32>, { <3 x i32>, i32, ptr addrspace(5) }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v20i32.sl_v3i32i32p5s(ptr inreg [[TMP62]], i32 inreg [[TMP57]], <20 x i32> inreg [[TMP47]], { <3 x i32>, i32, ptr addrspace(5) } [[TMP20]], i32 0)
+; CHECK-NEXT: [[TMP38:%.*]] = and i32 [[TMP35]], -64
+; CHECK-NEXT: [[TMP39:%.*]] = insertelement <2 x i32> [[TMP9]], i32 [[TMP38]], i64 0
+; CHECK-NEXT: [[TMP40:%.*]] = bitcast <2 x i32> [[TMP39]] to i64
+; CHECK-NEXT: [[TMP41:%.*]] = inttoptr i64 [[TMP40]] to ptr
+; CHECK-NEXT: [[TMP42:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
+; CHECK-NEXT: [[TMP43:%.*]] = bitcast i64 [[TMP42]] to <2 x i32>
+; CHECK-NEXT: [[TMP44:%.*]] = extractelement <2 x i32> [[TMP43]], i64 0
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <2 x i32> [[TMP43]], i64 1
+; CHECK-NEXT: [[TMP46:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 0
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 1
+; CHECK-NEXT: [[TMP48:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 2
+; CHECK-NEXT: [[TMP49:%.*]] = insertelement <20 x i32> poison, i32 [[GLOBALTABLE]], i64 0
+; CHECK-NEXT: [[TMP50:%.*]] = insertelement <20 x i32> [[TMP49]], i32 [[TMP44]], i64 1
+; CHECK-NEXT: [[TMP51:%.*]] = insertelement <20 x i32> [[TMP50]], i32 [[TMP45]], i64 2
+; CHECK-NEXT: [[TMP52:%.*]] = insertelement <20 x i32> [[TMP51]], i32 [[USERDATA0]], i64 3
+; CHECK-NEXT: [[TMP53:%.*]] = insertelement <20 x i32> [[TMP52]], i32 [[USERDATA1]], i64 4
+; CHECK-NEXT: [[TMP54:%.*]] = insertelement <20 x i32> [[TMP53]], i32 [[USERDATA2]], i64 5
+; CHECK-NEXT: [[TMP55:%.*]] = insertelement <20 x i32> [[TMP54]], i32 [[USERDATA3]], i64 6
+; CHECK-NEXT: [[TMP56:%.*]] = insertelement <20 x i32> [[TMP55]], i32 [[USERDATA4]], i64 7
+; CHECK-NEXT: [[TMP57:%.*]] = insertelement <20 x i32> [[TMP56]], i32 [[USERDATA5]], i64 8
+; CHECK-NEXT: [[TMP58:%.*]] = insertelement <20 x i32> [[TMP57]], i32 [[PAD6]], i64 9
+; CHECK-NEXT: [[TMP59:%.*]] = insertelement <20 x i32> [[TMP58]], i32 [[PAD7]], i64 10
+; CHECK-NEXT: [[TMP60:%.*]] = insertelement <20 x i32> [[TMP59]], i32 [[PAD8]], i64 11
+; CHECK-NEXT: [[TMP61:%.*]] = insertelement <20 x i32> [[TMP60]], i32 [[PAD9]], i64 12
+; CHECK-NEXT: [[TMP62:%.*]] = insertelement <20 x i32> [[TMP61]], i32 [[PAD10]], i64 13
+; CHECK-NEXT: [[TMP63:%.*]] = insertelement <20 x i32> [[TMP62]], i32 [[PAD11]], i64 14
+; CHECK-NEXT: [[TMP64:%.*]] = insertelement <20 x i32> [[TMP63]], i32 [[SPILLTABLE]], i64 15
+; CHECK-NEXT: [[TMP65:%.*]] = insertelement <20 x i32> [[TMP64]], i32 [[TMP46]], i64 16
+; CHECK-NEXT: [[TMP66:%.*]] = insertelement <20 x i32> [[TMP65]], i32 [[TMP47]], i64 17
+; CHECK-NEXT: [[TMP67:%.*]] = insertelement <20 x i32> [[TMP66]], i32 [[TMP48]], i64 18
+; CHECK-NEXT: [[TMP68:%.*]] = insertelement <20 x i32> [[TMP67]], i32 [[MULTIDISPATCHINFO]], i64 19
+; CHECK-NEXT: call void (ptr, i32, <20 x i32>, { <3 x i32>, i32, ptr addrspace(5) }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v20i32.sl_v3i32i32p5s(ptr inreg [[TMP41]], i32 inreg [[TMP36]], <20 x i32> inreg [[TMP68]], { <3 x i32>, i32, ptr addrspace(5) } [[TMP26]], i32 0)
; CHECK-NEXT: unreachable
; CHECK: ret.block:
; CHECK-NEXT: ret void
diff --git a/lgc/test/Transforms/CpsLowering/cps-stack-lowering.lgc b/lgc/test/Transforms/CpsLowering/cps-stack-lowering.lgc
index 5a24d312f1..ed1fcb50dc 100644
--- a/lgc/test/Transforms/CpsLowering/cps-stack-lowering.lgc
+++ b/lgc/test/Transforms/CpsLowering/cps-stack-lowering.lgc
@@ -6,6 +6,10 @@ declare ptr addrspace(32) @lgc.cps.alloc(i32)
declare void @lgc.cps.free(i32)
declare i32 @lgc.cps.as.continuation.reference(ptr)
declare ptr addrspace(32) @lgc.cps.peek(i32)
+declare ptr addrspace(32) @lgc.cps.get.vsp()
+declare i32 @lgc.cps.get.dummy.index(i32)
+
+%_rgen_1.Frame = type { ptr addrspace(5), ptr addrspace(5), i32 }
define void @test.0({} %unused) !lgc.cps !{i32 1} !lgc.shaderstage !{i32 7} {
%mem = call ptr addrspace(32) @lgc.cps.alloc(i32 10) ; round up to 12 during lowering
@@ -47,9 +51,54 @@ define void @test.2({ ptr addrspace(32) } %state) !lgc.cps !{i32 1} !lgc.shaders
call void @lgc.cps.free(i32 10) ; round up to 12 during lowering
ret void
}
+
+; Dummy test to show behavior with lowering of non-constant GEP indices.
+define void @test.gep({} %unused) !lgc.cps !{i32 1} !lgc.shaderstage !{i32 7} {
+ %mem = call ptr addrspace(32) @lgc.cps.alloc(i32 10) ; round up to 12 during lowering
+
+ %stack.el0 = call i32 @lgc.cps.get.dummy.index(i32 0)
+ %1 = getelementptr inbounds %_rgen_1.Frame, ptr addrspace(32) %mem, i32 %stack.el0
+ %vsp = call ptr addrspace(32) @lgc.cps.get.vsp()
+ %vsp.i = ptrtoint ptr addrspace(32) %vsp to i32
+ store i32 %vsp.i, ptr addrspace(32) %1
+
+ %stack.el1 = call i32 @lgc.cps.get.dummy.index(i32 1)
+ %2 = getelementptr inbounds %_rgen_1.Frame, ptr addrspace(32) %mem, i32 %stack.el1
+ %vsp.2 = call ptr addrspace(32) @lgc.cps.peek(i32 4)
+ %vsp.2.i = ptrtoint ptr addrspace(32) %vsp.2 to i32
+ store i32 %vsp.2.i, ptr addrspace(32) %2
+
+ %stack.el2 = call i32 @lgc.cps.get.dummy.index(i32 2)
+ %stack.el2.div = sdiv i32 %stack.el2, 2
+ %3 = getelementptr inbounds %_rgen_1.Frame, ptr addrspace(32) %mem, i32 %stack.el2.div, i32 1
+ %vsp.3 = call ptr addrspace(32) @lgc.cps.peek(i32 8)
+ %vsp.3.i = ptrtoint ptr addrspace(32) %vsp.3 to i32
+ store i32 %vsp.3.i, ptr addrspace(32) %3
+
+ %cr = call i32 @lgc.cps.as.continuation.reference(ptr @test.1)
+ call void (...) @lgc.cps.jump(i32 %cr, i32 2, {} poison, ptr addrspace(32) %vsp.3, i32 %vsp.3.i)
+ unreachable
+}
+
+; Dummy test to show behavior with lowering of nested GEPs.
+define void @test.nested.gep({} %unused) !lgc.cps !{i32 1} !lgc.shaderstage !{i32 7} {
+ %mem = call ptr addrspace(32) @lgc.cps.alloc(i32 10) ; round up to 12 during lowering
+
+ %stack.el0 = call i32 @lgc.cps.get.dummy.index(i32 0)
+ %gep.base = getelementptr inbounds %_rgen_1.Frame, ptr addrspace(32) %mem, i32 %stack.el0
+ %1 = getelementptr inbounds %_rgen_1.Frame, ptr addrspace(32) %gep.base, i32 0, i32 2
+ %vsp = call ptr addrspace(32) @lgc.cps.get.vsp()
+ %vsp.i = ptrtoint ptr addrspace(32) %vsp to i32
+ store i32 %vsp.i, ptr addrspace(32) %1
+
+ %cr = call i32 @lgc.cps.as.continuation.reference(ptr @test.1)
+ call void (...) @lgc.cps.jump(i32 %cr, i32 2, {} poison, ptr addrspace(32) %vsp, i32 %vsp.i)
+ unreachable
+}
+
; CHECK-LABEL: define {{[^@]+}}@test.0
-; CHECK-SAME: (i32 inreg [[GLOBALTABLE:%.*]], ptr addrspace(4) inreg [[NUMWORKGROUPSPTR:%.*]], i32 inreg [[PAD0:%.*]], i32 inreg [[PAD1:%.*]], i32 inreg [[PAD2:%.*]], i32 inreg [[PAD3:%.*]], i32 inreg [[PAD4:%.*]], i32 inreg [[PAD5:%.*]], i32 inreg [[PAD6:%.*]], i32 inreg [[PAD7:%.*]], i32 inreg [[PAD8:%.*]], i32 inreg [[PAD9:%.*]], i32 inreg [[PAD10:%.*]], i32 inreg [[PAD11:%.*]], i32 inreg [[SPILLTABLE:%.*]], i32 [[VCR:%.*]], ptr addrspace(5) [[VSP:%.*]]) #[[ATTR1:[0-9]+]] align 64 !lgc.cps !2 !lgc.shaderstage !3 {
-; CHECK-NEXT: [[TMP1:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+; CHECK-SAME: (i32 inreg [[GLOBALTABLE:%.*]], ptr addrspace(4) inreg [[NUMWORKGROUPSPTR:%.*]], i32 inreg [[PAD0:%.*]], i32 inreg [[PAD1:%.*]], i32 inreg [[PAD2:%.*]], i32 inreg [[PAD3:%.*]], i32 inreg [[PAD4:%.*]], i32 inreg [[PAD5:%.*]], i32 inreg [[PAD6:%.*]], i32 inreg [[PAD7:%.*]], i32 inreg [[PAD8:%.*]], i32 inreg [[PAD9:%.*]], i32 inreg [[PAD10:%.*]], i32 inreg [[PAD11:%.*]], i32 inreg [[SPILLTABLE:%.*]], <3 x i32> inreg [[WORKGROUPID:%.*]], i32 inreg [[MULTIDISPATCHINFO:%.*]], <3 x i32> [[LOCALINVOCATIONID:%.*]], i32 [[VCR:%.*]], ptr addrspace(5) [[VSP:%.*]]) #[[ATTR1:[0-9]+]] align 64 !lgc.cps !2 !lgc.shaderstage !3 {
+; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4, addrspace(5)
; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.amdgcn.s.getpc()
; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[TMP2]] to <2 x i32>
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[SPILLTABLE]], i64 0
@@ -57,67 +106,79 @@ define void @test.2({ ptr addrspace(32) } %state) !lgc.cps !{i32 1} !lgc.shaders
; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr addrspace(4)
; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.amdgcn.s.getpc()
; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[TMP7]] to <2 x i32>
-; CHECK-NEXT: store ptr addrspace(5) [[VSP]], ptr addrspace(5) [[TMP1]], align 4
-; CHECK-NEXT: [[TMP9:%.*]] = load ptr addrspace(5), ptr addrspace(5) [[TMP1]], align 4
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr addrspace(5) [[TMP9]], i32 12
-; CHECK-NEXT: store ptr addrspace(5) [[TMP10]], ptr addrspace(5) [[TMP1]], align 4
-; CHECK-NEXT: store i32 333, ptr addrspace(5) [[TMP9]], align 4
-; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr addrspace(5) [[TMP9]], i32 1
-; CHECK-NEXT: store i32 111, ptr addrspace(5) [[TMP11]], align 4
-; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr addrspace(5) [[TMP9]], i32 9
-; CHECK-NEXT: store i8 99, ptr addrspace(5) [[TMP12]], align 1
-; CHECK-NEXT: [[Q1:%.*]] = ptrtoint ptr addrspace(5) [[TMP11]] to i32
-; CHECK-NEXT: [[STATE:%.*]] = insertvalue { ptr addrspace(5) } poison, ptr addrspace(5) [[TMP12]], 0
-; CHECK-NEXT: [[TMP13:%.*]] = load ptr addrspace(5), ptr addrspace(5) [[TMP1]], align 4
-; CHECK-NEXT: store { ptr addrspace(5) } [[STATE]], ptr addrspace(5) [[TMP13]], align 4
-; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr addrspace(5) [[TMP13]], i32 4
-; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr addrspace(5) [[TMP12]] to i32
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr addrspace(5) [[VSP]] to i32
+; CHECK-NEXT: store i32 [[TMP9]], ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], 12
+; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr addrspace(5) null, i32 [[TMP10]]
+; CHECK-NEXT: store i32 333, ptr addrspace(5) [[TMP12]], align 4
+; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[TMP10]], 4
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr addrspace(5) null, i32 [[TMP13]]
+; CHECK-NEXT: store i32 111, ptr addrspace(5) [[TMP14]], align 4
+; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP10]], 9
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr addrspace(5) null, i32 [[TMP15]]
+; CHECK-NEXT: store i8 99, ptr addrspace(5) [[TMP16]], align 1
+; CHECK-NEXT: [[STATE:%.*]] = insertvalue { i32 } poison, i32 [[TMP15]], 0
+; CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i32 [[TMP17]] to ptr addrspace(5)
+; CHECK-NEXT: store { i32 } [[STATE]], ptr addrspace(5) [[TMP18]], align 4
+; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr addrspace(5) [[TMP18]], i32 4
; CHECK-NEXT: br label [[TAIL_BLOCK:%.*]]
; CHECK: tail.block:
-; CHECK-NEXT: [[TMP16:%.*]] = insertvalue { i32, ptr addrspace(5), i32, i32 } { i32 ptrtoint (ptr getelementptr (i8, ptr @test.1, i32 1) to i32), ptr addrspace(5) poison, i32 poison, i32 poison }, ptr addrspace(5) [[TMP14]], 1
-; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { i32, ptr addrspace(5), i32, i32 } [[TMP16]], i32 [[TMP15]], 2
-; CHECK-NEXT: [[TMP18:%.*]] = insertvalue { i32, ptr addrspace(5), i32, i32 } [[TMP17]], i32 [[Q1]], 3
-; CHECK-NEXT: [[TMP19:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
-; CHECK-NEXT: [[TMP20:%.*]] = bitcast i64 [[TMP19]] to <2 x i32>
-; CHECK-NEXT: [[TMP21:%.*]] = extractelement <2 x i32> [[TMP20]], i64 0
-; CHECK-NEXT: [[TMP22:%.*]] = extractelement <2 x i32> [[TMP20]], i64 1
-; CHECK-NEXT: [[TMP23:%.*]] = insertelement <16 x i32> poison, i32 [[GLOBALTABLE]], i64 0
-; CHECK-NEXT: [[TMP24:%.*]] = insertelement <16 x i32> [[TMP23]], i32 [[TMP21]], i64 1
-; CHECK-NEXT: [[TMP25:%.*]] = insertelement <16 x i32> [[TMP24]], i32 [[TMP22]], i64 2
-; CHECK-NEXT: [[TMP26:%.*]] = insertelement <16 x i32> [[TMP25]], i32 [[PAD0]], i64 3
-; CHECK-NEXT: [[TMP27:%.*]] = insertelement <16 x i32> [[TMP26]], i32 [[PAD1]], i64 4
-; CHECK-NEXT: [[TMP28:%.*]] = insertelement <16 x i32> [[TMP27]], i32 [[PAD2]], i64 5
-; CHECK-NEXT: [[TMP29:%.*]] = insertelement <16 x i32> [[TMP28]], i32 [[PAD3]], i64 6
-; CHECK-NEXT: [[TMP30:%.*]] = insertelement <16 x i32> [[TMP29]], i32 [[PAD4]], i64 7
-; CHECK-NEXT: [[TMP31:%.*]] = insertelement <16 x i32> [[TMP30]], i32 [[PAD5]], i64 8
-; CHECK-NEXT: [[TMP32:%.*]] = insertelement <16 x i32> [[TMP31]], i32 [[PAD6]], i64 9
-; CHECK-NEXT: [[TMP33:%.*]] = insertelement <16 x i32> [[TMP32]], i32 [[PAD7]], i64 10
-; CHECK-NEXT: [[TMP34:%.*]] = insertelement <16 x i32> [[TMP33]], i32 [[PAD8]], i64 11
-; CHECK-NEXT: [[TMP35:%.*]] = insertelement <16 x i32> [[TMP34]], i32 [[PAD9]], i64 12
-; CHECK-NEXT: [[TMP36:%.*]] = insertelement <16 x i32> [[TMP35]], i32 [[PAD10]], i64 13
-; CHECK-NEXT: [[TMP37:%.*]] = insertelement <16 x i32> [[TMP36]], i32 [[PAD11]], i64 14
-; CHECK-NEXT: [[TMP38:%.*]] = insertelement <16 x i32> [[TMP37]], i32 [[SPILLTABLE]], i64 15
-; CHECK-NEXT: [[TMP39:%.*]] = extractvalue { i32, ptr addrspace(5), i32, i32 } [[TMP18]], 0
-; CHECK-NEXT: [[TMP40:%.*]] = call i32 @llvm.amdgcn.set.inactive.{{(chain.arg.)?}}i32(i32 [[TMP39]], i32 [[VCR]])
-; CHECK-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
-; CHECK-NEXT: [[TMP42:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP41]])
-; CHECK-NEXT: [[TMP43:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP42]], i1 true)
-; CHECK-NEXT: [[TMP44:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP40]], i32 [[TMP43]])
-; CHECK-NEXT: [[TMP45:%.*]] = icmp eq i32 [[TMP40]], [[TMP44]]
-; CHECK-NEXT: [[TMP46:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP45]])
-; CHECK-NEXT: [[TMP47:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP44]])
-; CHECK-NEXT: [[TMP48:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP46]])
-; CHECK-NEXT: [[TMP49:%.*]] = and i32 [[TMP47]], -64
-; CHECK-NEXT: [[TMP50:%.*]] = insertelement <2 x i32> [[TMP8]], i32 [[TMP49]], i64 0
-; CHECK-NEXT: [[TMP51:%.*]] = bitcast <2 x i32> [[TMP50]] to i64
-; CHECK-NEXT: [[TMP52:%.*]] = inttoptr i64 [[TMP51]] to ptr
-; CHECK-NEXT: call void (ptr, i32, <16 x i32>, { i32, ptr addrspace(5), i32, i32 }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v16i32.sl_i32p5i32i32s(ptr inreg [[TMP52]], i32 inreg [[TMP48]], <16 x i32> inreg [[TMP38]], { i32, ptr addrspace(5), i32, i32 } [[TMP18]], i32 0)
+; CHECK-NEXT: [[TMP20:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } poison, <3 x i32> [[LOCALINVOCATIONID]], 0
+; CHECK-NEXT: [[TMP21:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP20]], i32 add (i32 ptrtoint (ptr @test.1 to i32), i32 1), 1
+; CHECK-NEXT: [[TMP22:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP21]], ptr addrspace(5) [[TMP19]], 2
+; CHECK-NEXT: [[TMP23:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP22]], i32 [[TMP15]], 3
+; CHECK-NEXT: [[TMP24:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP23]], i32 [[TMP13]], 4
+; CHECK-NEXT: [[TMP25:%.*]] = extractvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP24]], 1
+; CHECK-NEXT: [[TMP26:%.*]] = call i32 @llvm.amdgcn.set.inactive.chain.arg.i32(i32 [[TMP25]], i32 [[VCR]])
+; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
+; CHECK-NEXT: [[TMP28:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP27]])
+; CHECK-NEXT: [[TMP29:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP28]], i1 true)
+; CHECK-NEXT: [[TMP30:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP26]], i32 [[TMP29]])
+; CHECK-NEXT: [[TMP31:%.*]] = icmp eq i32 [[TMP26]], [[TMP30]]
+; CHECK-NEXT: [[TMP32:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP31]])
+; CHECK-NEXT: [[TMP33:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP30]])
+; CHECK-NEXT: [[TMP34:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP32]])
+; CHECK-NEXT: [[TMP35:%.*]] = and i32 [[TMP33]], -64
+; CHECK-NEXT: [[TMP36:%.*]] = insertelement <2 x i32> [[TMP8]], i32 [[TMP35]], i64 0
+; CHECK-NEXT: [[TMP37:%.*]] = bitcast <2 x i32> [[TMP36]] to i64
+; CHECK-NEXT: [[TMP38:%.*]] = inttoptr i64 [[TMP37]] to ptr
+; CHECK-NEXT: [[TMP39:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
+; CHECK-NEXT: [[TMP40:%.*]] = bitcast i64 [[TMP39]] to <2 x i32>
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <2 x i32> [[TMP40]], i64 0
+; CHECK-NEXT: [[TMP42:%.*]] = extractelement <2 x i32> [[TMP40]], i64 1
+; CHECK-NEXT: [[TMP43:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 0
+; CHECK-NEXT: [[TMP44:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 1
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 2
+; CHECK-NEXT: [[TMP46:%.*]] = insertelement <20 x i32> poison, i32 [[GLOBALTABLE]], i64 0
+; CHECK-NEXT: [[TMP47:%.*]] = insertelement <20 x i32> [[TMP46]], i32 [[TMP41]], i64 1
+; CHECK-NEXT: [[TMP48:%.*]] = insertelement <20 x i32> [[TMP47]], i32 [[TMP42]], i64 2
+; CHECK-NEXT: [[TMP49:%.*]] = insertelement <20 x i32> [[TMP48]], i32 [[PAD0]], i64 3
+; CHECK-NEXT: [[TMP50:%.*]] = insertelement <20 x i32> [[TMP49]], i32 [[PAD1]], i64 4
+; CHECK-NEXT: [[TMP51:%.*]] = insertelement <20 x i32> [[TMP50]], i32 [[PAD2]], i64 5
+; CHECK-NEXT: [[TMP52:%.*]] = insertelement <20 x i32> [[TMP51]], i32 [[PAD3]], i64 6
+; CHECK-NEXT: [[TMP53:%.*]] = insertelement <20 x i32> [[TMP52]], i32 [[PAD4]], i64 7
+; CHECK-NEXT: [[TMP54:%.*]] = insertelement <20 x i32> [[TMP53]], i32 [[PAD5]], i64 8
+; CHECK-NEXT: [[TMP55:%.*]] = insertelement <20 x i32> [[TMP54]], i32 [[PAD6]], i64 9
+; CHECK-NEXT: [[TMP56:%.*]] = insertelement <20 x i32> [[TMP55]], i32 [[PAD7]], i64 10
+; CHECK-NEXT: [[TMP57:%.*]] = insertelement <20 x i32> [[TMP56]], i32 [[PAD8]], i64 11
+; CHECK-NEXT: [[TMP58:%.*]] = insertelement <20 x i32> [[TMP57]], i32 [[PAD9]], i64 12
+; CHECK-NEXT: [[TMP59:%.*]] = insertelement <20 x i32> [[TMP58]], i32 [[PAD10]], i64 13
+; CHECK-NEXT: [[TMP60:%.*]] = insertelement <20 x i32> [[TMP59]], i32 [[PAD11]], i64 14
+; CHECK-NEXT: [[TMP61:%.*]] = insertelement <20 x i32> [[TMP60]], i32 [[SPILLTABLE]], i64 15
+; CHECK-NEXT: [[TMP62:%.*]] = insertelement <20 x i32> [[TMP61]], i32 [[TMP43]], i64 16
+; CHECK-NEXT: [[TMP63:%.*]] = insertelement <20 x i32> [[TMP62]], i32 [[TMP44]], i64 17
+; CHECK-NEXT: [[TMP64:%.*]] = insertelement <20 x i32> [[TMP63]], i32 [[TMP45]], i64 18
+; CHECK-NEXT: [[TMP65:%.*]] = insertelement <20 x i32> [[TMP64]], i32 [[MULTIDISPATCHINFO]], i64 19
+; CHECK-NEXT: call void (ptr, i32, <20 x i32>, { <3 x i32>, i32, ptr addrspace(5), i32, i32 }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v20i32.sl_v3i32i32p5i32i32s(ptr inreg [[TMP38]], i32 inreg [[TMP34]], <20 x i32> inreg [[TMP65]], { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP24]], i32 0)
; CHECK-NEXT: unreachable
;
;
; CHECK-LABEL: define {{[^@]+}}@test.1
-; CHECK-SAME: (i32 inreg [[GLOBALTABLE:%.*]], ptr addrspace(4) inreg [[NUMWORKGROUPSPTR:%.*]], i32 inreg [[PAD0:%.*]], i32 inreg [[PAD1:%.*]], i32 inreg [[PAD2:%.*]], i32 inreg [[PAD3:%.*]], i32 inreg [[PAD4:%.*]], i32 inreg [[PAD5:%.*]], i32 inreg [[PAD6:%.*]], i32 inreg [[PAD7:%.*]], i32 inreg [[PAD8:%.*]], i32 inreg [[PAD9:%.*]], i32 inreg [[PAD10:%.*]], i32 inreg [[PAD11:%.*]], i32 inreg [[SPILLTABLE:%.*]], i32 [[VCR:%.*]], ptr addrspace(5) [[VSP:%.*]], ptr addrspace(5) [[P2:%.*]], i32 [[Q1:%.*]]) #[[ATTR1]] align 64 !lgc.cps !2 !lgc.shaderstage !3 {
-; CHECK-NEXT: [[TMP1:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+; CHECK-SAME: (i32 inreg [[GLOBALTABLE:%.*]], ptr addrspace(4) inreg [[NUMWORKGROUPSPTR:%.*]], i32 inreg [[PAD0:%.*]], i32 inreg [[PAD1:%.*]], i32 inreg [[PAD2:%.*]], i32 inreg [[PAD3:%.*]], i32 inreg [[PAD4:%.*]], i32 inreg [[PAD5:%.*]], i32 inreg [[PAD6:%.*]], i32 inreg [[PAD7:%.*]], i32 inreg [[PAD8:%.*]], i32 inreg [[PAD9:%.*]], i32 inreg [[PAD10:%.*]], i32 inreg [[PAD11:%.*]], i32 inreg [[SPILLTABLE:%.*]], <3 x i32> inreg [[WORKGROUPID:%.*]], i32 inreg [[MULTIDISPATCHINFO:%.*]], <3 x i32> [[LOCALINVOCATIONID:%.*]], i32 [[VCR:%.*]], ptr addrspace(5) [[VSP:%.*]], i32 [[P2:%.*]], i32 [[Q1:%.*]]) #[[ATTR1]] align 64 !lgc.cps !2 !lgc.shaderstage !3 {
+; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4, addrspace(5)
; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.amdgcn.s.getpc()
; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[TMP2]] to <2 x i32>
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[SPILLTABLE]], i64 0
@@ -125,55 +186,67 @@ define void @test.2({ ptr addrspace(32) } %state) !lgc.cps !{i32 1} !lgc.shaders
; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr addrspace(4)
; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.amdgcn.s.getpc()
; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[TMP7]] to <2 x i32>
-; CHECK-NEXT: store ptr addrspace(5) [[VSP]], ptr addrspace(5) [[TMP1]], align 4
-; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i32 [[Q1]] to ptr addrspace(5)
-; CHECK-NEXT: [[N111:%.*]] = load i32, ptr addrspace(5) [[TMP9]], align 4
-; CHECK-NEXT: [[N99:%.*]] = load i8, ptr addrspace(5) [[P2]], align 1
-; CHECK-NEXT: [[TMP10:%.*]] = load ptr addrspace(5), ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr addrspace(5) [[VSP]] to i32
+; CHECK-NEXT: store i32 [[TMP9]], ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr addrspace(5) null, i32 [[Q1]]
+; CHECK-NEXT: [[N111:%.*]] = load i32, ptr addrspace(5) [[TMP10]], align 4
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr addrspace(5) null, i32 [[P2]]
+; CHECK-NEXT: [[N99:%.*]] = load i8, ptr addrspace(5) [[TMP11]], align 1
+; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i32 [[TMP12]] to ptr addrspace(5)
; CHECK-NEXT: br label [[TAIL_BLOCK:%.*]]
; CHECK: tail.block:
-; CHECK-NEXT: [[TMP11:%.*]] = insertvalue { i32, ptr addrspace(5) } { i32 ptrtoint (ptr getelementptr (i8, ptr @test.2, i32 1) to i32), ptr addrspace(5) poison }, ptr addrspace(5) [[TMP10]], 1
-; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
-; CHECK-NEXT: [[TMP13:%.*]] = bitcast i64 [[TMP12]] to <2 x i32>
-; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x i32> [[TMP13]], i64 0
-; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x i32> [[TMP13]], i64 1
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <16 x i32> poison, i32 [[GLOBALTABLE]], i64 0
-; CHECK-NEXT: [[TMP17:%.*]] = insertelement <16 x i32> [[TMP16]], i32 [[TMP14]], i64 1
-; CHECK-NEXT: [[TMP18:%.*]] = insertelement <16 x i32> [[TMP17]], i32 [[TMP15]], i64 2
-; CHECK-NEXT: [[TMP19:%.*]] = insertelement <16 x i32> [[TMP18]], i32 [[PAD0]], i64 3
-; CHECK-NEXT: [[TMP20:%.*]] = insertelement <16 x i32> [[TMP19]], i32 [[PAD1]], i64 4
-; CHECK-NEXT: [[TMP21:%.*]] = insertelement <16 x i32> [[TMP20]], i32 [[PAD2]], i64 5
-; CHECK-NEXT: [[TMP22:%.*]] = insertelement <16 x i32> [[TMP21]], i32 [[PAD3]], i64 6
-; CHECK-NEXT: [[TMP23:%.*]] = insertelement <16 x i32> [[TMP22]], i32 [[PAD4]], i64 7
-; CHECK-NEXT: [[TMP24:%.*]] = insertelement <16 x i32> [[TMP23]], i32 [[PAD5]], i64 8
-; CHECK-NEXT: [[TMP25:%.*]] = insertelement <16 x i32> [[TMP24]], i32 [[PAD6]], i64 9
-; CHECK-NEXT: [[TMP26:%.*]] = insertelement <16 x i32> [[TMP25]], i32 [[PAD7]], i64 10
-; CHECK-NEXT: [[TMP27:%.*]] = insertelement <16 x i32> [[TMP26]], i32 [[PAD8]], i64 11
-; CHECK-NEXT: [[TMP28:%.*]] = insertelement <16 x i32> [[TMP27]], i32 [[PAD9]], i64 12
-; CHECK-NEXT: [[TMP29:%.*]] = insertelement <16 x i32> [[TMP28]], i32 [[PAD10]], i64 13
-; CHECK-NEXT: [[TMP30:%.*]] = insertelement <16 x i32> [[TMP29]], i32 [[PAD11]], i64 14
-; CHECK-NEXT: [[TMP31:%.*]] = insertelement <16 x i32> [[TMP30]], i32 [[SPILLTABLE]], i64 15
-; CHECK-NEXT: [[TMP32:%.*]] = extractvalue { i32, ptr addrspace(5) } [[TMP11]], 0
-; CHECK-NEXT: [[TMP33:%.*]] = call i32 @llvm.amdgcn.set.inactive.{{(chain.arg.)?}}i32(i32 [[TMP32]], i32 [[VCR]])
-; CHECK-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
-; CHECK-NEXT: [[TMP35:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP34]])
-; CHECK-NEXT: [[TMP36:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP35]], i1 true)
-; CHECK-NEXT: [[TMP37:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP33]], i32 [[TMP36]])
-; CHECK-NEXT: [[TMP38:%.*]] = icmp eq i32 [[TMP33]], [[TMP37]]
-; CHECK-NEXT: [[TMP39:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP38]])
-; CHECK-NEXT: [[TMP40:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP37]])
-; CHECK-NEXT: [[TMP41:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP39]])
-; CHECK-NEXT: [[TMP42:%.*]] = and i32 [[TMP40]], -64
-; CHECK-NEXT: [[TMP43:%.*]] = insertelement <2 x i32> [[TMP8]], i32 [[TMP42]], i64 0
-; CHECK-NEXT: [[TMP44:%.*]] = bitcast <2 x i32> [[TMP43]] to i64
-; CHECK-NEXT: [[TMP45:%.*]] = inttoptr i64 [[TMP44]] to ptr
-; CHECK-NEXT: call void (ptr, i32, <16 x i32>, { i32, ptr addrspace(5) }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v16i32.sl_i32p5s(ptr inreg [[TMP45]], i32 inreg [[TMP41]], <16 x i32> inreg [[TMP31]], { i32, ptr addrspace(5) } [[TMP11]], i32 0)
+; CHECK-NEXT: [[TMP14:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5) } poison, <3 x i32> [[LOCALINVOCATIONID]], 0
+; CHECK-NEXT: [[TMP15:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5) } [[TMP14]], i32 add (i32 ptrtoint (ptr @test.2 to i32), i32 1), 1
+; CHECK-NEXT: [[TMP16:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5) } [[TMP15]], ptr addrspace(5) [[TMP13]], 2
+; CHECK-NEXT: [[TMP17:%.*]] = extractvalue { <3 x i32>, i32, ptr addrspace(5) } [[TMP16]], 1
+; CHECK-NEXT: [[TMP18:%.*]] = call i32 @llvm.amdgcn.set.inactive.chain.arg.i32(i32 [[TMP17]], i32 [[VCR]])
+; CHECK-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
+; CHECK-NEXT: [[TMP20:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP19]])
+; CHECK-NEXT: [[TMP21:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP20]], i1 true)
+; CHECK-NEXT: [[TMP22:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP18]], i32 [[TMP21]])
+; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i32 [[TMP18]], [[TMP22]]
+; CHECK-NEXT: [[TMP24:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP23]])
+; CHECK-NEXT: [[TMP25:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP22]])
+; CHECK-NEXT: [[TMP26:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP24]])
+; CHECK-NEXT: [[TMP27:%.*]] = and i32 [[TMP25]], -64
+; CHECK-NEXT: [[TMP28:%.*]] = insertelement <2 x i32> [[TMP8]], i32 [[TMP27]], i64 0
+; CHECK-NEXT: [[TMP29:%.*]] = bitcast <2 x i32> [[TMP28]] to i64
+; CHECK-NEXT: [[TMP30:%.*]] = inttoptr i64 [[TMP29]] to ptr
+; CHECK-NEXT: [[TMP31:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
+; CHECK-NEXT: [[TMP32:%.*]] = bitcast i64 [[TMP31]] to <2 x i32>
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <2 x i32> [[TMP32]], i64 0
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <2 x i32> [[TMP32]], i64 1
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 0
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 1
+; CHECK-NEXT: [[TMP37:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 2
+; CHECK-NEXT: [[TMP38:%.*]] = insertelement <20 x i32> poison, i32 [[GLOBALTABLE]], i64 0
+; CHECK-NEXT: [[TMP39:%.*]] = insertelement <20 x i32> [[TMP38]], i32 [[TMP33]], i64 1
+; CHECK-NEXT: [[TMP40:%.*]] = insertelement <20 x i32> [[TMP39]], i32 [[TMP34]], i64 2
+; CHECK-NEXT: [[TMP41:%.*]] = insertelement <20 x i32> [[TMP40]], i32 [[PAD0]], i64 3
+; CHECK-NEXT: [[TMP42:%.*]] = insertelement <20 x i32> [[TMP41]], i32 [[PAD1]], i64 4
+; CHECK-NEXT: [[TMP43:%.*]] = insertelement <20 x i32> [[TMP42]], i32 [[PAD2]], i64 5
+; CHECK-NEXT: [[TMP44:%.*]] = insertelement <20 x i32> [[TMP43]], i32 [[PAD3]], i64 6
+; CHECK-NEXT: [[TMP45:%.*]] = insertelement <20 x i32> [[TMP44]], i32 [[PAD4]], i64 7
+; CHECK-NEXT: [[TMP46:%.*]] = insertelement <20 x i32> [[TMP45]], i32 [[PAD5]], i64 8
+; CHECK-NEXT: [[TMP47:%.*]] = insertelement <20 x i32> [[TMP46]], i32 [[PAD6]], i64 9
+; CHECK-NEXT: [[TMP48:%.*]] = insertelement <20 x i32> [[TMP47]], i32 [[PAD7]], i64 10
+; CHECK-NEXT: [[TMP49:%.*]] = insertelement <20 x i32> [[TMP48]], i32 [[PAD8]], i64 11
+; CHECK-NEXT: [[TMP50:%.*]] = insertelement <20 x i32> [[TMP49]], i32 [[PAD9]], i64 12
+; CHECK-NEXT: [[TMP51:%.*]] = insertelement <20 x i32> [[TMP50]], i32 [[PAD10]], i64 13
+; CHECK-NEXT: [[TMP52:%.*]] = insertelement <20 x i32> [[TMP51]], i32 [[PAD11]], i64 14
+; CHECK-NEXT: [[TMP53:%.*]] = insertelement <20 x i32> [[TMP52]], i32 [[SPILLTABLE]], i64 15
+; CHECK-NEXT: [[TMP54:%.*]] = insertelement <20 x i32> [[TMP53]], i32 [[TMP35]], i64 16
+; CHECK-NEXT: [[TMP55:%.*]] = insertelement <20 x i32> [[TMP54]], i32 [[TMP36]], i64 17
+; CHECK-NEXT: [[TMP56:%.*]] = insertelement <20 x i32> [[TMP55]], i32 [[TMP37]], i64 18
+; CHECK-NEXT: [[TMP57:%.*]] = insertelement <20 x i32> [[TMP56]], i32 [[MULTIDISPATCHINFO]], i64 19
+; CHECK-NEXT: call void (ptr, i32, <20 x i32>, { <3 x i32>, i32, ptr addrspace(5) }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v20i32.sl_v3i32i32p5s(ptr inreg [[TMP30]], i32 inreg [[TMP26]], <20 x i32> inreg [[TMP57]], { <3 x i32>, i32, ptr addrspace(5) } [[TMP16]], i32 0)
; CHECK-NEXT: unreachable
;
;
; CHECK-LABEL: define {{[^@]+}}@test.2
-; CHECK-SAME: (i32 inreg [[GLOBALTABLE:%.*]], ptr addrspace(4) inreg [[NUMWORKGROUPSPTR:%.*]], i32 inreg [[PAD0:%.*]], i32 inreg [[PAD1:%.*]], i32 inreg [[PAD2:%.*]], i32 inreg [[PAD3:%.*]], i32 inreg [[PAD4:%.*]], i32 inreg [[PAD5:%.*]], i32 inreg [[PAD6:%.*]], i32 inreg [[PAD7:%.*]], i32 inreg [[PAD8:%.*]], i32 inreg [[PAD9:%.*]], i32 inreg [[PAD10:%.*]], i32 inreg [[PAD11:%.*]], i32 inreg [[SPILLTABLE:%.*]], i32 [[VCR:%.*]], ptr addrspace(5) [[VSP:%.*]]) #[[ATTR1]] align 64 !lgc.cps !2 !lgc.shaderstage !3 {
-; CHECK-NEXT: [[TMP1:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+; CHECK-SAME: (i32 inreg [[GLOBALTABLE:%.*]], ptr addrspace(4) inreg [[NUMWORKGROUPSPTR:%.*]], i32 inreg [[PAD0:%.*]], i32 inreg [[PAD1:%.*]], i32 inreg [[PAD2:%.*]], i32 inreg [[PAD3:%.*]], i32 inreg [[PAD4:%.*]], i32 inreg [[PAD5:%.*]], i32 inreg [[PAD6:%.*]], i32 inreg [[PAD7:%.*]], i32 inreg [[PAD8:%.*]], i32 inreg [[PAD9:%.*]], i32 inreg [[PAD10:%.*]], i32 inreg [[PAD11:%.*]], i32 inreg [[SPILLTABLE:%.*]], <3 x i32> inreg [[WORKGROUPID:%.*]], i32 inreg [[MULTIDISPATCHINFO:%.*]], <3 x i32> [[LOCALINVOCATIONID:%.*]], i32 [[VCR:%.*]], ptr addrspace(5) [[VSP:%.*]]) #[[ATTR1]] align 64 !lgc.cps !2 !lgc.shaderstage !3 {
+; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4, addrspace(5)
; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.amdgcn.s.getpc()
; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[TMP2]] to <2 x i32>
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[SPILLTABLE]], i64 0
@@ -182,58 +255,239 @@ define void @test.2({ ptr addrspace(32) } %state) !lgc.cps !{i32 1} !lgc.shaders
; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.amdgcn.s.getpc()
; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[TMP7]] to <2 x i32>
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr addrspace(5) [[VSP]], i32 -4
-; CHECK-NEXT: [[CPS_STATE:%.*]] = load { ptr addrspace(5) }, ptr addrspace(5) [[TMP9]], align 4
-; CHECK-NEXT: store ptr addrspace(5) [[TMP9]], ptr addrspace(5) [[TMP1]], align 4
-; CHECK-NEXT: [[TMP10:%.*]] = load ptr addrspace(5), ptr addrspace(5) [[TMP1]], align 4
-; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr addrspace(5) [[TMP10]], i32 -12
-; CHECK-NEXT: [[P2:%.*]] = extractvalue { ptr addrspace(5) } [[CPS_STATE]], 0
-; CHECK-NEXT: [[N333:%.*]] = load i32, ptr addrspace(5) [[TMP11]], align 4
-; CHECK-NEXT: [[N99:%.*]] = load i8, ptr addrspace(5) [[P2]], align 1
-; CHECK-NEXT: [[TMP12:%.*]] = load ptr addrspace(5), ptr addrspace(5) [[TMP1]], align 4
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr addrspace(5) [[TMP12]], i32 -12
-; CHECK-NEXT: store ptr addrspace(5) [[TMP13]], ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[CPS_STATE:%.*]] = load { i32 }, ptr addrspace(5) [[TMP9]], align 4
+; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr addrspace(5) [[TMP9]] to i32
+; CHECK-NEXT: store i32 [[TMP10]], ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], -12
+; CHECK-NEXT: [[P2:%.*]] = extractvalue { i32 } [[CPS_STATE]], 0
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr addrspace(5) null, i32 [[TMP12]]
+; CHECK-NEXT: [[N333:%.*]] = load i32, ptr addrspace(5) [[TMP13]], align 4
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr addrspace(5) null, i32 [[P2]]
+; CHECK-NEXT: [[N99:%.*]] = load i8, ptr addrspace(5) [[TMP14]], align 1
+; CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP16:%.*]] = add i32 [[TMP15]], -12
+; CHECK-NEXT: store i32 [[TMP16]], ptr addrspace(5) [[TMP1]], align 4
; CHECK-NEXT: br label [[TAIL_BLOCK:%.*]]
; CHECK: tail.block:
-; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
-; CHECK-NEXT: [[TMP15:%.*]] = bitcast i64 [[TMP14]] to <2 x i32>
-; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x i32> [[TMP15]], i64 0
-; CHECK-NEXT: [[TMP17:%.*]] = extractelement <2 x i32> [[TMP15]], i64 1
-; CHECK-NEXT: [[TMP18:%.*]] = insertelement <16 x i32> poison, i32 [[GLOBALTABLE]], i64 0
-; CHECK-NEXT: [[TMP19:%.*]] = insertelement <16 x i32> [[TMP18]], i32 [[TMP16]], i64 1
-; CHECK-NEXT: [[TMP20:%.*]] = insertelement <16 x i32> [[TMP19]], i32 [[TMP17]], i64 2
-; CHECK-NEXT: [[TMP21:%.*]] = insertelement <16 x i32> [[TMP20]], i32 [[PAD0]], i64 3
-; CHECK-NEXT: [[TMP22:%.*]] = insertelement <16 x i32> [[TMP21]], i32 [[PAD1]], i64 4
-; CHECK-NEXT: [[TMP23:%.*]] = insertelement <16 x i32> [[TMP22]], i32 [[PAD2]], i64 5
-; CHECK-NEXT: [[TMP24:%.*]] = insertelement <16 x i32> [[TMP23]], i32 [[PAD3]], i64 6
-; CHECK-NEXT: [[TMP25:%.*]] = insertelement <16 x i32> [[TMP24]], i32 [[PAD4]], i64 7
-; CHECK-NEXT: [[TMP26:%.*]] = insertelement <16 x i32> [[TMP25]], i32 [[PAD5]], i64 8
-; CHECK-NEXT: [[TMP27:%.*]] = insertelement <16 x i32> [[TMP26]], i32 [[PAD6]], i64 9
-; CHECK-NEXT: [[TMP28:%.*]] = insertelement <16 x i32> [[TMP27]], i32 [[PAD7]], i64 10
-; CHECK-NEXT: [[TMP29:%.*]] = insertelement <16 x i32> [[TMP28]], i32 [[PAD8]], i64 11
-; CHECK-NEXT: [[TMP30:%.*]] = insertelement <16 x i32> [[TMP29]], i32 [[PAD9]], i64 12
-; CHECK-NEXT: [[TMP31:%.*]] = insertelement <16 x i32> [[TMP30]], i32 [[PAD10]], i64 13
-; CHECK-NEXT: [[TMP32:%.*]] = insertelement <16 x i32> [[TMP31]], i32 [[PAD11]], i64 14
-; CHECK-NEXT: [[TMP33:%.*]] = insertelement <16 x i32> [[TMP32]], i32 [[SPILLTABLE]], i64 15
-; CHECK-NEXT: [[TMP34:%.*]] = call i32 @llvm.amdgcn.set.inactive.{{(chain.arg.)?}}i32(i32 0, i32 [[VCR]])
-; CHECK-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
-; CHECK-NEXT: [[TMP36:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP35]])
-; CHECK-NEXT: [[TMP37:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP36]], i1 true)
-; CHECK-NEXT: [[TMP38:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP34]], i32 [[TMP37]])
-; CHECK-NEXT: [[TMP39:%.*]] = icmp eq i32 [[TMP34]], [[TMP38]]
-; CHECK-NEXT: [[TMP40:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP39]])
-; CHECK-NEXT: [[TMP41:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP38]])
-; CHECK-NEXT: [[TMP42:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP40]])
-; CHECK-NEXT: [[TMP43:%.*]] = icmp eq i32 [[TMP41]], 0
-; CHECK-NEXT: br i1 [[TMP43]], label [[RET_BLOCK:%.*]], label [[CHAIN_BLOCK:%.*]]
+; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5) } poison, <3 x i32> [[LOCALINVOCATIONID]], 0
+; CHECK-NEXT: [[TMP18:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5) } [[TMP17]], i32 0, 1
+; CHECK-NEXT: [[TMP19:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5) } [[TMP18]], ptr addrspace(5) poison, 2
+; CHECK-NEXT: [[TMP20:%.*]] = extractvalue { <3 x i32>, i32, ptr addrspace(5) } [[TMP19]], 1
+; CHECK-NEXT: [[TMP21:%.*]] = call i32 @llvm.amdgcn.set.inactive.chain.arg.i32(i32 [[TMP20]], i32 [[VCR]])
+; CHECK-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
+; CHECK-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP22]])
+; CHECK-NEXT: [[TMP24:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP23]], i1 true)
+; CHECK-NEXT: [[TMP25:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP21]], i32 [[TMP24]])
+; CHECK-NEXT: [[TMP26:%.*]] = icmp eq i32 [[TMP21]], [[TMP25]]
+; CHECK-NEXT: [[TMP27:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP26]])
+; CHECK-NEXT: [[TMP28:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP25]])
+; CHECK-NEXT: [[TMP29:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP27]])
+; CHECK-NEXT: [[TMP30:%.*]] = icmp eq i32 [[TMP28]], 0
+; CHECK-NEXT: br i1 [[TMP30]], label [[RET_BLOCK:%.*]], label [[CHAIN_BLOCK:%.*]]
; CHECK: chain.block:
-; CHECK-NEXT: [[TMP44:%.*]] = and i32 [[TMP41]], -64
+; CHECK-NEXT: [[TMP31:%.*]] = and i32 [[TMP28]], -64
+; CHECK-NEXT: [[TMP32:%.*]] = insertelement <2 x i32> [[TMP8]], i32 [[TMP31]], i64 0
+; CHECK-NEXT: [[TMP33:%.*]] = bitcast <2 x i32> [[TMP32]] to i64
+; CHECK-NEXT: [[TMP34:%.*]] = inttoptr i64 [[TMP33]] to ptr
+; CHECK-NEXT: [[TMP35:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
+; CHECK-NEXT: [[TMP36:%.*]] = bitcast i64 [[TMP35]] to <2 x i32>
+; CHECK-NEXT: [[TMP37:%.*]] = extractelement <2 x i32> [[TMP36]], i64 0
+; CHECK-NEXT: [[TMP38:%.*]] = extractelement <2 x i32> [[TMP36]], i64 1
+; CHECK-NEXT: [[TMP39:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 0
+; CHECK-NEXT: [[TMP40:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 1
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 2
+; CHECK-NEXT: [[TMP42:%.*]] = insertelement <20 x i32> poison, i32 [[GLOBALTABLE]], i64 0
+; CHECK-NEXT: [[TMP43:%.*]] = insertelement <20 x i32> [[TMP42]], i32 [[TMP37]], i64 1
+; CHECK-NEXT: [[TMP44:%.*]] = insertelement <20 x i32> [[TMP43]], i32 [[TMP38]], i64 2
+; CHECK-NEXT: [[TMP45:%.*]] = insertelement <20 x i32> [[TMP44]], i32 [[PAD0]], i64 3
+; CHECK-NEXT: [[TMP46:%.*]] = insertelement <20 x i32> [[TMP45]], i32 [[PAD1]], i64 4
+; CHECK-NEXT: [[TMP47:%.*]] = insertelement <20 x i32> [[TMP46]], i32 [[PAD2]], i64 5
+; CHECK-NEXT: [[TMP48:%.*]] = insertelement <20 x i32> [[TMP47]], i32 [[PAD3]], i64 6
+; CHECK-NEXT: [[TMP49:%.*]] = insertelement <20 x i32> [[TMP48]], i32 [[PAD4]], i64 7
+; CHECK-NEXT: [[TMP50:%.*]] = insertelement <20 x i32> [[TMP49]], i32 [[PAD5]], i64 8
+; CHECK-NEXT: [[TMP51:%.*]] = insertelement <20 x i32> [[TMP50]], i32 [[PAD6]], i64 9
+; CHECK-NEXT: [[TMP52:%.*]] = insertelement <20 x i32> [[TMP51]], i32 [[PAD7]], i64 10
+; CHECK-NEXT: [[TMP53:%.*]] = insertelement <20 x i32> [[TMP52]], i32 [[PAD8]], i64 11
+; CHECK-NEXT: [[TMP54:%.*]] = insertelement <20 x i32> [[TMP53]], i32 [[PAD9]], i64 12
+; CHECK-NEXT: [[TMP55:%.*]] = insertelement <20 x i32> [[TMP54]], i32 [[PAD10]], i64 13
+; CHECK-NEXT: [[TMP56:%.*]] = insertelement <20 x i32> [[TMP55]], i32 [[PAD11]], i64 14
+; CHECK-NEXT: [[TMP57:%.*]] = insertelement <20 x i32> [[TMP56]], i32 [[SPILLTABLE]], i64 15
+; CHECK-NEXT: [[TMP58:%.*]] = insertelement <20 x i32> [[TMP57]], i32 [[TMP39]], i64 16
+; CHECK-NEXT: [[TMP59:%.*]] = insertelement <20 x i32> [[TMP58]], i32 [[TMP40]], i64 17
+; CHECK-NEXT: [[TMP60:%.*]] = insertelement <20 x i32> [[TMP59]], i32 [[TMP41]], i64 18
+; CHECK-NEXT: [[TMP61:%.*]] = insertelement <20 x i32> [[TMP60]], i32 [[MULTIDISPATCHINFO]], i64 19
+; CHECK-NEXT: call void (ptr, i32, <20 x i32>, { <3 x i32>, i32, ptr addrspace(5) }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v20i32.sl_v3i32i32p5s(ptr inreg [[TMP34]], i32 inreg [[TMP29]], <20 x i32> inreg [[TMP61]], { <3 x i32>, i32, ptr addrspace(5) } [[TMP19]], i32 0)
+; CHECK-NEXT: unreachable
+; CHECK: ret.block:
+; CHECK-NEXT: ret void
+;
+;
+; CHECK-LABEL: define {{[^@]+}}@test.gep
+; CHECK-SAME: (i32 inreg [[GLOBALTABLE:%.*]], ptr addrspace(4) inreg [[NUMWORKGROUPSPTR:%.*]], i32 inreg [[PAD0:%.*]], i32 inreg [[PAD1:%.*]], i32 inreg [[PAD2:%.*]], i32 inreg [[PAD3:%.*]], i32 inreg [[PAD4:%.*]], i32 inreg [[PAD5:%.*]], i32 inreg [[PAD6:%.*]], i32 inreg [[PAD7:%.*]], i32 inreg [[PAD8:%.*]], i32 inreg [[PAD9:%.*]], i32 inreg [[PAD10:%.*]], i32 inreg [[PAD11:%.*]], i32 inreg [[SPILLTABLE:%.*]], <3 x i32> inreg [[WORKGROUPID:%.*]], i32 inreg [[MULTIDISPATCHINFO:%.*]], <3 x i32> [[LOCALINVOCATIONID:%.*]], i32 [[VCR:%.*]], ptr addrspace(5) [[VSP1:%.*]]) #[[ATTR1]] align 64 !lgc.cps !2 !lgc.shaderstage !3 {
+; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4, addrspace(5)
+; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.amdgcn.s.getpc()
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[TMP2]] to <2 x i32>
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[SPILLTABLE]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP4]] to i64
+; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr addrspace(4)
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.amdgcn.s.getpc()
+; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[TMP7]] to <2 x i32>
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr addrspace(5) [[VSP1]] to i32
+; CHECK-NEXT: store i32 [[TMP9]], ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], 12
+; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[STACK_EL0:%.*]] = call i32 @lgc.cps.get.dummy.index(i32 0)
+; CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[STACK_EL0]], 12
+; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[TMP10]], [[TMP12]]
+; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr addrspace(5) null, i32 [[TMP13]]
+; CHECK-NEXT: store i32 [[TMP14]], ptr addrspace(5) [[TMP15]], align 4
+; CHECK-NEXT: [[STACK_EL1:%.*]] = call i32 @lgc.cps.get.dummy.index(i32 1)
+; CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[STACK_EL1]], 12
+; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP10]], [[TMP16]]
+; CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], -4
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr addrspace(5) null, i32 [[TMP17]]
+; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(5) [[TMP20]], align 4
+; CHECK-NEXT: [[STACK_EL2:%.*]] = call i32 @lgc.cps.get.dummy.index(i32 2)
+; CHECK-NEXT: [[STACK_EL2_DIV:%.*]] = sdiv i32 [[STACK_EL2]], 2
+; CHECK-NEXT: [[TMP21:%.*]] = add i32 [[TMP10]], 4
+; CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[STACK_EL2_DIV]], 12
+; CHECK-NEXT: [[TMP23:%.*]] = add i32 [[TMP21]], [[TMP22]]
+; CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP25:%.*]] = add i32 [[TMP24]], -8
+; CHECK-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr addrspace(5) null, i32 [[TMP23]]
+; CHECK-NEXT: store i32 [[TMP25]], ptr addrspace(5) [[TMP26]], align 4
+; CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP28:%.*]] = inttoptr i32 [[TMP27]] to ptr addrspace(5)
+; CHECK-NEXT: br label [[TAIL_BLOCK:%.*]]
+; CHECK: tail.block:
+; CHECK-NEXT: [[TMP29:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } poison, <3 x i32> [[LOCALINVOCATIONID]], 0
+; CHECK-NEXT: [[TMP30:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP29]], i32 add (i32 ptrtoint (ptr @test.1 to i32), i32 1), 1
+; CHECK-NEXT: [[TMP31:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP30]], ptr addrspace(5) [[TMP28]], 2
+; CHECK-NEXT: [[TMP32:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP31]], i32 [[TMP25]], 3
+; CHECK-NEXT: [[TMP33:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP32]], i32 [[TMP25]], 4
+; CHECK-NEXT: [[TMP34:%.*]] = extractvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP33]], 1
+; CHECK-NEXT: [[TMP35:%.*]] = call i32 @llvm.amdgcn.set.inactive.chain.arg.i32(i32 [[TMP34]], i32 [[VCR]])
+; CHECK-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
+; CHECK-NEXT: [[TMP37:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP36]])
+; CHECK-NEXT: [[TMP38:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP37]], i1 true)
+; CHECK-NEXT: [[TMP39:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP35]], i32 [[TMP38]])
+; CHECK-NEXT: [[TMP40:%.*]] = icmp eq i32 [[TMP35]], [[TMP39]]
+; CHECK-NEXT: [[TMP41:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP40]])
+; CHECK-NEXT: [[TMP42:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP39]])
+; CHECK-NEXT: [[TMP43:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP41]])
+; CHECK-NEXT: [[TMP44:%.*]] = and i32 [[TMP42]], -64
; CHECK-NEXT: [[TMP45:%.*]] = insertelement <2 x i32> [[TMP8]], i32 [[TMP44]], i64 0
; CHECK-NEXT: [[TMP46:%.*]] = bitcast <2 x i32> [[TMP45]] to i64
; CHECK-NEXT: [[TMP47:%.*]] = inttoptr i64 [[TMP46]] to ptr
-; CHECK-NEXT: call void (ptr, i32, <16 x i32>, { i32, ptr addrspace(5) }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v16i32.sl_i32p5s(ptr inreg [[TMP47]], i32 inreg [[TMP42]], <16 x i32> inreg [[TMP33]], { i32, ptr addrspace(5) } { i32 0, ptr addrspace(5) poison }, i32 0)
+; CHECK-NEXT: [[TMP48:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
+; CHECK-NEXT: [[TMP49:%.*]] = bitcast i64 [[TMP48]] to <2 x i32>
+; CHECK-NEXT: [[TMP50:%.*]] = extractelement <2 x i32> [[TMP49]], i64 0
+; CHECK-NEXT: [[TMP51:%.*]] = extractelement <2 x i32> [[TMP49]], i64 1
+; CHECK-NEXT: [[TMP52:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 0
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 1
+; CHECK-NEXT: [[TMP54:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 2
+; CHECK-NEXT: [[TMP55:%.*]] = insertelement <20 x i32> poison, i32 [[GLOBALTABLE]], i64 0
+; CHECK-NEXT: [[TMP56:%.*]] = insertelement <20 x i32> [[TMP55]], i32 [[TMP50]], i64 1
+; CHECK-NEXT: [[TMP57:%.*]] = insertelement <20 x i32> [[TMP56]], i32 [[TMP51]], i64 2
+; CHECK-NEXT: [[TMP58:%.*]] = insertelement <20 x i32> [[TMP57]], i32 [[PAD0]], i64 3
+; CHECK-NEXT: [[TMP59:%.*]] = insertelement <20 x i32> [[TMP58]], i32 [[PAD1]], i64 4
+; CHECK-NEXT: [[TMP60:%.*]] = insertelement <20 x i32> [[TMP59]], i32 [[PAD2]], i64 5
+; CHECK-NEXT: [[TMP61:%.*]] = insertelement <20 x i32> [[TMP60]], i32 [[PAD3]], i64 6
+; CHECK-NEXT: [[TMP62:%.*]] = insertelement <20 x i32> [[TMP61]], i32 [[PAD4]], i64 7
+; CHECK-NEXT: [[TMP63:%.*]] = insertelement <20 x i32> [[TMP62]], i32 [[PAD5]], i64 8
+; CHECK-NEXT: [[TMP64:%.*]] = insertelement <20 x i32> [[TMP63]], i32 [[PAD6]], i64 9
+; CHECK-NEXT: [[TMP65:%.*]] = insertelement <20 x i32> [[TMP64]], i32 [[PAD7]], i64 10
+; CHECK-NEXT: [[TMP66:%.*]] = insertelement <20 x i32> [[TMP65]], i32 [[PAD8]], i64 11
+; CHECK-NEXT: [[TMP67:%.*]] = insertelement <20 x i32> [[TMP66]], i32 [[PAD9]], i64 12
+; CHECK-NEXT: [[TMP68:%.*]] = insertelement <20 x i32> [[TMP67]], i32 [[PAD10]], i64 13
+; CHECK-NEXT: [[TMP69:%.*]] = insertelement <20 x i32> [[TMP68]], i32 [[PAD11]], i64 14
+; CHECK-NEXT: [[TMP70:%.*]] = insertelement <20 x i32> [[TMP69]], i32 [[SPILLTABLE]], i64 15
+; CHECK-NEXT: [[TMP71:%.*]] = insertelement <20 x i32> [[TMP70]], i32 [[TMP52]], i64 16
+; CHECK-NEXT: [[TMP72:%.*]] = insertelement <20 x i32> [[TMP71]], i32 [[TMP53]], i64 17
+; CHECK-NEXT: [[TMP73:%.*]] = insertelement <20 x i32> [[TMP72]], i32 [[TMP54]], i64 18
+; CHECK-NEXT: [[TMP74:%.*]] = insertelement <20 x i32> [[TMP73]], i32 [[MULTIDISPATCHINFO]], i64 19
+; CHECK-NEXT: call void (ptr, i32, <20 x i32>, { <3 x i32>, i32, ptr addrspace(5), i32, i32 }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v20i32.sl_v3i32i32p5i32i32s(ptr inreg [[TMP47]], i32 inreg [[TMP43]], <20 x i32> inreg [[TMP74]], { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP33]], i32 0)
+; CHECK-NEXT: unreachable
+;
+;
+; CHECK-LABEL: define {{[^@]+}}@test.nested.gep
+; CHECK-SAME: (i32 inreg [[GLOBALTABLE:%.*]], ptr addrspace(4) inreg [[NUMWORKGROUPSPTR:%.*]], i32 inreg [[PAD0:%.*]], i32 inreg [[PAD1:%.*]], i32 inreg [[PAD2:%.*]], i32 inreg [[PAD3:%.*]], i32 inreg [[PAD4:%.*]], i32 inreg [[PAD5:%.*]], i32 inreg [[PAD6:%.*]], i32 inreg [[PAD7:%.*]], i32 inreg [[PAD8:%.*]], i32 inreg [[PAD9:%.*]], i32 inreg [[PAD10:%.*]], i32 inreg [[PAD11:%.*]], i32 inreg [[SPILLTABLE:%.*]], <3 x i32> inreg [[WORKGROUPID:%.*]], i32 inreg [[MULTIDISPATCHINFO:%.*]], <3 x i32> [[LOCALINVOCATIONID:%.*]], i32 [[VCR:%.*]], ptr addrspace(5) [[VSP1:%.*]]) #[[ATTR1]] align 64 !lgc.cps !2 !lgc.shaderstage !3 {
+; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4, addrspace(5)
+; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.amdgcn.s.getpc()
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[TMP2]] to <2 x i32>
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[SPILLTABLE]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP4]] to i64
+; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr addrspace(4)
+; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.amdgcn.s.getpc()
+; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[TMP7]] to <2 x i32>
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr addrspace(5) [[VSP1]] to i32
+; CHECK-NEXT: store i32 [[TMP9]], ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], 12
+; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[STACK_EL0:%.*]] = call i32 @lgc.cps.get.dummy.index(i32 0)
+; CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[STACK_EL0]], 12
+; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[TMP10]], [[TMP12]]
+; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], 8
+; CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr addrspace(5) null, i32 [[TMP14]]
+; CHECK-NEXT: store i32 [[TMP15]], ptr addrspace(5) [[TMP16]], align 4
+; CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(5) [[TMP1]], align 4
+; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i32 [[TMP17]] to ptr addrspace(5)
+; CHECK-NEXT: br label [[TAIL_BLOCK:%.*]]
+; CHECK: tail.block:
+; CHECK-NEXT: [[TMP19:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } poison, <3 x i32> [[LOCALINVOCATIONID]], 0
+; CHECK-NEXT: [[TMP20:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP19]], i32 add (i32 ptrtoint (ptr @test.1 to i32), i32 1), 1
+; CHECK-NEXT: [[TMP21:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP20]], ptr addrspace(5) [[TMP18]], 2
+; CHECK-NEXT: [[TMP22:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP21]], i32 [[TMP15]], 3
+; CHECK-NEXT: [[TMP23:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP22]], i32 [[TMP15]], 4
+; CHECK-NEXT: [[TMP24:%.*]] = extractvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP23]], 1
+; CHECK-NEXT: [[TMP25:%.*]] = call i32 @llvm.amdgcn.set.inactive.chain.arg.i32(i32 [[TMP24]], i32 [[VCR]])
+; CHECK-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
+; CHECK-NEXT: [[TMP27:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP26]])
+; CHECK-NEXT: [[TMP28:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP27]], i1 true)
+; CHECK-NEXT: [[TMP29:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP25]], i32 [[TMP28]])
+; CHECK-NEXT: [[TMP30:%.*]] = icmp eq i32 [[TMP25]], [[TMP29]]
+; CHECK-NEXT: [[TMP31:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP30]])
+; CHECK-NEXT: [[TMP32:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP29]])
+; CHECK-NEXT: [[TMP33:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP31]])
+; CHECK-NEXT: [[TMP34:%.*]] = and i32 [[TMP32]], -64
+; CHECK-NEXT: [[TMP35:%.*]] = insertelement <2 x i32> [[TMP8]], i32 [[TMP34]], i64 0
+; CHECK-NEXT: [[TMP36:%.*]] = bitcast <2 x i32> [[TMP35]] to i64
+; CHECK-NEXT: [[TMP37:%.*]] = inttoptr i64 [[TMP36]] to ptr
+; CHECK-NEXT: [[TMP38:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
+; CHECK-NEXT: [[TMP39:%.*]] = bitcast i64 [[TMP38]] to <2 x i32>
+; CHECK-NEXT: [[TMP40:%.*]] = extractelement <2 x i32> [[TMP39]], i64 0
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <2 x i32> [[TMP39]], i64 1
+; CHECK-NEXT: [[TMP42:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 0
+; CHECK-NEXT: [[TMP43:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 1
+; CHECK-NEXT: [[TMP44:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 2
+; CHECK-NEXT: [[TMP45:%.*]] = insertelement <20 x i32> poison, i32 [[GLOBALTABLE]], i64 0
+; CHECK-NEXT: [[TMP46:%.*]] = insertelement <20 x i32> [[TMP45]], i32 [[TMP40]], i64 1
+; CHECK-NEXT: [[TMP47:%.*]] = insertelement <20 x i32> [[TMP46]], i32 [[TMP41]], i64 2
+; CHECK-NEXT: [[TMP48:%.*]] = insertelement <20 x i32> [[TMP47]], i32 [[PAD0]], i64 3
+; CHECK-NEXT: [[TMP49:%.*]] = insertelement <20 x i32> [[TMP48]], i32 [[PAD1]], i64 4
+; CHECK-NEXT: [[TMP50:%.*]] = insertelement <20 x i32> [[TMP49]], i32 [[PAD2]], i64 5
+; CHECK-NEXT: [[TMP51:%.*]] = insertelement <20 x i32> [[TMP50]], i32 [[PAD3]], i64 6
+; CHECK-NEXT: [[TMP52:%.*]] = insertelement <20 x i32> [[TMP51]], i32 [[PAD4]], i64 7
+; CHECK-NEXT: [[TMP53:%.*]] = insertelement <20 x i32> [[TMP52]], i32 [[PAD5]], i64 8
+; CHECK-NEXT: [[TMP54:%.*]] = insertelement <20 x i32> [[TMP53]], i32 [[PAD6]], i64 9
+; CHECK-NEXT: [[TMP55:%.*]] = insertelement <20 x i32> [[TMP54]], i32 [[PAD7]], i64 10
+; CHECK-NEXT: [[TMP56:%.*]] = insertelement <20 x i32> [[TMP55]], i32 [[PAD8]], i64 11
+; CHECK-NEXT: [[TMP57:%.*]] = insertelement <20 x i32> [[TMP56]], i32 [[PAD9]], i64 12
+; CHECK-NEXT: [[TMP58:%.*]] = insertelement <20 x i32> [[TMP57]], i32 [[PAD10]], i64 13
+; CHECK-NEXT: [[TMP59:%.*]] = insertelement <20 x i32> [[TMP58]], i32 [[PAD11]], i64 14
+; CHECK-NEXT: [[TMP60:%.*]] = insertelement <20 x i32> [[TMP59]], i32 [[SPILLTABLE]], i64 15
+; CHECK-NEXT: [[TMP61:%.*]] = insertelement <20 x i32> [[TMP60]], i32 [[TMP42]], i64 16
+; CHECK-NEXT: [[TMP62:%.*]] = insertelement <20 x i32> [[TMP61]], i32 [[TMP43]], i64 17
+; CHECK-NEXT: [[TMP63:%.*]] = insertelement <20 x i32> [[TMP62]], i32 [[TMP44]], i64 18
+; CHECK-NEXT: [[TMP64:%.*]] = insertelement <20 x i32> [[TMP63]], i32 [[MULTIDISPATCHINFO]], i64 19
+; CHECK-NEXT: call void (ptr, i32, <20 x i32>, { <3 x i32>, i32, ptr addrspace(5), i32, i32 }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v20i32.sl_v3i32i32p5i32i32s(ptr inreg [[TMP37]], i32 inreg [[TMP33]], <20 x i32> inreg [[TMP64]], { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP23]], i32 0)
; CHECK-NEXT: unreachable
-; CHECK: ret.block:
-; CHECK-NEXT: ret void
;
;.
; CHECK: attributes #[[ATTR0:[0-9]+]] = { noreturn }
@@ -244,7 +498,7 @@ define void @test.2({ ptr addrspace(32) } %state) !lgc.cps !{i32 1} !lgc.shaders
; CHECK: attributes #[[ATTR5:[0-9]+]] = { convergent noreturn nounwind }
;.
; CHECK: [[META0:![0-9]+]] = !{!""}
-; CHECK: [[META1:![0-9]+]] = !{!"\82\B0amdpal.pipelines\91\83\B1.shader_functions\83\A6test.0\81\B4.frontend_stack_size\10\A6test.1\81\B4.frontend_stack_size\00\A6test.2\81\B4.frontend_stack_size\00\B0.spill_threshold\CD\FF\FF\B0.user_data_limit\00\AEamdpal.version\92\03\00"}
+; CHECK: [[META1:![0-9]+]] = !{!"\82\B0amdpal.pipelines\91\83\B1.shader_functions\85\A6test.0\81\B4.frontend_stack_size\10\A6test.1\81\B4.frontend_stack_size\00\A6test.2\81\B4.frontend_stack_size\00\A8test.gep\81\B4.frontend_stack_size\0C\AFtest.nested.gep\81\B4.frontend_stack_size\0C\B0.spill_threshold\CD\FF\FF\B0.user_data_limit\00\AEamdpal.version\92\03\00"}
; CHECK: [[META2:![0-9]+]] = !{i32 1}
; CHECK: [[META3:![0-9]+]] = !{i32 7}
;.
diff --git a/lgc/test/Transforms/CpsLowering/cps-unify-exits.lgc b/lgc/test/Transforms/CpsLowering/cps-unify-exits.lgc
index 5d60d2d644..e748f9cf55 100644
--- a/lgc/test/Transforms/CpsLowering/cps-unify-exits.lgc
+++ b/lgc/test/Transforms/CpsLowering/cps-unify-exits.lgc
@@ -47,9 +47,9 @@ else:
!0 = !{i32 1} ; level 1
; CHECK-LABEL: define {{[^@]+}}@unify_jumps
-; CHECK-SAME: (i32 inreg [[GLOBALTABLE:%.*]], ptr addrspace(4) inreg [[NUMWORKGROUPSPTR:%.*]], i32 inreg [[PAD0:%.*]], i32 inreg [[PAD1:%.*]], i32 inreg [[PAD2:%.*]], i32 inreg [[PAD3:%.*]], i32 inreg [[PAD4:%.*]], i32 inreg [[PAD5:%.*]], i32 inreg [[PAD6:%.*]], i32 inreg [[PAD7:%.*]], i32 inreg [[PAD8:%.*]], i32 inreg [[PAD9:%.*]], i32 inreg [[PAD10:%.*]], i32 inreg [[PAD11:%.*]], i32 inreg [[SPILLTABLE:%.*]], i32 [[VCR:%.*]], ptr addrspace(5) [[VSP:%.*]], i32 [[ARG:%.*]], ptr [[TABLE:%.*]]) #[[ATTR1:[0-9]+]] align 64 !lgc.cps !2 !lgc.shaderstage !3 {
+; CHECK-SAME: (i32 inreg [[GLOBALTABLE:%.*]], ptr addrspace(4) inreg [[NUMWORKGROUPSPTR:%.*]], i32 inreg [[PAD0:%.*]], i32 inreg [[PAD1:%.*]], i32 inreg [[PAD2:%.*]], i32 inreg [[PAD3:%.*]], i32 inreg [[PAD4:%.*]], i32 inreg [[PAD5:%.*]], i32 inreg [[PAD6:%.*]], i32 inreg [[PAD7:%.*]], i32 inreg [[PAD8:%.*]], i32 inreg [[PAD9:%.*]], i32 inreg [[PAD10:%.*]], i32 inreg [[PAD11:%.*]], i32 inreg [[SPILLTABLE:%.*]], <3 x i32> inreg [[WORKGROUPID:%.*]], i32 inreg [[MULTIDISPATCHINFO:%.*]], <3 x i32> [[LOCALINVOCATIONID:%.*]], i32 [[VCR:%.*]], ptr addrspace(5) [[VSP:%.*]], i32 [[ARG:%.*]], ptr [[TABLE:%.*]]) #[[ATTR1:[0-9]+]] align 64 !lgc.cps !2 !lgc.shaderstage !3 {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+; CHECK-NEXT: [[TMP0:%.*]] = alloca i32, align 4, addrspace(5)
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.amdgcn.s.getpc()
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[TMP1]] to <2 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[SPILLTABLE]], i64 0
@@ -59,7 +59,8 @@ else:
; CHECK-NEXT: [[TMP7:%.*]] = bitcast i64 [[TMP6]] to <2 x i32>
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr addrspace(5) [[VSP]], i32 -4
; CHECK-NEXT: [[CPS_STATE:%.*]] = load { i32 }, ptr addrspace(5) [[TMP8]], align 4
-; CHECK-NEXT: store ptr addrspace(5) [[TMP8]], ptr addrspace(5) [[TMP0]], align 4
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr addrspace(5) [[TMP8]] to i32
+; CHECK-NEXT: store i32 [[TMP9]], ptr addrspace(5) [[TMP0]], align 4
; CHECK-NEXT: [[V:%.*]] = extractvalue { i32 } [[CPS_STATE]], 0
; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[V]], 3
; CHECK-NEXT: br i1 [[COND]], label [[THEN:%.*]], label [[ELSE:%.*]]
@@ -69,68 +70,78 @@ else:
; CHECK-NEXT: [[THEN_ARG:%.*]] = add i32 [[ARG]], 1
; CHECK-NEXT: [[V_THEN:%.*]] = mul i32 [[V]], 2
; CHECK-NEXT: [[STATE_THEN:%.*]] = insertvalue { i32 } poison, i32 [[V_THEN]], 0
-; CHECK-NEXT: [[TMP9:%.*]] = load ptr addrspace(5), ptr addrspace(5) [[TMP0]], align 4
-; CHECK-NEXT: store { i32 } [[STATE_THEN]], ptr addrspace(5) [[TMP9]], align 4
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr addrspace(5) [[TMP9]], i32 4
+; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(5) [[TMP0]], align 4
+; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP10]] to ptr addrspace(5)
+; CHECK-NEXT: store { i32 } [[STATE_THEN]], ptr addrspace(5) [[TMP11]], align 4
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr addrspace(5) [[TMP11]], i32 4
; CHECK-NEXT: br label [[TAIL_BLOCK:%.*]]
; CHECK: else:
; CHECK-NEXT: [[TABLE_1:%.*]] = getelementptr i32, ptr [[TABLE]], i32 1
; CHECK-NEXT: [[CR_ELSE:%.*]] = load i32, ptr [[TABLE_1]], align 4
; CHECK-NEXT: [[ELSE_ARG:%.*]] = uitofp i32 [[ARG]] to float
-; CHECK-NEXT: [[TMP11:%.*]] = load ptr addrspace(5), ptr addrspace(5) [[TMP0]], align 4
-; CHECK-NEXT: [[TMP12:%.*]] = bitcast float [[ELSE_ARG]] to i32
+; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(5) [[TMP0]], align 4
+; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i32 [[TMP13]] to ptr addrspace(5)
+; CHECK-NEXT: [[TMP15:%.*]] = bitcast float [[ELSE_ARG]] to i32
; CHECK-NEXT: br label [[TAIL_BLOCK]]
; CHECK: tail.block:
-; CHECK-NEXT: [[TMP13:%.*]] = phi i32 [ [[CR_ELSE]], [[ELSE]] ], [ [[CR_THEN]], [[THEN]] ]
-; CHECK-NEXT: [[TMP14:%.*]] = phi ptr addrspace(5) [ [[TMP11]], [[ELSE]] ], [ [[TMP10]], [[THEN]] ]
-; CHECK-NEXT: [[TMP15:%.*]] = phi i32 [ [[TMP12]], [[ELSE]] ], [ [[THEN_ARG]], [[THEN]] ]
-; CHECK-NEXT: [[TMP16:%.*]] = phi i32 [ 5, [[ELSE]] ], [ poison, [[THEN]] ]
-; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { i32, ptr addrspace(5), i32, i32 } poison, i32 [[TMP13]], 0
-; CHECK-NEXT: [[TMP18:%.*]] = insertvalue { i32, ptr addrspace(5), i32, i32 } [[TMP17]], ptr addrspace(5) [[TMP14]], 1
-; CHECK-NEXT: [[TMP19:%.*]] = insertvalue { i32, ptr addrspace(5), i32, i32 } [[TMP18]], i32 [[TMP15]], 2
-; CHECK-NEXT: [[TMP20:%.*]] = insertvalue { i32, ptr addrspace(5), i32, i32 } [[TMP19]], i32 [[TMP16]], 3
-; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
-; CHECK-NEXT: [[TMP22:%.*]] = bitcast i64 [[TMP21]] to <2 x i32>
-; CHECK-NEXT: [[TMP23:%.*]] = extractelement <2 x i32> [[TMP22]], i64 0
-; CHECK-NEXT: [[TMP24:%.*]] = extractelement <2 x i32> [[TMP22]], i64 1
-; CHECK-NEXT: [[TMP25:%.*]] = insertelement <16 x i32> poison, i32 [[GLOBALTABLE]], i64 0
-; CHECK-NEXT: [[TMP26:%.*]] = insertelement <16 x i32> [[TMP25]], i32 [[TMP23]], i64 1
-; CHECK-NEXT: [[TMP27:%.*]] = insertelement <16 x i32> [[TMP26]], i32 [[TMP24]], i64 2
-; CHECK-NEXT: [[TMP28:%.*]] = insertelement <16 x i32> [[TMP27]], i32 [[PAD0]], i64 3
-; CHECK-NEXT: [[TMP29:%.*]] = insertelement <16 x i32> [[TMP28]], i32 [[PAD1]], i64 4
-; CHECK-NEXT: [[TMP30:%.*]] = insertelement <16 x i32> [[TMP29]], i32 [[PAD2]], i64 5
-; CHECK-NEXT: [[TMP31:%.*]] = insertelement <16 x i32> [[TMP30]], i32 [[PAD3]], i64 6
-; CHECK-NEXT: [[TMP32:%.*]] = insertelement <16 x i32> [[TMP31]], i32 [[PAD4]], i64 7
-; CHECK-NEXT: [[TMP33:%.*]] = insertelement <16 x i32> [[TMP32]], i32 [[PAD5]], i64 8
-; CHECK-NEXT: [[TMP34:%.*]] = insertelement <16 x i32> [[TMP33]], i32 [[PAD6]], i64 9
-; CHECK-NEXT: [[TMP35:%.*]] = insertelement <16 x i32> [[TMP34]], i32 [[PAD7]], i64 10
-; CHECK-NEXT: [[TMP36:%.*]] = insertelement <16 x i32> [[TMP35]], i32 [[PAD8]], i64 11
-; CHECK-NEXT: [[TMP37:%.*]] = insertelement <16 x i32> [[TMP36]], i32 [[PAD9]], i64 12
-; CHECK-NEXT: [[TMP38:%.*]] = insertelement <16 x i32> [[TMP37]], i32 [[PAD10]], i64 13
-; CHECK-NEXT: [[TMP39:%.*]] = insertelement <16 x i32> [[TMP38]], i32 [[PAD11]], i64 14
-; CHECK-NEXT: [[TMP40:%.*]] = insertelement <16 x i32> [[TMP39]], i32 [[SPILLTABLE]], i64 15
-; CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i32, ptr addrspace(5), i32, i32 } [[TMP20]], 0
-; CHECK-NEXT: [[TMP42:%.*]] = call i32 @llvm.amdgcn.set.inactive.{{(chain.arg.)?}}i32(i32 [[TMP41]], i32 [[VCR]])
-; CHECK-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
-; CHECK-NEXT: [[TMP44:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP43]])
-; CHECK-NEXT: [[TMP45:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP44]], i1 true)
-; CHECK-NEXT: [[TMP46:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP42]], i32 [[TMP45]])
-; CHECK-NEXT: [[TMP47:%.*]] = icmp eq i32 [[TMP42]], [[TMP46]]
-; CHECK-NEXT: [[TMP48:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP47]])
-; CHECK-NEXT: [[TMP49:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP46]])
-; CHECK-NEXT: [[TMP50:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP48]])
-; CHECK-NEXT: [[TMP51:%.*]] = and i32 [[TMP49]], -64
-; CHECK-NEXT: [[TMP52:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP51]], i64 0
-; CHECK-NEXT: [[TMP53:%.*]] = bitcast <2 x i32> [[TMP52]] to i64
-; CHECK-NEXT: [[TMP54:%.*]] = inttoptr i64 [[TMP53]] to ptr
-; CHECK-NEXT: call void (ptr, i32, <16 x i32>, { i32, ptr addrspace(5), i32, i32 }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v16i32.sl_i32p5i32i32s(ptr inreg [[TMP54]], i32 inreg [[TMP50]], <16 x i32> inreg [[TMP40]], { i32, ptr addrspace(5), i32, i32 } [[TMP20]], i32 0)
+; CHECK-NEXT: [[TMP16:%.*]] = phi i32 [ [[CR_ELSE]], [[ELSE]] ], [ [[CR_THEN]], [[THEN]] ]
+; CHECK-NEXT: [[TMP17:%.*]] = phi ptr addrspace(5) [ [[TMP14]], [[ELSE]] ], [ [[TMP12]], [[THEN]] ]
+; CHECK-NEXT: [[TMP18:%.*]] = phi i32 [ [[TMP15]], [[ELSE]] ], [ [[THEN_ARG]], [[THEN]] ]
+; CHECK-NEXT: [[TMP19:%.*]] = phi i32 [ 5, [[ELSE]] ], [ poison, [[THEN]] ]
+; CHECK-NEXT: [[TMP20:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } poison, <3 x i32> [[LOCALINVOCATIONID]], 0
+; CHECK-NEXT: [[TMP21:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP20]], i32 [[TMP16]], 1
+; CHECK-NEXT: [[TMP22:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP21]], ptr addrspace(5) [[TMP17]], 2
+; CHECK-NEXT: [[TMP23:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP22]], i32 [[TMP18]], 3
+; CHECK-NEXT: [[TMP24:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP23]], i32 [[TMP19]], 4
+; CHECK-NEXT: [[TMP25:%.*]] = extractvalue { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP24]], 1
+; CHECK-NEXT: [[TMP26:%.*]] = call i32 @llvm.amdgcn.set.inactive.chain.arg.i32(i32 [[TMP25]], i32 [[VCR]])
+; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
+; CHECK-NEXT: [[TMP28:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP27]])
+; CHECK-NEXT: [[TMP29:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP28]], i1 true)
+; CHECK-NEXT: [[TMP30:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP26]], i32 [[TMP29]])
+; CHECK-NEXT: [[TMP31:%.*]] = icmp eq i32 [[TMP26]], [[TMP30]]
+; CHECK-NEXT: [[TMP32:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP31]])
+; CHECK-NEXT: [[TMP33:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP30]])
+; CHECK-NEXT: [[TMP34:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP32]])
+; CHECK-NEXT: [[TMP35:%.*]] = and i32 [[TMP33]], -64
+; CHECK-NEXT: [[TMP36:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP35]], i64 0
+; CHECK-NEXT: [[TMP37:%.*]] = bitcast <2 x i32> [[TMP36]] to i64
+; CHECK-NEXT: [[TMP38:%.*]] = inttoptr i64 [[TMP37]] to ptr
+; CHECK-NEXT: [[TMP39:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
+; CHECK-NEXT: [[TMP40:%.*]] = bitcast i64 [[TMP39]] to <2 x i32>
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <2 x i32> [[TMP40]], i64 0
+; CHECK-NEXT: [[TMP42:%.*]] = extractelement <2 x i32> [[TMP40]], i64 1
+; CHECK-NEXT: [[TMP43:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 0
+; CHECK-NEXT: [[TMP44:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 1
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 2
+; CHECK-NEXT: [[TMP46:%.*]] = insertelement <20 x i32> poison, i32 [[GLOBALTABLE]], i64 0
+; CHECK-NEXT: [[TMP47:%.*]] = insertelement <20 x i32> [[TMP46]], i32 [[TMP41]], i64 1
+; CHECK-NEXT: [[TMP48:%.*]] = insertelement <20 x i32> [[TMP47]], i32 [[TMP42]], i64 2
+; CHECK-NEXT: [[TMP49:%.*]] = insertelement <20 x i32> [[TMP48]], i32 [[PAD0]], i64 3
+; CHECK-NEXT: [[TMP50:%.*]] = insertelement <20 x i32> [[TMP49]], i32 [[PAD1]], i64 4
+; CHECK-NEXT: [[TMP51:%.*]] = insertelement <20 x i32> [[TMP50]], i32 [[PAD2]], i64 5
+; CHECK-NEXT: [[TMP52:%.*]] = insertelement <20 x i32> [[TMP51]], i32 [[PAD3]], i64 6
+; CHECK-NEXT: [[TMP53:%.*]] = insertelement <20 x i32> [[TMP52]], i32 [[PAD4]], i64 7
+; CHECK-NEXT: [[TMP54:%.*]] = insertelement <20 x i32> [[TMP53]], i32 [[PAD5]], i64 8
+; CHECK-NEXT: [[TMP55:%.*]] = insertelement <20 x i32> [[TMP54]], i32 [[PAD6]], i64 9
+; CHECK-NEXT: [[TMP56:%.*]] = insertelement <20 x i32> [[TMP55]], i32 [[PAD7]], i64 10
+; CHECK-NEXT: [[TMP57:%.*]] = insertelement <20 x i32> [[TMP56]], i32 [[PAD8]], i64 11
+; CHECK-NEXT: [[TMP58:%.*]] = insertelement <20 x i32> [[TMP57]], i32 [[PAD9]], i64 12
+; CHECK-NEXT: [[TMP59:%.*]] = insertelement <20 x i32> [[TMP58]], i32 [[PAD10]], i64 13
+; CHECK-NEXT: [[TMP60:%.*]] = insertelement <20 x i32> [[TMP59]], i32 [[PAD11]], i64 14
+; CHECK-NEXT: [[TMP61:%.*]] = insertelement <20 x i32> [[TMP60]], i32 [[SPILLTABLE]], i64 15
+; CHECK-NEXT: [[TMP62:%.*]] = insertelement <20 x i32> [[TMP61]], i32 [[TMP43]], i64 16
+; CHECK-NEXT: [[TMP63:%.*]] = insertelement <20 x i32> [[TMP62]], i32 [[TMP44]], i64 17
+; CHECK-NEXT: [[TMP64:%.*]] = insertelement <20 x i32> [[TMP63]], i32 [[TMP45]], i64 18
+; CHECK-NEXT: [[TMP65:%.*]] = insertelement <20 x i32> [[TMP64]], i32 [[MULTIDISPATCHINFO]], i64 19
+; CHECK-NEXT: call void (ptr, i32, <20 x i32>, { <3 x i32>, i32, ptr addrspace(5), i32, i32 }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v20i32.sl_v3i32i32p5i32i32s(ptr inreg [[TMP38]], i32 inreg [[TMP34]], <20 x i32> inreg [[TMP65]], { <3 x i32>, i32, ptr addrspace(5), i32, i32 } [[TMP24]], i32 0)
; CHECK-NEXT: unreachable
;
;
; CHECK-LABEL: define {{[^@]+}}@unify_jump_ret
-; CHECK-SAME: (i32 inreg [[GLOBALTABLE:%.*]], ptr addrspace(4) inreg [[NUMWORKGROUPSPTR:%.*]], i32 inreg [[PAD0:%.*]], i32 inreg [[PAD1:%.*]], i32 inreg [[PAD2:%.*]], i32 inreg [[PAD3:%.*]], i32 inreg [[PAD4:%.*]], i32 inreg [[PAD5:%.*]], i32 inreg [[PAD6:%.*]], i32 inreg [[PAD7:%.*]], i32 inreg [[PAD8:%.*]], i32 inreg [[PAD9:%.*]], i32 inreg [[PAD10:%.*]], i32 inreg [[PAD11:%.*]], i32 inreg [[SPILLTABLE:%.*]], i32 [[VCR:%.*]], ptr addrspace(5) [[VSP:%.*]], i32 [[ARG:%.*]], ptr [[TABLE:%.*]]) #[[ATTR1]] align 64 !lgc.cps !2 !lgc.shaderstage !3 {
+; CHECK-SAME: (i32 inreg [[GLOBALTABLE:%.*]], ptr addrspace(4) inreg [[NUMWORKGROUPSPTR:%.*]], i32 inreg [[PAD0:%.*]], i32 inreg [[PAD1:%.*]], i32 inreg [[PAD2:%.*]], i32 inreg [[PAD3:%.*]], i32 inreg [[PAD4:%.*]], i32 inreg [[PAD5:%.*]], i32 inreg [[PAD6:%.*]], i32 inreg [[PAD7:%.*]], i32 inreg [[PAD8:%.*]], i32 inreg [[PAD9:%.*]], i32 inreg [[PAD10:%.*]], i32 inreg [[PAD11:%.*]], i32 inreg [[SPILLTABLE:%.*]], <3 x i32> inreg [[WORKGROUPID:%.*]], i32 inreg [[MULTIDISPATCHINFO:%.*]], <3 x i32> [[LOCALINVOCATIONID:%.*]], i32 [[VCR:%.*]], ptr addrspace(5) [[VSP:%.*]], i32 [[ARG:%.*]], ptr [[TABLE:%.*]]) #[[ATTR1]] align 64 !lgc.cps !2 !lgc.shaderstage !3 {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+; CHECK-NEXT: [[TMP0:%.*]] = alloca i32, align 4, addrspace(5)
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.amdgcn.s.getpc()
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[TMP1]] to <2 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[SPILLTABLE]], i64 0
@@ -140,7 +151,8 @@ else:
; CHECK-NEXT: [[TMP7:%.*]] = bitcast i64 [[TMP6]] to <2 x i32>
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr addrspace(5) [[VSP]], i32 -4
; CHECK-NEXT: [[CPS_STATE:%.*]] = load { i32 }, ptr addrspace(5) [[TMP8]], align 4
-; CHECK-NEXT: store ptr addrspace(5) [[TMP8]], ptr addrspace(5) [[TMP0]], align 4
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr addrspace(5) [[TMP8]] to i32
+; CHECK-NEXT: store i32 [[TMP9]], ptr addrspace(5) [[TMP0]], align 4
; CHECK-NEXT: [[V:%.*]] = extractvalue { i32 } [[CPS_STATE]], 0
; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[V]], 3
; CHECK-NEXT: br i1 [[COND]], label [[THEN:%.*]], label [[ELSE:%.*]]
@@ -150,57 +162,66 @@ else:
; CHECK-NEXT: [[THEN_ARG:%.*]] = add i32 [[ARG]], 1
; CHECK-NEXT: [[V_THEN:%.*]] = mul i32 [[V]], 2
; CHECK-NEXT: [[STATE_THEN:%.*]] = insertvalue { i32 } poison, i32 [[V_THEN]], 0
-; CHECK-NEXT: [[TMP9:%.*]] = load ptr addrspace(5), ptr addrspace(5) [[TMP0]], align 4
-; CHECK-NEXT: store { i32 } [[STATE_THEN]], ptr addrspace(5) [[TMP9]], align 4
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr addrspace(5) [[TMP9]], i32 4
+; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(5) [[TMP0]], align 4
+; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP10]] to ptr addrspace(5)
+; CHECK-NEXT: store { i32 } [[STATE_THEN]], ptr addrspace(5) [[TMP11]], align 4
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr addrspace(5) [[TMP11]], i32 4
; CHECK-NEXT: br label [[TAIL_BLOCK:%.*]]
; CHECK: else:
; CHECK-NEXT: br label [[TAIL_BLOCK]]
; CHECK: tail.block:
-; CHECK-NEXT: [[TMP11:%.*]] = phi i32 [ [[CR_THEN]], [[THEN]] ], [ 0, [[ELSE]] ]
-; CHECK-NEXT: [[TMP12:%.*]] = phi ptr addrspace(5) [ [[TMP10]], [[THEN]] ], [ poison, [[ELSE]] ]
-; CHECK-NEXT: [[TMP13:%.*]] = phi i32 [ [[THEN_ARG]], [[THEN]] ], [ poison, [[ELSE]] ]
-; CHECK-NEXT: [[TMP14:%.*]] = insertvalue { i32, ptr addrspace(5), i32 } poison, i32 [[TMP11]], 0
-; CHECK-NEXT: [[TMP15:%.*]] = insertvalue { i32, ptr addrspace(5), i32 } [[TMP14]], ptr addrspace(5) [[TMP12]], 1
-; CHECK-NEXT: [[TMP16:%.*]] = insertvalue { i32, ptr addrspace(5), i32 } [[TMP15]], i32 [[TMP13]], 2
-; CHECK-NEXT: [[TMP17:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
-; CHECK-NEXT: [[TMP18:%.*]] = bitcast i64 [[TMP17]] to <2 x i32>
-; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x i32> [[TMP18]], i64 0
-; CHECK-NEXT: [[TMP20:%.*]] = extractelement <2 x i32> [[TMP18]], i64 1
-; CHECK-NEXT: [[TMP21:%.*]] = insertelement <16 x i32> poison, i32 [[GLOBALTABLE]], i64 0
-; CHECK-NEXT: [[TMP22:%.*]] = insertelement <16 x i32> [[TMP21]], i32 [[TMP19]], i64 1
-; CHECK-NEXT: [[TMP23:%.*]] = insertelement <16 x i32> [[TMP22]], i32 [[TMP20]], i64 2
-; CHECK-NEXT: [[TMP24:%.*]] = insertelement <16 x i32> [[TMP23]], i32 [[PAD0]], i64 3
-; CHECK-NEXT: [[TMP25:%.*]] = insertelement <16 x i32> [[TMP24]], i32 [[PAD1]], i64 4
-; CHECK-NEXT: [[TMP26:%.*]] = insertelement <16 x i32> [[TMP25]], i32 [[PAD2]], i64 5
-; CHECK-NEXT: [[TMP27:%.*]] = insertelement <16 x i32> [[TMP26]], i32 [[PAD3]], i64 6
-; CHECK-NEXT: [[TMP28:%.*]] = insertelement <16 x i32> [[TMP27]], i32 [[PAD4]], i64 7
-; CHECK-NEXT: [[TMP29:%.*]] = insertelement <16 x i32> [[TMP28]], i32 [[PAD5]], i64 8
-; CHECK-NEXT: [[TMP30:%.*]] = insertelement <16 x i32> [[TMP29]], i32 [[PAD6]], i64 9
-; CHECK-NEXT: [[TMP31:%.*]] = insertelement <16 x i32> [[TMP30]], i32 [[PAD7]], i64 10
-; CHECK-NEXT: [[TMP32:%.*]] = insertelement <16 x i32> [[TMP31]], i32 [[PAD8]], i64 11
-; CHECK-NEXT: [[TMP33:%.*]] = insertelement <16 x i32> [[TMP32]], i32 [[PAD9]], i64 12
-; CHECK-NEXT: [[TMP34:%.*]] = insertelement <16 x i32> [[TMP33]], i32 [[PAD10]], i64 13
-; CHECK-NEXT: [[TMP35:%.*]] = insertelement <16 x i32> [[TMP34]], i32 [[PAD11]], i64 14
-; CHECK-NEXT: [[TMP36:%.*]] = insertelement <16 x i32> [[TMP35]], i32 [[SPILLTABLE]], i64 15
-; CHECK-NEXT: [[TMP37:%.*]] = extractvalue { i32, ptr addrspace(5), i32 } [[TMP16]], 0
-; CHECK-NEXT: [[TMP38:%.*]] = call i32 @llvm.amdgcn.set.inactive.{{(chain.arg.)?}}i32(i32 [[TMP37]], i32 [[VCR]])
-; CHECK-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0
-; CHECK-NEXT: [[TMP40:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP39]])
-; CHECK-NEXT: [[TMP41:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP40]], i1 true)
-; CHECK-NEXT: [[TMP42:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP38]], i32 [[TMP41]])
-; CHECK-NEXT: [[TMP43:%.*]] = icmp eq i32 [[TMP38]], [[TMP42]]
-; CHECK-NEXT: [[TMP44:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP43]])
-; CHECK-NEXT: [[TMP45:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP42]])
-; CHECK-NEXT: [[TMP46:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP44]])
-; CHECK-NEXT: [[TMP47:%.*]] = icmp eq i32 [[TMP45]], 0
-; CHECK-NEXT: br i1 [[TMP47]], label [[RET_BLOCK:%.*]], label [[CHAIN_BLOCK:%.*]]
+; CHECK-NEXT: [[TMP13:%.*]] = phi i32 [ [[CR_THEN]], [[THEN]] ], [ 0, [[ELSE]] ]
+; CHECK-NEXT: [[TMP14:%.*]] = phi ptr addrspace(5) [ [[TMP12]], [[THEN]] ], [ poison, [[ELSE]] ]
+; CHECK-NEXT: [[TMP15:%.*]] = phi i32 [ [[THEN_ARG]], [[THEN]] ], [ poison, [[ELSE]] ]
+; CHECK-NEXT: [[TMP16:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32 } poison, <3 x i32> [[LOCALINVOCATIONID]], 0
+; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32 } [[TMP16]], i32 [[TMP13]], 1
+; CHECK-NEXT: [[TMP18:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32 } [[TMP17]], ptr addrspace(5) [[TMP14]], 2
+; CHECK-NEXT: [[TMP19:%.*]] = insertvalue { <3 x i32>, i32, ptr addrspace(5), i32 } [[TMP18]], i32 [[TMP15]], 3
+; CHECK-NEXT: [[TMP20:%.*]] = extractvalue { <3 x i32>, i32, ptr addrspace(5), i32 } [[TMP19]], 1
+; CHECK-NEXT: [[TMP21:%.*]] = call i32 @llvm.amdgcn.set.inactive.chain.arg.i32(i32 [[TMP20]], i32 [[VCR]])
+; CHECK-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
+; CHECK-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP22]])
+; CHECK-NEXT: [[TMP24:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP23]], i1 true)
+; CHECK-NEXT: [[TMP25:%.*]] = call i32 @llvm.amdgcn.readlane(i32 [[TMP21]], i32 [[TMP24]])
+; CHECK-NEXT: [[TMP26:%.*]] = icmp eq i32 [[TMP21]], [[TMP25]]
+; CHECK-NEXT: [[TMP27:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP26]])
+; CHECK-NEXT: [[TMP28:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP25]])
+; CHECK-NEXT: [[TMP29:%.*]] = call i32 @llvm.amdgcn.wwm.i32(i32 [[TMP27]])
+; CHECK-NEXT: [[TMP30:%.*]] = icmp eq i32 [[TMP28]], 0
+; CHECK-NEXT: br i1 [[TMP30]], label [[RET_BLOCK:%.*]], label [[CHAIN_BLOCK:%.*]]
; CHECK: chain.block:
-; CHECK-NEXT: [[TMP48:%.*]] = and i32 [[TMP45]], -64
-; CHECK-NEXT: [[TMP49:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP48]], i64 0
-; CHECK-NEXT: [[TMP50:%.*]] = bitcast <2 x i32> [[TMP49]] to i64
-; CHECK-NEXT: [[TMP51:%.*]] = inttoptr i64 [[TMP50]] to ptr
-; CHECK-NEXT: call void (ptr, i32, <16 x i32>, { i32, ptr addrspace(5), i32 }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v16i32.sl_i32p5i32s(ptr inreg [[TMP51]], i32 inreg [[TMP46]], <16 x i32> inreg [[TMP36]], { i32, ptr addrspace(5), i32 } [[TMP16]], i32 0)
+; CHECK-NEXT: [[TMP31:%.*]] = and i32 [[TMP28]], -64
+; CHECK-NEXT: [[TMP32:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP31]], i64 0
+; CHECK-NEXT: [[TMP33:%.*]] = bitcast <2 x i32> [[TMP32]] to i64
+; CHECK-NEXT: [[TMP34:%.*]] = inttoptr i64 [[TMP33]] to ptr
+; CHECK-NEXT: [[TMP35:%.*]] = ptrtoint ptr addrspace(4) [[NUMWORKGROUPSPTR]] to i64
+; CHECK-NEXT: [[TMP36:%.*]] = bitcast i64 [[TMP35]] to <2 x i32>
+; CHECK-NEXT: [[TMP37:%.*]] = extractelement <2 x i32> [[TMP36]], i64 0
+; CHECK-NEXT: [[TMP38:%.*]] = extractelement <2 x i32> [[TMP36]], i64 1
+; CHECK-NEXT: [[TMP39:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 0
+; CHECK-NEXT: [[TMP40:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 1
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <3 x i32> [[WORKGROUPID]], i64 2
+; CHECK-NEXT: [[TMP42:%.*]] = insertelement <20 x i32> poison, i32 [[GLOBALTABLE]], i64 0
+; CHECK-NEXT: [[TMP43:%.*]] = insertelement <20 x i32> [[TMP42]], i32 [[TMP37]], i64 1
+; CHECK-NEXT: [[TMP44:%.*]] = insertelement <20 x i32> [[TMP43]], i32 [[TMP38]], i64 2
+; CHECK-NEXT: [[TMP45:%.*]] = insertelement <20 x i32> [[TMP44]], i32 [[PAD0]], i64 3
+; CHECK-NEXT: [[TMP46:%.*]] = insertelement <20 x i32> [[TMP45]], i32 [[PAD1]], i64 4
+; CHECK-NEXT: [[TMP47:%.*]] = insertelement <20 x i32> [[TMP46]], i32 [[PAD2]], i64 5
+; CHECK-NEXT: [[TMP48:%.*]] = insertelement <20 x i32> [[TMP47]], i32 [[PAD3]], i64 6
+; CHECK-NEXT: [[TMP49:%.*]] = insertelement <20 x i32> [[TMP48]], i32 [[PAD4]], i64 7
+; CHECK-NEXT: [[TMP50:%.*]] = insertelement <20 x i32> [[TMP49]], i32 [[PAD5]], i64 8
+; CHECK-NEXT: [[TMP51:%.*]] = insertelement <20 x i32> [[TMP50]], i32 [[PAD6]], i64 9
+; CHECK-NEXT: [[TMP52:%.*]] = insertelement <20 x i32> [[TMP51]], i32 [[PAD7]], i64 10
+; CHECK-NEXT: [[TMP53:%.*]] = insertelement <20 x i32> [[TMP52]], i32 [[PAD8]], i64 11
+; CHECK-NEXT: [[TMP54:%.*]] = insertelement <20 x i32> [[TMP53]], i32 [[PAD9]], i64 12
+; CHECK-NEXT: [[TMP55:%.*]] = insertelement <20 x i32> [[TMP54]], i32 [[PAD10]], i64 13
+; CHECK-NEXT: [[TMP56:%.*]] = insertelement <20 x i32> [[TMP55]], i32 [[PAD11]], i64 14
+; CHECK-NEXT: [[TMP57:%.*]] = insertelement <20 x i32> [[TMP56]], i32 [[SPILLTABLE]], i64 15
+; CHECK-NEXT: [[TMP58:%.*]] = insertelement <20 x i32> [[TMP57]], i32 [[TMP39]], i64 16
+; CHECK-NEXT: [[TMP59:%.*]] = insertelement <20 x i32> [[TMP58]], i32 [[TMP40]], i64 17
+; CHECK-NEXT: [[TMP60:%.*]] = insertelement <20 x i32> [[TMP59]], i32 [[TMP41]], i64 18
+; CHECK-NEXT: [[TMP61:%.*]] = insertelement <20 x i32> [[TMP60]], i32 [[MULTIDISPATCHINFO]], i64 19
+; CHECK-NEXT: call void (ptr, i32, <20 x i32>, { <3 x i32>, i32, ptr addrspace(5), i32 }, i32, ...) @llvm.amdgcn.cs.chain.p0.i32.v20i32.sl_v3i32i32p5i32s(ptr inreg [[TMP34]], i32 inreg [[TMP29]], <20 x i32> inreg [[TMP61]], { <3 x i32>, i32, ptr addrspace(5), i32 } [[TMP19]], i32 0)
; CHECK-NEXT: unreachable
; CHECK: ret.block:
; CHECK-NEXT: ret void
diff --git a/lgc/test/Transforms/PatchBufferOp/strided-buffer-ops.lgc b/lgc/test/Transforms/PatchBufferOp/strided-buffer-ops.lgc
new file mode 100644
index 0000000000..843fdbf3ba
--- /dev/null
+++ b/lgc/test/Transforms/PatchBufferOp/strided-buffer-ops.lgc
@@ -0,0 +1,271 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --tool lgc --version 2
+; RUN: lgc --mcpu=gfx1100 -o - -passes='require<lgc-pipeline-state>,function(lgc-patch-buffer-op)' %s | FileCheck --check-prefixes=GFX11 %s
+
+define amdgpu_kernel void @strided_buffer_desc_to_ptr(<4 x i32> inreg %desc, ptr %out) {
+; GFX11-LABEL: define amdgpu_kernel void @strided_buffer_desc_to_ptr
+; GFX11-SAME: (<4 x i32> inreg [[DESC:%.*]], ptr [[OUT:%.*]]) {
+; GFX11-NEXT: entry:
+; GFX11-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32> [[DESC]], i32 0, i32 0, i32 0, i32 0)
+; GFX11-NEXT: [[TMP1:%.*]] = bitcast i32 [[TMP0]] to float
+; GFX11-NEXT: store float [[TMP1]], ptr [[OUT]], align 4
+; GFX11-NEXT: ret void
+;
+entry:
+ %buf = call ptr addrspace(9) @lgc.strided.buffer.desc.to.ptr(<4 x i32> %desc)
+ %res = load float, ptr addrspace(9) %buf, align 4
+ store float %res, ptr %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @strided_buffer_desc_to_ptr_index(<4 x i32> inreg %desc, i32 %index, ptr %out) {
+; GFX11-LABEL: define amdgpu_kernel void @strided_buffer_desc_to_ptr_index
+; GFX11-SAME: (<4 x i32> inreg [[DESC:%.*]], i32 [[INDEX:%.*]], ptr [[OUT:%.*]]) {
+; GFX11-NEXT: entry:
+; GFX11-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32> [[DESC]], i32 [[INDEX]], i32 0, i32 0, i32 0)
+; GFX11-NEXT: [[TMP1:%.*]] = bitcast i32 [[TMP0]] to float
+; GFX11-NEXT: store float [[TMP1]], ptr [[OUT]], align 4
+; GFX11-NEXT: ret void
+;
+entry:
+ %buf = call ptr addrspace(9) @lgc.strided.buffer.desc.to.ptr(<4 x i32> %desc)
+ %buf.idx = call ptr addrspace(9) @lgc.strided.index.add(ptr addrspace(9) %buf, i32 %index)
+ %res = load float, ptr addrspace(9) %buf.idx, align 4
+ store float %res, ptr %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @strided_buffer_desc_to_ptr_index_offset(<4 x i32> inreg %desc, i32 %index, ptr %out) {
+; GFX11-LABEL: define amdgpu_kernel void @strided_buffer_desc_to_ptr_index_offset
+; GFX11-SAME: (<4 x i32> inreg [[DESC:%.*]], i32 [[INDEX:%.*]], ptr [[OUT:%.*]]) {
+; GFX11-NEXT: entry:
+; GFX11-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32> [[DESC]], i32 [[INDEX]], i32 ptrtoint (ptr addrspace(6) getelementptr inbounds (i8, ptr addrspace(6) null, i32 8) to i32), i32 0, i32 0)
+; GFX11-NEXT: [[TMP1:%.*]] = bitcast i32 [[TMP0]] to float
+; GFX11-NEXT: store float [[TMP1]], ptr [[OUT]], align 4
+; GFX11-NEXT: ret void
+;
+entry:
+ %buf = call ptr addrspace(9) @lgc.strided.buffer.desc.to.ptr(<4 x i32> %desc)
+ %buf.idx = call ptr addrspace(9) @lgc.strided.index.add(ptr addrspace(9) %buf, i32 %index)
+ %buf.off = getelementptr inbounds i8, ptr addrspace(9) %buf.idx, i32 8
+ %res = load float, ptr addrspace(9) %buf.off, align 4
+ store float %res, ptr %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @strided_buffer_desc_to_ptr_index_add_zero(<4 x i32> inreg %desc, ptr %out) {
+; GFX11-LABEL: define amdgpu_kernel void @strided_buffer_desc_to_ptr_index_add_zero
+; GFX11-SAME: (<4 x i32> inreg [[DESC:%.*]], ptr [[OUT:%.*]]) {
+; GFX11-NEXT: entry:
+; GFX11-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32> [[DESC]], i32 0, i32 0, i32 0, i32 0)
+; GFX11-NEXT: [[TMP1:%.*]] = bitcast i32 [[TMP0]] to float
+; GFX11-NEXT: store float [[TMP1]], ptr [[OUT]], align 4
+; GFX11-NEXT: ret void
+;
+entry:
+ %buf = call ptr addrspace(9) @lgc.strided.buffer.desc.to.ptr(<4 x i32> %desc)
+ %buf.idx = call ptr addrspace(9) @lgc.strided.index.add(ptr addrspace(9) %buf, i32 0)
+ %res = load float, ptr addrspace(9) %buf.idx, align 4
+ store float %res, ptr %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @strided_buffer_desc_to_ptr_index_add_twice(<4 x i32> inreg %desc, i32 %index, ptr %out) {
+; GFX11-LABEL: define amdgpu_kernel void @strided_buffer_desc_to_ptr_index_add_twice
+; GFX11-SAME: (<4 x i32> inreg [[DESC:%.*]], i32 [[INDEX:%.*]], ptr [[OUT:%.*]]) {
+; GFX11-NEXT: entry:
+; GFX11-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], [[INDEX]]
+; GFX11-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32> [[DESC]], i32 [[TMP0]], i32 0, i32 0, i32 0)
+; GFX11-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to float
+; GFX11-NEXT: store float [[TMP2]], ptr [[OUT]], align 4
+; GFX11-NEXT: ret void
+;
+entry:
+ %buf = call ptr addrspace(9) @lgc.strided.buffer.desc.to.ptr(<4 x i32> %desc)
+ %buf.idx = call ptr addrspace(9) @lgc.strided.index.add(ptr addrspace(9) %buf, i32 %index)
+ %buf.idx.2 = call ptr addrspace(9) @lgc.strided.index.add(ptr addrspace(9) %buf.idx, i32 %index)
+ %res = load float, ptr addrspace(9) %buf.idx.2, align 4
+ store float %res, ptr %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @strided_buffer_desc_to_ptr_index_add_twice_constant_new(<4 x i32> inreg %desc, i32 %index, ptr %out) {
+; GFX11-LABEL: define amdgpu_kernel void @strided_buffer_desc_to_ptr_index_add_twice_constant_new
+; GFX11-SAME: (<4 x i32> inreg [[DESC:%.*]], i32 [[INDEX:%.*]], ptr [[OUT:%.*]]) {
+; GFX11-NEXT: entry:
+; GFX11-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 4
+; GFX11-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32> [[DESC]], i32 [[TMP0]], i32 0, i32 0, i32 0)
+; GFX11-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to float
+; GFX11-NEXT: store float [[TMP2]], ptr [[OUT]], align 4
+; GFX11-NEXT: ret void
+;
+entry:
+ %buf = call ptr addrspace(9) @lgc.strided.buffer.desc.to.ptr(<4 x i32> %desc)
+ %buf.idx = call ptr addrspace(9) @lgc.strided.index.add(ptr addrspace(9) %buf, i32 %index)
+ %buf.idx.2 = call ptr addrspace(9) @lgc.strided.index.add(ptr addrspace(9) %buf.idx, i32 4)
+ %res = load float, ptr addrspace(9) %buf.idx.2, align 4
+ store float %res, ptr %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @strided_buffer_desc_to_ptr_index_add_twice_constant_old(<4 x i32> inreg %desc, i32 %index, ptr %out) {
+; GFX11-LABEL: define amdgpu_kernel void @strided_buffer_desc_to_ptr_index_add_twice_constant_old
+; GFX11-SAME: (<4 x i32> inreg [[DESC:%.*]], i32 [[INDEX:%.*]], ptr [[OUT:%.*]]) {
+; GFX11-NEXT: entry:
+; GFX11-NEXT: [[TMP0:%.*]] = add i32 4, [[INDEX]]
+; GFX11-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32> [[DESC]], i32 [[TMP0]], i32 0, i32 0, i32 0)
+; GFX11-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to float
+; GFX11-NEXT: store float [[TMP2]], ptr [[OUT]], align 4
+; GFX11-NEXT: ret void
+;
+entry:
+ %buf = call ptr addrspace(9) @lgc.strided.buffer.desc.to.ptr(<4 x i32> %desc)
+ %buf.idx = call ptr addrspace(9) @lgc.strided.index.add(ptr addrspace(9) %buf, i32 4)
+ %buf.idx.2 = call ptr addrspace(9) @lgc.strided.index.add(ptr addrspace(9) %buf.idx, i32 %index)
+ %res = load float, ptr addrspace(9) %buf.idx.2, align 4
+ store float %res, ptr %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @strided_buffer_desc_to_ptr_index_add_twice_constant_both(<4 x i32> inreg %desc, ptr %out) {
+; GFX11-LABEL: define amdgpu_kernel void @strided_buffer_desc_to_ptr_index_add_twice_constant_both
+; GFX11-SAME: (<4 x i32> inreg [[DESC:%.*]], ptr [[OUT:%.*]]) {
+; GFX11-NEXT: entry:
+; GFX11-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32> [[DESC]], i32 6, i32 0, i32 0, i32 0)
+; GFX11-NEXT: [[TMP1:%.*]] = bitcast i32 [[TMP0]] to float
+; GFX11-NEXT: store float [[TMP1]], ptr [[OUT]], align 4
+; GFX11-NEXT: ret void
+;
+entry:
+ %buf = call ptr addrspace(9) @lgc.strided.buffer.desc.to.ptr(<4 x i32> %desc)
+ %buf.idx = call ptr addrspace(9) @lgc.strided.index.add(ptr addrspace(9) %buf, i32 4)
+ %buf.idx.2 = call ptr addrspace(9) @lgc.strided.index.add(ptr addrspace(9) %buf.idx, i32 2)
+ %res = load float, ptr addrspace(9) %buf.idx.2, align 4
+ store float %res, ptr %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @strided_buffer_desc_to_ptr_offset_index(<4 x i32> inreg %desc, i32 %index, ptr %out) {
+; GFX11-LABEL: define amdgpu_kernel void @strided_buffer_desc_to_ptr_offset_index
+; GFX11-SAME: (<4 x i32> inreg [[DESC:%.*]], i32 [[INDEX:%.*]], ptr [[OUT:%.*]]) {
+; GFX11-NEXT: entry:
+; GFX11-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32> [[DESC]], i32 [[INDEX]], i32 ptrtoint (ptr addrspace(6) getelementptr inbounds (i8, ptr addrspace(6) null, i32 8) to i32), i32 0, i32 0)
+; GFX11-NEXT: [[TMP1:%.*]] = bitcast i32 [[TMP0]] to float
+; GFX11-NEXT: store float [[TMP1]], ptr [[OUT]], align 4
+; GFX11-NEXT: ret void
+;
+entry:
+ %buf = call ptr addrspace(9) @lgc.strided.buffer.desc.to.ptr(<4 x i32> %desc)
+ %buf.off = getelementptr inbounds i8, ptr addrspace(9) %buf, i32 8
+ %buf.idx = call ptr addrspace(9) @lgc.strided.index.add(ptr addrspace(9) %buf.off, i32 %index)
+ %res = load float, ptr addrspace(9) %buf.idx, align 4
+ store float %res, ptr %out, align 4
+ ret void
+}
+
+define float @addr_and_stride_to_ptr(i64 %addr, i32 %stride) {
+; GFX11-LABEL: define float @addr_and_stride_to_ptr
+; GFX11-SAME: (i64 [[ADDR:%.*]], i32 [[STRIDE:%.*]]) {
+; GFX11-NEXT: entry:
+; GFX11-NEXT: [[TMP0:%.*]] = trunc i64 [[ADDR]] to i32
+; GFX11-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0
+; GFX11-NEXT: [[TMP2:%.*]] = lshr i64 [[ADDR]], 32
+; GFX11-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32
+; GFX11-NEXT: [[TMP4:%.*]] = shl i32 [[STRIDE]], 16
+; GFX11-NEXT: [[TMP5:%.*]] = or i32 [[TMP3]], [[TMP4]]
+; GFX11-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[TMP5]], i64 1
+; GFX11-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 -1, i64 2
+; GFX11-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP7]], i32 536956844, i64 3
+; GFX11-NEXT: [[TMP9:%.*]] = call i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32> [[TMP8]], i32 0, i32 0, i32 0, i32 0)
+; GFX11-NEXT: [[TMP10:%.*]] = bitcast i32 [[TMP9]] to float
+; GFX11-NEXT: ret float [[TMP10]]
+;
+entry:
+ %buf = call ptr addrspace(9) @lgc.strided.buffer.addr.and.stride.to.ptr(i64 %addr, i32 %stride)
+ %res = load float, ptr addrspace(9) %buf, align 4
+ ret float %res
+}
+
+define float @addr_and_stride_to_ptr_index(i64 %addr, i32 %index, i32 %stride) {
+; GFX11-LABEL: define float @addr_and_stride_to_ptr_index
+; GFX11-SAME: (i64 [[ADDR:%.*]], i32 [[INDEX:%.*]], i32 [[STRIDE:%.*]]) {
+; GFX11-NEXT: entry:
+; GFX11-NEXT: [[TMP0:%.*]] = trunc i64 [[ADDR]] to i32
+; GFX11-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0
+; GFX11-NEXT: [[TMP2:%.*]] = lshr i64 [[ADDR]], 32
+; GFX11-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32
+; GFX11-NEXT: [[TMP4:%.*]] = shl i32 [[STRIDE]], 16
+; GFX11-NEXT: [[TMP5:%.*]] = or i32 [[TMP3]], [[TMP4]]
+; GFX11-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[TMP5]], i64 1
+; GFX11-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 -1, i64 2
+; GFX11-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP7]], i32 536956844, i64 3
+; GFX11-NEXT: [[TMP9:%.*]] = call i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32> [[TMP8]], i32 [[INDEX]], i32 0, i32 0, i32 0)
+; GFX11-NEXT: [[TMP10:%.*]] = bitcast i32 [[TMP9]] to float
+; GFX11-NEXT: ret float [[TMP10]]
+;
+entry:
+ %buf = call ptr addrspace(9) @lgc.strided.buffer.addr.and.stride.to.ptr(i64 %addr, i32 %stride)
+ %buf.idx = call ptr addrspace(9) @lgc.strided.index.add(ptr addrspace(9) %buf, i32 %index)
+ %res = load float, ptr addrspace(9) %buf.idx, align 4
+ ret float %res
+}
+
+define float @addr_and_stride_to_ptr_index_offset(i64 %addr, i32 %index, i32 %stride) {
+; GFX11-LABEL: define float @addr_and_stride_to_ptr_index_offset
+; GFX11-SAME: (i64 [[ADDR:%.*]], i32 [[INDEX:%.*]], i32 [[STRIDE:%.*]]) {
+; GFX11-NEXT: entry:
+; GFX11-NEXT: [[TMP0:%.*]] = trunc i64 [[ADDR]] to i32
+; GFX11-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0
+; GFX11-NEXT: [[TMP2:%.*]] = lshr i64 [[ADDR]], 32
+; GFX11-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32
+; GFX11-NEXT: [[TMP4:%.*]] = shl i32 [[STRIDE]], 16
+; GFX11-NEXT: [[TMP5:%.*]] = or i32 [[TMP3]], [[TMP4]]
+; GFX11-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[TMP5]], i64 1
+; GFX11-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 -1, i64 2
+; GFX11-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP7]], i32 536956844, i64 3
+; GFX11-NEXT: [[TMP9:%.*]] = call i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32> [[TMP8]], i32 [[INDEX]], i32 ptrtoint (ptr addrspace(6) getelementptr inbounds (i8, ptr addrspace(6) null, i32 8) to i32), i32 0, i32 0)
+; GFX11-NEXT: [[TMP10:%.*]] = bitcast i32 [[TMP9]] to float
+; GFX11-NEXT: ret float [[TMP10]]
+;
+entry:
+ %buf = call ptr addrspace(9) @lgc.strided.buffer.addr.and.stride.to.ptr(i64 %addr, i32 %stride)
+ %buf.idx = call ptr addrspace(9) @lgc.strided.index.add(ptr addrspace(9) %buf, i32 %index)
+ %buf.offs = getelementptr inbounds i8, ptr addrspace(9) %buf.idx, i32 8
+ %res = load float, ptr addrspace(9) %buf.offs, align 4
+ ret float %res
+}
+
+define float @addr_and_stride_to_ptr_offset_index(i64 %addr, i32 %index, i32 %stride) {
+; GFX11-LABEL: define float @addr_and_stride_to_ptr_offset_index
+; GFX11-SAME: (i64 [[ADDR:%.*]], i32 [[INDEX:%.*]], i32 [[STRIDE:%.*]]) {
+; GFX11-NEXT: entry:
+; GFX11-NEXT: [[TMP0:%.*]] = trunc i64 [[ADDR]] to i32
+; GFX11-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0
+; GFX11-NEXT: [[TMP2:%.*]] = lshr i64 [[ADDR]], 32
+; GFX11-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32
+; GFX11-NEXT: [[TMP4:%.*]] = shl i32 [[STRIDE]], 16
+; GFX11-NEXT: [[TMP5:%.*]] = or i32 [[TMP3]], [[TMP4]]
+; GFX11-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[TMP5]], i64 1
+; GFX11-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 -1, i64 2
+; GFX11-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP7]], i32 536956844, i64 3
+; GFX11-NEXT: [[TMP9:%.*]] = call i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32> [[TMP8]], i32 [[INDEX]], i32 ptrtoint (ptr addrspace(6) getelementptr inbounds (i8, ptr addrspace(6) null, i32 8) to i32), i32 0, i32 0)
+; GFX11-NEXT: [[TMP10:%.*]] = bitcast i32 [[TMP9]] to float
+; GFX11-NEXT: ret float [[TMP10]]
+;
+entry:
+ %buf = call ptr addrspace(9) @lgc.strided.buffer.addr.and.stride.to.ptr(i64 %addr, i32 %stride)
+ %buf.offs = getelementptr inbounds i8, ptr addrspace(9) %buf, i32 8
+ %buf.idx = call ptr addrspace(9) @lgc.strided.index.add(ptr addrspace(9) %buf.offs, i32 %index)
+ %res = load float, ptr addrspace(9) %buf.idx, align 4
+ ret float %res
+}
+
+; Function Attrs: nounwind willreturn memory(none)
+declare ptr addrspace(9) @lgc.strided.buffer.desc.to.ptr(<4 x i32>) #0
+
+; Function Attrs: nounwind willreturn memory(none)
+declare ptr addrspace(9) @lgc.strided.buffer.addr.and.stride.to.ptr(i64, i32) #0
+
+; Function Attrs: nounwind willreturn memory(none)
+declare ptr addrspace(9) @lgc.strided.index.add(ptr addrspace(9), i32) #0
+
+attributes #0 = { nounwind willreturn memory(none) }
diff --git a/lgc/test/Transforms/ReadFirstLane/PatchReadLane.lgc b/lgc/test/Transforms/ReadFirstLane/PatchReadLane.lgc
index 58b0556e20..4278762b19 100644
--- a/lgc/test/Transforms/ReadFirstLane/PatchReadLane.lgc
+++ b/lgc/test/Transforms/ReadFirstLane/PatchReadLane.lgc
@@ -1,5 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --tool lgc
-; RUN: lgc -o - -mcpu=gfx900 -passes=lgc-patch-read-first-lane %s | FileCheck %s
; RUN: lgc -o - -mcpu=gfx1010 -passes=lgc-patch-read-first-lane %s | FileCheck %s
; ModuleID = 'lgcPipeline'
diff --git a/lgc/test/UnlinkedTessFetches.lgc b/lgc/test/UnlinkedTessFetches.lgc
index 850386de4f..29420f387c 100644
--- a/lgc/test/UnlinkedTessFetches.lgc
+++ b/lgc/test/UnlinkedTessFetches.lgc
@@ -1,6 +1,6 @@
; Test that the fetches are added to the merged Vs-Tcs shader.
-; RUN: lgc -mcpu=gfx900 --print-after=lgc-patch-prepare-pipeline-abi -o - - <%s 2>&1 | FileCheck --check-prefixes=CHECK %s
+; RUN: lgc -mcpu=gfx1010 --print-after=lgc-patch-prepare-pipeline-abi -o - - <%s 2>&1 | FileCheck --check-prefixes=CHECK %s
; Find the second run of Patch LLVM for preparing pipeline ABI
; CHECK: IR Dump After Patch LLVM for preparing pipeline ABI
diff --git a/lgc/test/UnlinkedVsGsInputs.lgc b/lgc/test/UnlinkedVsGsInputs.lgc
index d3e79e787f..68090ad11e 100644
--- a/lgc/test/UnlinkedVsGsInputs.lgc
+++ b/lgc/test/UnlinkedVsGsInputs.lgc
@@ -1,6 +1,6 @@
; Check that after merging the VS and GS shader the result has the vertex input as the last parameter, and it is being passed
; to the vertex shader, which expects it as the last parameter.
-; RUN: lgc -mcpu=gfx900 %s -o /dev/null -print-after=lgc-patch-prepare-pipeline-abi 2>&1 | FileCheck --check-prefixes=CHECK %s
+; RUN: lgc -mcpu=gfx1010 %s -o /dev/null -print-after=lgc-patch-prepare-pipeline-abi 2>&1 | FileCheck --check-prefixes=CHECK %s
; CHECK: IR Dump After Patch LLVM for preparing pipeline ABI on [module]
; CHECK: define dllexport amdgpu_gs void @_amdgpu_gs_main_fetchless({{.*}}, <2 x float> noundef [[vertInput:%[0-9]*]])
; CHECK: call amdgpu_es void @_amdgpu_es_main_fetchless({{.*}}, <2 x float> [[vertInput]])
diff --git a/lgc/tool/lgc/CMakeLists.txt b/lgc/tool/lgc/CMakeLists.txt
index ee9d05baad..cd4d5c2e6c 100644
--- a/lgc/tool/lgc/CMakeLists.txt
+++ b/lgc/tool/lgc/CMakeLists.txt
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/lgc/tool/lgc/lgc.cpp b/lgc/tool/lgc/lgc.cpp
index 41b0f8f77b..357bd39224 100644
--- a/lgc/tool/lgc/lgc.cpp
+++ b/lgc/tool/lgc/lgc.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -127,7 +127,7 @@ static bool isIsaText(StringRef data) {
// This is called by the lgc standalone tool to help distinguish between its three output types of ELF binary,
// LLVM IR assembler and ISA assembler. Here we use the fact that ISA assembler is the only one that starts
// with a tab character.
- return data.startswith("\t");
+ return data.starts_with("\t");
}
// =====================================================================================================================
@@ -325,8 +325,8 @@ int main(int argc, char **argv) {
if (notSpacePos != StringRef::npos) {
if (remaining[notSpacePos] == '!')
hadMetadata = true;
- else if (hadMetadata && (remaining.drop_front(notSpacePos).startswith("target") ||
- remaining.drop_front(notSpacePos).startswith("define"))) {
+ else if (hadMetadata && (remaining.drop_front(notSpacePos).starts_with("target") ||
+ remaining.drop_front(notSpacePos).starts_with("define"))) {
// End the current split module and go on to the next one.
separatedAsms.back() = separatedAsms.back().slice(0, remaining.data() - separatedAsms.back().data());
separatedAsms.push_back(remaining);
diff --git a/lgc/tool/lgcdis/CMakeLists.txt b/lgc/tool/lgcdis/CMakeLists.txt
index 4cfc6a7ba2..dde114ebce 100644
--- a/lgc/tool/lgcdis/CMakeLists.txt
+++ b/lgc/tool/lgcdis/CMakeLists.txt
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/lgc/tool/lgcdis/lgcdis.cpp b/lgc/tool/lgcdis/lgcdis.cpp
index 674f5ff045..1303fb0ef6 100644
--- a/lgc/tool/lgcdis/lgcdis.cpp
+++ b/lgc/tool/lgcdis/lgcdis.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/util/AddressExtender.cpp b/lgc/util/AddressExtender.cpp
index 1b66357f55..c9480353d8 100644
--- a/lgc/util/AddressExtender.cpp
+++ b/lgc/util/AddressExtender.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/util/Debug.cpp b/lgc/util/Debug.cpp
index ee9e241321..abf923c519 100644
--- a/lgc/util/Debug.cpp
+++ b/lgc/util/Debug.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/util/GfxRegHandler.cpp b/lgc/util/GfxRegHandler.cpp
index 8c99e084f0..7bc615f599 100644
--- a/lgc/util/GfxRegHandler.cpp
+++ b/lgc/util/GfxRegHandler.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -172,6 +172,7 @@ static constexpr BitsInfo SqImgRsrcRegBitsGfx9[static_cast<unsigned>(SqRsrcRegs:
{2, 14, 14}, // Height
{3, 0, 12}, // DstSelXYZW
{3, 20, 5}, // SwizzleMode
+ {3, 28, 4}, // Type
{4, 0, 13}, // Depth
{4, 13, 12}, // Pitch
{4, 29, 3}, // BcSwizzle
@@ -194,6 +195,7 @@ static constexpr BitsInfo SqImgRsrcRegBitsGfx10[static_cast<unsigned>(SqRsrcRegs
{2, 14, 14}, // Height
{3, 0, 12}, // DstSelXYZW
{3, 20, 5}, // SwizzleMode
+ {3, 28, 4}, // Type
{4, 0, 13}, // Depth
{}, // Pitch
{3, 25, 3}, // BcSwizzle
@@ -216,6 +218,7 @@ static constexpr BitsInfo SqImgRsrcRegBitsGfx11[static_cast<unsigned>(SqRsrcRegs
{2, 14, 14}, // Height
{3, 0, 12}, // DstSelXYZW
{3, 20, 5}, // SwizzleMode
+ {3, 28, 4}, // Type
{4, 0, 13}, // Depth
{}, // Pitch
{3, 25, 3}, // BcSwizzle
@@ -264,6 +267,7 @@ Value *SqImgRsrcRegHandler::getReg(SqRsrcRegs regId) {
case SqRsrcRegs::Format:
case SqRsrcRegs::DstSelXYZW:
case SqRsrcRegs::SwizzleMode:
+ case SqRsrcRegs::Type:
case SqRsrcRegs::BcSwizzle:
case SqRsrcRegs::BaseLevel:
case SqRsrcRegs::LastLevel:
@@ -305,6 +309,7 @@ void SqImgRsrcRegHandler::setReg(SqRsrcRegs regId, Value *regValue) {
case SqRsrcRegs::Format:
case SqRsrcRegs::DstSelXYZW:
case SqRsrcRegs::SwizzleMode:
+ case SqRsrcRegs::Type:
case SqRsrcRegs::Depth:
case SqRsrcRegs::BcSwizzle:
setRegCommon(static_cast<unsigned>(regId), regValue);
@@ -333,3 +338,12 @@ void SqImgRsrcRegHandler::setReg(SqRsrcRegs regId, Value *regValue) {
break;
}
}
+
+// =====================================================================================================================
+// Get the bitmask that covers the hardware register
+//
+// @param regId : Register ID
+unsigned SqImgRsrcRegHandler::getRegMask(SqRsrcRegs regId) {
+ const auto &bitsInfo = m_bitsInfo[static_cast<unsigned>(regId)];
+ return ((1ULL << bitsInfo.count) - 1) << bitsInfo.offset;
+}
diff --git a/lgc/util/GfxRegHandlerBase.cpp b/lgc/util/GfxRegHandlerBase.cpp
index d22d0121a1..0a963e9576 100644
--- a/lgc/util/GfxRegHandlerBase.cpp
+++ b/lgc/util/GfxRegHandlerBase.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/util/Internal.cpp b/lgc/util/Internal.cpp
index bb17000f9d..5a9a24a81e 100644
--- a/lgc/util/Internal.cpp
+++ b/lgc/util/Internal.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/lgc/util/MbStandardInstrumentations.cpp b/lgc/util/MbStandardInstrumentations.cpp
index ed0245ebec..8c5de79205 100644
--- a/lgc/util/MbStandardInstrumentations.cpp
+++ b/lgc/util/MbStandardInstrumentations.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/lgc/util/ModuleBunch.cpp b/lgc/util/ModuleBunch.cpp
index dd2a870202..24f71f94a9 100644
--- a/lgc/util/ModuleBunch.cpp
+++ b/lgc/util/ModuleBunch.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/lgc/util/PassManager.cpp b/lgc/util/PassManager.cpp
index c74588f52a..b33b8e0b6e 100644
--- a/lgc/util/PassManager.cpp
+++ b/lgc/util/PassManager.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -61,6 +61,10 @@ static cl::list<unsigned> DisablePassIndices("disable-pass-indices", cl::ZeroOrM
static cl::opt<bool> DebugPassManager("debug-pass-manager", cl::desc("Print pass management debugging information"),
cl::Hidden, cl::init(false));
+static cl::opt<std::string> StartLowerAfterOpt("start-lower-after",
+ cl::desc("Resume compilation after a specific lower pass"), cl::init(""),
+ cl::Hidden);
+
} // namespace cl
// A proxy from a ModuleAnalysisManager to a loop.
@@ -115,7 +119,10 @@ class PassManagerImpl final : public lgc::PassManager {
unsigned *m_passIndex = nullptr; // Pass Index.
bool m_initialized = false; // Whether the pass manager is initialized or not
bool m_stopped = false;
+ bool m_start = false; // Whether the pass manager will execute the following passes
std::string m_stopAfter;
+ std::string m_startAfter; // Specify the pass name to start from
+ StringMap<std::string> m_passToClassName;
};
// =====================================================================================================================
@@ -215,6 +222,12 @@ PassManagerImpl::PassManagerImpl(TargetMachine *targetMachine, LLVMContext &cont
assert(it != options.end());
m_stopAfter = static_cast<cl::opt<std::string> *>(it->second)->getValue();
+ // Find the pass name to start from
+ it = options.find("start-lower-after");
+ m_startAfter = static_cast<cl::opt<std::string> *>(it->second)->getValue();
+ if (m_startAfter.empty())
+ m_start = true;
+
// Setup custom instrumentation callbacks and register LLVM's default module
// analyses to the analysis manager.
registerCallbacks();
@@ -249,6 +262,8 @@ MbPassManagerImpl::MbPassManagerImpl(TargetMachine *targetMachine)
// @param className : Full pass name
void PassManagerImpl::registerPass(StringRef passName, StringRef className) {
m_instrumentationCallbacks.addClassToPassName(className, passName);
+ assert(!m_passToClassName.count(passName)); // Passes shouldn't be registered twice
+ m_passToClassName[passName] = className.str();
}
// =====================================================================================================================
@@ -278,6 +293,14 @@ void PassManagerImpl::run(Module &module) {
m_loopAnalysisManager.registerPass([&] { return ModuleAnalysisManagerLoopProxy(m_moduleAnalysisManager); });
m_initialized = true;
}
+
+ // If couldn't find the 'start-after' pass name from the registered passes, execute all passes
+ if (!m_startAfter.empty()) {
+ if (!m_passToClassName.count(m_startAfter)) {
+ m_startAfter.clear();
+ m_start = true;
+ }
+ }
ModulePassManager::run(module, m_moduleAnalysisManager);
}
@@ -344,6 +367,15 @@ void PassManagerImpl::registerCallbacks() {
// This particular pass still gets to run, but we skip everything afterwards.
m_stopped = true;
}
+ // If find the 'start-after' pass name, inform the pass manager to start the following passes
+ // But not execute current pass
+ if (!m_startAfter.empty()) {
+ if (!m_start && passName == m_startAfter) {
+ m_start = true;
+ return false;
+ }
+ return m_start;
+ }
return true;
});
}
diff --git a/lgc/util/StartStopTimer.cpp b/lgc/util/StartStopTimer.cpp
index 9c09188a4f..1949ba1153 100644
--- a/lgc/util/StartStopTimer.cpp
+++ b/lgc/util/StartStopTimer.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/CMakeLists.txt b/llpc/CMakeLists.txt
index d99e2ff799..0fe1470c68 100644
--- a/llpc/CMakeLists.txt
+++ b/llpc/CMakeLists.txt
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/llpc/context/llpcCompiler.cpp b/llpc/context/llpcCompiler.cpp
index 3fda5ead00..7110ec7112 100644
--- a/llpc/context/llpcCompiler.cpp
+++ b/llpc/context/llpcCompiler.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -65,6 +65,7 @@
#include "llvm-dialects/Dialect/Dialect.h"
#include "llvm/ADT/ScopeExit.h"
#include "llvm/ADT/SmallSet.h"
+#include "llvm/AsmParser/Parser.h"
#include "llvm/BinaryFormat/MsgPackDocument.h"
#include "llvm/Bitcode/BitcodeReader.h"
#include "llvm/Bitcode/BitcodeWriter.h"
@@ -652,7 +653,8 @@ Result Compiler::BuildShaderModule(const ShaderModuleBuildInfo *shaderInfo, Shad
std::vector<ResourceNodeData> imageSymbolInfo;
std::vector<ResourceNodeData> atomicCounterSymbolInfo;
std::vector<ResourceNodeData> defaultUniformSymbolInfo;
- if (shaderInfo->options.pipelineOptions.buildResourcesDataForShaderModule) {
+ if (shaderInfo->options.pipelineOptions.buildResourcesDataForShaderModule &&
+ moduleData.binType == BinaryType::Spirv) {
buildShaderModuleResourceUsage(shaderInfo, resourceNodes, inputSymbolInfo, outputSymbolInfo, uniformBufferInfo,
storageBufferInfo, textureSymbolInfo, imageSymbolInfo, atomicCounterSymbolInfo,
defaultUniformSymbolInfo, moduleData.usage);
@@ -694,7 +696,8 @@ Result Compiler::BuildShaderModule(const ShaderModuleBuildInfo *shaderInfo, Shad
pShaderModuleData->binCode.pCode = bufferWritePtr;
bufferWritePtr += codeBuffer.size() * sizeof(unsigned);
- if (shaderInfo->options.pipelineOptions.buildResourcesDataForShaderModule) {
+ if (shaderInfo->options.pipelineOptions.buildResourcesDataForShaderModule &&
+ moduleData.binType == BinaryType::Spirv) {
memcpy(bufferWritePtr, &resourceNodes, sizeof(ResourcesNodes));
pResourcesNodes = reinterpret_cast<ResourcesNodes *>(bufferWritePtr);
pShaderModuleData->usage.pResources = pResourcesNodes;
@@ -755,6 +758,7 @@ static bool getSymbolInfoFromSpvVariable(const SPIRVVariable *spvVar, ResourceNo
SPIRVWord binding = 0;
SPIRVWord varId = 0;
BasicType basicType = BasicType::Unknown;
+ symbolInfo->columnCount = 1;
SPIRVWord builtIn = false;
bool isBuiltIn = spvVar->hasDecorate(DecorationBuiltIn, 0, &builtIn);
@@ -764,7 +768,7 @@ static bool getSymbolInfoFromSpvVariable(const SPIRVVariable *spvVar, ResourceNo
SPIRVType *varElemTy = spvVar->getType()->getPointerElementType();
while (varElemTy->isTypeArray()) {
- arraySize = varElemTy->getArrayLength();
+ arraySize *= varElemTy->getArrayLength();
varElemTy = varElemTy->getArrayElementType();
}
if (varElemTy->getOpCode() == OpTypeStruct) {
@@ -774,8 +778,10 @@ static bool getSymbolInfoFromSpvVariable(const SPIRVVariable *spvVar, ResourceNo
isBuiltIn = varElemTy->hasMemberDecorate(i, DecorationBuiltIn, 0, &builtIn);
}
}
- if (varElemTy->getOpCode() == OpTypeMatrix)
+ if (varElemTy->getOpCode() == OpTypeMatrix) {
+ symbolInfo->columnCount = varElemTy->getMatrixColumnCount();
varElemTy = varElemTy->getMatrixColumnType();
+ }
if (varElemTy->getOpCode() == OpTypeVector)
varElemTy = varElemTy->getVectorComponentType();
@@ -854,7 +860,7 @@ static unsigned getSamplerArraySizeInSpvStruct(const SPIRVType *spvStruct) {
samplerArraySize += (arraySize * getSamplerArraySizeInSpvStruct(memberTy));
}
} else if (memberTy->isTypeStruct()) {
- samplerArraySize *= getSamplerArraySizeInSpvStruct(memberTy);
+ samplerArraySize += getSamplerArraySizeInSpvStruct(memberTy);
}
}
@@ -931,16 +937,19 @@ void Compiler::buildShaderModuleResourceUsage(
}
}
+ // Spirv Reader will expand matrix to vector arrays.
+ // Add more rsrc node here to avoid poison value in vtxFetch.
if (shaderInfo->entryStage == ShaderStage::ShaderStageVertex) {
size_t inputSymbolSize = inputSymbolWithArrayInfo.size();
for (size_t i = 0; i < inputSymbolSize; i++) {
auto symbol = inputSymbolWithArrayInfo[i];
- inputSymbolInfo.push_back(symbol);
+ int baseLocation = symbol.location;
- for (uint32_t ite = 1; ite < symbol.arraySize; ite++) {
+ for (uint32_t ite = 0; ite < symbol.arraySize * symbol.columnCount; ite++) {
ResourceNodeData elemSymbolInfo = symbol;
- elemSymbolInfo.location = symbol.location + ite;
inputSymbolInfo.push_back(elemSymbolInfo);
+ inputSymbolInfo.back().location = baseLocation;
+ baseLocation++;
}
}
}
@@ -994,7 +1003,8 @@ void Compiler::buildShaderModuleResourceUsage(
textureSymbol.location = defaultUniformSymbol.location;
textureSymbol.arraySize = getSamplerArraySizeInSpvStruct(varElemTy) * defaultUniformSymbol.arraySize;
textureSymbol.isDefaultUniformSampler = true;
- textureSymbolInfo.push_back(textureSymbol);
+ if (textureSymbol.arraySize > 0)
+ textureSymbolInfo.push_back(textureSymbol);
}
}
} break;
@@ -1416,6 +1426,15 @@ Result Compiler::buildUnlinkedShaderInternal(Context *context, ArrayRef<const Pi
static_cast<const ShaderModuleData *>(shaderInfo[ShaderStageFragment]->pModuleData);
if (moduleData->usage.useGenericBuiltIn || moduleData->usage.useBarycentric)
return Result::RequireFullPipeline;
+ } else if (stage == UnlinkedStageVertexProcess) {
+ bool hasVs = shaderInfo[ShaderStageVertex]->pModuleData != nullptr;
+ bool hasTes = (shaderInfo[ShaderStageTessControl]->pModuleData != nullptr) ||
+ (shaderInfo[ShaderStageTessControlBit]->pModuleData != nullptr);
+ bool hasGs = shaderInfo[ShaderStageGeometry]->pModuleData != nullptr;
+ if (m_gfxIp.major >= 11 && hasVs && !hasGs && !hasTes &&
+ static_cast<const ShaderModuleData *>(shaderInfo[ShaderStageVertex]->pModuleData)->usage.enableXfb) {
+ return Result::RequireFullPipeline;
+ }
}
unsigned originalShaderStageMask = context->getPipelineContext()->getShaderStageMask();
@@ -1554,28 +1573,6 @@ bool Compiler::canUseRelocatableGraphicsShaderElf(const ArrayRef<const PipelineS
if (pipelineInfo->iaState.enableMultiView)
return false;
- // NOTE: On gfx11, Xfb depends on the count of primitive vertex. If UnlinkedStageVertexProcess only contains
- // VS (no TES and GS), the primitive type might be unknown at compiling VS time, so we have to fall back to full
- // pipeline.
- // Currently, We treat Triangle_list as the default value. Therefore, we only disable relocatable compilation
- // when primitive is point or line.
- bool hasVs = pipelineInfo->vs.pModuleData != nullptr;
- bool hasTes = (pipelineInfo->tes.pModuleData != nullptr) || (pipelineInfo->tcs.pModuleData != nullptr);
- bool hasGs = pipelineInfo->gs.pModuleData != nullptr;
- if (m_gfxIp.major >= 11 && hasVs && !hasGs && !hasTes &&
- static_cast<const ShaderModuleData *>(pipelineInfo->vs.pModuleData)->usage.enableXfb) {
- switch (pipelineInfo->iaState.topology) {
- case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
- case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
- case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
- case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
- case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
- return false;
- default:
- break;
- }
- }
-
if (shaderInfos[0]) {
const ShaderModuleData *moduleData = reinterpret_cast<const ShaderModuleData *>(shaderInfos[0]->pModuleData);
if (moduleData && moduleData->binType != BinaryType::Spirv)
@@ -1642,6 +1639,7 @@ Result Compiler::buildPipelineInternal(Context *context, ArrayRef<const Pipeline
context->setBuilder(builderContext->createBuilder(&*pipeline));
std::unique_ptr<Module> pipelineModule;
+ bool needLowerGpurt = false;
// NOTE: If input is LLVM IR, read it now. There is now only ever one IR module representing the
// whole pipeline.
@@ -1656,40 +1654,50 @@ Result Compiler::buildPipelineInternal(Context *context, ArrayRef<const Pipeline
// into a single pipeline module.
if (!pipelineModule) {
// Create empty modules and set target machine in each.
- std::vector<Module *> modules(shaderInfo.size());
+ SmallVector<std::unique_ptr<Module>> modules(shaderInfo.size());
unsigned stageSkipMask = 0;
+ unsigned numStagesWithRayQuery = 0;
+
for (unsigned shaderIndex = 0; shaderIndex < shaderInfo.size() && result == Result::Success; ++shaderIndex) {
const PipelineShaderInfo *shaderInfoEntry = shaderInfo[shaderIndex];
if (!shaderInfoEntry || !shaderInfoEntry->pModuleData)
continue;
- const ShaderModuleData *moduleDataEx = reinterpret_cast<const ShaderModuleData *>(shaderInfoEntry->pModuleData);
+ ShaderStage entryStage = shaderInfoEntry ? shaderInfoEntry->entryStage : ShaderStageInvalid;
+ if (stageSkipMask & shaderStageToMask(entryStage))
+ continue;
+
+ const ShaderModuleData *moduleData = reinterpret_cast<const ShaderModuleData *>(shaderInfoEntry->pModuleData);
- Module *module = nullptr;
- if (moduleDataEx->binType == BinaryType::MultiLlvmBc) {
+ if (moduleData->binType == BinaryType::MultiLlvmBc) {
result = Result::ErrorInvalidShader;
- } else {
- module = new Module((Twine("llpc") + "_" + getShaderStageName(shaderInfoEntry->entryStage)).str() + "_" +
- std::to_string(getModuleIdByIndex(shaderIndex)),
- *context);
+ continue;
}
- modules[shaderIndex] = module;
- context->setModuleTargetMachine(module);
- }
+ modules[shaderIndex].reset(
+ new Module((Twine("llpc") + "_" + getShaderStageName(shaderInfoEntry->entryStage)).str() + "_" +
+ std::to_string(getModuleIdByIndex(shaderIndex)),
+ *context));
- unsigned numStagesWithRayQuery = 0;
+ context->setModuleTargetMachine(modules[shaderIndex].get());
- for (unsigned shaderIndex = 0; shaderIndex < shaderInfo.size() && result == Result::Success; ++shaderIndex) {
- const PipelineShaderInfo *shaderInfoEntry = shaderInfo[shaderIndex];
- ShaderStage entryStage = shaderInfoEntry ? shaderInfoEntry->entryStage : ShaderStageInvalid;
+ // If input shader module is llvm bc, skip spirv to llvm translation
+ if (moduleData->binType == BinaryType::LlvmBc) {
+ llvm::SMDiagnostic errDiag;
+ llvm::StringRef bcStringRef(static_cast<const char *>(moduleData->binCode.pCode), moduleData->binCode.codeSize);
+ llvm::MemoryBufferRef bcBufferRef(bcStringRef, "");
- if (!shaderInfoEntry || !shaderInfoEntry->pModuleData || (stageSkipMask & shaderStageToMask(entryStage)))
- continue;
+ Expected<std::unique_ptr<Module>> MOrErr = llvm::parseBitcodeFile(bcBufferRef, *context);
+ if (!MOrErr) {
+ report_fatal_error("Failed to read bitcode");
+ continue;
+ }
+ modules[shaderIndex] = std::move(*MOrErr);
+ }
std::unique_ptr<lgc::PassManager> lowerPassMgr(lgc::PassManager::Create(context->getLgcContext()));
lowerPassMgr->setPassIndex(&passIndex);
- SpirvLower::registerPasses(*lowerPassMgr);
+ SpirvLower::registerTranslationPasses(*lowerPassMgr);
// Start timer for translate.
timerProfiler.addTimerStartStopPass(*lowerPassMgr, TimerTranslate, true);
@@ -1703,19 +1711,24 @@ Result Compiler::buildPipelineInternal(Context *context, ArrayRef<const Pipeline
"// LLPC SPIRV-to-LLVM translation results\n"));
}
- const ShaderModuleData *moduleData = reinterpret_cast<const ShaderModuleData *>(shaderInfoEntry->pModuleData);
if (moduleData->usage.enableRayQuery) {
assert(!moduleData->usage.rayQueryLibrary);
lowerPassMgr->addPass(SpirvLowerRayQuery(false));
++numStagesWithRayQuery;
}
+ if (moduleData->usage.isInternalRtShader)
+ setUseGpurt(&*pipeline);
+
assert(!moduleData->usage.isInternalRtShader || entryStage == ShaderStageCompute);
+ if (moduleData->usage.isInternalRtShader || moduleData->usage.enableRayQuery)
+ needLowerGpurt |= true;
+
// Stop timer for translate.
timerProfiler.addTimerStartStopPass(*lowerPassMgr, TimerTranslate, false);
- bool success = runPasses(&*lowerPassMgr, modules[shaderIndex]);
+ bool success = runPasses(&*lowerPassMgr, modules[shaderIndex].get());
if (!success) {
LLPC_ERRS("Failed to translate SPIR-V or run per-shader passes\n");
result = Result::ErrorInvalidShader;
@@ -1724,12 +1737,14 @@ Result Compiler::buildPipelineInternal(Context *context, ArrayRef<const Pipeline
// If this is TCS, set inputVertices from patchControlPoints in the pipeline state.
if (entryStage == ShaderStageTessControl ||
(entryStage == ShaderStageTessEval && shaderInfo[ShaderStageTessControl]->pModuleData == nullptr))
- context->getPipelineContext()->setTcsInputVertices(modules[shaderIndex]);
+ context->getPipelineContext()->setTcsInputVertices(modules[shaderIndex].get());
}
+ if (needLowerGpurt)
+ setUseGpurt(&*pipeline);
+
if (numStagesWithRayQuery) {
std::unique_ptr<Module> gpurtShaderLibrary = createGpurtShaderLibrary(context);
- setUseGpurt(&*pipeline);
if (!gpurtShaderLibrary)
return Result::ErrorInvalidShader;
@@ -1758,7 +1773,7 @@ Result Compiler::buildPipelineInternal(Context *context, ArrayRef<const Pipeline
}
}
- SmallVector<Module *, ShaderStageGfxCount> modulesToLink;
+ SmallVector<std::unique_ptr<Module>, ShaderStageGfxCount> modulesToLink;
for (unsigned shaderIndex = 0; shaderIndex < shaderInfo.size() && result == Result::Success; ++shaderIndex) {
// Per-shader SPIR-V lowering passes.
const PipelineShaderInfo *shaderInfoEntry = shaderInfo[shaderIndex];
@@ -1768,13 +1783,13 @@ Result Compiler::buildPipelineInternal(Context *context, ArrayRef<const Pipeline
if (stageSkipMask & shaderStageToMask(entryStage)) {
// Do not run SPIR-V translator and lowering passes on this shader; we were given it as IR ready
// to link into pipeline module.
- modulesToLink.push_back(modules[shaderIndex]);
+ modulesToLink.push_back(std::move(modules[shaderIndex]));
continue;
}
std::unique_ptr<lgc::PassManager> lowerPassMgr(lgc::PassManager::Create(context->getLgcContext()));
lowerPassMgr->setPassIndex(&passIndex);
- SpirvLower::registerPasses(*lowerPassMgr);
+ SpirvLower::registerLoweringPasses(*lowerPassMgr);
const ShaderModuleData *moduleData = reinterpret_cast<const ShaderModuleData *>(shaderInfoEntry->pModuleData);
@@ -1782,14 +1797,14 @@ Result Compiler::buildPipelineInternal(Context *context, ArrayRef<const Pipeline
/*rayTracing=*/false, moduleData->usage.enableRayQuery,
moduleData->usage.isInternalRtShader);
// Run the passes.
- bool success = runPasses(&*lowerPassMgr, modules[shaderIndex]);
+ bool success = runPasses(&*lowerPassMgr, modules[shaderIndex].get());
if (!success) {
LLPC_ERRS("Failed to translate SPIR-V or run per-shader passes\n");
result = Result::ErrorInvalidShader;
}
// Add the shader module to the list for the pipeline.
- modulesToLink.push_back(modules[shaderIndex]);
+ modulesToLink.push_back(std::move(modules[shaderIndex]));
}
// If this is a part-pipeline compile of the pre-rasterization stages, give the "other" pipeline object
@@ -1798,8 +1813,8 @@ Result Compiler::buildPipelineInternal(Context *context, ArrayRef<const Pipeline
pipeline->setOtherPartPipeline(*otherPartPipeline);
// Link the shader modules into a single pipeline module.
- pipelineModule.reset(pipeline->irLink(
- modulesToLink, context->getPipelineContext()->isUnlinked() ? PipelineLink::Unlinked : pipelineLink));
+ pipelineModule = pipeline->irLink(
+ modulesToLink, context->getPipelineContext()->isUnlinked() ? PipelineLink::Unlinked : pipelineLink);
if (!pipelineModule) {
LLPC_ERRS("Failed to link shader modules into pipeline module\n");
result = Result::ErrorInvalidShader;
@@ -1814,9 +1829,11 @@ Result Compiler::buildPipelineInternal(Context *context, ArrayRef<const Pipeline
// @param stageMask : Shader stage mask
// @param stageHashes : Per-stage hash of in/out usage
// @returns : Stage mask of stages not found in cache
- [&graphicsShaderCacheChecker, stageCacheAccesses](const Module *module, unsigned stageMask,
+ [&graphicsShaderCacheChecker, stageCacheAccesses](const Module *module, ShaderStageMask stageMask,
ArrayRef<ArrayRef<uint8_t>> stageHashes) {
- return graphicsShaderCacheChecker.check(module, stageMask, stageHashes, stageCacheAccesses);
+ ShaderStageMask result;
+ result.m_value = graphicsShaderCacheChecker.check(module, stageMask.m_value, stageHashes, stageCacheAccesses);
+ return result;
};
// Only enable per stage cache for full graphics pipeline (traditional pipeline or mesh pipeline)
@@ -2148,7 +2165,7 @@ Result Compiler::buildGraphicsPipelineWithPartPipelines(Context *context,
// If the "ELF" does not look like ELF, then it must be textual output from -emit-lgc, -emit-llvm, -filetype=asm.
// We can't link that, so just concatenate it on to the output.
- if (partPipelineElf.size() < 4 || !partPipelineElf.startswith("\177ELF")) {
+ if (partPipelineElf.size() < 4 || !partPipelineElf.starts_with("\177ELF")) {
const unsigned char magic[] = {'B', 'C', 0xC0, 0xDE};
if (partPipelineElf.size() > 4 && memcmp(partPipelineElf.data(), magic, sizeof(magic)) == 0)
report_fatal_error("Cannot emit llvm bitcode with part pipeline compilation.");
@@ -2247,8 +2264,7 @@ Result Compiler::BuildGraphicsPipeline(const GraphicsPipelineBuildInfo *pipeline
LLPC_OUTS("\n");
}
- if (result == Result::Success)
- dumpCompilerOptions(pipelineDumpFile);
+ dumpCompilerOptions(pipelineDumpFile);
std::optional<CacheAccessor> cacheAccessor;
if (cl::CacheFullPipelines) {
@@ -2377,7 +2393,8 @@ Result Compiler::BuildComputePipeline(const ComputePipelineBuildInfo *pipelineIn
LLPC_OUTS("\n");
}
- dumpCompilerOptions(pipelineDumpFile);
+ if (result == Result::Success)
+ dumpCompilerOptions(pipelineDumpFile);
std::optional<CacheAccessor> cacheAccessor;
if (cl::CacheFullPipelines) {
@@ -2455,7 +2472,7 @@ std::unique_ptr<Module> Compiler::createGpurtShaderLibrary(Context *context) {
TimerProfiler timerProfiler(context->getPipelineHashCode(), "LLPC", TimerProfiler::PipelineTimerEnableMask);
std::unique_ptr<lgc::PassManager> lowerPassMgr(lgc::PassManager::Create(context->getLgcContext()));
- SpirvLower::registerPasses(*lowerPassMgr);
+ SpirvLower::registerTranslationPasses(*lowerPassMgr);
timerProfiler.addTimerStartStopPass(*lowerPassMgr, TimerTranslate, true);
@@ -2539,6 +2556,20 @@ Result Compiler::BuildRayTracingPipeline(const RayTracingPipelineBuildInfo *pipe
RayTracingContext rayTracingContext(m_gfxIp, pipelineInfo, representativeShaderInfo, &pipelineHash, &cacheHash,
pipelineInfo->indirectStageMask);
+ auto &summary = rayTracingContext.getRayTracingLibrarySummary();
+ summary.knownSetRayFlags = ~0;
+ summary.knownUnsetRayFlags = ~0;
+
+ // Note: These values are provided by the application via the ABI.
+ summary.maxRayPayloadSize = pipelineInfo->payloadSizeMaxInLib;
+ summary.maxHitAttributeSize = pipelineInfo->attributeSizeMaxInLib;
+
+ for (unsigned i = 0; i < pipelineInfo->libraryCount; ++i) {
+ const BinaryData &data = pipelineInfo->pLibrarySummaries[i];
+ auto rls = cantFail(
+ lgc::RayTracingLibrarySummary::decodeMsgpack(StringRef(static_cast<const char *>(data.pCode), data.codeSize)));
+ summary.merge(rls);
+ }
pipelineOut->hasTraceRay = false;
for (unsigned i = 0; i < pipelineInfo->shaderCount; ++i) {
@@ -2546,6 +2577,12 @@ Result Compiler::BuildRayTracingPipeline(const RayTracingPipelineBuildInfo *pipe
const ShaderModuleData *moduleData = reinterpret_cast<const ShaderModuleData *>(shaderInfo.pModuleData);
if (moduleData->usage.hasTraceRay) {
pipelineOut->hasTraceRay = true;
+
+ summary.usesTraceRay = true;
+
+ // TODO: Leverage static analysis (could be moved to *after* the compilation of shaders?)
+ summary.knownSetRayFlags = 0;
+ summary.knownUnsetRayFlags = 0;
break;
}
}
@@ -2574,6 +2611,7 @@ Result Compiler::BuildRayTracingPipeline(const RayTracingPipelineBuildInfo *pipe
helperThreadProvider);
if (result == Result::Success) {
+ std::string summaryMsgpack = summary.encodeMsgpack();
void *allocBuf = nullptr;
size_t shaderGroupHandleSize = pipelineInfo->shaderGroupCount * sizeof(RayTracingShaderIdentifier);
size_t binaryDataSize = sizeof(BinaryData) * elfBinarys.size();
@@ -2594,6 +2632,8 @@ Result Compiler::BuildRayTracingPipeline(const RayTracingPipelineBuildInfo *pipe
allocSize += shaderGroupHandleSize;
+ allocSize += alignTo(summaryMsgpack.size(), 8);
+
if (pipelineInfo->pfnOutputAlloc)
allocBuf = pipelineInfo->pfnOutputAlloc(pipelineInfo->pInstance, pipelineInfo->pUserData, allocSize);
else {
@@ -2626,6 +2666,7 @@ Result Compiler::BuildRayTracingPipeline(const RayTracingPipelineBuildInfo *pipe
// Get to the address of shaderGroupHandles pass elfCode size
RayTracingShaderIdentifier *shaderHandles = reinterpret_cast<RayTracingShaderIdentifier *>(allocBuf);
+ allocBuf = voidPtrInc(allocBuf, shaderGroupHandleSize);
memset(shaderHandles, 0, shaderGroupHandleSize);
pipelineOut->shaderGroupHandle.shaderHandles = shaderHandles;
pipelineOut->shaderGroupHandle.shaderHandleCount = pipelineInfo->shaderGroupCount;
@@ -2647,6 +2688,12 @@ Result Compiler::BuildRayTracingPipeline(const RayTracingPipelineBuildInfo *pipe
shaderHandles[i].intersectionId = getModuleIdByIndex(shaderGroup->intersectionShader);
}
}
+
+ void *summaryOut = allocBuf;
+ allocBuf = voidPtrInc(allocBuf, alignTo(summaryMsgpack.size(), 8));
+ pipelineOut->librarySummary.pCode = summaryOut;
+ pipelineOut->librarySummary.codeSize = summaryMsgpack.size();
+ memcpy(summaryOut, summaryMsgpack.data(), summaryMsgpack.size());
}
return result;
@@ -2713,9 +2760,8 @@ Result Compiler::generatePipeline(Context *context, unsigned moduleIndex, std::u
// Generate pipeline.
std::unique_ptr<Module> pipelineModule;
- pipelineModule.reset(pipeline->irLink(module.release(), context->getPipelineContext()->isUnlinked()
- ? PipelineLink::Unlinked
- : PipelineLink::WholePipeline));
+ pipelineModule = pipeline->irLink(module, context->getPipelineContext()->isUnlinked() ? PipelineLink::Unlinked
+ : PipelineLink::WholePipeline);
if (!pipelineModule) {
LLPC_ERRS("Failed to link shader modules into pipeline module\n");
return Result::ErrorInvalidShader;
@@ -2945,7 +2991,7 @@ Result Compiler::buildRayTracingPipelineInternal(RayTracingContext &rtContext,
std::unique_ptr<lgc::PassManager> lowerPassMgr(lgc::PassManager::Create(builderContext));
lowerPassMgr->setPassIndex(&passIndex);
- SpirvLower::registerPasses(*lowerPassMgr);
+ SpirvLower::registerTranslationPasses(*lowerPassMgr);
// SPIR-V translation, then dump the result.
lowerPassMgr->addPass(SpirvLowerTranslator(shaderInfoEntry->entryStage, shaderInfoEntry));
@@ -3015,13 +3061,13 @@ Result Compiler::buildRayTracingPipelineInternal(RayTracingContext &rtContext,
// Prepare GpuRt module to be compiled separately
for (auto funcIt = gpurtShaderLibrary->begin(), funcEnd = gpurtShaderLibrary->end(); funcIt != funcEnd;) {
Function *func = &*funcIt++;
- if (func->getName().startswith(traceRayFuncName)) {
+ if (func->getName().starts_with(traceRayFuncName)) {
// We assigned GpuRt functions weak linkage prior to linking into app modules to not confuse the entry
// point determination mechanism. Undo that on TraceRay to make it the entry of the module.
func->setLinkage(GlobalValue::ExternalLinkage);
lgc::rt::setLgcRtShaderStage(func, lgc::rt::RayTracingShaderStage::Traversal);
} else if (func->getLinkage() == GlobalValue::WeakAnyLinkage &&
- !func->getName().startswith(fetchTrianglePosFunc) && !func->empty()) {
+ !func->getName().starts_with(fetchTrianglePosFunc) && !func->empty()) {
// Preserve fetchTrianglePosFunc because we need to inline it into Traversal later on.
// Remove other function definitions both for compile speed, and to work around an
// issue with private globals used in multiple functions in GpuRt which confuses SpirvLowerGlobal.
@@ -3041,7 +3087,7 @@ Result Compiler::buildRayTracingPipelineInternal(RayTracingContext &rtContext,
for (unsigned i = 0; i < newModules.size(); i++) {
auto module = (newModules[i].get());
std::unique_ptr<lgc::PassManager> passMgr(lgc::PassManager::Create(builderContext));
- SpirvLower::registerPasses(*passMgr);
+ SpirvLower::registerLoweringPasses(*passMgr);
SpirvLower::addPasses(mainContext, ShaderStageCompute, *passMgr, timerProfiler.getTimer(TimerLower), true,
moduleUsesRayQuery[i], false);
bool success = runPasses(&*passMgr, module);
@@ -3232,7 +3278,7 @@ MetroHash::Hash Compiler::generateHashForCompileOptions(unsigned optionCount, co
StringRef option = options[i] + 1; // Skip '-' in options
bool ignore = false;
for (unsigned j = 0; j < sizeof(IgnoredOptions) / sizeof(IgnoredOptions[0]); ++j) {
- if (option.startswith(IgnoredOptions[j])) {
+ if (option.starts_with(IgnoredOptions[j])) {
ignore = true;
break;
}
@@ -3483,36 +3529,36 @@ std::optional<lgc::rt::RayTracingShaderStage> getLgcRtShaderStage(Llpc::ShaderSt
// Convert front-end LLPC shader stage to middle-end LGC shader type
//
// @param stage : Front-end LLPC shader stage
-lgc::ShaderStage getLgcShaderStage(Llpc::ShaderStage stage) {
+lgc::ShaderStageEnum getLgcShaderStage(Llpc::ShaderStage stage) {
switch (stage) {
case ShaderStageTask:
- return lgc::ShaderStageTask;
+ return lgc::ShaderStage::Task;
case ShaderStageCompute:
- return lgc::ShaderStageCompute;
+ return lgc::ShaderStage::Compute;
case ShaderStageVertex:
- return lgc::ShaderStageVertex;
+ return lgc::ShaderStage::Vertex;
case ShaderStageTessControl:
- return lgc::ShaderStageTessControl;
+ return lgc::ShaderStage::TessControl;
case ShaderStageTessEval:
- return lgc::ShaderStageTessEval;
+ return lgc::ShaderStage::TessEval;
case ShaderStageGeometry:
- return lgc::ShaderStageGeometry;
+ return lgc::ShaderStage::Geometry;
case ShaderStageMesh:
- return lgc::ShaderStageMesh;
+ return lgc::ShaderStage::Mesh;
case ShaderStageFragment:
- return lgc::ShaderStageFragment;
+ return lgc::ShaderStage::Fragment;
case ShaderStageCopyShader:
- return lgc::ShaderStageCopyShader;
+ return lgc::ShaderStage::CopyShader;
case ShaderStageRayTracingRayGen:
case ShaderStageRayTracingIntersect:
case ShaderStageRayTracingAnyHit:
case ShaderStageRayTracingClosestHit:
case ShaderStageRayTracingMiss:
case ShaderStageRayTracingCallable:
- return lgc::ShaderStageCompute;
+ return lgc::ShaderStage::Compute;
default:
llvm_unreachable("");
- return lgc::ShaderStageInvalid;
+ return lgc::ShaderStage::Invalid;
}
}
diff --git a/llpc/context/llpcCompiler.h b/llpc/context/llpcCompiler.h
index c51334405b..0e39d3c590 100644
--- a/llpc/context/llpcCompiler.h
+++ b/llpc/context/llpcCompiler.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -224,7 +224,7 @@ class Compiler : public ICompiler {
};
// Convert front-end LLPC shader stage to middle-end LGC shader stage
-lgc::ShaderStage getLgcShaderStage(ShaderStage stage);
+lgc::ShaderStageEnum getLgcShaderStage(ShaderStage stage);
// Convert front-end LLPC shader stage to middle-end LGC rt shader stage.
// Returns std::nullopt if not a raytracing stage.
diff --git a/llpc/context/llpcComputeContext.cpp b/llpc/context/llpcComputeContext.cpp
index 13dd529fba..c2a6b9b9f0 100644
--- a/llpc/context/llpcComputeContext.cpp
+++ b/llpc/context/llpcComputeContext.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -79,7 +79,7 @@ void ComputeContext::setPipelineState(lgc::Pipeline *pipeline, Util::MetroHash64
PipelineContext::setPipelineState(pipeline, hasher, unlinked);
if (pipeline)
- pipeline->setShaderOptions(lgc::ShaderStageCompute, computeShaderOptions(m_pipelineInfo->cs));
+ pipeline->setShaderOptions(lgc::ShaderStage::Compute, computeShaderOptions(m_pipelineInfo->cs));
}
// =====================================================================================================================
diff --git a/llpc/context/llpcComputeContext.h b/llpc/context/llpcComputeContext.h
index 08809842bd..7dccf683bc 100644
--- a/llpc/context/llpcComputeContext.h
+++ b/llpc/context/llpcComputeContext.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/context/llpcContext.cpp b/llpc/context/llpcContext.cpp
index f7cdd0dc54..ec5f7946fb 100644
--- a/llpc/context/llpcContext.cpp
+++ b/llpc/context/llpcContext.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/context/llpcContext.h b/llpc/context/llpcContext.h
index 54b77138dd..992c2d5a6e 100644
--- a/llpc/context/llpcContext.h
+++ b/llpc/context/llpcContext.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/context/llpcDialect.h b/llpc/context/llpcDialect.h
index a03b39e54a..1bc9471c52 100644
--- a/llpc/context/llpcDialect.h
+++ b/llpc/context/llpcDialect.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/context/llpcGraphicsContext.cpp b/llpc/context/llpcGraphicsContext.cpp
index e9aa0de691..1839b03d41 100644
--- a/llpc/context/llpcGraphicsContext.cpp
+++ b/llpc/context/llpcGraphicsContext.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -217,9 +217,9 @@ void GraphicsContext::setTcsInputVertices(Module *tcsModule) {
const auto &inputIaState = static_cast<const GraphicsPipelineBuildInfo *>(getPipelineBuildInfo())->iaState;
if (inputIaState.patchControlPoints == 0)
return;
- TessellationMode tessellationMode = lgc::Pipeline::getTessellationMode(*tcsModule, lgc::ShaderStageTessControl);
+ TessellationMode tessellationMode = lgc::Pipeline::getTessellationMode(*tcsModule, lgc::ShaderStage::TessControl);
tessellationMode.inputVertices = inputIaState.patchControlPoints;
- lgc::Pipeline::setTessellationMode(*tcsModule, lgc::ShaderStageTessControl, tessellationMode);
+ lgc::Pipeline::setTessellationMode(*tcsModule, lgc::ShaderStage::TessControl, tessellationMode);
}
// =====================================================================================================================
@@ -250,6 +250,7 @@ Options GraphicsContext::computePipelineOptions() const {
options.enableUberFetchShader = pipelineInfo->enableUberFetchShader;
options.enableColorExportShader = pipelineInfo->enableColorExportShader;
options.useSoftwareVertexBufferDescriptors = pipelineInfo->useSoftwareVertexBufferDescriptors;
+ options.vbAddressLowBitsKnown = pipelineInfo->vbAddressLowBitsKnown;
if (getGfxIpVersion().major >= 10) {
// Only set NGG options for a GFX10+ graphics pipeline.
const auto &nggState = pipelineInfo->nggState;
@@ -389,6 +390,9 @@ void GraphicsContext::setVertexInputDescriptions(Pipeline *pipeline, Util::Metro
// Gather the vertex inputs.
SmallVector<VertexInputDescription, 8> descriptions;
+ auto vbLowBits = static_cast<const GraphicsPipelineBuildInfo *>(getPipelineBuildInfo())->vbAddressLowBits;
+ auto vbAddressLowBitsKnown =
+ static_cast<const GraphicsPipelineBuildInfo *>(getPipelineBuildInfo())->vbAddressLowBitsKnown;
for (unsigned i = 0; i < vertexInput->vertexAttributeDescriptionCount; ++i) {
auto attrib = &vertexInput->pVertexAttributeDescriptions[i];
if (attrib->binding >= bindings.size())
@@ -400,20 +404,15 @@ void GraphicsContext::setVertexInputDescriptions(Pipeline *pipeline, Util::Metro
auto dfmt = BufDataFormatInvalid;
auto nfmt = BufNumFormatUnorm;
std::tie(dfmt, nfmt) = mapVkFormat(attrib->format, /*isColorExport=*/false);
+ const uint8_t vbOffsetLowBits = vbAddressLowBitsKnown ? vbLowBits[attrib->binding] : 0;
if (dfmt != BufDataFormatInvalid) {
- descriptions.push_back({
- attrib->location,
- attrib->binding,
- attrib->offset,
- (static_cast<const GraphicsPipelineBuildInfo *>(getPipelineBuildInfo())->dynamicVertexStride
- ? 0
- : binding->stride),
- dfmt,
- nfmt,
- binding->inputRate,
- binding->divisor,
- });
+ descriptions.push_back(
+ {attrib->location, attrib->binding, attrib->offset,
+ (static_cast<const GraphicsPipelineBuildInfo *>(getPipelineBuildInfo())->dynamicVertexStride
+ ? 0
+ : binding->stride),
+ dfmt, nfmt, binding->inputRate, binding->divisor, vbOffsetLowBits});
}
}
diff --git a/llpc/context/llpcGraphicsContext.h b/llpc/context/llpcGraphicsContext.h
index 968e6d0ca3..9ff9ac8cd1 100644
--- a/llpc/context/llpcGraphicsContext.h
+++ b/llpc/context/llpcGraphicsContext.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/context/llpcPipelineContext.cpp b/llpc/context/llpcPipelineContext.cpp
index f808c4d294..888afca8a6 100644
--- a/llpc/context/llpcPipelineContext.cpp
+++ b/llpc/context/llpcPipelineContext.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -256,7 +256,7 @@ void PipelineContext::setPipelineState(Pipeline *pipeline, Util::MetroHash64 *ha
pipeline->setPreRasterHasGs(true);
}
// Give the shader stage mask to the middle-end. We need to translate the Vkgc::ShaderStage bit numbers
- // to lgc::ShaderStage bit numbers. We only process native shader stages, ignoring the CopyShader stage.
+ // to lgc::ShaderStageEnum bit numbers. We only process native shader stages, ignoring the CopyShader stage.
unsigned stageMask = getShaderStageMask();
if (hasRayTracingShaderStage(stageMask))
stageMask = ShaderStageComputeBit;
@@ -346,6 +346,7 @@ Options PipelineContext::computePipelineOptions() const {
options.rtBoxSortHeuristicMode = m_rtState.boxSortHeuristicMode;
options.rtStaticPipelineFlags = m_rtState.staticPipelineFlags;
options.rtTriCompressMode = m_rtState.triCompressMode;
+ options.disablePerCompFetch = getPipelineOptions()->disablePerCompFetch;
return options;
}
diff --git a/llpc/context/llpcPipelineContext.h b/llpc/context/llpcPipelineContext.h
index 8087285c05..cd51374f20 100644
--- a/llpc/context/llpcPipelineContext.h
+++ b/llpc/context/llpcPipelineContext.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/context/llpcRayTracingContext.cpp b/llpc/context/llpcRayTracingContext.cpp
index 42b28539bd..61be633825 100644
--- a/llpc/context/llpcRayTracingContext.cpp
+++ b/llpc/context/llpcRayTracingContext.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -49,9 +49,7 @@ RayTracingContext::RayTracingContext(GfxIpVersion gfxIP, const RayTracingPipelin
const PipelineShaderInfo *representativeShaderInfo, MetroHash::Hash *pipelineHash,
MetroHash::Hash *cacheHash, unsigned indirectStageMask)
: PipelineContext(gfxIP, pipelineHash, cacheHash), m_pipelineInfo(pipelineInfo), m_representativeShaderInfo(),
- m_linked(false), m_indirectStageMask(indirectStageMask), m_entryName(""),
- m_payloadMaxSize(pipelineInfo->payloadSizeMaxInLib), m_callableDataMaxSize(0),
- m_attributeDataMaxSize(pipelineInfo->attributeSizeMaxInLib) {
+ m_linked(false), m_indirectStageMask(indirectStageMask), m_entryName(""), m_callableDataMaxSize(0) {
const Vkgc::BinaryData *gpurtShaderLibrary = nullptr;
#if LLPC_CLIENT_INTERFACE_MAJOR_VERSION < 62
gpurtShaderLibrary = &pipelineInfo->shaderTraceRay;
@@ -104,7 +102,7 @@ void RayTracingContext::collectBuiltIn(unsigned builtIn) {
// @param dataLayout : Payload module data layout
void RayTracingContext::collectPayloadSize(llvm::Type *type, const DataLayout &dataLayout) {
unsigned payloadTypeSize = alignTo(dataLayout.getTypeAllocSize(type), 4);
- m_payloadMaxSize = std::max(m_payloadMaxSize, payloadTypeSize);
+ m_rtLibSummary.maxRayPayloadSize = std::max(m_rtLibSummary.maxRayPayloadSize, payloadTypeSize);
}
// =====================================================================================================================
@@ -124,14 +122,14 @@ void RayTracingContext::collectCallableDataSize(llvm::Type *type, const DataLayo
// @param dataLayout : module data layout
void RayTracingContext::collectAttributeDataSize(llvm::Type *type, const DataLayout &dataLayout) {
unsigned dataTypeSize = alignTo(dataLayout.getTypeAllocSize(type), 4);
- m_attributeDataMaxSize = std::max(m_attributeDataMaxSize, dataTypeSize);
+ m_rtLibSummary.maxHitAttributeSize = std::max(m_rtLibSummary.maxHitAttributeSize, dataTypeSize);
}
// =====================================================================================================================
// Get payload information
//
// @param builder : LGC builder
llvm::Type *RayTracingContext::getPayloadType(lgc::Builder *builder) {
- return ArrayType::get(builder->getInt32Ty(), m_payloadMaxSize / 4);
+ return ArrayType::get(builder->getInt32Ty(), divideCeil(m_rtLibSummary.maxRayPayloadSize, 4));
}
// =====================================================================================================================
@@ -139,7 +137,7 @@ llvm::Type *RayTracingContext::getPayloadType(lgc::Builder *builder) {
//
// @param builder : LGC builder
llvm::Type *RayTracingContext::getCallableDataType(lgc::Builder *builder) {
- return ArrayType::get(builder->getInt32Ty(), m_callableDataMaxSize / 4);
+ return ArrayType::get(builder->getInt32Ty(), divideCeil(m_callableDataMaxSize, 4));
}
// =====================================================================================================================
@@ -147,7 +145,7 @@ llvm::Type *RayTracingContext::getCallableDataType(lgc::Builder *builder) {
//
// @param builder : LGC builder
unsigned RayTracingContext::getAttributeDataSize() {
- return m_attributeDataMaxSize / 4;
+ return divideCeil(m_rtLibSummary.maxHitAttributeSize, 4);
}
// =====================================================================================================================
@@ -261,7 +259,7 @@ void RayTracingContext::setPipelineState(lgc::Pipeline *pipeline, Util::MetroHas
}
if (!hasRayTracingShaderStage(stageMask)) {
- unsigned deviceIndex = static_cast<const ComputePipelineBuildInfo *>(getPipelineBuildInfo())->deviceIndex;
+ unsigned deviceIndex = getRayTracingPipelineBuildInfo()->deviceIndex;
if (pipeline)
pipeline->setDeviceIndex(deviceIndex);
if (hasher)
@@ -283,6 +281,7 @@ lgc::Options RayTracingContext::computePipelineOptions() const {
options.rtIndirectMode = lgc::RayTracingIndirectMode::Continuations;
options.cpsFlags = m_pipelineInfo->cpsFlags;
+
#endif
return options;
diff --git a/llpc/context/llpcRayTracingContext.h b/llpc/context/llpcRayTracingContext.h
index 70275e018d..5b4eaa0db5 100644
--- a/llpc/context/llpcRayTracingContext.h
+++ b/llpc/context/llpcRayTracingContext.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -31,6 +31,7 @@
#pragma once
#include "llpcPipelineContext.h"
+#include "lgc/RayTracingLibrarySummary.h"
#include <set>
namespace lgc {
@@ -53,6 +54,7 @@ class RayTracingContext : public PipelineContext {
// Gets pipeline build info
virtual const void *getPipelineBuildInfo() const override { return m_pipelineInfo; }
+ const Vkgc::RayTracingPipelineBuildInfo *getRayTracingPipelineBuildInfo() const { return m_pipelineInfo; }
// Gets the mask of active shader stages bound to this pipeline
virtual unsigned getShaderStageMask() const override;
@@ -86,6 +88,8 @@ class RayTracingContext : public PipelineContext {
// Set the Context linked state
void setLinked(bool linked) { m_linked = linked; }
+ lgc::RayTracingLibrarySummary &getRayTracingLibrarySummary() { return m_rtLibSummary; }
+
// Get the raytracing indirect mask
const unsigned getIndirectStageMask() const { return m_indirectStageMask; }
@@ -104,11 +108,11 @@ class RayTracingContext : public PipelineContext {
llvm::Type *getCallableDataType(lgc::Builder *builder);
unsigned getCallableDataSizeInBytes() { return m_callableDataMaxSize; }
unsigned getAttributeDataSize();
- unsigned getAttributeDataSizeInBytes() { return m_attributeDataMaxSize; };
+ unsigned getAttributeDataSizeInBytes() { return m_rtLibSummary.maxHitAttributeSize; };
std::set<unsigned, std::less<unsigned>> &getBuiltIns() { return m_builtIns; }
- bool getHitAttribute() { return m_attributeDataMaxSize > 0; }
- unsigned getPayloadSizeInDword() { return m_payloadMaxSize / 4; }
- unsigned getPayloadSizeInBytes() { return m_payloadMaxSize; }
+ bool getHitAttribute() { return m_rtLibSummary.maxHitAttributeSize > 0; }
+ unsigned getPayloadSizeInDword() { return llvm::divideCeil(m_rtLibSummary.maxRayPayloadSize, 4); }
+ unsigned getPayloadSizeInBytes() { return m_rtLibSummary.maxRayPayloadSize; }
bool hasPipelineLibrary() { return m_pipelineInfo->hasPipelineLibrary; }
unsigned hasLibraryStage(unsigned stageMask) { return m_pipelineInfo->pipelineLibStageMask & stageMask; }
bool isReplay() { return m_pipelineInfo->isReplay; }
@@ -133,10 +137,9 @@ class RayTracingContext : public PipelineContext {
bool m_linked; // Whether the context is linked or not
unsigned m_indirectStageMask; // Which stages enable indirect call for ray tracing
std::string m_entryName; // Entry function of the raytracing module
- unsigned m_payloadMaxSize; // Payloads maximum size
unsigned m_callableDataMaxSize; // Callable maximum size
- unsigned m_attributeDataMaxSize; // Attribute maximum size
std::set<unsigned, std::less<unsigned>> m_builtIns; // Collected raytracing
+ lgc::RayTracingLibrarySummary m_rtLibSummary = {};
};
} // namespace Llpc
diff --git a/llpc/context/llpcStub.cpp b/llpc/context/llpcStub.cpp
index 993ac36539..30b8484b21 100644
--- a/llpc/context/llpcStub.cpp
+++ b/llpc/context/llpcStub.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/llpc/include/llpc.h b/llpc/include/llpc.h
index 60735d54f2..ff6d917946 100644
--- a/llpc/include/llpc.h
+++ b/llpc/include/llpc.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -154,6 +154,8 @@ struct RayTracingPipelineBuildOut {
BinaryData *pipelineBins; ///< Output pipeline binary datas
Vkgc::RayTracingShaderGroupHandle shaderGroupHandle; ///< Output data for shader group handle
Vkgc::RayTracingShaderPropertySet shaderPropSet; ///< Output property of a set of shader
+ BinaryData librarySummary; ///< Output MsgPack summary for use in library link; not created
+ ///< when compiling in pure pipeline mode
bool hasTraceRay; ///< Output whether have traceray module
};
diff --git a/llpc/lower/LowerGLCompatibility.cpp b/llpc/lower/LowerGLCompatibility.cpp
index 5a2c2cad54..cb2d972495 100644
--- a/llpc/lower/LowerGLCompatibility.cpp
+++ b/llpc/lower/LowerGLCompatibility.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -46,7 +46,8 @@ namespace Llpc {
// =====================================================================================================================
LowerGLCompatibility::LowerGLCompatibility()
- : m_retInst(nullptr), m_out(nullptr), m_clipVertex(nullptr), m_clipDistance(nullptr), m_clipPlane(nullptr) {
+ : m_retInst(nullptr), m_out(nullptr), m_clipVertex(nullptr), m_clipDistance(nullptr), m_clipPlane(nullptr),
+ m_frontColor(nullptr), m_backColor(nullptr), m_frontSecondaryColor(nullptr), m_backSecondaryColor(nullptr) {
}
// =====================================================================================================================
@@ -63,7 +64,8 @@ PreservedAnalyses LowerGLCompatibility::run(Module &module, ModuleAnalysisManage
collectEmulationResource();
- if (!needLowerClipVertex())
+ if (!needLowerClipVertex() && !needLowerFrontColor() && !needLowerBackColor() && !needLowerFrontSecondaryColor() &&
+ !needLowerBackSecondaryColor())
return PreservedAnalyses::all();
buildPatchPositionInfo();
@@ -71,6 +73,18 @@ PreservedAnalyses LowerGLCompatibility::run(Module &module, ModuleAnalysisManage
if (needLowerClipVertex())
lowerClipVertex();
+ if (needLowerFrontColor())
+ lowerFrontColor();
+
+ if (needLowerBackColor())
+ lowerBackColor();
+
+ if (needLowerFrontSecondaryColor())
+ lowerFrontSecondaryColor();
+
+ if (needLowerBackSecondaryColor())
+ lowerBackSecondaryColor();
+
return PreservedAnalyses::none();
}
@@ -84,6 +98,10 @@ bool LowerGLCompatibility::needRun() {
->getPipelineShaderInfo(m_shaderStage)
->pModuleData);
result |= moduleData->usage.useClipVertex;
+ result |= moduleData->usage.useFrontColor;
+ result |= moduleData->usage.useBackColor;
+ result |= moduleData->usage.useFrontSecondaryColor;
+ result |= moduleData->usage.useBackSecondaryColor;
}
return result;
}
@@ -212,7 +230,7 @@ void LowerGLCompatibility::collectEmitInst() {
auto mangledName = function.getName();
// We get all users before iterating because the iterator can be invalidated
// by interpolateInputElement
- if (mangledName.startswith(gSPIRVName::EmitVertex) || mangledName.startswith(gSPIRVName::EmitStreamVertex)) {
+ if (mangledName.starts_with(gSPIRVName::EmitVertex) || mangledName.starts_with(gSPIRVName::EmitStreamVertex)) {
SmallVector<User *> users(function.users());
for (User *user : users) {
assert(isa<CallInst>(user) && "We should only have CallInst instructions here.");
@@ -252,6 +270,30 @@ void LowerGLCompatibility::collectEmulationResource() {
else
m_clipVertex = &global;
}
+ if (md.Value == Vkgc::GlCompatibilityInOutLocation::FrontColor) {
+ if (isStructureOrArrayOfStructure)
+ m_out = &global;
+ else
+ m_frontColor = &global;
+ }
+ if (md.Value == Vkgc::GlCompatibilityInOutLocation::BackColor) {
+ if (isStructureOrArrayOfStructure)
+ m_out = &global;
+ else
+ m_backColor = &global;
+ }
+ if (md.Value == Vkgc::GlCompatibilityInOutLocation::FrontSecondaryColor) {
+ if (isStructureOrArrayOfStructure)
+ m_out = &global;
+ else
+ m_frontSecondaryColor = &global;
+ }
+ if (md.Value == Vkgc::GlCompatibilityInOutLocation::BackSecondaryColor) {
+ if (isStructureOrArrayOfStructure)
+ m_out = &global;
+ else
+ m_backSecondaryColor = &global;
+ }
} else if (md.IsBuiltIn && md.Value == spv::BuiltInClipDistance) {
if (isStructureOrArrayOfStructure)
m_out = &global;
@@ -272,30 +314,51 @@ void LowerGLCompatibility::collectEmulationResource() {
assert(metaNode);
auto inOutMetaConst = mdconst::dyn_extract<Constant>(metaNode->getOperand(0));
for (User *user : m_out->users()) {
- if (GetElementPtrInst *gep = dyn_cast<GetElementPtrInst>(user)) {
- // The user is a GEP
- // Check to see if the value has been stored.
- bool beenModified = false;
- for (User *gepUser : gep->users()) {
- assert(!isa<GetElementPtrInst>(gepUser));
- beenModified |= isa<StoreInst>(gepUser);
+ SmallVector<Value *> indexOperands;
+ // The user is a GEP
+ // Check to see if the value has been stored.
+ bool beenModified = false;
+ User *gep = nullptr;
+ if (auto *gepConst = dyn_cast<ConstantExpr>(user)) {
+ auto operandsCount = gepConst->getNumOperands();
+ // Skip the first indices, and the access chain target.
+ for (size_t index = 2; index < operandsCount; index++) {
+ auto *pIndex = dyn_cast<ConstantInt>(gepConst->getOperand(index));
+ if (pIndex) {
+ indexOperands.push_back(pIndex);
+ }
}
-
+ gep = gepConst;
+ } else if (auto *gepInst = dyn_cast<GetElementPtrInst>(user)) {
// We shouldn't have any chained GEPs here, they are coalesced by the LowerAccessChain pass.
- SmallVector<Value *> indexOperands;
- for (auto index = gep->idx_begin(); index != gep->idx_end(); index++) {
+ for (auto index = gepInst->idx_begin(); index != gepInst->idx_end(); index++) {
// Skip the first indices, it should be 0 in most of time.
- if (index == gep->idx_begin()) {
- assert(cast<ConstantInt>(gep->idx_begin())->isZero() && "Non-zero GEP first index\n");
+ if (index == gepInst->idx_begin()) {
+ assert(cast<ConstantInt>(gepInst->idx_begin())->isZero() && "Non-zero GEP first index\n");
continue;
}
indexOperands.push_back(m_builder->CreateZExtOrTrunc(index->get(), m_builder->getInt32Ty()));
}
+ gep = gepInst;
+ }
+ if (gep != nullptr) {
+ for (User *gepUser : gep->users()) {
+ assert(!isa<GetElementPtrInst>(gepUser));
+ beenModified |= isa<StoreInst>(gepUser);
+ }
decodeInOutMetaRecursivelyByIndex(glOut->getValueType(), inOutMetaConst, indexOperands, mds);
for (auto md : mds) {
if (md.IsLoc) {
if (beenModified && (md.Value == Vkgc::GlCompatibilityInOutLocation::ClipVertex))
m_clipVertex = gep;
+ if (beenModified && (md.Value == Vkgc::GlCompatibilityInOutLocation::FrontColor))
+ m_frontColor = gep;
+ if (beenModified && (md.Value == Vkgc::GlCompatibilityInOutLocation::BackColor))
+ m_backColor = gep;
+ if (beenModified && (md.Value == Vkgc::GlCompatibilityInOutLocation::FrontSecondaryColor))
+ m_frontSecondaryColor = gep;
+ if (beenModified && (md.Value == Vkgc::GlCompatibilityInOutLocation::BackSecondaryColor))
+ m_backSecondaryColor = gep;
} else if (md.IsBuiltIn && md.Value == spv::BuiltInClipDistance) {
m_clipDistance = gep;
}
@@ -320,6 +383,30 @@ bool LowerGLCompatibility::needLowerClipVertex() {
return (m_clipVertex != nullptr && !m_clipVertex->user_empty());
}
+// =====================================================================================================================
+// Check whether need do lower for FrontColor.
+bool LowerGLCompatibility::needLowerFrontColor() {
+ return (m_frontColor != nullptr && !m_frontColor->user_empty());
+}
+
+// =====================================================================================================================
+// Check whether need do lower for FrontColor.
+bool LowerGLCompatibility::needLowerBackColor() {
+ return (m_backColor != nullptr && !m_backColor->user_empty());
+}
+
+// =====================================================================================================================
+// Check whether need do lower for FrontColor.
+bool LowerGLCompatibility::needLowerFrontSecondaryColor() {
+ return (m_frontSecondaryColor != nullptr && !m_frontSecondaryColor->user_empty());
+}
+
+// =====================================================================================================================
+// Check whether need do lower for FrontColor.
+bool LowerGLCompatibility::needLowerBackSecondaryColor() {
+ return (m_backSecondaryColor != nullptr && !m_backSecondaryColor->user_empty());
+}
+
// =====================================================================================================================
// Create the SPIR-V output builtin variable "ClipDistance".
void LowerGLCompatibility::createClipDistance() {
@@ -430,6 +517,19 @@ void LowerGLCompatibility::emulateStoreClipVertex() {
}
}
+// =====================================================================================================================
+// Inline the emulation instruction of front/back/front secondary/back secondary color.
+void LowerGLCompatibility::emulationOutputColor(llvm::User *color) {
+ auto floatType = m_builder->getFloatTy();
+ Type *vec4Type = VectorType::get(floatType, 4, false);
+ // Load frontColor
+ Value *colorOperand = m_builder->CreateLoad(vec4Type, color);
+ Value *clampedColor =
+ m_builder->CreateFClamp(colorOperand, ConstantFP::get(vec4Type, 0.0), ConstantFP::get(vec4Type, 1.0));
+ // Store frontColor
+ m_builder->CreateStore(clampedColor, color);
+}
+
// =====================================================================================================================
// Does lowering operations for GLSL variable "gl_ClipVertex".
void LowerGLCompatibility::lowerClipVertex() {
@@ -451,4 +551,45 @@ void LowerGLCompatibility::lowerClipVertex() {
}
}
+// =====================================================================================================================
+// Does lowering operations for GLSL variable "gl_FrontColor" or "gl_BackColor" or "gl_FrontSecondaryColor" or
+// "gl_BackSecondaryColor".
+void LowerGLCompatibility::lowerColor(llvm::User *color) {
+ if (m_shaderStage == ShaderStageVertex || m_shaderStage == ShaderStageTessControl ||
+ m_shaderStage == ShaderStageTessEval) {
+ assert(m_retInst != nullptr);
+ m_builder->SetInsertPoint(m_retInst);
+ emulationOutputColor(color);
+ } else if (m_shaderStage == ShaderStageGeometry) {
+ for (auto emitCall : m_emitCalls) {
+ m_builder->SetInsertPoint(emitCall);
+ emulationOutputColor(color);
+ }
+ }
+}
+
+// =====================================================================================================================
+// Does lowering operations for GLSL variable "gl_FrontColor".
+void LowerGLCompatibility::lowerFrontColor() {
+ lowerColor(m_frontColor);
+}
+
+// =====================================================================================================================
+// Does lowering operations for GLSL variable "gl_BackColor".
+void LowerGLCompatibility::lowerBackColor() {
+ lowerColor(m_backColor);
+}
+
+// =====================================================================================================================
+// Does lowering operations for GLSL variable "gl_FrontSecondaryColor".
+void LowerGLCompatibility::lowerFrontSecondaryColor() {
+ lowerColor(m_frontSecondaryColor);
+}
+
+// =====================================================================================================================
+// Does lowering operations for GLSL variable "gl_BackSecondaryColor".
+void LowerGLCompatibility::lowerBackSecondaryColor() {
+ lowerColor(m_backSecondaryColor);
+}
+
} // namespace Llpc
diff --git a/llpc/lower/LowerGLCompatibility.h b/llpc/lower/LowerGLCompatibility.h
index e8fde951c7..6ab393a41b 100644
--- a/llpc/lower/LowerGLCompatibility.h
+++ b/llpc/lower/LowerGLCompatibility.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -58,19 +58,33 @@ class LowerGLCompatibility : public SpirvLower, public llvm::PassInfoMixin<Lower
// The function use to lower gl_ClipVertex
bool needLowerClipVertex();
+ bool needLowerFrontColor();
+ bool needLowerBackColor();
+ bool needLowerFrontSecondaryColor();
+ bool needLowerBackSecondaryColor();
void createClipDistance();
void createClipPlane();
void emulateStoreClipVertex();
+ void emulationOutputColor(llvm::User *color);
void lowerClipVertex();
+ void lowerColor(llvm::User *color);
+ void lowerFrontColor();
+ void lowerBackColor();
+ void lowerFrontSecondaryColor();
+ void lowerBackSecondaryColor();
llvm::SmallVector<llvm::CallInst *> m_emitCalls; // "Call" instructions to emit vertex (geometry shader).
llvm::ReturnInst *m_retInst; // "Return" of the entry point.
// The resource use to lower gl_ClipVertex
- llvm::User *m_out; // The global variable of gl_out[]
- llvm::User *m_clipVertex; // The global variable of gl_ClipVertex
- llvm::User *m_clipDistance; // The global variable of gl_ClipDistance
- llvm::User *m_clipPlane; // The global variable of gl_ClipPlane
+ llvm::User *m_out; // The global variable of gl_out[]
+ llvm::User *m_clipVertex; // The global variable of gl_ClipVertex
+ llvm::User *m_clipDistance; // The global variable of gl_ClipDistance
+ llvm::User *m_clipPlane; // The global variable of gl_ClipPlane
+ llvm::User *m_frontColor; // The global variable of gl_FrontColor
+ llvm::User *m_backColor; // The global variable of gl_BackColor
+ llvm::User *m_frontSecondaryColor; // The global variable of gl_FrontSecondaryColor
+ llvm::User *m_backSecondaryColor; // The global variable of gl_BackSecondaryColor
};
} // namespace Llpc
diff --git a/llpc/lower/PassRegistry.inc b/llpc/lower/PassRegistry.inc
index c0afde0d2a..d38e26d0c4 100644
--- a/llpc/lower/PassRegistry.inc
+++ b/llpc/lower/PassRegistry.inc
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -33,6 +33,14 @@
#define LLPC_MODULE_PASS LLPC_PASS
#endif
+LLPC_MODULE_PASS("inline", AlwaysInlinerPass)
+LLPC_MODULE_PASS("globaldce", GlobalDCEPass)
+LLPC_MODULE_PASS("sroa", SROAPass)
+LLPC_MODULE_PASS("globalopt", GlobalOptPass)
+LLPC_MODULE_PASS("adce", ADCEPass)
+LLPC_MODULE_PASS("instcombine", InstCombinePass)
+LLPC_MODULE_PASS("simplifycfg", SimplifyCFGPass)
+LLPC_MODULE_PASS("early-cse", EarlyCSEPass)
LLPC_MODULE_PASS("llpc-spirv-lower-gl-compatibility", LowerGLCompatibility)
LLPC_MODULE_PASS("llpc-spirv-lower-access-chain", SpirvLowerAccessChain)
LLPC_MODULE_PASS("llpc-spirv-lower-cfg-merges", SpirvLowerCfgMerges)
@@ -40,13 +48,11 @@ LLPC_MODULE_PASS("llpc-spirv-lower-const-immediate-store", SpirvLowerConstImmedi
LLPC_MODULE_PASS("llpc-spirv-lower-cooperative-matrix", SpirvLowerCooperativeMatrix)
LLPC_MODULE_PASS("llpc-spirv-lower-inst-meta-remove", SpirvLowerInstMetaRemove)
LLPC_MODULE_PASS("llpc-spirv-lower-terminator", SpirvLowerTerminator)
-LLPC_MODULE_PASS("llpc-spirv-lower-translator", SpirvLowerTranslator)
LLPC_MODULE_PASS("llpc-spirv-lower-global", SpirvLowerGlobal)
LLPC_MODULE_PASS("llpc-spirv-lower-math-const-folding", SpirvLowerMathConstFolding)
LLPC_MODULE_PASS("llpc-spirv-lower-math-precision", SpirvLowerMathPrecision)
LLPC_MODULE_PASS("llpc-spirv-lower-math-float-op", SpirvLowerMathFloatOp)
LLPC_MODULE_PASS("llpc-spirv-lower-memory-op", SpirvLowerMemoryOp)
-LLPC_MODULE_PASS("llpc-spirv-lower-ray-query", SpirvLowerRayQuery)
LLPC_MODULE_PASS("llpc-spirv-lower-ray-tracing", SpirvLowerRayTracing)
LLPC_MODULE_PASS("llpc-spirv-lower-ray-query-post-inline", SpirvLowerRayQueryPostInline)
diff --git a/llpc/lower/llpcSpirvLower.cpp b/llpc/lower/llpcSpirvLower.cpp
index f9dd95d2fa..2dbc5697ad 100644
--- a/llpc/lower/llpcSpirvLower.cpp
+++ b/llpc/lower/llpcSpirvLower.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -286,11 +286,21 @@ void SpirvLower::addPasses(Context *context, ShaderStage stage, lgc::PassManager
}
}
+// =====================================================================================================================
+// Register all the translation passes into the given pass manager
+//
+// @param [in/out] passMgr : Pass manager
+void SpirvLower::registerTranslationPasses(lgc::PassManager &passMgr) {
+ passMgr.registerPass("llpc-spirv-lower-translator", SpirvLowerTranslator::name());
+ passMgr.registerPass("llpc-spirv-lower-ray-query", SpirvLowerRayQuery::name());
+ passMgr.registerPass("llpc-spirv-lower-gpurt-library", SpirvProcessGpuRtLibrary::name());
+}
+
// =====================================================================================================================
// Register all the lowering passes into the given pass manager
//
// @param [in/out] passMgr : Pass manager
-void SpirvLower::registerPasses(lgc::PassManager &passMgr) {
+void SpirvLower::registerLoweringPasses(lgc::PassManager &passMgr) {
#define LLPC_PASS(NAME, CLASS) passMgr.registerPass(NAME, CLASS::name());
#include "PassRegistry.inc"
}
diff --git a/llpc/lower/llpcSpirvLower.h b/llpc/lower/llpcSpirvLower.h
index 0b88628b87..c2e866df35 100644
--- a/llpc/lower/llpcSpirvLower.h
+++ b/llpc/lower/llpcSpirvLower.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -61,8 +61,10 @@ class SpirvLower {
// Add per-shader lowering passes to pass manager
static void addPasses(Context *context, ShaderStage stage, lgc::PassManager &passMgr, llvm::Timer *lowerTimer,
bool rayTracing, bool rayQuery, bool isInternalRtShader);
+ // Register all the translation passes into the given pass manager
+ static void registerTranslationPasses(lgc::PassManager &passMgr);
// Register all the lowering passes into the given pass manager
- static void registerPasses(lgc::PassManager &passMgr);
+ static void registerLoweringPasses(lgc::PassManager &passMgr);
static void removeConstantExpr(Context *context, llvm::GlobalVariable *global);
static void replaceConstWithInsts(Context *context, llvm::Constant *const constVal);
diff --git a/llpc/lower/llpcSpirvLowerAccessChain.cpp b/llpc/lower/llpcSpirvLowerAccessChain.cpp
index bf839c5ecb..5036f55d22 100644
--- a/llpc/lower/llpcSpirvLowerAccessChain.cpp
+++ b/llpc/lower/llpcSpirvLowerAccessChain.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/lower/llpcSpirvLowerAccessChain.h b/llpc/lower/llpcSpirvLowerAccessChain.h
index f2f57d7d30..fde884b00c 100644
--- a/llpc/lower/llpcSpirvLowerAccessChain.h
+++ b/llpc/lower/llpcSpirvLowerAccessChain.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/lower/llpcSpirvLowerCfgMerges.cpp b/llpc/lower/llpcSpirvLowerCfgMerges.cpp
index dd32838b27..94a82b6ebc 100644
--- a/llpc/lower/llpcSpirvLowerCfgMerges.cpp
+++ b/llpc/lower/llpcSpirvLowerCfgMerges.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -286,7 +286,7 @@ void SpirvLowerCfgMerges::mapConvergentValues(Module &module) {
Function *func = worklist.pop_back_val();
if (visited.count(func))
continue;
- if (func->getName().startswith("spirv.loop."))
+ if (func->getName().starts_with("spirv.loop."))
continue;
// Record each convergent call block and function
diff --git a/llpc/lower/llpcSpirvLowerCfgMerges.h b/llpc/lower/llpcSpirvLowerCfgMerges.h
index 18bb281a6a..39848809d2 100644
--- a/llpc/lower/llpcSpirvLowerCfgMerges.h
+++ b/llpc/lower/llpcSpirvLowerCfgMerges.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/lower/llpcSpirvLowerConstImmediateStore.cpp b/llpc/lower/llpcSpirvLowerConstImmediateStore.cpp
index 2ad59bca4c..e98e629ec6 100644
--- a/llpc/lower/llpcSpirvLowerConstImmediateStore.cpp
+++ b/llpc/lower/llpcSpirvLowerConstImmediateStore.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/lower/llpcSpirvLowerConstImmediateStore.h b/llpc/lower/llpcSpirvLowerConstImmediateStore.h
index 9dc51158c3..b506268dda 100644
--- a/llpc/lower/llpcSpirvLowerConstImmediateStore.h
+++ b/llpc/lower/llpcSpirvLowerConstImmediateStore.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/lower/llpcSpirvLowerCooperativeMatrix.cpp b/llpc/lower/llpcSpirvLowerCooperativeMatrix.cpp
index 6280a79364..0ecd2fb6b4 100644
--- a/llpc/lower/llpcSpirvLowerCooperativeMatrix.cpp
+++ b/llpc/lower/llpcSpirvLowerCooperativeMatrix.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -71,7 +71,7 @@ PreservedAnalyses LowerCooperativeMatrix::run() {
bool changed = false;
for (Function &function : m_module.functions()) {
- if (function.isDeclaration() && function.getName().startswith(LlpcName::SpirvCooperativeMatrixProxy)) {
+ if (function.isDeclaration() && function.getName().starts_with(LlpcName::SpirvCooperativeMatrixProxy)) {
for (User *user : function.users()) {
if (auto *call = dyn_cast<CallInst>(user)) {
assert(call->getCalledOperand() == &function);
diff --git a/llpc/lower/llpcSpirvLowerCooperativeMatrix.h b/llpc/lower/llpcSpirvLowerCooperativeMatrix.h
index 36eb73a0b2..dca651645f 100644
--- a/llpc/lower/llpcSpirvLowerCooperativeMatrix.h
+++ b/llpc/lower/llpcSpirvLowerCooperativeMatrix.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/lower/llpcSpirvLowerGlobal.cpp b/llpc/lower/llpcSpirvLowerGlobal.cpp
index d42db9252c..10bc5d68d3 100644
--- a/llpc/lower/llpcSpirvLowerGlobal.cpp
+++ b/llpc/lower/llpcSpirvLowerGlobal.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -194,8 +194,7 @@ static_assert(lgc::ShadingRateHorizontal4Pixels ==
// =====================================================================================================================
SpirvLowerGlobal::SpirvLowerGlobal()
- : m_retBlock(nullptr), m_lowerInputInPlace(false), m_lowerOutputInPlace(false),
- m_lastVertexProcessingStage(ShaderStageInvalid) {
+ : m_lowerInputInPlace(false), m_lowerOutputInPlace(false), m_lastVertexProcessingStage(ShaderStageInvalid) {
}
// =====================================================================================================================
@@ -271,7 +270,6 @@ bool SpirvLowerGlobal::runImpl(Module &module) {
lowerUniformConstants();
lowerAliasedVal();
lowerShaderRecordBuffer();
- cleanupReturnBlock();
return true;
}
@@ -307,21 +305,31 @@ void SpirvLowerGlobal::lowerEdgeFlag() {
// =====================================================================================================================
// Handle "return" instructions.
-void SpirvLowerGlobal::handleReturnInst() {
- for (Function &function : m_module->functions()) {
- // We only handle the "return" in entry point
- if (function.getLinkage() == GlobalValue::InternalLinkage)
- continue;
- for (BasicBlock &block : function) {
- Instruction *terminator = block.getTerminator();
- if (!terminator || terminator->getOpcode() != Instruction::Ret)
- continue;
- ReturnInst *returnInst = cast<ReturnInst>(terminator);
- assert(m_retBlock);
- BranchInst::Create(m_retBlock, &block);
- m_retInsts.insert(returnInst);
- }
+ReturnInst *SpirvLowerGlobal::ensureUnifiedReturn() {
+ SmallVector<ReturnInst *> retInsts;
+
+ for (BasicBlock &block : *m_entryPoint) {
+ if (auto *retInst = dyn_cast<ReturnInst>(block.getTerminator()))
+ retInsts.push_back(retInst);
}
+
+ if (retInsts.size() == 1)
+ return retInsts[0];
+
+ // There are more than 2 returns; create a unified return block.
+ //
+ // Also create a "unified return block" if there are no returns at all. Such a shader will surely hang or otherwise
+ // trigger UB if it is ever executed, but we still need to compile it correctly in case it never runs.
+ BasicBlock *retBlock = BasicBlock::Create(*m_context, "", m_entryPoint);
+
+ for (ReturnInst *retInst : retInsts) {
+ m_builder->SetInsertPoint(retInst);
+ m_builder->CreateBr(retBlock);
+ retInst->eraseFromParent();
+ }
+
+ m_builder->SetInsertPoint(retBlock);
+ return m_builder->CreateRetVoid();
}
// =====================================================================================================================
@@ -341,30 +349,30 @@ void SpirvLowerGlobal::handleCallInst(bool checkEmitCall, bool checkInterpCall)
assert(isa<CallInst>(user) && "We should only have CallInst instructions here.");
CallInst *callInst = cast<CallInst>(user);
if (checkEmitCall) {
- if (mangledName.startswith(gSPIRVName::EmitVertex) || mangledName.startswith(gSPIRVName::EmitStreamVertex))
+ if (mangledName.starts_with(gSPIRVName::EmitVertex) || mangledName.starts_with(gSPIRVName::EmitStreamVertex))
m_emitCalls.insert(callInst);
} else {
assert(checkInterpCall);
- if (mangledName.startswith(gSPIRVName::InterpolateAtCentroid) ||
- mangledName.startswith(gSPIRVName::InterpolateAtSample) ||
- mangledName.startswith(gSPIRVName::InterpolateAtOffset) ||
- mangledName.startswith(gSPIRVName::InterpolateAtVertexAMD)) {
+ if (mangledName.starts_with(gSPIRVName::InterpolateAtCentroid) ||
+ mangledName.starts_with(gSPIRVName::InterpolateAtSample) ||
+ mangledName.starts_with(gSPIRVName::InterpolateAtOffset) ||
+ mangledName.starts_with(gSPIRVName::InterpolateAtVertexAMD)) {
// Translate interpolation functions to LLPC intrinsic calls
auto loadSrc = callInst->getArgOperand(0);
unsigned interpLoc = InterpLocUnknown;
Value *auxInterpValue = nullptr;
- if (mangledName.startswith(gSPIRVName::InterpolateAtCentroid))
+ if (mangledName.starts_with(gSPIRVName::InterpolateAtCentroid))
interpLoc = InterpLocCentroid;
- else if (mangledName.startswith(gSPIRVName::InterpolateAtSample)) {
+ else if (mangledName.starts_with(gSPIRVName::InterpolateAtSample)) {
interpLoc = InterpLocSample;
auxInterpValue = callInst->getArgOperand(1); // Sample ID
- } else if (mangledName.startswith(gSPIRVName::InterpolateAtOffset)) {
+ } else if (mangledName.starts_with(gSPIRVName::InterpolateAtOffset)) {
interpLoc = InterpLocCenter;
auxInterpValue = callInst->getArgOperand(1); // Offset from pixel center
} else {
- assert(mangledName.startswith(gSPIRVName::InterpolateAtVertexAMD));
+ assert(mangledName.starts_with(gSPIRVName::InterpolateAtVertexAMD));
interpLoc = InterpLocCustom;
auxInterpValue = callInst->getArgOperand(1); // Vertex no.
}
@@ -595,13 +603,13 @@ void SpirvLowerGlobal::mapGlobalVariableToProxy(GlobalVariable *globalVar) {
assert(m_entryPoint);
removeConstantExpr(m_context, globalVar);
// Handle special globals, regular allocas will be removed by SROA pass.
- if (globalVar->getName().startswith(RtName::HitAttribute)) {
+ if (globalVar->getName().starts_with(RtName::HitAttribute)) {
proxy = m_entryPoint->getArg(1);
globalVar->replaceAllUsesWith(proxy);
- } else if (globalVar->getName().startswith(RtName::IncomingRayPayLoad)) {
+ } else if (globalVar->getName().starts_with(RtName::IncomingRayPayLoad)) {
proxy = m_entryPoint->getArg(0);
globalVar->replaceAllUsesWith(proxy);
- } else if (globalVar->getName().startswith(RtName::IncomingCallableData)) {
+ } else if (globalVar->getName().starts_with(RtName::IncomingCallableData)) {
proxy = m_entryPoint->getArg(0);
globalVar->replaceAllUsesWith(proxy);
} else {
@@ -786,27 +794,17 @@ void SpirvLowerGlobal::lowerInput() {
// =====================================================================================================================
// Does lowering operations for SPIR-V outputs, replaces outputs with proxy variables.
void SpirvLowerGlobal::lowerOutput() {
- // Note: indirect raytracing does not have output to lower and must return payload value
- if (m_context->getPipelineType() == PipelineType::RayTracing)
+ if (m_outputProxyMap.empty() && m_shaderStage != ShaderStageGeometry) {
+ // Skip lowering if there is no output for non-geometry shader
return;
+ }
- m_retBlock = BasicBlock::Create(*m_context, "", m_entryPoint);
- // Invoke handling of "return" instructions or "emit" calls
+ // Collect "emit" calls
if (m_shaderStage == ShaderStageGeometry)
handleCallInst(true, false);
- handleReturnInst();
-
- auto retInst = ReturnInst::Create(*m_context, m_retBlock);
-
- for (auto retInst : m_retInsts) {
- retInst->dropAllReferences();
- retInst->eraseFromParent();
- }
- if (m_outputProxyMap.empty() && m_shaderStage != ShaderStageGeometry) {
- // Skip lowering if there is no output for non-geometry shader
- return;
- }
+ // Create unified return block in which to place all the outputs from proxy variables
+ ReturnInst *retInst = ensureUnifiedReturn();
// NOTE: For tessellation control shader, we invoke handling of "load"/"store" instructions and replace all those
// instructions with import/export calls in-place.
@@ -847,10 +845,10 @@ void SpirvLowerGlobal::lowerOutput() {
m_builder->SetInsertPoint(emitCall);
auto mangledName = emitCall->getCalledFunction()->getName();
- if (mangledName.startswith(gSPIRVName::EmitStreamVertex))
+ if (mangledName.starts_with(gSPIRVName::EmitStreamVertex))
emitStreamId = cast<ConstantInt>(emitCall->getOperand(0))->getZExtValue();
else
- assert(mangledName.startswith(gSPIRVName::EmitVertex));
+ assert(mangledName.starts_with(gSPIRVName::EmitVertex));
Value *outputValue = m_builder->CreateLoad(proxyTy, proxy);
addCallInstForOutputExport(outputValue, meta, nullptr, 0, 0, 0, nullptr, nullptr, emitStreamId);
@@ -867,20 +865,29 @@ void SpirvLowerGlobal::lowerOutput() {
emitCall->eraseFromParent();
}
+ // NOTE: "Getelementptr" will propagate the address space of pointer value (output variable)
+ // to the element pointer value (destination). We have to clear the address space of this element pointer
+ // value. The original pointer value has been lowered and therefore the address space is invalid now.
for (auto outputMap : m_outputProxyMap) {
auto output = cast<GlobalVariable>(outputMap.first);
- for (auto user = output->user_begin(), end = output->user_end(); user != end; ++user) {
- // NOTE: "Getelementptr" and "bitCast" will propagate the address space of pointer value (output variable)
- // to the element pointer value (destination). We have to clear the address space of this element pointer
- // value. The original pointer value has been lowered and therefore the address space is invalid now.
- Instruction *inst = dyn_cast<Instruction>(*user);
- if (inst) {
- Type *instTy = inst->getType();
- if (isa<PointerType>(instTy) && instTy->getPointerAddressSpace() == SPIRAS_Output) {
- assert(isa<GetElementPtrInst>(inst) || isa<BitCastInst>(inst));
- Type *newInstTy = PointerType::get(*m_context, SPIRAS_Private);
- inst->mutateType(newInstTy);
+ SmallVector<Value *> propagationWorklist;
+ propagationWorklist.push_back(output);
+
+ while (!propagationWorklist.empty()) {
+ Value *current = propagationWorklist.pop_back_val();
+
+ for (User *user : current->users()) {
+ Instruction *inst = dyn_cast<Instruction>(user);
+ if (inst) {
+ Type *instTy = inst->getType();
+ if (isa<PointerType>(instTy) && instTy->getPointerAddressSpace() == SPIRAS_Output) {
+ assert(isa<GetElementPtrInst>(inst));
+ Type *newInstTy = PointerType::get(*m_context, SPIRAS_Private);
+ inst->mutateType(newInstTy);
+
+ propagationWorklist.push_back(user);
+ }
}
}
}
@@ -932,27 +939,6 @@ void SpirvLowerGlobal::lowerInOutInPlace() {
m_storeInsts.clear();
- // Remove unnecessary "atomicrmw" or "cmpxchg" instructions
- for (auto atomicInst : m_atomicInsts) {
- Value *pointer = nullptr;
- if (auto atomicRmw = dyn_cast<AtomicRMWInst>(atomicInst)) {
- pointer = atomicRmw->getPointerOperand();
- } else {
- auto cmpXchg = dyn_cast<AtomicCmpXchgInst>(atomicInst);
- assert(cmpXchg);
- pointer = cmpXchg->getPointerOperand();
- }
- GetElementPtrInst *const getElemPtr = dyn_cast<GetElementPtrInst>(pointer);
- if (getElemPtr)
- getElemInsts.insert(getElemPtr);
-
- assert(atomicInst->use_empty());
- atomicInst->dropAllReferences();
- atomicInst->eraseFromParent();
- }
-
- m_atomicInsts.clear();
-
// Remove unnecessary "getelementptr" instructions
while (!getElemInsts.empty()) {
GetElementPtrInst *const getElemPtr = *getElemInsts.begin();
@@ -1252,8 +1238,8 @@ Value *SpirvLowerGlobal::addCallInstForInOutImport(Type *inOutTy, unsigned addrS
->options.constantBufferBindingOffset;
Value *bufferDesc =
- m_builder->CreateLoadBufferDesc(Vkgc::InternalDescriptorSetId, constBufferBinding,
- m_builder->getInt32(0), lgc::Builder::BufferFlagNonConst);
+ m_builder->create<lgc::LoadBufferDescOp>(Vkgc::InternalDescriptorSetId, constBufferBinding,
+ m_builder->getInt32(0), lgc::Builder::BufferFlagNonConst);
// Layout is {width, height}, so the offset of height is added sizeof(float).
Value *winHeightPtr =
m_builder->CreateConstInBoundsGEP1_32(m_builder->getInt8Ty(), bufferDesc, offset + sizeof(float));
@@ -1864,7 +1850,7 @@ void SpirvLowerGlobal::lowerBufferBlock() {
SmallVector<ReplaceInstsInfo> instructionsToReplace;
for (Function *const func : funcsUsedIn) {
// Check if our block is an array of blocks.
- if (global.getValueType()->isArrayTy()) {
+ if (!atomicCounterMD && global.getValueType()->isArrayTy()) {
Type *const elementType = global.getValueType()->getArrayElementType();
// We need to run over the users of the global, find the GEPs, and add a load for each.
@@ -1908,20 +1894,13 @@ void SpirvLowerGlobal::lowerBufferBlock() {
Value *const bufferDesc =
isAccelerationStructure
? m_builder->CreateGetDescPtr(descTy, descTy, descSet, binding)
- : m_builder->CreateLoadBufferDesc(descSet, binding, m_builder->getInt32(0), bufferFlags);
+ : m_builder->create<lgc::LoadBufferDescOp>(descSet, binding, m_builder->getInt32(0), bufferFlags);
// If the global variable is a constant, the data it points to is invariant.
if (global.isConstant())
m_builder->CreateInvariantStart(bufferDesc);
- Value *newDescPtr = bufferDesc;
- if (atomicCounterMD) {
- SmallVector<Value *, 8> indices;
- indices.push_back(m_builder->getInt32(atomicCounterMeta.offset));
- newDescPtr = m_builder->CreateInBoundsGEP(m_builder->getInt8Ty(), bufferDesc, indices);
- }
-
- replaceInstsInfo.otherInst->replaceUsesOfWith(&global, newDescPtr);
+ replaceInstsInfo.otherInst->replaceUsesOfWith(&global, bufferDesc);
} else {
assert(!replaceInstsInfo.getElemPtrInsts.empty());
@@ -1944,7 +1923,7 @@ void SpirvLowerGlobal::lowerBufferBlock() {
(isa<ConstantInt>(indices[0]) && cast<ConstantInt>(indices[0])->getZExtValue() == 0));
// Get block index from the second gep index, if it is not zero.
- Value *const blockIndex = (isBlockIndexZero || atomicCounterMD) ? m_builder->getInt32(0) : indices[1];
+ Value *const blockIndex = isBlockIndexZero ? m_builder->getInt32(0) : indices[1];
bool isNonUniform = isShaderStageInMask(
m_shaderStage,
@@ -1961,7 +1940,7 @@ void SpirvLowerGlobal::lowerBufferBlock() {
if (!callee)
continue;
// If the call is our non uniform decoration, record we are non uniform.
- isNonUniform = callee->getName().startswith(gSPIRVName::NonUniform);
+ isNonUniform = callee->getName().starts_with(gSPIRVName::NonUniform);
break;
}
}
@@ -1975,7 +1954,7 @@ void SpirvLowerGlobal::lowerBufferBlock() {
continue;
// If the call is our non uniform decoration, record we are non uniform.
auto callee = call->getCalledFunction();
- if (callee && callee->getName().startswith(gSPIRVName::NonUniform)) {
+ if (callee && callee->getName().starts_with(gSPIRVName::NonUniform)) {
isNonUniform = true;
break;
}
@@ -2033,7 +2012,7 @@ void SpirvLowerGlobal::lowerBufferBlock() {
bufferDescs[idx] = m_builder->CreateGEP(m_builder->getInt8Ty(), descPtr, index);
} else {
bufferDescs[idx] =
- m_builder->CreateLoadBufferDesc(descSets[idx], bindings[idx], blockIndex, bufferFlags);
+ m_builder->create<lgc::LoadBufferDescOp>(descSets[idx], bindings[idx], blockIndex, bufferFlags);
}
// If the global variable is a constant, the data it points to is invariant.
if (global.isConstant())
@@ -2045,22 +2024,6 @@ void SpirvLowerGlobal::lowerBufferBlock() {
newSelect = m_builder->CreateSelect(select->getCondition(), bufferDescs[0], bufferDescs[1]);
Value *base = newSelect ? newSelect : bufferDescs[0];
- // If zero-index elimination removed leading zeros from OldGEP indices then we need to use OldGEP Source
- // type as a Source type for newGEP. In other cases use global variable array element type.
- Type *newGetElemType = gepsLeadingZerosEliminated ? getElemPtr->getSourceElementType() : elementType;
- if (atomicCounterMD) {
- // indices[1] store the array index, but may not be a constant
- if (isa<ConstantInt>(indices[1])) {
- indices[0] =
- m_builder->getInt32(atomicCounterMeta.offset + cast<ConstantInt>(indices[1])->getZExtValue() * 4);
- } else {
- auto atomicCounterElemOffset = m_builder->CreateMul(m_builder->getInt32(4), indices[1]);
- indices[0] =
- m_builder->CreateAdd(atomicCounterElemOffset, m_builder->getInt32(atomicCounterMeta.offset));
- }
- newGetElemType = m_builder->getInt8Ty();
- }
-
// We need to remove the block index from the original GEP indices so that we can use them, but first we
// have to check if it was not removed already by zero-index elimination.
if (!gepsLeadingZerosEliminated)
@@ -2073,6 +2036,9 @@ void SpirvLowerGlobal::lowerBufferBlock() {
newIndices = newIndices.drop_front(1);
Value *newGetElemPtr = nullptr;
+ // If zero-index elimination removed leading zeros from OldGEP indices then we need to use OldGEP Source
+ // type as a Source type for newGEP. In other cases use global variable array element type.
+ Type *newGetElemType = gepsLeadingZerosEliminated ? getElemPtr->getSourceElementType() : elementType;
if (getElemPtr->isInBounds())
newGetElemPtr = m_builder->CreateInBoundsGEP(newGetElemType, base, newIndices);
@@ -2095,7 +2061,7 @@ void SpirvLowerGlobal::lowerBufferBlock() {
Value *const bufferDesc =
isAccelerationStructure
? m_builder->CreateGetDescPtr(descTy, descTy, descSet, binding)
- : m_builder->CreateLoadBufferDesc(descSet, binding, m_builder->getInt32(0), bufferFlags);
+ : m_builder->create<lgc::LoadBufferDescOp>(descSet, binding, m_builder->getInt32(0), bufferFlags);
// If the global variable is a constant, the data it points to is invariant.
if (global.isConstant())
@@ -2120,8 +2086,8 @@ void SpirvLowerGlobal::lowerBufferBlock() {
Value *newLoadPtr = bufferDesc;
if (atomicCounterMD) {
SmallVector<Value *, 8> indices;
- indices.push_back(m_builder->getInt32(atomicCounterMeta.offset));
- newLoadPtr = m_builder->CreateInBoundsGEP(m_builder->getInt8Ty(), bufferDesc, indices);
+ indices.push_back(m_builder->getInt32(atomicCounterMeta.offset / 4));
+ newLoadPtr = m_builder->CreateInBoundsGEP(m_builder->getInt32Ty(), bufferDesc, indices);
}
for (Instruction *const use : usesToReplace)
@@ -2321,8 +2287,8 @@ void SpirvLowerGlobal::lowerUniformConstants() {
auto uniformConstantsOffset = mdconst::dyn_extract<ConstantInt>(metaNode->getOperand(2))->getZExtValue();
m_builder->SetInsertPointPastAllocas(eachFunc.first);
- Value *bufferDesc = m_builder->CreateLoadBufferDesc(uniformConstantsSet, uniformConstantsBinding,
- m_builder->getInt32(0), lgc::Builder::BufferFlagNonConst);
+ Value *bufferDesc = m_builder->create<lgc::LoadBufferDescOp>(
+ uniformConstantsSet, uniformConstantsBinding, m_builder->getInt32(0), lgc::Builder::BufferFlagNonConst);
Value *newPtr = m_builder->CreateConstInBoundsGEP1_32(m_builder->getInt8Ty(), bufferDesc, uniformConstantsOffset);
for (auto *inst : eachFunc.second)
inst->replaceUsesOfWith(&global, newPtr);
@@ -2337,17 +2303,6 @@ void SpirvLowerGlobal::lowerUniformConstants() {
}
}
-// =====================================================================================================================
-// Removes the created return block if it has a single predecessor. This is to avoid
-// scheduling future heavy-weight cleanup passes if we can trivially simplify the CFG here.
-void SpirvLowerGlobal::cleanupReturnBlock() {
- if (!m_retBlock)
- return;
-
- if (MergeBlockIntoPredecessor(m_retBlock))
- m_retBlock = nullptr;
-}
-
// =====================================================================================================================
// Interpolates an element of the input.
//
@@ -2518,7 +2473,7 @@ void SpirvLowerGlobal::lowerShaderRecordBuffer() {
static const char *ShaderRecordBuffer = "ShaderRecordBuffer";
for (GlobalVariable &global : m_module->globals()) {
- if (!global.getName().startswith(ShaderRecordBuffer))
+ if (!global.getName().starts_with(ShaderRecordBuffer))
continue;
removeConstantExpr(m_context, &global);
diff --git a/llpc/lower/llpcSpirvLowerGlobal.h b/llpc/lower/llpcSpirvLowerGlobal.h
index 720ba54684..1d0af2dde3 100644
--- a/llpc/lower/llpcSpirvLowerGlobal.h
+++ b/llpc/lower/llpcSpirvLowerGlobal.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -52,7 +52,6 @@ class SpirvLowerGlobal : public SpirvLower, public llvm::PassInfoMixin<SpirvLowe
bool runImpl(llvm::Module &module);
void handleCallInst(bool checkEmitCall, bool checkInterpCall);
- void handleReturnInst();
void handleLoadInst();
void handleLoadInstGEP(GlobalVariable *inOut, ArrayRef<Value *> indexOperands, LoadInst &loadInst);
@@ -67,6 +66,8 @@ class SpirvLowerGlobal : public SpirvLower, public llvm::PassInfoMixin<SpirvLowe
void mapInputToProxy(llvm::GlobalVariable *input);
void mapOutputToProxy(llvm::GlobalVariable *input);
+ llvm::ReturnInst *ensureUnifiedReturn();
+
void lowerGlobalVar();
void lowerInput();
void lowerOutput();
@@ -78,7 +79,6 @@ class SpirvLowerGlobal : public SpirvLower, public llvm::PassInfoMixin<SpirvLowe
void lowerAliasedVal();
void lowerEdgeFlag();
void lowerShaderRecordBuffer();
- void cleanupReturnBlock();
void handleVolatileInput(llvm::GlobalVariable *input, llvm::Value *proxy);
@@ -122,19 +122,15 @@ class SpirvLowerGlobal : public SpirvLower, public llvm::PassInfoMixin<SpirvLowe
// "ordered" (resulting LLVM IR for the patching always be consistent).
std::list<std::pair<llvm::Value *, llvm::AllocaInst *>> m_outputProxyMap; // Proxy list for lowering outputs
- llvm::BasicBlock *m_retBlock; // The return block of entry point
-
bool m_lowerInputInPlace; // Whether to lower input inplace
bool m_lowerOutputInPlace; // Whether to lower output inplace
- std::unordered_set<llvm::ReturnInst *> m_retInsts; // "Return" instructions to be removed
- std::unordered_set<llvm::CallInst *> m_emitCalls; // "Call" instructions to emit vertex (geometry shader)
- std::unordered_set<llvm::LoadInst *> m_loadInsts; // "Load" instructions to be removed
- std::unordered_set<llvm::StoreInst *> m_storeInsts; // "Store" instructions to be removed
- std::unordered_set<llvm::Instruction *> m_atomicInsts; // "Atomicrwm" or "cmpxchg" instructions to be removed
- std::unordered_set<llvm::CallInst *> m_interpCalls; // "Call" instruction to do input interpolation
- // (fragment shader)
- ShaderStage m_lastVertexProcessingStage; // The last vertex processing stage
+ std::unordered_set<llvm::CallInst *> m_emitCalls; // "Call" instructions to emit vertex (geometry shader)
+ std::unordered_set<llvm::LoadInst *> m_loadInsts; // "Load" instructions to be removed
+ std::unordered_set<llvm::StoreInst *> m_storeInsts; // "Store" instructions to be removed
+ std::unordered_set<llvm::CallInst *> m_interpCalls; // "Call" instruction to do input interpolation
+ // (fragment shader)
+ ShaderStage m_lastVertexProcessingStage; // The last vertex processing stage
llvm::DenseMap<unsigned, Vkgc::XfbOutInfo>
m_builtInXfbMap; // Map built-in to XFB output info specified by API interface
llvm::DenseMap<unsigned, Vkgc::XfbOutInfo>
diff --git a/llpc/lower/llpcSpirvLowerInstMetaRemove.cpp b/llpc/lower/llpcSpirvLowerInstMetaRemove.cpp
index 2a1be0eb0b..73fba67862 100644
--- a/llpc/lower/llpcSpirvLowerInstMetaRemove.cpp
+++ b/llpc/lower/llpcSpirvLowerInstMetaRemove.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -70,7 +70,7 @@ bool SpirvLowerInstMetaRemove::runImpl(Module &module) {
// Remove calls to functions whose names start with "spirv.NonUniform".
SmallVector<CallInst *, 8> callsToRemove;
for (auto &func : *m_module) {
- if (func.getName().startswith(gSPIRVName::NonUniform)) {
+ if (func.getName().starts_with(gSPIRVName::NonUniform)) {
for (auto &use : func.uses()) {
if (auto *callInst = dyn_cast<CallInst>(use.getUser())) {
if (callInst->isCallee(&use))
@@ -88,7 +88,7 @@ bool SpirvLowerInstMetaRemove::runImpl(Module &module) {
// Remove any named metadata in the module that starts "spirv.".
SmallVector<NamedMDNode *, 8> nodesToRemove;
for (auto &namedMdNode : m_module->named_metadata()) {
- if (namedMdNode.getName().startswith(gSPIRVMD::Prefix))
+ if (namedMdNode.getName().starts_with(gSPIRVMD::Prefix))
nodesToRemove.push_back(&namedMdNode);
}
for (NamedMDNode *namedMdNode : nodesToRemove) {
diff --git a/llpc/lower/llpcSpirvLowerInstMetaRemove.h b/llpc/lower/llpcSpirvLowerInstMetaRemove.h
index 29e5f934fe..886a11aa55 100644
--- a/llpc/lower/llpcSpirvLowerInstMetaRemove.h
+++ b/llpc/lower/llpcSpirvLowerInstMetaRemove.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/lower/llpcSpirvLowerInternalLibraryIntrinsicUtil.cpp b/llpc/lower/llpcSpirvLowerInternalLibraryIntrinsicUtil.cpp
index 620c745f3c..32f12fda05 100644
--- a/llpc/lower/llpcSpirvLowerInternalLibraryIntrinsicUtil.cpp
+++ b/llpc/lower/llpcSpirvLowerInternalLibraryIntrinsicUtil.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -74,7 +74,7 @@ static void createHalt(Function *func, Builder *builder) {
// @param func : The function to process
// @param builder : The IR builder
static void createNumWavesCompute(Function *func, Builder *builder) {
- Value *workgroupSize = builder->CreateReadBuiltInInput(lgc::BuiltInWorkgroupSize, {}, nullptr, nullptr, "");
+ Value *workgroupSize = builder->CreateReadBuiltInInput(lgc::BuiltInWorkgroupSize);
Value *workgroupSizeX = builder->CreateExtractElement(workgroupSize, uint64_t(0));
Value *workgroupSizeY = builder->CreateExtractElement(workgroupSize, 1);
Value *workgroupSizeZ = builder->CreateExtractElement(workgroupSize, 2);
@@ -93,11 +93,8 @@ static void createNumWavesCompute(Function *func, Builder *builder) {
// @param func : The function to process
// @param builder : The IR builder
static void createWaveIndexCompute(Function *func, Builder *builder) {
- // return (gl_LocalInvocationIndex / WaveSize)
- Value *flattenedThreadId =
- builder->CreateReadBuiltInInput(lgc::BuiltInLocalInvocationIndex, {}, nullptr, nullptr, "");
- Value *waveSize = builder->CreateGetWaveSize();
- builder->CreateRet(builder->CreateUDiv(flattenedThreadId, waveSize));
+ Value *waveId = builder->CreateReadBuiltInInput(lgc::BuiltInSubgroupId, {}, nullptr, nullptr, "");
+ builder->CreateRet(waveId);
}
// =====================================================================================================================
@@ -106,7 +103,7 @@ static void createWaveIndexCompute(Function *func, Builder *builder) {
// @param func : The function to process
// @param builder : The IR builder
static void createGroupIdCompute(Function *func, Builder *builder) {
- Value *workGroupId = builder->CreateReadBuiltInInput(lgc::BuiltInWorkgroupId, {}, nullptr, nullptr, "");
+ Value *workGroupId = builder->CreateReadBuiltInInput(lgc::BuiltInWorkgroupId);
builder->CreateRet(workGroupId);
}
@@ -116,7 +113,7 @@ static void createGroupIdCompute(Function *func, Builder *builder) {
// @param func : The function to process
// @param builder : The IR builder
static void createGroupDimCompute(Function *func, Builder *builder) {
- Value *workGroupSize = builder->CreateReadBuiltInInput(lgc::BuiltInWorkgroupSize, {}, nullptr, nullptr, "");
+ Value *workGroupSize = builder->CreateReadBuiltInInput(lgc::BuiltInWorkgroupSize);
builder->CreateRet(workGroupSize);
}
@@ -126,7 +123,7 @@ static void createGroupDimCompute(Function *func, Builder *builder) {
// @param func : The function to process
// @param builder : The IR builder
static void createThreadIdInGroupCompute(Function *func, Builder *builder) {
- Value *threadId = builder->CreateReadBuiltInInput(lgc::BuiltInLocalInvocationId, {}, nullptr, nullptr, "");
+ Value *threadId = builder->CreateReadBuiltInInput(lgc::BuiltInLocalInvocationId);
builder->CreateRet(threadId);
}
@@ -136,7 +133,7 @@ static void createThreadIdInGroupCompute(Function *func, Builder *builder) {
// @param func : The function to process
// @param builder : The IR builder
static void createFlattenedThreadIdInGroupCompute(Function *func, Builder *builder) {
- Value *threadId = builder->CreateReadBuiltInInput(lgc::BuiltInLocalInvocationIndex, {}, nullptr, nullptr, "");
+ Value *threadId = builder->CreateReadBuiltInInput(lgc::BuiltInLocalInvocationIndex);
builder->CreateRet(threadId);
}
diff --git a/llpc/lower/llpcSpirvLowerInternalLibraryIntrinsicUtil.h b/llpc/lower/llpcSpirvLowerInternalLibraryIntrinsicUtil.h
index f3bfdb987a..63ab5549ce 100644
--- a/llpc/lower/llpcSpirvLowerInternalLibraryIntrinsicUtil.h
+++ b/llpc/lower/llpcSpirvLowerInternalLibraryIntrinsicUtil.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/lower/llpcSpirvLowerMath.cpp b/llpc/lower/llpcSpirvLowerMath.cpp
index d56a9f7561..cefdaf312e 100644
--- a/llpc/lower/llpcSpirvLowerMath.cpp
+++ b/llpc/lower/llpcSpirvLowerMath.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -284,9 +284,9 @@ bool SpirvLowerMathPrecision::adjustExports(Module &module) {
// We need to find a neater way to do it.
auto funcName = func.getName();
bool isExport;
- if (funcName.startswith("lgc.output.export.builtin."))
+ if (funcName.starts_with("lgc.output.export.builtin."))
isExport = true;
- else if (funcName.startswith("lgc.create.write.builtin"))
+ else if (funcName.starts_with("lgc.create.write.builtin"))
isExport = false;
else
continue;
diff --git a/llpc/lower/llpcSpirvLowerMath.h b/llpc/lower/llpcSpirvLowerMath.h
index c729d10897..7720d0e9bf 100644
--- a/llpc/lower/llpcSpirvLowerMath.h
+++ b/llpc/lower/llpcSpirvLowerMath.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/lower/llpcSpirvLowerMemoryOp.cpp b/llpc/lower/llpcSpirvLowerMemoryOp.cpp
index 9f480e0999..86d67bce4a 100644
--- a/llpc/lower/llpcSpirvLowerMemoryOp.cpp
+++ b/llpc/lower/llpcSpirvLowerMemoryOp.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/lower/llpcSpirvLowerMemoryOp.h b/llpc/lower/llpcSpirvLowerMemoryOp.h
index 856bc93ff3..18ec4227fb 100644
--- a/llpc/lower/llpcSpirvLowerMemoryOp.h
+++ b/llpc/lower/llpcSpirvLowerMemoryOp.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/lower/llpcSpirvLowerRayQuery.cpp b/llpc/lower/llpcSpirvLowerRayQuery.cpp
index b9c0906969..751b77d956 100644
--- a/llpc/lower/llpcSpirvLowerRayQuery.cpp
+++ b/llpc/lower/llpcSpirvLowerRayQuery.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/lower/llpcSpirvLowerRayQuery.h b/llpc/lower/llpcSpirvLowerRayQuery.h
index 2b60b71c18..e6274d3f2c 100644
--- a/llpc/lower/llpcSpirvLowerRayQuery.h
+++ b/llpc/lower/llpcSpirvLowerRayQuery.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/lower/llpcSpirvLowerRayQueryPostInline.cpp b/llpc/lower/llpcSpirvLowerRayQueryPostInline.cpp
index 2d1cc2ba08..0673d9a477 100644
--- a/llpc/lower/llpcSpirvLowerRayQueryPostInline.cpp
+++ b/llpc/lower/llpcSpirvLowerRayQueryPostInline.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -73,7 +73,7 @@ bool SpirvLowerRayQueryPostInline::runImpl(Module &module) {
Function *func = &*funcIt++;
if ((func->getLinkage() == GlobalValue::ExternalLinkage || func->getLinkage() == GlobalValue::WeakAnyLinkage) &&
!func->empty()) {
- if (!func->getName().startswith(m_entryPoint->getName())) {
+ if (!func->getName().starts_with(m_entryPoint->getName())) {
func->dropAllReferences();
func->eraseFromParent();
}
diff --git a/llpc/lower/llpcSpirvLowerRayQueryPostInline.h b/llpc/lower/llpcSpirvLowerRayQueryPostInline.h
index 49b91c4602..389b9430a9 100644
--- a/llpc/lower/llpcSpirvLowerRayQueryPostInline.h
+++ b/llpc/lower/llpcSpirvLowerRayQueryPostInline.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/lower/llpcSpirvLowerRayTracing.cpp b/llpc/lower/llpcSpirvLowerRayTracing.cpp
index 19a830f33b..5e788af226 100644
--- a/llpc/lower/llpcSpirvLowerRayTracing.cpp
+++ b/llpc/lower/llpcSpirvLowerRayTracing.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -31,13 +31,16 @@
#include "llpcSpirvLowerRayTracing.h"
#include "SPIRVInternal.h"
+#include "continuations/ContinuationsUtil.h"
#include "gpurt-compiler.h"
#include "llpcContext.h"
#include "llpcRayTracingContext.h"
#include "llpcSpirvLowerUtil.h"
#include "lgc/Builder.h"
+#include "lgc/CommonDefs.h"
#include "lgc/GpurtDialect.h"
#include "lgc/LgcCpsDialect.h"
+#include "lgc/LgcDialect.h"
#include "lgc/LgcRtDialect.h"
#include "lgc/Pipeline.h"
#include "llvm-dialects/Dialect/Visitor.h"
@@ -46,7 +49,9 @@
#include "llvm/Analysis/ProfileSummaryInfo.h"
#include "llvm/IR/DIBuilder.h"
#include "llvm/IR/InstVisitor.h"
+#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Transforms/Utils/Cloning.h"
#define DEBUG_TYPE "llpc-spirv-lower-ray-tracing"
@@ -110,96 +115,73 @@ SpirvLowerRayTracing::SpirvLowerRayTracing() : SpirvLowerRayQuery(false) {
//
// @param inst : The original call instruction
void SpirvLowerRayTracing::processTraceRayCall(BaseTraceRayOp *inst) {
- std::string mangledName = inst->getCalledFunction()->getName().str() + ".impl";
-
- SmallVector<Value *, 12> implCallArgs(inst->args());
-
- auto rayTracingContext = static_cast<RayTracingContext *>(m_context->getPipelineContext());
-
- implCallArgs.push_back(m_traceParams[TraceParam::RayStaticId]);
- implCallArgs.push_back(m_traceParams[TraceParam::ParentRayId]);
- implCallArgs.push_back(m_dispatchRaysInfoDesc);
m_builder->SetInsertPoint(inst);
- // Generate a unique static ID for each trace ray call
- m_builder->CreateStore(m_builder->getInt32(generateTraceRayStaticId()), m_traceParams[TraceParam::RayStaticId]);
- auto newCall = m_builder->CreateNamedCall(mangledName, inst->getFunctionType()->getReturnType(), implCallArgs,
- {Attribute::NoUnwind, Attribute::AlwaysInline});
-
- inst->replaceAllUsesWith(newCall);
-
- auto func = m_module->getFunction(mangledName);
-
- if (func->isDeclaration()) {
- func->setLinkage(GlobalVariable::InternalLinkage);
- func->addFnAttr(Attribute::AlwaysInline);
-
- bool indirect = rayTracingContext->getIndirectStageMask() & ShaderStageComputeBit;
-
- auto entryBlock = BasicBlock::Create(*m_context, ".entry", func);
- m_builder->SetInsertPoint(entryBlock);
-
- auto payloadTy = rayTracingContext->getPayloadType(m_builder);
- Value *localPayload = m_builder->CreateAlloca(payloadTy, SPIRAS_Private);
-
- auto payloadArg = func->getArg(TraceRayParam::Payload);
- auto paqArray = func->getArg(TraceRayParam::Paq);
-
- auto bufferDesc = func->arg_end() - 1;
- auto payloadArgSize = m_builder->CreateExtractValue(paqArray, 0);
- const Align align = Align(4);
- m_builder->CreateMemCpy(localPayload, align, payloadArg, align, payloadArgSize);
-
- SmallVector<Value *, 8> args;
- args.push_back(m_builder->CreateLoad(payloadTy, localPayload));
-
- // For trace ray entry, we decided to use <2 x i32> to pass acceleration structure so that we can easily retrieve
- // high/low part by extractelement.
- args.push_back(m_builder->CreateBitCast(func->getArg(TraceRayParam::AccelStruct),
- FixedVectorType::get(m_builder->getInt32Ty(), 2)));
-
- for (unsigned i = TraceRayParam::RayFlags; i < TraceRayParam::Payload; i++)
- args.push_back(func->getArg(i));
-
- Value *parentRayId = func->arg_end() - 2;
- Value *rayStaticId = func->arg_end() - 3;
-
- // RayGen shaders are non-recursive, initialize parent ray ID to -1 here.
- if (m_shaderStage == ShaderStageRayTracingRayGen)
- m_builder->CreateStore(m_builder->getInt32(InvalidValue), parentRayId);
-
- Value *currentParentRayId = m_builder->CreateLoad(m_builder->getInt32Ty(), parentRayId);
- if (m_context->getPipelineContext()->getRayTracingState()->enableRayTracingCounters) {
- args.push_back(currentParentRayId);
- args.push_back(m_builder->CreateLoad(m_builder->getInt32Ty(), rayStaticId));
- }
+ auto rayTracingContext = static_cast<RayTracingContext *>(m_context->getPipelineContext());
+ auto payloadTy = rayTracingContext->getPayloadType(m_builder);
+ AllocaInst *localPayload = nullptr;
+ {
+ IRBuilderBase::InsertPointGuard ipg(*m_builder);
+ m_builder->SetInsertPointPastAllocas(inst->getFunction());
+ localPayload = m_builder->CreateAlloca(payloadTy, SPIRAS_Private);
+ }
+
+ // Setup arguments
+ SmallVector<Value *> args;
+ auto payloadArgSize = m_builder->CreateExtractValue(inst->getPaq(), 0);
+ m_builder->CreateMemCpy(localPayload, localPayload->getAlign(), inst->getPayload(), Align(4), payloadArgSize);
+ args.push_back(m_builder->CreateLoad(payloadTy, localPayload));
+ args.push_back(m_builder->CreateBitCast(inst->getAccelStruct(), FixedVectorType::get(m_builder->getInt32Ty(), 2)));
+ args.push_back(inst->getRayFlags());
+ args.push_back(inst->getInstanceInclusionMask());
+ args.push_back(inst->getRayContributionToHitGroupIndex());
+ args.push_back(inst->getMultiplierForGeometryContribution());
+ args.push_back(inst->getMissShaderIndex());
+ args.push_back(inst->getOrigin());
+ args.push_back(inst->getTMin());
+ args.push_back(inst->getDirection());
+ args.push_back(inst->getTMax());
+
+ if (rayTracingContext->getRayTracingState()->enableRayTracingCounters) {
+ args.push_back(m_builder->CreateLoad(m_builder->getInt32Ty(), m_traceParams[TraceParam::ParentRayId]));
+ args.push_back(m_builder->getInt32(generateTraceRayStaticId()));
+ }
+
+ // Call the trace ray implementation
+ if (rayTracingContext->getRayTracingState()->exportConfig.emitRaytracingShaderDataToken)
+ createSqttCallCompactToken(ShaderStageCompute);
+
+ Value *result = nullptr;
+ bool indirect = rayTracingContext->getIndirectStageMask() & ShaderStageComputeBit;
+ auto funcTy = getTraceRayFuncTy();
+ if (indirect) {
+ Value *traceRayGpuVa = loadShaderTableVariable(ShaderTable::TraceRayGpuVirtAddr, m_dispatchRaysInfoDesc);
+ auto funcPtrTy = PointerType::get(funcTy, SPIRAS_Generic);
+ auto funcPtr = m_builder->CreateIntToPtr(traceRayGpuVa, funcPtrTy);
+ // Create the indirect function call
+ CallInst *call = m_builder->CreateCall(funcTy, funcPtr, args);
+ call->setCallingConv(CallingConv::SPIR_FUNC);
- CallInst *result = nullptr;
- auto funcTy = getTraceRayFuncTy();
- if (indirect) {
- Value *traceRayGpuVa = loadShaderTableVariable(ShaderTable::TraceRayGpuVirtAddr, bufferDesc);
- auto funcPtrTy = PointerType::get(funcTy, SPIRAS_Generic);
- auto funcPtr = m_builder->CreateIntToPtr(traceRayGpuVa, funcPtrTy);
- // Create the indirect function call
- result = m_builder->CreateCall(funcTy, funcPtr, args);
- result->setCallingConv(CallingConv::SPIR_FUNC);
+ unsigned lgcRtStage = ~0u;
+ call->setMetadata(RtName::ContinufyStageMeta,
+ MDNode::get(*m_context, ConstantAsMetadata::get(m_builder->getInt32(lgcRtStage))));
- unsigned lgcRtStage = ~0u;
- result->setMetadata(RtName::ContinufyStageMeta,
- MDNode::get(*m_context, ConstantAsMetadata::get(m_builder->getInt32(lgcRtStage))));
- } else {
- result =
- m_builder->CreateNamedCall(RtName::TraceRayKHR, funcTy->getReturnType(), args, {Attribute::AlwaysInline});
- }
+ result = call;
+ } else {
+ result = m_builder->CreateNamedCall(RtName::TraceRayKHR, funcTy->getReturnType(), args, {Attribute::AlwaysInline});
+ }
- // Restore parent ray ID after call
- m_builder->CreateStore(currentParentRayId, parentRayId);
+ if (rayTracingContext->getRayTracingState()->exportConfig.emitRaytracingShaderDataToken)
+ createSqttFunctionReturnToken();
- // Save the return value to the input payloads for memcpy of type conversion
- m_builder->CreateStore(result, localPayload);
- m_builder->CreateMemCpy(payloadArg, align, localPayload, align, payloadArgSize);
- m_builder->CreateRetVoid();
- }
+ // Handle the result
+ unsigned payloadSizeInDword = rayTracingContext->getPayloadSizeInDword();
+ unsigned index = 0;
+ Value *payloadVal = PoisonValue::get(rayTracingContext->getPayloadType(m_builder));
+ for (; index < payloadSizeInDword; index++)
+ payloadVal = m_builder->CreateInsertValue(payloadVal, m_builder->CreateExtractValue(result, index), index);
+ m_builder->CreateStore(payloadVal, localPayload);
+ m_builder->CreateMemCpy(inst->getPayload(), Align(4), localPayload, localPayload->getAlign(), payloadArgSize);
m_callsToLower.push_back(inst);
m_funcsToLower.insert(inst->getCalledFunction());
@@ -259,14 +241,23 @@ void SpirvLowerRayTracing::visitCallCallableShaderOp(CallCallableShaderOp &inst)
auto shaderIdentifier = getShaderIdentifier(ShaderStageRayTracingCallable, shaderRecordIndexValue, buffDesc);
if (indirect) {
- auto funcTy = getCallableShaderEntryFuncTy();
+ SmallVector<StringRef> argNames;
+ auto funcTy = getCallableShaderEntryFuncTy(argNames);
auto funcPtrTy = PointerType::get(funcTy, SPIRAS_Generic);
if (rayTracingContext->isReplay()) {
auto remapFunc = getOrCreateRemapCapturedVaToReplayVaFunc();
shaderIdentifier = m_builder->CreateCall(remapFunc->getFunctionType(), remapFunc, shaderIdentifier);
}
auto funcPtr = m_builder->CreateIntToPtr(shaderIdentifier, funcPtrTy);
+
+ if (rayTracingContext->getRayTracingState()->exportConfig.emitRaytracingShaderDataToken)
+ createSqttCallCompactToken(ShaderStageRayTracingCallable);
+
CallInst *result = m_builder->CreateCall(funcTy, funcPtr, args);
+
+ if (rayTracingContext->getRayTracingState()->exportConfig.emitRaytracingShaderDataToken)
+ createSqttFunctionReturnToken();
+
result->setCallingConv(CallingConv::SPIR_FUNC);
unsigned lgcRtStage = static_cast<unsigned>(mapStageToLgcRtShaderStage(ShaderStageRayTracingCallable));
@@ -294,124 +285,47 @@ void SpirvLowerRayTracing::visitCallCallableShaderOp(CallCallableShaderOp &inst)
//
// @param inst : The instruction
void SpirvLowerRayTracing::visitReportHitOp(ReportHitOp &inst) {
- std::string mangledName = inst.getCalledFunction()->getName().str() + ".impl";
-
- auto hitT = inst.getThit();
- auto hitKind = inst.getHitKind();
-
m_builder->SetInsertPoint(&inst);
- SmallVector<Value *> args = {hitT, hitKind, m_dispatchRaysInfoDesc, m_shaderRecordIndex};
- unsigned traceParamsArgOffset = args.size();
- for (uint32_t i = TraceParam::RayFlags; i < TraceParam::Count; ++i)
- args.push_back(m_traceParams[i]);
-
- auto retTy = ArrayType::get(m_builder->getInt1Ty(), 2);
- auto retVal = m_builder->CreateNamedCall(mangledName, retTy, args, {Attribute::NoUnwind, Attribute::AlwaysInline});
-
- auto reportHitResult = m_builder->CreateExtractValue(retVal, 0);
- auto funcRetFlag = m_builder->CreateExtractValue(retVal, 1);
- inst.replaceAllUsesWith(reportHitResult);
-
- auto func = m_module->getFunction(mangledName);
-
- if (func->isDeclaration()) {
- // .entry
- // %checkStatus = icmp ne i32 %status, %AcceptAndEndSearch
- // store i1 1, i1 addrspace(5)* @funcRetFlag
- // br i1 %checkStatus, label %.notAcceptAndSearch, label %.end
- //
- // .notAcceptAndSearch:
- // %shift = fsub float %paramHitT, %tMin
- // %tCurrentGeShift = fcmp float %tCurrent, %shift
- // %shiftGeZero = fcmp float %shift, 0.0
- // %checkStatus = and i1 %tCurrentGeShift, %shiftGeZero
- // br i1 %checkStatus, label %.accept, label %.end
- //
- // .accept:
- // store float %tCurrentValue, float addrspace(5)* %tCurrentLocal
- // store float %tMaxValue, float addrspace(5)* %tMaxLocal
- // store i32 %kindValue, i32 addrspace(5)* %kindLocal
- // store i32 %statusValue, i32 addrspace(5)* %statusLocal
- //
- // store float %shift, float addrspace(5)* @tCurrent
- // store float %paramHitT, float addrspace(5)* @tMax
- // store i32 %paramKind, i32 addrspace(5)* @kind
- // call void @AmdTraceRayCallAnyHitShader()
- // %checkStatus = icmp ne i32 %status, 0
- // br i1 %checkStatus, label %.notIgnore, label %.ignore
- //
- // .notIgnore:
- // %and = and i32 %rayflag, 4
- // %checkStatus = icmp ne i32 %and, 0
- // %checkAcceptHitAndSearch = icmp eq i32 %status, %AcceptAndEndSearch
- // %checkStatus = or i1 %checkStatus, %checkAcceptHitAndSearch
- // br i1 %checkStatus, label %.acceptHitAndSearch, label %.funcRet
- //
- // .acceptHitAndSearch:
- // store i32 AcceptAndEndSearch, i32 addrspace(5)* @status
- // br label %.end
- //
- // .ignore:
- // store float %tCurrentLocalValue, float addrspace(5)* @tCurrent
- // store float %tMaxLocalValue, float addrspace(5)* @tMax
- // store i32 %kindLocalValue, i32 addrspace(5)* @kind
- // store i32 %statusLocalValue, i32 addrspace(5)* @status
- // br label %.funcRet
- //
- //.funcRet:
- // store i1 0, i1 addrspace(5)* @funcRetFlag
- // br label %.end
- //
- //.end:
- // %result = icmp ne i32 %status, %Ignore
- // ret i1 %result
- assert(m_shaderStage == ShaderStageRayTracingIntersect);
- func->setLinkage(GlobalVariable::InternalLinkage);
- func->addFnAttr(Attribute::AlwaysInline);
- // Function input parameters
- Value *paramHitT = func->arg_begin();
- Value *paramHitKind = func->arg_begin() + 1;
- Value *bufferDesc = func->arg_begin() + 2;
- Value *shaderRecordIndex = func->arg_begin() + 3;
- Function::arg_iterator traceParams = func->arg_begin() + traceParamsArgOffset;
+ assert(m_shaderStage == ShaderStageRayTracingIntersect);
- // Create the entry block
- auto entryBlock = BasicBlock::Create(*m_context, ".entry", func);
- // Create notAcceptAndSearch
- auto notAcceptAndSearchBlock = BasicBlock::Create(*m_context, ".notAcceptAndSearch", func);
- // Create acceptBlock
- auto acceptBlock = BasicBlock::Create(*m_context, ".accept", func);
- // Create not ignore block
- auto notIgnoreBlock = BasicBlock::Create(*m_context, ".notIgnore", func);
- // Create accept hit end block
- auto acceptHitEndBlock = BasicBlock::Create(*m_context, ".acceptHitEnd", func);
- // Create ignore block
- auto ignoreBlock = BasicBlock::Create(*m_context, ".ignore", func);
- // Create funcRet block to set funcRetFlag
- auto funcRetBlock = BasicBlock::Create(*m_context, ".funcRet", func);
- // Create end block
- auto endBlock = BasicBlock::Create(*m_context, ".end", func);
-
- // Construct entry block
- m_builder->SetInsertPoint(entryBlock);
-
- // Use a [2 x i1] to store results, index 0 for report hit result, index 1 for function return flag.
- auto retPtr = m_builder->CreateAlloca(retTy);
- auto reportHitResultPtr = m_builder->CreateConstGEP2_32(retTy, retPtr, 0, 0);
- auto funcRetFlagPtr = m_builder->CreateConstGEP2_32(retTy, retPtr, 0, 1);
+ Value *acceptedPtr = nullptr;
+ {
+ IRBuilderBase::InsertPointGuard ipg(*m_builder);
+ m_builder->SetInsertPointPastAllocas(inst.getFunction());
+ acceptedPtr = m_builder->CreateAlloca(m_builder->getInt1Ty(), SPIRAS_Private);
+ m_builder->CreateStore(m_builder->getFalse(), acceptedPtr);
+ }
- m_builder->CreateStore(m_builder->getTrue(), funcRetFlagPtr);
+ // Check whether candidate Thit is between Tmin and the current committed hit.
+ Value *tMin = m_builder->CreateLoad(m_traceParamsTys[TraceParam::TMin], m_traceParams[TraceParam::TMin]);
+ Value *committedTCurrent =
+ m_builder->CreateLoad(m_traceParamsTys[TraceParam::TCurrent], m_traceParams[TraceParam::TCurrent]);
- // Create local copies
- auto tCurrentLocal = m_builder->CreateAlloca(m_builder->getFloatTy(), SPIRAS_Private);
- auto tMaxLocal = m_builder->CreateAlloca(m_builder->getFloatTy(), SPIRAS_Private);
- auto hitKindLocal = m_builder->CreateAlloca(m_builder->getInt32Ty(), SPIRAS_Private);
- auto statusLocal = m_builder->CreateAlloca(m_builder->getInt32Ty(), SPIRAS_Private);
+ Value *shift = m_builder->CreateFSub(inst.getThit(), tMin);
+ Value *shiftGeZero = m_builder->CreateFCmpOGE(shift, ConstantFP::get(m_builder->getFloatTy(), 0.0));
+ Value *tCurrentGeShift = m_builder->CreateFCmpOGE(committedTCurrent, shift);
+ Value *tmp = m_builder->CreateAnd(shiftGeZero, tCurrentGeShift);
+ {
+ Instruction *endThitAccept = SplitBlockAndInsertIfThen(tmp, m_builder->GetInsertPoint(), false);
+ m_builder->SetInsertPoint(endThitAccept);
+
+ // Backup the committed hit
+ Value *committedTMax = m_builder->CreateLoad(m_traceParamsTys[TraceParam::TMax], m_traceParams[TraceParam::TMax]);
+ Value *committedKind = m_builder->CreateLoad(m_traceParamsTys[TraceParam::Kind], m_traceParams[TraceParam::Kind]);
+ Value *committedStatus =
+ m_builder->CreateLoad(m_traceParamsTys[TraceParam::Status], m_traceParams[TraceParam::Status]);
+
+ // Tentatively commit the candidate hit
+ m_builder->CreateStore(shift, m_traceParams[TraceParam::TCurrent]);
+ m_builder->CreateStore(inst.getThit(), m_traceParams[TraceParam::TMax]);
+ m_builder->CreateStore(inst.getHitKind(), m_traceParams[TraceParam::Kind]);
+ m_builder->CreateStore(m_builder->getInt32(RayHitStatus::Accept), m_traceParams[TraceParam::Status]);
+
+ // Call the anyhit shader if there is one; this updates trace params
const static std::string ModuleNamePrefix =
std::string("_") + getShaderStageAbbreviation(ShaderStageRayTracingIntersect) + "_";
-
unsigned intersectId = 0;
m_module->getName().substr(ModuleNamePrefix.size()).consumeInteger(0, intersectId);
@@ -419,101 +333,65 @@ void SpirvLowerRayTracing::visitReportHitOp(ReportHitOp &inst) {
auto context = static_cast<RayTracingContext *>(m_context->getPipelineContext());
context->getStageModuleIds(ShaderStageRayTracingAnyHit, intersectId, anyHitIds);
- Value *status = traceParams + TraceParam::Status;
- Type *statusTy = m_traceParamsTys[TraceParam::Status];
- Value *statusValue = m_builder->CreateLoad(statusTy, status);
- Value *checkStatus = m_builder->CreateICmpNE(statusValue, m_builder->getInt32(RayHitStatus::AcceptAndEndSearch));
- m_builder->CreateCondBr(checkStatus, notAcceptAndSearchBlock, endBlock);
-
- // Construct notAcceptAndSearch block
- m_builder->SetInsertPoint(notAcceptAndSearchBlock);
- Value *tMin = m_builder->CreateLoad(m_traceParamsTys[TraceParam::TMin], traceParams + TraceParam::TMin);
- Value *tMax = m_builder->CreateLoad(m_traceParamsTys[TraceParam::TMax], traceParams + TraceParam::TMax);
- Value *kind = m_builder->CreateLoad(m_traceParamsTys[TraceParam::Kind], traceParams + TraceParam::Kind);
-
- Value *shift = m_builder->CreateFSub(paramHitT, tMin);
- Value *tCurrent = m_builder->CreateLoad(m_traceParamsTys[TraceParam::TCurrent], traceParams + TraceParam::TCurrent);
- Value *shiftGeZero = m_builder->CreateFCmpOGE(shift, ConstantFP::get(shift->getType(), 0.0));
- Value *tCurrentGeShift = m_builder->CreateFCmpOGE(tCurrent, shift);
- checkStatus = m_builder->CreateAnd(shiftGeZero, tCurrentGeShift);
- m_builder->CreateCondBr(checkStatus, acceptBlock, endBlock);
-
- // Construct accept block
- m_builder->SetInsertPoint(acceptBlock);
-
- // Backup tCurrent, tMax, hitKind, hitStatus
- m_builder->CreateStore(tCurrent, tCurrentLocal);
- m_builder->CreateStore(tMax, tMaxLocal);
- m_builder->CreateStore(kind, hitKindLocal);
- m_builder->CreateStore(statusValue, statusLocal);
-
- // Replace tCurrent with tShift
- m_builder->CreateStore(shift, traceParams + TraceParam::TCurrent);
- // Replace tMax with paramHit
- m_builder->CreateStore(paramHitT, traceParams + TraceParam::TMax);
- // Replace hitKind with paramHitKind
- m_builder->CreateStore(paramHitKind, traceParams + TraceParam::Kind);
- m_builder->CreateStore(m_builder->getInt32(RayHitStatus::Accept), status);
if (!anyHitIds.empty() || context->hasLibraryStage(shaderStageToMask(ShaderStageRayTracingAnyHit))) {
- auto shaderIdentifier = getShaderIdentifier(ShaderStageRayTracingAnyHit, shaderRecordIndex, bufferDesc);
- auto curPos = m_builder->saveIP();
- createAnyHitFunc(shaderIdentifier, shaderRecordIndex);
- m_builder->restoreIP(curPos);
- args = {shaderIdentifier, shaderRecordIndex};
+ auto shaderIdentifier =
+ getShaderIdentifier(ShaderStageRayTracingAnyHit, m_shaderRecordIndex, m_dispatchRaysInfoDesc);
+
+ SmallVector<Value *> args;
+ args.push_back(shaderIdentifier);
+ args.push_back(m_shaderRecordIndex);
for (unsigned i = 0; i < TraceParam::Count; ++i)
- args.push_back(traceParams + i);
+ args.push_back(m_traceParams[i]);
+
+ createAnyHitFunc(shaderIdentifier, m_shaderRecordIndex);
m_builder->CreateNamedCall(RtName::CallAnyHitShader, m_builder->getVoidTy(), args,
{Attribute::NoUnwind, Attribute::AlwaysInline});
}
- // Update the status value after callAnyHit function
- statusValue = m_builder->CreateLoad(statusTy, status);
- checkStatus = m_builder->CreateICmpNE(statusValue, m_builder->getInt32(RayHitStatus::Ignore));
- m_builder->CreateCondBr(checkStatus, notIgnoreBlock, ignoreBlock);
-
- // Construct notIgnore block
- m_builder->SetInsertPoint(notIgnoreBlock);
- Value *rayFlags = m_builder->CreateLoad(m_traceParamsTys[TraceParam::RayFlags], traceParams + TraceParam::RayFlags);
- auto checkRayFlags = m_builder->CreateAnd(rayFlags, m_builder->getInt32(RayFlag::AcceptFirstHitAndEndSearch));
- checkRayFlags = m_builder->CreateICmpEQ(checkRayFlags, m_builder->getInt32(RayFlag::AcceptFirstHitAndEndSearch));
- checkStatus = m_builder->CreateICmpEQ(statusValue, m_builder->getInt32(RayHitStatus::AcceptAndEndSearch));
- checkStatus = m_builder->CreateOr(checkRayFlags, checkStatus);
- m_builder->CreateCondBr(checkStatus, acceptHitEndBlock, funcRetBlock);
-
- // Construct acceptHitEnd block
- m_builder->SetInsertPoint(acceptHitEndBlock);
- // Set status value to the AcceptAndEndSearch
- m_builder->CreateStore(m_builder->getInt32(RayHitStatus::AcceptAndEndSearch), status);
- m_builder->CreateBr(endBlock);
- // Construct ignore block
- m_builder->SetInsertPoint(ignoreBlock);
- // Restore local copies to tCurrent, tMax, kind
- auto tCurrentLocalValue = m_builder->CreateLoad(m_builder->getFloatTy(), tCurrentLocal);
- auto tMaxLocalValue = m_builder->CreateLoad(m_builder->getFloatTy(), tMaxLocal);
- auto kindLocalValue = m_builder->CreateLoad(m_builder->getInt32Ty(), hitKindLocal);
- auto statusLocalValue = m_builder->CreateLoad(m_builder->getInt32Ty(), statusLocal);
-
- m_builder->CreateStore(tCurrentLocalValue, traceParams + TraceParam::TCurrent);
- m_builder->CreateStore(tMaxLocalValue, traceParams + TraceParam::TMax);
- m_builder->CreateStore(kindLocalValue, traceParams + TraceParam::Kind);
- m_builder->CreateStore(statusLocalValue, traceParams + TraceParam::Status);
- m_builder->CreateBr(funcRetBlock);
-
- // Construct funcRet block
- m_builder->SetInsertPoint(funcRetBlock);
- m_builder->CreateStore(m_builder->getFalse(), funcRetFlagPtr);
- m_builder->CreateBr(endBlock);
+ // Check if the AHS accepted
+ Value *status = m_builder->CreateLoad(m_traceParamsTys[TraceParam::Status], m_traceParams[TraceParam::Status]);
+ Value *accepted = m_builder->CreateICmpNE(status, m_builder->getInt32(RayHitStatus::Ignore));
+ Value *endFromAhs = m_builder->CreateICmpEQ(status, m_builder->getInt32(RayHitStatus::AcceptAndEndSearch));
+ tmp = m_builder->CreateLoad(m_traceParamsTys[TraceParam::RayFlags], m_traceParams[TraceParam::RayFlags]);
+ tmp = m_builder->CreateAnd(tmp, m_builder->getInt32(RayFlag::AcceptFirstHitAndEndSearch));
+ tmp = m_builder->CreateICmpNE(tmp, m_builder->getInt32(0));
+ Value *endFromRayFlags = m_builder->CreateAnd(accepted, tmp);
+ Value *endRay = m_builder->CreateOr(endFromAhs, endFromRayFlags);
+
+ {
+ // Accept the hit and end the ray for one reason or another. Immediately return from the IS.
+ Instruction *endEndRay = SplitBlockAndInsertIfThen(endRay, m_builder->GetInsertPoint(), true);
+ m_builder->SetInsertPoint(endEndRay);
+
+ // Override the status because it may only be "Accept" if we return due to ray flags.
+ m_builder->CreateStore(m_builder->getInt32(RayHitStatus::AcceptAndEndSearch), m_traceParams[TraceParam::Status]);
+ m_builder->CreateRetVoid();
+ endEndRay->eraseFromParent(); // erase `unreachable`
+ }
+ m_builder->SetInsertPoint(endThitAccept); // also reset the insert block
- // Construct end block
- m_builder->SetInsertPoint(endBlock);
- Value *result =
- m_builder->CreateICmpNE(m_builder->CreateLoad(statusTy, status), m_builder->getInt32(RayHitStatus::Ignore));
- m_builder->CreateStore(result, reportHitResultPtr);
- m_builder->CreateRet(m_builder->CreateLoad(retTy, retPtr));
- }
+ // Restore the old committed hit if the candidate wasn't accepted
+ Value *newTCurrent =
+ m_builder->CreateLoad(m_traceParamsTys[TraceParam::TCurrent], m_traceParams[TraceParam::TCurrent]);
+ Value *newTMax = m_builder->CreateLoad(m_traceParamsTys[TraceParam::TMax], m_traceParams[TraceParam::TMax]);
+ Value *newKind = m_builder->CreateLoad(m_traceParamsTys[TraceParam::Kind], m_traceParams[TraceParam::Kind]);
+ Value *newStatus = m_builder->CreateLoad(m_traceParamsTys[TraceParam::Status], m_traceParams[TraceParam::Status]);
+
+ newTCurrent = m_builder->CreateSelect(accepted, newTCurrent, committedTCurrent);
+ newTMax = m_builder->CreateSelect(accepted, newTMax, committedTMax);
+ newKind = m_builder->CreateSelect(accepted, newKind, committedKind);
+ newStatus = m_builder->CreateSelect(accepted, newStatus, committedStatus);
- processPostReportIntersection(m_entryPoint, cast<Instruction>(funcRetFlag));
+ m_builder->CreateStore(newTCurrent, m_traceParams[TraceParam::TCurrent]);
+ m_builder->CreateStore(newTMax, m_traceParams[TraceParam::TMax]);
+ m_builder->CreateStore(newKind, m_traceParams[TraceParam::Kind]);
+ m_builder->CreateStore(newStatus, m_traceParams[TraceParam::Status]);
+ m_builder->CreateStore(accepted, acceptedPtr);
+ }
+ m_builder->SetInsertPoint(&inst); // also reset the insert block
+
+ inst.replaceAllUsesWith(m_builder->CreateLoad(m_builder->getInt1Ty(), acceptedPtr));
m_callsToLower.push_back(&inst);
m_funcsToLower.insert(inst.getCalledFunction());
}
@@ -656,7 +534,7 @@ PreservedAnalyses SpirvLowerRayTracing::run(Module &module, ModuleAnalysisManage
for (auto funcIt = module.begin(), funcEnd = module.end(); funcIt != funcEnd;) {
Function *func = &*funcIt++;
- if (!func->empty() && !func->getName().startswith(module.getName()) &&
+ if (!func->empty() && !func->getName().starts_with(module.getName()) &&
((func->getLinkage() == GlobalValue::ExternalLinkage) || (func->getLinkage() == GlobalValue::WeakAnyLinkage))) {
// Newly generated implementation functions have external linkage, but should have internal linkage.
// Weak-linkage functions are GpuRt functions that we just added calls to, and which are no longer required apart
@@ -675,8 +553,8 @@ PreservedAnalyses SpirvLowerRayTracing::run(Module &module, ModuleAnalysisManage
void SpirvLowerRayTracing::createTraceParams(Function *entryFunc) {
m_builder->SetInsertPointPastAllocas(entryFunc);
for (unsigned i = 0; i < TraceParam::Count; ++i) {
- m_traceParams[i] = m_builder->CreateAlloca(m_traceParamsTys[i], SPIRAS_Private, nullptr,
- Twine(RtName::TraceRaySetTraceParams) + std::to_string(i));
+ m_traceParams[i] =
+ m_builder->CreateAlloca(m_traceParamsTys[i], SPIRAS_Private, nullptr, Twine("local.") + m_traceParamNames[i]);
}
}
@@ -856,7 +734,8 @@ void SpirvLowerRayTracing::createCallShader(Function *func, ShaderStage stage, u
auto payload = traceParams[TraceParam::Payload];
if (indirectShader) {
- auto funcTy = getShaderEntryFuncTy(stage);
+ SmallVector<StringRef> argNames;
+ auto funcTy = getShaderEntryFuncTy(stage, argNames);
auto funcPtrTy = PointerType::get(funcTy, SPIRAS_Generic);
if (rayTracingContext->isReplay()) {
@@ -865,8 +744,15 @@ void SpirvLowerRayTracing::createCallShader(Function *func, ShaderStage stage, u
}
auto funcPtr = m_builder->CreateIntToPtr(shaderId, funcPtrTy);
+
+ if (rayTracingContext->getRayTracingState()->exportConfig.emitRaytracingShaderDataToken)
+ createSqttCallCompactToken(stage);
+
CallInst *result = m_builder->CreateCall(funcTy, funcPtr, args);
+ if (rayTracingContext->getRayTracingState()->exportConfig.emitRaytracingShaderDataToken)
+ createSqttFunctionReturnToken();
+
unsigned lgcRtStage = static_cast<unsigned>(mapStageToLgcRtShaderStage(stage));
result->setMetadata(RtName::ContinufyStageMeta,
MDNode::get(*m_context, ConstantAsMetadata::get(m_builder->getInt32(lgcRtStage))));
@@ -1041,8 +927,7 @@ Value *SpirvLowerRayTracing::loadShaderTableVariable(ShaderTable tableKind, Valu
// @param inResultTy : Base type of inResult param
void SpirvLowerRayTracing::createShaderSelection(Function *func, BasicBlock *entryBlock, BasicBlock *endBlock,
Value *shaderId, unsigned intersectId, ShaderStage stage,
- const SmallVector<Value *, 8> &args, Value *inResult,
- Type *inResultTy) {
+ ArrayRef<Value *> args, Value *inResult, Type *inResultTy) {
// .entry:
// switch i32 %shaderId, label % .end[
// i32 2, label % .shader2
@@ -1074,8 +959,17 @@ void SpirvLowerRayTracing::createShaderSelection(Function *func, BasicBlock *ent
switchInst->addCase(m_builder->getInt32(moduleIds[i]), shaderBlock);
m_builder->SetInsertPoint(shaderBlock);
auto funcName = std::string("_") + getShaderStageAbbreviation(stage) + "_" + moduleIdStr;
+
+ auto rayTracingContext = static_cast<RayTracingContext *>(m_context->getPipelineContext());
+ if (rayTracingContext->getRayTracingState()->exportConfig.emitRaytracingShaderDataToken)
+ createSqttCallCompactToken(stage);
+
Value *result =
m_builder->CreateNamedCall(funcName, inResultTy, args, {Attribute::NoUnwind, Attribute::AlwaysInline});
+
+ if (rayTracingContext->getRayTracingState()->exportConfig.emitRaytracingShaderDataToken)
+ createSqttFunctionReturnToken();
+
if (inResult)
m_builder->CreateStore(result, inResult);
@@ -1160,6 +1054,7 @@ Value *SpirvLowerRayTracing::getShaderIdentifier(ShaderStage stage, Value *shade
// @param shaderIdentifier : Input shader identifier for the function
// @param shaderRecordIndex : Shader record index
void SpirvLowerRayTracing::createAnyHitFunc(Value *shaderIdentifier, Value *shaderRecordIndex) {
+ IRBuilderBase::InsertPointGuard ipg(*m_builder);
Function *func = dyn_cast_or_null<Function>(m_module->getFunction(RtName::CallAnyHitShader));
if (!func) {
SmallVector<Type *> tys = {shaderIdentifier->getType(), shaderRecordIndex->getType()};
@@ -1255,7 +1150,7 @@ void SpirvLowerRayTracing::createRayGenEntryFunc() {
auto mainBlock = BasicBlock::Create(*m_context, ".main", func);
auto endBlock = BasicBlock::Create(*m_context, ".end", func);
- lgc::Pipeline::markShaderEntryPoint(func, lgc::ShaderStageCompute);
+ lgc::Pipeline::markShaderEntryPoint(func, lgc::ShaderStage::Compute);
// Construct entry block guard the launchId from launchSize
m_builder->SetInsertPoint(entryBlock);
@@ -1282,10 +1177,8 @@ void SpirvLowerRayTracing::createRayGenEntryFunc() {
auto rayTracingContext = static_cast<RayTracingContext *>(m_context->getPipelineContext());
#if LLPC_CLIENT_INTERFACE_MAJOR_VERSION > 68
- if (rayTracingContext->getRaytracingMode() == Vkgc::LlpcRaytracingMode::Continufy) {
-#else
- if (rayTracingContext->getRaytracingMode() == Vkgc::LlpcRaytracingMode::Continuations) {
-#endif
+ if (rayTracingContext->getRaytracingMode() == Vkgc::LlpcRaytracingMode::Continufy &&
+ rayTracingContext->getIndirectStageMask() != 0) {
// Setup continuation stack pointer
auto offset = offsetof(GpuRt::DispatchRaysConstantData, cpsBackendStackSize);
auto gep = m_builder->CreateConstGEP1_32(m_builder->getInt8Ty(), m_dispatchRaysInfoDesc, offset);
@@ -1293,6 +1186,7 @@ void SpirvLowerRayTracing::createRayGenEntryFunc() {
stackPtr = m_builder->CreateIntToPtr(stackPtr, PointerType::get(*m_context, lgc::cps::stackAddrSpace));
m_builder->create<lgc::cps::SetVspOp>(stackPtr);
}
+#endif
bool indirect = rayTracingContext->getIndirectStageMask() & shaderStageToMask(m_shaderStage);
if (!indirect) {
@@ -1308,7 +1202,14 @@ void SpirvLowerRayTracing::createRayGenEntryFunc() {
rayGenId = m_builder->CreateCall(remapFunc->getFunctionType(), remapFunc, rayGenId);
}
auto funcPtr = m_builder->CreateIntToPtr(rayGenId, funcPtrTy);
+
+ if (rayTracingContext->getRayTracingState()->exportConfig.emitRaytracingShaderDataToken)
+ createSqttCallCompactToken(ShaderStageRayTracingRayGen);
+
CallInst *call = m_builder->CreateCall(funcTy, funcPtr, {});
+
+ if (rayTracingContext->getRayTracingState()->exportConfig.emitRaytracingShaderDataToken)
+ createSqttFunctionReturnToken();
call->setCallingConv(CallingConv::SPIR_FUNC);
unsigned lgcRtStage = static_cast<unsigned>(mapStageToLgcRtShaderStage(ShaderStageRayTracingRayGen));
@@ -1395,43 +1296,6 @@ void SpirvLowerRayTracing::processTerminalFunc(Function *func, CallInst *callIns
m_callsToLower.push_back(callInst);
}
-// =====================================================================================================================
-// Process termination after reportIntersection
-//
-// @param func : Processed function
-// @param inst : The instruction to split block after
-void SpirvLowerRayTracing::processPostReportIntersection(Function *func, Instruction *inst) {
- // .entry:
- // ...
- // %check = call spir_func i1 @ReportIntersectionKHR
- // ...
- // ret void
- //
- // ===>
- //
- // .entry:
- // call spir_func i1 @ReportIntersectionKHR
- // %check = load i1, i1 addrspace(5)* funcRetFlag
- // br i1 %check, label %.ret, label %.split
- // .ret:
- // ret void
- // .split:
- // ...
-
- auto currentBlock = inst->getParent();
- auto splitBlock = currentBlock->splitBasicBlock(inst->getNextNonDebugInstruction(), ".split");
- auto retBlock = BasicBlock::Create(*m_context, ".ret", func, splitBlock);
- m_builder->SetInsertPoint(retBlock);
- m_builder->CreateRetVoid();
-
- auto terminator = currentBlock->getTerminator();
- m_builder->SetInsertPoint(terminator);
- m_builder->CreateCondBr(inst, retBlock, splitBlock);
-
- terminator->dropAllReferences();
- terminator->eraseFromParent();
-}
-
// =====================================================================================================================
// Create traceray module entry function
CallInst *SpirvLowerRayTracing::createTraceRay() {
@@ -1684,6 +1548,26 @@ void SpirvLowerRayTracing::initTraceParamsTy(unsigned attributeSize) {
TraceParamsTySize[TraceParam::HitAttributes] = attributeSize;
TraceParamsTySize[TraceParam::Payload] = payloadType->getArrayNumElements();
assert(sizeof(TraceParamsTySize) / sizeof(TraceParamsTySize[0]) == TraceParam::Count);
+
+ m_traceParamNames[TraceParam::RayFlags] = "RayFlags";
+ m_traceParamNames[TraceParam::InstanceInclusionMask] = "InstanceInclusionMask";
+ m_traceParamNames[TraceParam::Origin] = "Origin";
+ m_traceParamNames[TraceParam::TMin] = "TMin";
+ m_traceParamNames[TraceParam::Dir] = "Dir";
+ m_traceParamNames[TraceParam::TMax] = "TMax";
+ m_traceParamNames[TraceParam::TCurrent] = "TCurrent";
+ m_traceParamNames[TraceParam::Kind] = "Kind";
+ m_traceParamNames[TraceParam::Status] = "Status";
+ m_traceParamNames[TraceParam::InstNodeAddrLo] = "InstNodeAddrLo";
+ m_traceParamNames[TraceParam::InstNodeAddrHi] = "InstNodeAddrHi";
+ m_traceParamNames[TraceParam::PrimitiveIndex] = "PrimitiveIndex";
+ m_traceParamNames[TraceParam::DuplicateAnyHit] = "DuplicateAnyHit";
+ m_traceParamNames[TraceParam::GeometryIndex] = "GeometryIndex";
+ m_traceParamNames[TraceParam::HitAttributes] = "HitAttributes";
+ m_traceParamNames[TraceParam::ParentRayId] = "ParentRayId";
+ m_traceParamNames[TraceParam::HitTriangleVertexPositions] = "HitTriangleVertexPositions";
+ m_traceParamNames[TraceParam::Payload] = "Payload";
+ m_traceParamNames[TraceParam::RayStaticId] = "RayStaticId";
}
// =====================================================================================================================
@@ -1691,6 +1575,31 @@ void SpirvLowerRayTracing::initTraceParamsTy(unsigned attributeSize) {
void SpirvLowerRayTracing::initShaderBuiltIns() {
assert(m_builtInParams.size() == 0);
auto rayTracingContext = static_cast<RayTracingContext *>(m_context->getPipelineContext());
+ const auto *buildInfo = rayTracingContext->getRayTracingPipelineBuildInfo();
+
+ if (buildInfo->libraryMode != Vkgc::LibraryMode::Pipeline || buildInfo->libraryCount != 0) {
+ // We're using a library or compiling to be used as a library. When shaders are compiled for library use, we
+ // cannot know the full set of required builtins for the shaders that are compiled first (that may already have
+ // been compiled at this time!), so we need to define a stable function signature by assuming that *all* builtins
+ // are used.
+ //
+ // Note: The build of traversal could still be optimized in some regards when libraryMode is Pipeline.
+ m_builtInParams.insert(TraceParam::PrimitiveIndex);
+ m_builtInParams.insert(TraceParam::Kind);
+ m_builtInParams.insert(TraceParam::RayFlags);
+ m_builtInParams.insert(TraceParam::InstNodeAddrLo);
+ m_builtInParams.insert(TraceParam::InstNodeAddrHi);
+ m_builtInParams.insert(TraceParam::TMin);
+ m_builtInParams.insert(TraceParam::Origin);
+ m_builtInParams.insert(TraceParam::Dir);
+ m_builtInParams.insert(TraceParam::GeometryIndex);
+ m_builtInParams.insert(TraceParam::TMax);
+ m_builtInParams.insert(TraceParam::InstanceInclusionMask);
+ m_builtInParams.insert(TraceParam::HitTriangleVertexPositions);
+ m_builtInParams.insert(TraceParam::HitAttributes);
+ return;
+ }
+
auto &contextBuiltIn = rayTracingContext->getBuiltIns();
for (const unsigned builtIn : contextBuiltIn) {
@@ -1768,20 +1677,24 @@ void SpirvLowerRayTracing::initShaderBuiltIns() {
// Get closeshit/miss/anyhit/intersect entry function type
//
// @param func : The shader stage of entry function
-FunctionType *SpirvLowerRayTracing::getShaderEntryFuncTy(ShaderStage stage) {
+// @param argNames : Filled with the names of arguments
+FunctionType *SpirvLowerRayTracing::getShaderEntryFuncTy(ShaderStage stage, SmallVectorImpl<StringRef> &argNames) {
SmallVector<Type *, 8> argTys;
auto retTy = getShaderReturnTy(stage);
for (auto &builtIn : m_builtInParams) {
argTys.push_back(m_traceParamsTys[builtIn]);
+ argNames.push_back(m_traceParamNames[builtIn]);
}
for (auto ¶m : getShaderExtraInputParams(stage)) {
argTys.push_back(m_traceParamsTys[param]);
+ argNames.push_back(m_traceParamNames[param]);
}
argTys.push_back(m_builder->getInt32Ty());
+ argNames.push_back("shaderRecordIndex");
return FunctionType::get(retTy, argTys, false);
}
@@ -1795,10 +1708,14 @@ Instruction *SpirvLowerRayTracing::createEntryFunc(Function *func) {
func->setName("deprecated");
// Create new entry function with new payload and builtIns arguments
- auto newFuncTy = getShaderEntryFuncTy(m_shaderStage);
+ SmallVector<StringRef> argNames;
+ auto newFuncTy = getShaderEntryFuncTy(m_shaderStage, argNames);
Function *newFunc = Function::Create(newFuncTy, GlobalValue::ExternalLinkage, m_module->getName(), m_module);
newFunc->setCallingConv(CallingConv::SPIR_FUNC);
+ for (auto [i, argName] : enumerate(argNames))
+ newFunc->getArg(i)->setName(argName);
+
createTraceParams(func);
func->getArg(0)->replaceAllUsesWith(m_traceParams[TraceParam::Payload]);
setShaderPaq(newFunc, getShaderPaq(func));
@@ -1878,13 +1795,15 @@ void SpirvLowerRayTracing::updateGlobalFromCallShaderFunc(Function *func, Shader
// =====================================================================================================================
// Get callabe shader entry function type
-FunctionType *SpirvLowerRayTracing::getCallableShaderEntryFuncTy() {
+FunctionType *SpirvLowerRayTracing::getCallableShaderEntryFuncTy(SmallVectorImpl<StringRef> &argNames) {
auto rayTracingContext = static_cast<RayTracingContext *>(m_context->getPipelineContext());
SmallVector<Type *, 8> argTys;
auto callableDataTy = rayTracingContext->getCallableDataType(m_builder);
argTys.push_back(callableDataTy);
- // Add shaderRecordIndex type
+ argNames.push_back("CallableData");
+
argTys.push_back(m_builder->getInt32Ty());
+ argNames.push_back("ShaderRecordIndex");
return FunctionType::get(callableDataTy, argTys, false);
}
@@ -1927,10 +1846,14 @@ Instruction *SpirvLowerRayTracing::createCallableShaderEntryFunc(Function *func)
func->setName("deprecatedCallableShader");
// Create new entry function with new callable data
- auto newFuncTy = getCallableShaderEntryFuncTy();
+ SmallVector<StringRef> argNames;
+ auto newFuncTy = getCallableShaderEntryFuncTy(argNames);
Function *newFunc = Function::Create(newFuncTy, GlobalValue::ExternalLinkage, m_module->getName(), m_module);
newFunc->setCallingConv(CallingConv::C);
+ for (auto [idx, argName] : enumerate(argNames))
+ newFunc->getArg(idx)->setName(argName);
+
m_builder->SetInsertPointPastAllocas(func);
m_callableData = m_builder->CreateAlloca(newFunc->getReturnType());
func->getArg(0)->replaceAllUsesWith(m_callableData);
@@ -1970,13 +1893,14 @@ Instruction *SpirvLowerRayTracing::createCallableShaderEntryFunc(Function *func)
// Get all the function ReturnInst
//
// @param func : Function to gather ReturnInst
-// @param rets : returned vector of ReturnInst instructions
-void SpirvLowerRayTracing::getFuncRets(Function *func, SmallVector<Instruction *, 4> &rets) {
+SmallVector<Instruction *> SpirvLowerRayTracing::getFuncRets(Function *func) const {
+ SmallVector<Instruction *> rets;
for (auto &block : *func) {
auto blockTerm = block.getTerminator();
if (blockTerm != nullptr && isa<ReturnInst>(blockTerm))
rets.push_back(blockTerm);
}
+ return rets;
}
// =====================================================================================================================
@@ -2224,9 +2148,7 @@ void SpirvLowerRayTracing::createSetHitTriangleNodePointer(Function *func) {
void SpirvLowerRayTracing::createEntryTerminator(Function *func) {
// Return incoming payload, and other values if needed
auto rayTracingContext = static_cast<RayTracingContext *>(m_context->getPipelineContext());
- SmallVector<Instruction *, 4> rets;
- getFuncRets(func, rets);
- for (auto ret : rets) {
+ for (auto ret : getFuncRets(func)) {
m_builder->SetInsertPoint(ret);
const auto payloadType = rayTracingContext->getPayloadType(m_builder);
Value *retVal = m_builder->CreateLoad(payloadType, m_traceParams[TraceParam::Payload]);
@@ -2272,9 +2194,7 @@ void SpirvLowerRayTracing::createEntryTerminator(Function *func) {
// @param func : The function to process
void SpirvLowerRayTracing::createCallableShaderEntryTerminator(Function *func) {
// return global callable data
- SmallVector<Instruction *, 4> rets;
- getFuncRets(func, rets);
- for (auto ret : rets) {
+ for (auto ret : getFuncRets(func)) {
m_builder->SetInsertPoint(ret);
Instruction *newfuncEnd =
m_builder->CreateRet(m_builder->CreateLoad(m_callableData->getAllocatedType(), m_callableData));
@@ -2329,8 +2249,8 @@ Function *SpirvLowerRayTracing::getOrCreateRemapCapturedVaToReplayVaFunc() {
auto loopIteratorPtr = m_builder->CreateAlloca(int32Ty, SPIRAS_Private);
- auto bufferDesc = m_builder->CreateLoadBufferDesc(Vkgc::InternalDescriptorSetId,
- Vkgc::RtCaptureReplayInternalBufferBinding, zero, 0);
+ auto bufferDesc = m_builder->create<lgc::LoadBufferDescOp>(Vkgc::InternalDescriptorSetId,
+ Vkgc::RtCaptureReplayInternalBufferBinding, zero, 0);
auto numEntriesPtr = m_builder->CreateInBoundsGEP(int8Ty, bufferDesc, zero);
auto numEntries = m_builder->CreateTrunc(m_builder->CreateLoad(int64Ty, numEntriesPtr), int32Ty);
@@ -2379,10 +2299,9 @@ Function *SpirvLowerRayTracing::getOrCreateRemapCapturedVaToReplayVaFunc() {
// =====================================================================================================================
// Get DispatchRaysInfo Descriptor
//
-// @param insertPos : Where to insert instructions
void SpirvLowerRayTracing::createDispatchRaysInfoDesc() {
if (!m_dispatchRaysInfoDesc) {
- m_dispatchRaysInfoDesc = m_builder->CreateLoadBufferDesc(
+ m_dispatchRaysInfoDesc = m_builder->create<lgc::LoadBufferDescOp>(
TraceRayDescriptorSet, RayTracingResourceIndexDispatchRaysInfo, m_builder->getInt32(0), 0);
m_builder->CreateInvariantStart(m_dispatchRaysInfoDesc);
}
@@ -2975,6 +2894,9 @@ void SpirvLowerRayTracing::visitShaderRecordBufferOp(lgc::rt::ShaderRecordBuffer
const unsigned shaderIdsSize = sizeof(Vkgc::RayTracingShaderIdentifier);
Value *shaderIdsSizeVal = m_builder->getInt32(shaderIdsSize);
+#if LLVM_MAIN_REVISION && LLVM_MAIN_REVISION < 484034
+ // Old version without the strided buffer pointers
+
// Byte offset = (tableStride * tableIndex) + shaderIdsSize
Value *offset = m_builder->CreateMul(tableIndex, tableStride);
offset = m_builder->CreateAdd(offset, shaderIdsSizeVal);
@@ -2992,6 +2914,89 @@ void SpirvLowerRayTracing::visitShaderRecordBufferOp(lgc::rt::ShaderRecordBuffer
m_callsToLower.push_back(&inst);
m_funcsToLower.insert(inst.getCalledFunction());
+#else
+ // New version of the code with strided buffer pointers (also handles unknown version, which we treat as latest)
+ tableAddr = m_builder->CreateAdd(tableAddr, m_builder->CreateZExt(shaderIdsSizeVal, m_builder->getInt64Ty()));
+ tableAddr = m_builder->create<lgc::StridedBufferAddrAndStrideToPtrOp>(tableAddr, tableStride);
+ tableAddr = m_builder->create<lgc::StridedIndexAddOp>(tableAddr, tableIndex);
+
+ SmallVector<Instruction *> toRemove;
+ toRemove.push_back(&inst);
+ replaceAllPointerUses(m_builder, &inst, tableAddr, toRemove);
+
+ for (auto *I : reverse(toRemove))
+ I->eraseFromParent();
+#endif
+}
+
+// =====================================================================================================================
+// Creates instructions to emit SQTT shader data call compact token
+//
+// @param stage : Ray tracing shader stage
+void SpirvLowerRayTracing::createSqttCallCompactToken(ShaderStage stage) {
+ // The token is a 32-bit uint compacted with following bit representation:
+ // 31-13: extended data, 12-8: data_tokens, 7: extended, 6: special, 5-0: well_known
+ // If extended is 0, this is a well known packet type, and data_tokens and extended_data may be interpreted as
+ // specified by the well_known packet specification.
+ union SqttShaderDataToken {
+ struct {
+ uint32_t well_known : 6;
+ uint32_t special : 1;
+ uint32_t extended : 1;
+ uint32_t data_token : 5;
+ uint32_t extended_data : 19;
+ } bits;
+
+ uint32_t u32All;
+ };
+
+ SqttShaderDataToken token = {};
+ token.bits.well_known = SqttWellKnownTypeFunctionCallCompact;
+ switch (stage) {
+ case ShaderStage::ShaderStageRayTracingAnyHit:
+ token.bits.data_token = 1;
+ break;
+ case ShaderStage::ShaderStageRayTracingClosestHit:
+ token.bits.data_token = 2;
+ break;
+ case ShaderStage::ShaderStageRayTracingIntersect:
+ token.bits.data_token = 3;
+ break;
+ case ShaderStage::ShaderStageRayTracingMiss:
+ token.bits.data_token = 4;
+ break;
+ case ShaderStage::ShaderStageRayTracingRayGen:
+ token.bits.data_token = 5;
+ break;
+ case ShaderStage::ShaderStageCompute:
+ token.bits.data_token = 6;
+ break;
+ case ShaderStage::ShaderStageRayTracingCallable:
+ token.bits.data_token = 7;
+ break;
+ default:
+ llvm_unreachable("Should never be called!");
+ break;
+ }
+
+ // Get number of active lanes
+ auto waveSize = m_context->getPipelineContext()->getRayTracingWaveSize();
+ Value *activeLaneCount =
+ m_builder->CreateIntrinsic(m_builder->getIntNTy(waveSize), Intrinsic::amdgcn_ballot, m_builder->getInt1(true));
+ activeLaneCount = m_builder->CreateUnaryIntrinsic(Intrinsic::ctpop, activeLaneCount);
+ if (waveSize > 32)
+ activeLaneCount = m_builder->CreateTrunc(activeLaneCount, m_builder->getInt32Ty());
+
+ // Left shift 13 to extended_data position
+ activeLaneCount = m_builder->CreateShl(activeLaneCount, 13);
+
+ m_builder->CreateIntrinsic(Intrinsic::amdgcn_s_ttracedata, {}, m_builder->CreateOr(activeLaneCount, token.u32All));
+}
+
+// =====================================================================================================================
+// Creates instructions to emit SQTT shader data function return token
+void SpirvLowerRayTracing::createSqttFunctionReturnToken() {
+ m_builder->CreateIntrinsic(Intrinsic::amdgcn_s_ttracedata, {}, m_builder->getInt32(SqttWellKnownTypeFunctionReturn));
}
// =====================================================================================================================
diff --git a/llpc/lower/llpcSpirvLowerRayTracing.h b/llpc/lower/llpcSpirvLowerRayTracing.h
index 61bf5681d8..c3c4f84ead 100644
--- a/llpc/lower/llpcSpirvLowerRayTracing.h
+++ b/llpc/lower/llpcSpirvLowerRayTracing.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -169,6 +169,9 @@ enum RayHitStatus : unsigned {
AcceptAndEndSearch = 2, // Accept hit and end traversal
};
+constexpr unsigned SqttWellKnownTypeFunctionCallCompact = 0x11;
+constexpr unsigned SqttWellKnownTypeFunctionReturn = 0x10;
+
// =====================================================================================================================
// Represents the pass of SPIR-V lowering ray tracing.
class SpirvLowerRayTracing : public SpirvLowerRayQuery {
@@ -196,25 +199,23 @@ class SpirvLowerRayTracing : public SpirvLowerRayQuery {
void createSetTriangleInsection(llvm::Function *func);
void createShaderSelection(llvm::Function *func, llvm::BasicBlock *entryBlock, llvm::BasicBlock *endBlock,
llvm::Value *shaderId, unsigned intersectId, ShaderStage stage,
- const llvm::SmallVector<llvm::Value *, 8> &args, llvm::Value *result,
- llvm::Type *inResultTy);
+ llvm::ArrayRef<llvm::Value *> args, llvm::Value *result, llvm::Type *inResultTy);
llvm::Value *loadShaderTableVariable(ShaderTable tableKind, llvm::Value *bufferDesc);
llvm::Value *getShaderIdentifier(ShaderStage stage, llvm::Value *shaderRecordIndex, llvm::Value *bufferDesc);
void createDbgInfo(llvm::Module &module, llvm::Function *func);
void processTerminalFunc(llvm::Function *func, llvm::CallInst *inst, RayHitStatus hitStatus);
- void processPostReportIntersection(llvm::Function *func, llvm::Instruction *inst);
void initTraceParamsTy(unsigned attributeSize);
void initShaderBuiltIns();
void inlineTraceRay(llvm::CallInst *callInst, ModuleAnalysisManager &analysisManager);
llvm::Instruction *createEntryFunc(llvm::Function *func);
void createEntryTerminator(llvm::Function *func);
- llvm::FunctionType *getShaderEntryFuncTy(ShaderStage stage);
- llvm::FunctionType *getCallableShaderEntryFuncTy();
+ llvm::FunctionType *getShaderEntryFuncTy(ShaderStage stage, llvm::SmallVectorImpl<llvm::StringRef> &argNames);
+ llvm::FunctionType *getCallableShaderEntryFuncTy(llvm::SmallVectorImpl<llvm::StringRef> &argNames);
llvm::FunctionType *getTraceRayFuncTy();
void createDispatchRaysInfoDesc();
llvm::Instruction *createCallableShaderEntryFunc(llvm::Function *func);
void createCallableShaderEntryTerminator(llvm::Function *func);
- void getFuncRets(llvm::Function *func, llvm::SmallVector<llvm::Instruction *, 4> &rets);
+ llvm::SmallVector<llvm::Instruction *> getFuncRets(llvm::Function *func) const;
llvm::SmallSet<unsigned, 4> getShaderExtraInputParams(ShaderStage stage);
llvm::SmallSet<unsigned, 4> getShaderExtraRets(ShaderStage stage);
llvm::Type *getShaderReturnTy(ShaderStage stage);
@@ -270,11 +271,15 @@ class SpirvLowerRayTracing : public SpirvLowerRayQuery {
void visitShaderIndexOp(lgc::rt::ShaderIndexOp &inst);
void visitShaderRecordBufferOp(lgc::rt::ShaderRecordBufferOp &inst);
+ void createSqttCallCompactToken(ShaderStage stage);
+ void createSqttFunctionReturnToken();
+
llvm::Value *createLoadInstNodeAddr();
lgc::rt::RayTracingShaderStage mapStageToLgcRtShaderStage(ShaderStage stage);
- llvm::Value *m_traceParams[TraceParam::Count]; // Trace ray set parameters
+ llvm::Value *m_traceParams[TraceParam::Count]; // Trace ray set parameters
+ llvm::StringRef m_traceParamNames[TraceParam::Count];
llvm::Value *m_worldToObjMatrix = nullptr; // World to Object matrix
llvm::AllocaInst *m_callableData = nullptr; // Callable data variable for current callable shader
std::set<unsigned, std::less<unsigned>> m_builtInParams; // Indirect max builtins;
diff --git a/llpc/lower/llpcSpirvLowerTerminator.cpp b/llpc/lower/llpcSpirvLowerTerminator.cpp
index f092cc236c..7a98c2683e 100644
--- a/llpc/lower/llpcSpirvLowerTerminator.cpp
+++ b/llpc/lower/llpcSpirvLowerTerminator.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/lower/llpcSpirvLowerTerminator.h b/llpc/lower/llpcSpirvLowerTerminator.h
index 75f04a5709..0711b6d663 100644
--- a/llpc/lower/llpcSpirvLowerTerminator.h
+++ b/llpc/lower/llpcSpirvLowerTerminator.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2021-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/lower/llpcSpirvLowerTranslator.cpp b/llpc/lower/llpcSpirvLowerTranslator.cpp
index b334e1dc0a..380617a67b 100644
--- a/llpc/lower/llpcSpirvLowerTranslator.cpp
+++ b/llpc/lower/llpcSpirvLowerTranslator.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/lower/llpcSpirvLowerTranslator.h b/llpc/lower/llpcSpirvLowerTranslator.h
index 00e249f2f6..161754a959 100644
--- a/llpc/lower/llpcSpirvLowerTranslator.h
+++ b/llpc/lower/llpcSpirvLowerTranslator.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/lower/llpcSpirvLowerUtil.cpp b/llpc/lower/llpcSpirvLowerUtil.cpp
index b055eefcce..6a7f860f5b 100644
--- a/llpc/lower/llpcSpirvLowerUtil.cpp
+++ b/llpc/lower/llpcSpirvLowerUtil.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -139,7 +139,7 @@ void clearNonEntryFunctions(Module *module, StringRef entryName) {
Function *func = &*funcIt++;
if ((func->getLinkage() == GlobalValue::ExternalLinkage || func->getLinkage() == GlobalValue::WeakAnyLinkage) &&
!func->empty()) {
- if (!func->getName().startswith(entryName)) {
+ if (!func->getName().starts_with(entryName)) {
func->dropAllReferences();
func->eraseFromParent();
}
diff --git a/llpc/lower/llpcSpirvLowerUtil.h b/llpc/lower/llpcSpirvLowerUtil.h
index eeeaeb3393..4e05b016de 100644
--- a/llpc/lower/llpcSpirvLowerUtil.h
+++ b/llpc/lower/llpcSpirvLowerUtil.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/lower/llpcSpirvProcessGpuRtLibrary.cpp b/llpc/lower/llpcSpirvProcessGpuRtLibrary.cpp
index 2282124c4a..a6d539f83c 100644
--- a/llpc/lower/llpcSpirvProcessGpuRtLibrary.cpp
+++ b/llpc/lower/llpcSpirvProcessGpuRtLibrary.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -30,6 +30,7 @@
*/
#include "llpcSpirvProcessGpuRtLibrary.h"
#include "SPIRVInternal.h"
+#include "continuations/ContinuationsUtil.h"
#include "llpcContext.h"
#include "llpcSpirvLowerInternalLibraryIntrinsicUtil.h"
#include "llpcSpirvLowerUtil.h"
@@ -80,6 +81,12 @@ SpirvProcessGpuRtLibrary::LibraryFunctionTable::LibraryFunctionTable() {
m_libFuncPtrs["AmdExtD3DShaderIntrinsics_LoadDwordAtAddr"] = &SpirvProcessGpuRtLibrary::createLoadDwordAtAddr;
m_libFuncPtrs["AmdExtD3DShaderIntrinsics_LoadDwordAtAddrx2"] = &SpirvProcessGpuRtLibrary::createLoadDwordAtAddrx2;
m_libFuncPtrs["AmdExtD3DShaderIntrinsics_LoadDwordAtAddrx4"] = &SpirvProcessGpuRtLibrary::createLoadDwordAtAddrx4;
+ m_libFuncPtrs["AmdExtD3DShaderIntrinsics_ConstantLoadDwordAtAddr"] =
+ &SpirvProcessGpuRtLibrary::createConstantLoadDwordAtAddr;
+ m_libFuncPtrs["AmdExtD3DShaderIntrinsics_ConstantLoadDwordAtAddrx2"] =
+ &SpirvProcessGpuRtLibrary::createConstantLoadDwordAtAddrx2;
+ m_libFuncPtrs["AmdExtD3DShaderIntrinsics_ConstantLoadDwordAtAddrx4"] =
+ &SpirvProcessGpuRtLibrary::createConstantLoadDwordAtAddrx4;
m_libFuncPtrs["AmdExtD3DShaderIntrinsics_ConvertF32toF16NegInf"] =
&SpirvProcessGpuRtLibrary::createConvertF32toF16NegInf;
m_libFuncPtrs["AmdExtD3DShaderIntrinsics_ConvertF32toF16PosInf"] =
@@ -89,6 +96,8 @@ SpirvProcessGpuRtLibrary::LibraryFunctionTable::LibraryFunctionTable() {
#else
m_libFuncPtrs["AmdExtD3DShaderIntrinsics_IntersectInternal"] = &SpirvProcessGpuRtLibrary::createIntersectBvh;
#endif
+ m_libFuncPtrs["AmdExtD3DShaderIntrinsics_FloatOpWithRoundMode"] =
+ &SpirvProcessGpuRtLibrary::createFloatOpWithRoundMode;
m_libFuncPtrs["AmdTraceRaySampleGpuTimer"] = &SpirvProcessGpuRtLibrary::createSampleGpuTimer;
m_libFuncPtrs["AmdTraceRayGetFlattenedGroupThreadId"] = &SpirvProcessGpuRtLibrary::createGetFlattenedGroupThreadId;
m_libFuncPtrs["AmdTraceRayGetHitAttributes"] = &SpirvProcessGpuRtLibrary::createGetHitAttributes;
@@ -139,17 +148,17 @@ void SpirvProcessGpuRtLibrary::processLibraryFunction(Function *&func) {
assert(!fetchTrianglePositionFromRayQueryFuncName.empty());
// Set external linkage for library entry functions
- if (funcName.startswith(traceRayFuncName) || funcName.startswith(rayQueryInitializeFuncName) ||
- funcName.startswith(rayQueryProceedFuncName) ||
- funcName.startswith(fetchTrianglePositionFromNodePointerFuncName) ||
- funcName.startswith(fetchTrianglePositionFromRayQueryFuncName) || funcName.startswith("_cont_")) {
+ if (funcName.starts_with(traceRayFuncName) || funcName.starts_with(rayQueryInitializeFuncName) ||
+ funcName.starts_with(rayQueryProceedFuncName) ||
+ funcName.starts_with(fetchTrianglePositionFromNodePointerFuncName) ||
+ funcName.starts_with(fetchTrianglePositionFromRayQueryFuncName) || funcName.starts_with("_cont_")) {
func->setLinkage(GlobalValue::WeakAnyLinkage);
return;
}
// Drop dummy entry function.
static const char *LibraryEntryFuncName = "libraryEntry";
- if (funcName.startswith(LibraryEntryFuncName)) {
+ if (funcName.starts_with(LibraryEntryFuncName)) {
func->dropAllReferences();
func->eraseFromParent();
func = nullptr;
@@ -157,11 +166,11 @@ void SpirvProcessGpuRtLibrary::processLibraryFunction(Function *&func) {
}
// Special handling for _AmdContStackStore* and _AmdContStackLoad* to accept arbitrary type
- if (funcName.startswith("_AmdContStackStore")) {
+ if (funcName.starts_with("_AmdContStackStore")) {
m_builder->SetInsertPoint(clearBlock(func));
createContStackStore(func);
return;
- } else if (funcName.startswith("_AmdContStackLoad")) {
+ } else if (funcName.starts_with("_AmdContStackLoad")) {
m_builder->SetInsertPoint(clearBlock(func));
createContStackLoad(func);
return;
@@ -240,6 +249,18 @@ void SpirvProcessGpuRtLibrary::createLdsStackInit(Function *func) {
m_builder->CreateRet(m_builder->create<GpurtLdsStackInitOp>());
}
+// =====================================================================================================================
+void SpirvProcessGpuRtLibrary::createFloatOpWithRoundMode(llvm::Function *func) {
+ auto argIt = func->arg_begin();
+ auto retType = cast<FixedVectorType>(func->getReturnType());
+ auto int32Ty = m_builder->getInt32Ty();
+ Value *roundMode = m_builder->CreateLoad(int32Ty, argIt++);
+ Value *operation = m_builder->CreateLoad(int32Ty, argIt++);
+ Value *src0 = m_builder->CreateLoad(retType, argIt++);
+ Value *src1 = m_builder->CreateLoad(retType, argIt);
+ m_builder->CreateRet(m_builder->create<GpurtFloatWithRoundModeOp>(roundMode, operation, src0, src1));
+}
+
// =====================================================================================================================
// Fill in function to store stack LDS
//
@@ -278,29 +299,55 @@ void SpirvProcessGpuRtLibrary::createGetTriangleCompressionMode(Function *func)
}
// =====================================================================================================================
-// Fill in function to load 1 dword at given address
+// Fill in function to global load 1 dword at given address
//
// @param func : The function to process
void SpirvProcessGpuRtLibrary::createLoadDwordAtAddr(Function *func) {
- createLoadDwordAtAddrWithType(func, m_builder->getInt32Ty());
+ createLoadDwordAtAddrWithType(func, m_builder->getInt32Ty(), SPIRAS_Global);
}
// =====================================================================================================================
-// Fill in function to load 2 dwords at given address
+// Fill in function to global load 2 dwords at given address
//
// @param func : The function to process
void SpirvProcessGpuRtLibrary::createLoadDwordAtAddrx2(Function *func) {
auto int32x2Ty = FixedVectorType::get(m_builder->getInt32Ty(), 2);
- createLoadDwordAtAddrWithType(func, int32x2Ty);
+ createLoadDwordAtAddrWithType(func, int32x2Ty, SPIRAS_Global);
}
// =====================================================================================================================
-// Fill in function to load 4 dwords at given address
+// Fill in function to global load 4 dwords at given address
//
// @param func : The function to process
void SpirvProcessGpuRtLibrary::createLoadDwordAtAddrx4(Function *func) {
auto int32x4Ty = FixedVectorType::get(m_builder->getInt32Ty(), 4);
- createLoadDwordAtAddrWithType(func, int32x4Ty);
+ createLoadDwordAtAddrWithType(func, int32x4Ty, SPIRAS_Global);
+}
+
+// =====================================================================================================================
+// Fill in function to constant load 1 dword at given address
+//
+// @param func : The function to process
+void SpirvProcessGpuRtLibrary::createConstantLoadDwordAtAddr(Function *func) {
+ createLoadDwordAtAddrWithType(func, m_builder->getInt32Ty(), SPIRAS_Constant);
+}
+
+// =====================================================================================================================
+// Fill in function to constant load 2 dwords at given address
+//
+// @param func : The function to process
+void SpirvProcessGpuRtLibrary::createConstantLoadDwordAtAddrx2(Function *func) {
+ auto int32x2Ty = FixedVectorType::get(m_builder->getInt32Ty(), 2);
+ createLoadDwordAtAddrWithType(func, int32x2Ty, SPIRAS_Constant);
+}
+
+// =====================================================================================================================
+// Fill in function to constant load 4 dwords at given address
+//
+// @param func : The function to process
+void SpirvProcessGpuRtLibrary::createConstantLoadDwordAtAddrx4(Function *func) {
+ auto int32x4Ty = FixedVectorType::get(m_builder->getInt32Ty(), 4);
+ createLoadDwordAtAddrWithType(func, int32x4Ty, SPIRAS_Constant);
}
// =====================================================================================================================
@@ -308,7 +355,8 @@ void SpirvProcessGpuRtLibrary::createLoadDwordAtAddrx4(Function *func) {
//
// @param func : The function to process
// @param loadTy : Load type
-void SpirvProcessGpuRtLibrary::createLoadDwordAtAddrWithType(Function *func, Type *loadTy) {
+void SpirvProcessGpuRtLibrary::createLoadDwordAtAddrWithType(Function *func, Type *loadTy,
+ SPIRAddressSpace addressSpace) {
auto argIt = func->arg_begin();
Value *gpuLowAddr = m_builder->CreateLoad(m_builder->getInt32Ty(), argIt++);
@@ -321,7 +369,7 @@ void SpirvProcessGpuRtLibrary::createLoadDwordAtAddrWithType(Function *func, Typ
gpuHighAddr = m_builder->CreateShl(gpuHighAddr, m_builder->getInt64(32));
Value *gpuAddr = m_builder->CreateOr(gpuLowAddr, gpuHighAddr);
- Type *gpuAddrAsPtrTy = PointerType::get(m_builder->getContext(), SPIRAS_Global);
+ Type *gpuAddrAsPtrTy = PointerType::get(m_builder->getContext(), addressSpace);
auto gpuAddrAsPtr = m_builder->CreateIntToPtr(gpuAddr, gpuAddrAsPtrTy);
// Create GEP to get the byte address with byte offset
@@ -740,10 +788,8 @@ void SpirvProcessGpuRtLibrary::createContStackLoad(llvm::Function *func) {
//
// @param func : The function to create
void SpirvProcessGpuRtLibrary::createContStackStore(llvm::Function *func) {
- MDNode *storeTypeMeta = func->getMetadata(gSPIRVMD::ContStackStoreType);
- assert(storeTypeMeta);
- const auto constMD = cast<ConstantAsMetadata>(storeTypeMeta->getOperand(0));
- auto dataType = constMD->getType();
+ unsigned dataArgIndex = func->arg_size() - 1;
+ Type *dataType = getFuncArgPtrElementType(func, dataArgIndex);
auto addr = m_builder->CreateLoad(m_builder->getInt32Ty(), func->getArg(0));
auto data = m_builder->CreateLoad(dataType, func->getArg(1));
diff --git a/llpc/lower/llpcSpirvProcessGpuRtLibrary.h b/llpc/lower/llpcSpirvProcessGpuRtLibrary.h
index bd61a851ed..8acfcff410 100644
--- a/llpc/lower/llpcSpirvProcessGpuRtLibrary.h
+++ b/llpc/lower/llpcSpirvProcessGpuRtLibrary.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -29,7 +29,7 @@
***********************************************************************************************************************
*/
#pragma once
-
+#include "SPIRVInternal.h"
#include "llpcSpirvLower.h"
#include "llvm/ADT/FloatingPointMode.h"
#include "llvm/IR/PassManager.h"
@@ -64,7 +64,10 @@ class SpirvProcessGpuRtLibrary : public SpirvLower, public llvm::PassInfoMixin<S
void createLoadDwordAtAddr(llvm::Function *func);
void createLoadDwordAtAddrx2(llvm::Function *func);
void createLoadDwordAtAddrx4(llvm::Function *func);
- void createLoadDwordAtAddrWithType(llvm::Function *func, llvm::Type *loadTy);
+ void createConstantLoadDwordAtAddr(llvm::Function *func);
+ void createConstantLoadDwordAtAddrx2(llvm::Function *func);
+ void createConstantLoadDwordAtAddrx4(llvm::Function *func);
+ void createLoadDwordAtAddrWithType(llvm::Function *func, llvm::Type *loadTy, SPIRV::SPIRAddressSpace addressSpace);
void createConvertF32toF16NegInf(llvm::Function *func);
void createConvertF32toF16PosInf(llvm::Function *func);
void createConvertF32toF16WithRoundingMode(llvm::Function *func, llvm::RoundingMode rm);
@@ -92,6 +95,7 @@ class SpirvProcessGpuRtLibrary : public SpirvLower, public llvm::PassInfoMixin<S
void createContStackSetPtr(llvm::Function *func);
void createContStackLoad(llvm::Function *func);
void createContStackStore(llvm::Function *func);
+ void createFloatOpWithRoundMode(llvm::Function *func);
llvm::Value *createGetBvhSrd(llvm::Value *expansion, llvm::Value *boxSortMode);
};
} // namespace Llpc
diff --git a/llpc/test/CMakeLists.txt b/llpc/test/CMakeLists.txt
index 78b635b1c0..bd533a5802 100644
--- a/llpc/test/CMakeLists.txt
+++ b/llpc/test/CMakeLists.txt
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/llpc/test/lit.cfg.py b/llpc/test/lit.cfg.py
index 17f4e58f3e..d545648727 100644
--- a/llpc/test/lit.cfg.py
+++ b/llpc/test/lit.cfg.py
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/llpc/test/shaderdb/core/OpAccessChain_TestMultiLevelChain_lit.spvasm b/llpc/test/shaderdb/core/OpAccessChain_TestMultiLevelChain_lit.spvasm
index 0eb2934ea6..408b21f068 100644
--- a/llpc/test/shaderdb/core/OpAccessChain_TestMultiLevelChain_lit.spvasm
+++ b/llpc/test/shaderdb/core/OpAccessChain_TestMultiLevelChain_lit.spvasm
@@ -7,7 +7,7 @@
; SHADERTEST: getelementptr [4 x float], ptr addrspace({{.*}}) %{{[0-9]*}}, i32 0, i32 1
; SHADERTEST-LABEL: {{^// LLPC}} SPIR-V lowering results
-; SHADERTEST: @lgc.create.load.buffer.desc{{.*}}(i64 0, i32 0, i32 0,
+; SHADERTEST: @lgc.load.buffer.desc(i64 0, i32 0, i32 0,
; SHADERTEST: load i32, ptr addrspace({{.*}}) {{.*}}
; SHADERTEST: load float, ptr addrspace({{.*}}) {{.*}}
diff --git a/llpc/test/shaderdb/core/OpAccessChain_TestRowMajorBlockVectorExtract_lit.frag b/llpc/test/shaderdb/core/OpAccessChain_TestRowMajorBlockVectorExtract_lit.frag
index 50820535e9..60b4a7bc4e 100644
--- a/llpc/test/shaderdb/core/OpAccessChain_TestRowMajorBlockVectorExtract_lit.frag
+++ b/llpc/test/shaderdb/core/OpAccessChain_TestRowMajorBlockVectorExtract_lit.frag
@@ -43,10 +43,10 @@ void main()
// SHADERTEST-LABEL: @lgc.shader.FS.main(
// SHADERTEST-NEXT: .entry:
-// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 1, i32 1, i32 0, i32 2)
-// SHADERTEST-NEXT: [[TMP1:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 2, i32 0, i32 0, i32 0)
+// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 1, i32 1, i32 0, i32 2)
+// SHADERTEST-NEXT: [[TMP1:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 2, i32 0, i32 0, i32 0)
// SHADERTEST-NEXT: [[TMP2:%.*]] = call ptr @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) [[TMP1]])
-// SHADERTEST-NEXT: [[TMP3:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 0)
+// SHADERTEST-NEXT: [[TMP3:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
// SHADERTEST-NEXT: [[TMP4:%.*]] = call ptr @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) [[TMP3]])
// SHADERTEST-NEXT: [[TMP5:%.*]] = getelementptr inbounds <{ [3 x double], [8 x i8], [3 x %llpc.matrix.row] }>, ptr addrspace(7) [[TMP3]], i64 0, i32 0, i64 1
// SHADERTEST-NEXT: [[TMP6:%.*]] = load double, ptr addrspace(7) [[TMP5]], align 8
diff --git a/llpc/test/shaderdb/core/OpAny_TestBvec2_lit.frag b/llpc/test/shaderdb/core/OpAny_TestBvec2_lit.frag
index bc707069f1..2cad305b54 100644
--- a/llpc/test/shaderdb/core/OpAny_TestBvec2_lit.frag
+++ b/llpc/test/shaderdb/core/OpAny_TestBvec2_lit.frag
@@ -23,7 +23,7 @@ void main()
}
// CHECK-LABEL: @lgc.shader.FS.main(
// CHECK-NEXT: .entry:
-// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 0)
+// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr addrspace(7) [[TMP0]], align 8
// CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP2]], i64 0
diff --git a/llpc/test/shaderdb/core/OpDecorationGroup_TestGroupAndGroupMember_lit.spvasm b/llpc/test/shaderdb/core/OpDecorationGroup_TestGroupAndGroupMember_lit.spvasm
index a65d7377b3..4571be2480 100644
--- a/llpc/test/shaderdb/core/OpDecorationGroup_TestGroupAndGroupMember_lit.spvasm
+++ b/llpc/test/shaderdb/core/OpDecorationGroup_TestGroupAndGroupMember_lit.spvasm
@@ -1,12 +1,12 @@
; BEGIN_SHADERTEST
; RUN: amdllpc -v %gfxip %s | FileCheck -check-prefix=SHADERTEST %s
; SHADERTEST-LABEL: {{^// LLPC}} SPIRV-to-LLVM translation results
-; SHADERTEST: %{{[0-9]+}} = getelementptr { [4294967295 x float] }, ptr addrspace(7) @{{.*}}, i32 0, i32 0, i32 %{{[0-9]+}}
-; SHADERTEST: %{{[0-9]+}} = getelementptr { [4294967295 x float] }, ptr addrspace(7) @{{.*}}, i32 0, i32 0, i32 %{{[0-9]+}}
-; SHADERTEST: %{{[0-9]+}} = getelementptr { [4294967295 x float] }, ptr addrspace(7) @{{.*}}, i32 0, i32 0, i32 %{{[0-9]+}}
-; SHADERTEST: %{{[0-9]+}} = getelementptr { [4294967295 x float] }, ptr addrspace(7) @{{.*}}, i32 0, i32 0, i32 %{{[0-9]+}}
-; SHADERTEST: %{{[0-9]+}} = getelementptr { [4294967295 x float] }, ptr addrspace(7) @{{.*}}, i32 0, i32 0, i32 %{{[0-9]+}}
-; SHADERTEST: %{{[0-9]+}} = getelementptr { [4294967295 x float] }, ptr addrspace(7) @{{.*}}, i32 0, i32 0, i32 %{{[0-9]+}}
+; SHADERTEST: %{{[0-9]+}} = getelementptr <{ [4294967295 x float] }>, ptr addrspace(7) @{{.*}}, i32 0, i32 0, i32 %{{[0-9]+}}
+; SHADERTEST: %{{[0-9]+}} = getelementptr <{ [4294967295 x float] }>, ptr addrspace(7) @{{.*}}, i32 0, i32 0, i32 %{{[0-9]+}}
+; SHADERTEST: %{{[0-9]+}} = getelementptr <{ [4294967295 x float] }>, ptr addrspace(7) @{{.*}}, i32 0, i32 0, i32 %{{[0-9]+}}
+; SHADERTEST: %{{[0-9]+}} = getelementptr <{ [4294967295 x float] }>, ptr addrspace(7) @{{.*}}, i32 0, i32 0, i32 %{{[0-9]+}}
+; SHADERTEST: %{{[0-9]+}} = getelementptr <{ [4294967295 x float] }>, ptr addrspace(7) @{{.*}}, i32 0, i32 0, i32 %{{[0-9]+}}
+; SHADERTEST: %{{[0-9]+}} = getelementptr <{ [4294967295 x float] }>, ptr addrspace(7) @{{.*}}, i32 0, i32 0, i32 %{{[0-9]+}}
; SHADERTEST: AMDLLPC SUCCESS
; END_SHADERTEST
diff --git a/llpc/test/shaderdb/core/OpFOrdEqual_TestVec3_lit.frag b/llpc/test/shaderdb/core/OpFOrdEqual_TestVec3_lit.frag
index ca234dc3c5..7f127ad484 100644
--- a/llpc/test/shaderdb/core/OpFOrdEqual_TestVec3_lit.frag
+++ b/llpc/test/shaderdb/core/OpFOrdEqual_TestVec3_lit.frag
@@ -17,7 +17,7 @@ void main()
// CHECK-LABEL: @lgc.shader.FS.main(
// CHECK-NEXT: .entry:
-// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 0)
+// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = load <3 x float>, ptr addrspace(7) [[TMP0]], align 16
// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds <{ [3 x float], [4 x i8], [3 x float] }>, ptr addrspace(7) [[TMP0]], i32 0, i32 2
diff --git a/llpc/test/shaderdb/core/OpFOrdNotEqual_TestVec3_lit.frag b/llpc/test/shaderdb/core/OpFOrdNotEqual_TestVec3_lit.frag
index af323bdfaa..651505b77c 100644
--- a/llpc/test/shaderdb/core/OpFOrdNotEqual_TestVec3_lit.frag
+++ b/llpc/test/shaderdb/core/OpFOrdNotEqual_TestVec3_lit.frag
@@ -17,7 +17,7 @@ void main()
// CHECK-LABEL: @lgc.shader.FS.main(
// CHECK-NEXT: .entry:
-// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 0)
+// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = load <3 x float>, ptr addrspace(7) [[TMP0]], align 16
// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds <{ [3 x float], [4 x i8], [3 x float] }>, ptr addrspace(7) [[TMP0]], i32 0, i32 2
diff --git a/llpc/test/shaderdb/core/OpIEqual_TestIvec2_lit.frag b/llpc/test/shaderdb/core/OpIEqual_TestIvec2_lit.frag
index 80bc25d3b5..b209a31aa1 100644
--- a/llpc/test/shaderdb/core/OpIEqual_TestIvec2_lit.frag
+++ b/llpc/test/shaderdb/core/OpIEqual_TestIvec2_lit.frag
@@ -17,7 +17,7 @@ void main()
// SHADERTEST-LABEL: @lgc.shader.FS.main(
// SHADERTEST-NEXT: .entry:
-// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 0)
+// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
// SHADERTEST-NEXT: [[TMP1:%.*]] = call ptr @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) [[TMP0]])
// SHADERTEST-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr addrspace(7) [[TMP0]], align 8
// SHADERTEST-NEXT: [[TMP3:%.*]] = getelementptr inbounds <{ [2 x i32], [2 x i32] }>, ptr addrspace(7) [[TMP0]], i32 0, i32 1
diff --git a/llpc/test/shaderdb/core/OpINotEqual_TestIvec2_lit.frag b/llpc/test/shaderdb/core/OpINotEqual_TestIvec2_lit.frag
index 215bebfbf0..d423ef6ff8 100644
--- a/llpc/test/shaderdb/core/OpINotEqual_TestIvec2_lit.frag
+++ b/llpc/test/shaderdb/core/OpINotEqual_TestIvec2_lit.frag
@@ -17,7 +17,7 @@ void main()
// SHADERTEST-LABEL: @lgc.shader.FS.main(
// SHADERTEST-NEXT: .entry:
-// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 0)
+// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
// SHADERTEST-NEXT: [[TMP1:%.*]] = call ptr @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) [[TMP0]])
// SHADERTEST-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr addrspace(7) [[TMP0]], align 8
// SHADERTEST-NEXT: [[TMP3:%.*]] = getelementptr inbounds <{ [2 x i32], [2 x i32] }>, ptr addrspace(7) [[TMP0]], i32 0, i32 1
diff --git a/llpc/test/shaderdb/core/OpLogicalNotEqual_TestGeneral_lit.frag b/llpc/test/shaderdb/core/OpLogicalNotEqual_TestGeneral_lit.frag
index 9c14e6f452..70bf94b37a 100644
--- a/llpc/test/shaderdb/core/OpLogicalNotEqual_TestGeneral_lit.frag
+++ b/llpc/test/shaderdb/core/OpLogicalNotEqual_TestGeneral_lit.frag
@@ -27,7 +27,7 @@ void main()
// SHADERTEST-LABEL: @lgc.shader.FS.main(
// SHADERTEST-NEXT: .entry:
-// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 2)
+// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
// SHADERTEST-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(7) [[TMP0]], align 4
// SHADERTEST-NEXT: [[TMP2:%.*]] = getelementptr inbounds <{ i32, [4 x i8], [2 x i32] }>, ptr addrspace(7) [[TMP0]], i32 0, i32 2, i32 0
// SHADERTEST-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(7) [[TMP2]], align 4
diff --git a/llpc/test/shaderdb/core/OpPtrEqualTest.spvasm b/llpc/test/shaderdb/core/OpPtrEqualTest.spvasm
index b8f8ee94aa..820c25992e 100644
--- a/llpc/test/shaderdb/core/OpPtrEqualTest.spvasm
+++ b/llpc/test/shaderdb/core/OpPtrEqualTest.spvasm
@@ -87,7 +87,7 @@
; SHADERTEST-LABEL: @lgc.shader.CS.main(
; SHADERTEST-NEXT: .entry:
-; SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 2, i32 0, i32 2)
+; SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 2, i32 0, i32 2)
; SHADERTEST-NEXT: store i32 1, ptr addrspace(7) [[TMP0]], align 4
; SHADERTEST-NEXT: [[TMP1:%.*]] = getelementptr <{ [4294967295 x i32] }>, ptr addrspace(7) [[TMP0]], i32 0, i32 0, i32 1
; SHADERTEST-NEXT: store i32 1, ptr addrspace(7) [[TMP1]], align 4
diff --git a/llpc/test/shaderdb/core/OpQuantizeToF16_TestGeneral_lit.spvasm b/llpc/test/shaderdb/core/OpQuantizeToF16_TestGeneral_lit.spvasm
index eb86aca039..41affc27e7 100644
--- a/llpc/test/shaderdb/core/OpQuantizeToF16_TestGeneral_lit.spvasm
+++ b/llpc/test/shaderdb/core/OpQuantizeToF16_TestGeneral_lit.spvasm
@@ -45,7 +45,7 @@
; SHADERTEST-LABEL: @lgc.shader.FS.main(
; SHADERTEST-NEXT: .entry:
-; SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 0)
+; SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
; SHADERTEST-NEXT: [[TMP1:%.*]] = call ptr @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) [[TMP0]])
; SHADERTEST-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr addrspace(7) [[TMP0]], align 16
; SHADERTEST-NEXT: [[TMP3:%.*]] = call reassoc nnan nsz arcp contract afn <4 x float> (...) @lgc.create.quantize.to.fp16.v4f32(<4 x float> [[TMP2]])
diff --git a/llpc/test/shaderdb/core/OpSLessThanEqual_TestSignedAndUnsigned_lit.frag b/llpc/test/shaderdb/core/OpSLessThanEqual_TestSignedAndUnsigned_lit.frag
index dbc3ada9b8..21cdb8f20d 100644
--- a/llpc/test/shaderdb/core/OpSLessThanEqual_TestSignedAndUnsigned_lit.frag
+++ b/llpc/test/shaderdb/core/OpSLessThanEqual_TestSignedAndUnsigned_lit.frag
@@ -22,7 +22,7 @@ void main()
// SHADERTEST-LABEL: @lgc.shader.FS.main(
// SHADERTEST-NEXT: .entry:
-// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 0)
+// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
// SHADERTEST-NEXT: [[TMP1:%.*]] = call ptr @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) [[TMP0]])
// SHADERTEST-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr addrspace(7) [[TMP0]], align 8
// SHADERTEST-NEXT: [[TMP3:%.*]] = getelementptr inbounds <{ [2 x i32], [2 x i32], [2 x i32], [2 x i32] }>, ptr addrspace(7) [[TMP0]], i32 0, i32 1
diff --git a/llpc/test/shaderdb/core/OpSLessThan_TestSignedAndUnsigned_lit.frag b/llpc/test/shaderdb/core/OpSLessThan_TestSignedAndUnsigned_lit.frag
index 12e6965253..f9f18d7d0f 100644
--- a/llpc/test/shaderdb/core/OpSLessThan_TestSignedAndUnsigned_lit.frag
+++ b/llpc/test/shaderdb/core/OpSLessThan_TestSignedAndUnsigned_lit.frag
@@ -22,7 +22,7 @@ void main()
// SHADERTEST-LABEL: @lgc.shader.FS.main(
// SHADERTEST-NEXT: .entry:
-// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 0)
+// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
// SHADERTEST-NEXT: [[TMP1:%.*]] = call ptr @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) [[TMP0]])
// SHADERTEST-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr addrspace(7) [[TMP0]], align 8
// SHADERTEST-NEXT: [[TMP3:%.*]] = getelementptr inbounds <{ [2 x i32], [2 x i32], [2 x i32], [2 x i32] }>, ptr addrspace(7) [[TMP0]], i32 0, i32 1
diff --git a/llpc/test/shaderdb/core/OpSelect_TestGeneral_lit.frag b/llpc/test/shaderdb/core/OpSelect_TestGeneral_lit.frag
index 714b1573c8..2a4ebd233a 100644
--- a/llpc/test/shaderdb/core/OpSelect_TestGeneral_lit.frag
+++ b/llpc/test/shaderdb/core/OpSelect_TestGeneral_lit.frag
@@ -17,7 +17,7 @@ void main()
// SHADERTEST-LABEL: @lgc.shader.FS.main(
// SHADERTEST-NEXT: .entry:
-// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 0)
+// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
// SHADERTEST-NEXT: [[TMP1:%.*]] = call ptr @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) [[TMP0]])
// SHADERTEST-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(7) [[TMP0]], align 4
// SHADERTEST-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP2]], 0
diff --git a/llpc/test/shaderdb/core/OpVectorShuffle_TestDifferentInputVecSizes_lit.spvasm b/llpc/test/shaderdb/core/OpVectorShuffle_TestDifferentInputVecSizes_lit.spvasm
index 581831a5d2..43da432df1 100644
--- a/llpc/test/shaderdb/core/OpVectorShuffle_TestDifferentInputVecSizes_lit.spvasm
+++ b/llpc/test/shaderdb/core/OpVectorShuffle_TestDifferentInputVecSizes_lit.spvasm
@@ -10,7 +10,7 @@
; SHADERTEST: %{{.*}} = shufflevector <4 x double> [[TEMP_VEC]], <4 x double> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; SHADERTEST-LABEL: {{^// LLPC}} SPIR-V lowering results
-; SHADERTEST: %{{.*}} = shufflevector <4 x double> %{{.*}}, <4 x double> undef, <2 x i32> <i32 3, i32 2>
+; SHADERTEST: %{{.*}} = shufflevector <4 x double> %{{.*}}, <4 x double> {{poison|undef}}, <2 x i32> <i32 3, i32 2>
; SHADERTEST: [[TEMP_VEC:%[0-9]+]] = shufflevector <2 x double> %{{.*}}, <2 x double> {{undef|poison}}, <4 x i32> <i32 0, i32 1, i32 {{undef|poison}}, i32 {{undef|poison}}>
; SHADERTEST: %{{.*}} = shufflevector <4 x double> [[TEMP_VEC]], <4 x double> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; SHADERTEST: AMDLLPC SUCCESS
diff --git a/llpc/test/shaderdb/core/OpVectorShuffle_TestDvec4UndefVariable_lit.spvasm b/llpc/test/shaderdb/core/OpVectorShuffle_TestDvec4UndefVariable_lit.spvasm
index 0dee31afaf..2b02b7faa4 100644
--- a/llpc/test/shaderdb/core/OpVectorShuffle_TestDvec4UndefVariable_lit.spvasm
+++ b/llpc/test/shaderdb/core/OpVectorShuffle_TestDvec4UndefVariable_lit.spvasm
@@ -6,7 +6,7 @@
; SHADERTEST: [[TEMP_VEC:%[0-9]+]] = shufflevector <2 x double> %{{.*}}, <2 x double> {{undef|poison}}, <4 x i32> <i32 0, i32 1, i32 {{undef|poison}}, i32 {{undef|poison}}>
; SHADERTEST: %{{.*}} = shufflevector <4 x double> %{{.*}}, <4 x double> [[TEMP_VEC]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; SHADERTEST-LABEL: {{^// LLPC}} SPIR-V lowering results
-; SHADERTEST: %{{.*}} = shufflevector <4 x double> %{{.*}}, <4 x double> undef, <2 x i32> <i32 3, i32 2>
+; SHADERTEST: %{{.*}} = shufflevector <4 x double> %{{.*}}, <4 x double> {{poison|undef}}, <2 x i32> <i32 3, i32 2>
; SHADERTEST: [[TEMP_VEC:%[0-9]+]] = shufflevector <2 x double> %{{.*}}, <2 x double> {{undef|poison}}, <4 x i32> <i32 0, i32 1, i32 {{undef|poison}}, i32 {{undef|poison}}>
; SHADERTEST: %{{.*}} = shufflevector <4 x double> [[TEMP_VEC]], <4 x double> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
; SHADERTEST: AMDLLPC SUCCESS
diff --git a/llpc/test/shaderdb/core/OpVectorShuffle_TestDvec_lit.frag b/llpc/test/shaderdb/core/OpVectorShuffle_TestDvec_lit.frag
index c189715242..0ffea36feb 100644
--- a/llpc/test/shaderdb/core/OpVectorShuffle_TestDvec_lit.frag
+++ b/llpc/test/shaderdb/core/OpVectorShuffle_TestDvec_lit.frag
@@ -29,7 +29,7 @@ void main()
// SHADERTEST-LABEL: @lgc.shader.FS.main(
// SHADERTEST-NEXT: .entry:
-// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 0)
+// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
// SHADERTEST-NEXT: [[TMP1:%.*]] = call ptr @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) [[TMP0]])
// SHADERTEST-NEXT: [[TMP2:%.*]] = load <3 x double>, ptr addrspace(7) [[TMP0]], align 32
// SHADERTEST-NEXT: [[TMP3:%.*]] = extractelement <3 x double> [[TMP2]], i64 2
diff --git a/llpc/test/shaderdb/core/TestReverseThreadGroup.comp b/llpc/test/shaderdb/core/TestReverseThreadGroup.comp
index ee55b32f17..753ee7d3e9 100644
--- a/llpc/test/shaderdb/core/TestReverseThreadGroup.comp
+++ b/llpc/test/shaderdb/core/TestReverseThreadGroup.comp
@@ -13,12 +13,13 @@ void main()
}
// BEGIN_REVERSETEST
-// RUN: amdllpc -v %gfxip %s --reverse-thread-group=1 | FileCheck -check-prefix=REVERSETEST %s
+// RUN: amdllpc -v %gfxip %s --reverse-thread-group=1 --print-after=lgc-lower-desc 2>&1 | FileCheck -check-prefix=REVERSETEST %s
// REVERSETEST-LABEL: {{^// LLPC}} pipeline before-patching results
// There should be a calls to:
// - get the descriptor table containing the buffer descriptor
// - get the gl_NumWorkGroups
// - get the internal descriptor table
+// Note that `@lgc.load.user.data` is generated after lowering of `@lgc.load.buffer.desc` (lgc-lower-desc pass).
// REVERSETEST-DAG: %{{[0-9]+}} = call i32 @lgc.load.user.data.i32(i32 0)
// REVERSETEST-DAG: %{{[0-9]+}} = call ptr addrspace(4) @lgc.special.user.data.Workgroup(i32 268435462)
// REVERSETEST-DAG: %{{[0-9]+}} = call i32 @lgc.load.user.data.i32(i32 4)
diff --git a/llpc/test/shaderdb/extensions/ExtShaderFloat16_TestRelationalFuncs_lit.frag b/llpc/test/shaderdb/extensions/ExtShaderFloat16_TestRelationalFuncs_lit.frag
index 8169bd93be..59b52df5ae 100644
--- a/llpc/test/shaderdb/extensions/ExtShaderFloat16_TestRelationalFuncs_lit.frag
+++ b/llpc/test/shaderdb/extensions/ExtShaderFloat16_TestRelationalFuncs_lit.frag
@@ -41,7 +41,7 @@ void main()
// SHADERTEST-LABEL: @lgc.shader.FS.main(
// SHADERTEST-NEXT: .entry:
-// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 2)
+// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
// SHADERTEST-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr addrspace(7) [[TMP0]], align 16
// SHADERTEST-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <2 x i32> <i32 0, i32 poison>
// SHADERTEST-NEXT: [[TMP3:%.*]] = fptrunc <2 x float> [[TMP2]] to <2 x half>
diff --git a/llpc/test/shaderdb/extensions/ExtShaderInt64_TestRelationalOp_lit.frag b/llpc/test/shaderdb/extensions/ExtShaderInt64_TestRelationalOp_lit.frag
index 74a5173f78..0136adcbc0 100644
--- a/llpc/test/shaderdb/extensions/ExtShaderInt64_TestRelationalOp_lit.frag
+++ b/llpc/test/shaderdb/extensions/ExtShaderInt64_TestRelationalOp_lit.frag
@@ -34,7 +34,7 @@ void main()
// SHADERTEST-LABEL: @lgc.shader.FS.main(
// SHADERTEST-NEXT: .entry:
-// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 0)
+// SHADERTEST-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
// SHADERTEST-NEXT: [[TMP1:%.*]] = call ptr @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) [[TMP0]])
// SHADERTEST-NEXT: [[TMP2:%.*]] = getelementptr inbounds <{ i64, i64, [16 x i8], [3 x i64], [8 x i8], [3 x i64] }>, ptr addrspace(7) [[TMP0]], i32 0, i32 3
// SHADERTEST-NEXT: [[TMP3:%.*]] = load <3 x i64>, ptr addrspace(7) [[TMP2]], align 32
diff --git a/llpc/test/shaderdb/extensions/OpExtInst_TestFmaDouble_lit.frag b/llpc/test/shaderdb/extensions/OpExtInst_TestFmaDouble_lit.frag
index 3017f14622..696f3ba15c 100644
--- a/llpc/test/shaderdb/extensions/OpExtInst_TestFmaDouble_lit.frag
+++ b/llpc/test/shaderdb/extensions/OpExtInst_TestFmaDouble_lit.frag
@@ -20,7 +20,7 @@ void main()
}
// CHECK-LABEL: @lgc.shader.FS.main(
// CHECK-NEXT: .entry:
-// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 0)
+// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = load double, ptr addrspace(7) [[TMP0]], align 8
// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds <{ double, double, double, [8 x i8], [3 x double], [8 x i8], [3 x double], [8 x i8], [3 x double] }>, ptr addrspace(7) [[TMP0]], i32 0, i32 1
diff --git a/llpc/test/shaderdb/extensions/OpExtInst_TestFmaFloat_lit.frag b/llpc/test/shaderdb/extensions/OpExtInst_TestFmaFloat_lit.frag
index 83145a73b5..b4bfb876b2 100644
--- a/llpc/test/shaderdb/extensions/OpExtInst_TestFmaFloat_lit.frag
+++ b/llpc/test/shaderdb/extensions/OpExtInst_TestFmaFloat_lit.frag
@@ -20,7 +20,7 @@ void main()
}
// CHECK-LABEL: @lgc.shader.FS.main(
// CHECK-NEXT: .entry:
-// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 0)
+// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = load float, ptr addrspace(7) [[TMP0]], align 4
// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds <{ float, float, float, [4 x i8], [3 x float], [4 x i8], [3 x float], [4 x i8], [3 x float] }>, ptr addrspace(7) [[TMP0]], i32 0, i32 1
diff --git a/llpc/test/shaderdb/extensions/OpExtInst_TestMixSelectDouble_lit.frag b/llpc/test/shaderdb/extensions/OpExtInst_TestMixSelectDouble_lit.frag
index 6778c9c992..b57bee8eeb 100644
--- a/llpc/test/shaderdb/extensions/OpExtInst_TestMixSelectDouble_lit.frag
+++ b/llpc/test/shaderdb/extensions/OpExtInst_TestMixSelectDouble_lit.frag
@@ -25,7 +25,7 @@ void main()
// CHECK-LABEL: @lgc.shader.FS.main(
// CHECK-NEXT: .entry:
-// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 0)
+// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = load double, ptr addrspace(7) [[TMP0]], align 8
// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds <{ double, double, i32, [12 x i8], [3 x double], [8 x i8], [3 x double], [8 x i8], [3 x i32] }>, ptr addrspace(7) [[TMP0]], i32 0, i32 1
diff --git a/llpc/test/shaderdb/extensions/OpExtInst_TestMixSelectFloat_lit.frag b/llpc/test/shaderdb/extensions/OpExtInst_TestMixSelectFloat_lit.frag
index 8ab1a14c26..027ac67a06 100644
--- a/llpc/test/shaderdb/extensions/OpExtInst_TestMixSelectFloat_lit.frag
+++ b/llpc/test/shaderdb/extensions/OpExtInst_TestMixSelectFloat_lit.frag
@@ -25,7 +25,7 @@ void main()
// CHECK-LABEL: @lgc.shader.FS.main(
// CHECK-NEXT: .entry:
-// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 0)
+// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = load float, ptr addrspace(7) [[TMP0]], align 4
// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds <{ float, float, i32, [4 x i8], [3 x float], [4 x i8], [3 x float], [4 x i8], [3 x i32] }>, ptr addrspace(7) [[TMP0]], i32 0, i32 1
diff --git a/llpc/test/shaderdb/extensions/OpExtInst_TestMixSelectInt_lit.frag b/llpc/test/shaderdb/extensions/OpExtInst_TestMixSelectInt_lit.frag
index 03e3aa06d4..cdac65ca1e 100644
--- a/llpc/test/shaderdb/extensions/OpExtInst_TestMixSelectInt_lit.frag
+++ b/llpc/test/shaderdb/extensions/OpExtInst_TestMixSelectInt_lit.frag
@@ -25,7 +25,7 @@ void main()
// CHECK-LABEL: @lgc.shader.FS.main(
// CHECK-NEXT: .entry:
-// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 0)
+// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(7) [[TMP0]], align 4
// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds <{ i32, i32, i32, [4 x i8], [3 x i32], [4 x i8], [3 x i32], [4 x i8], [3 x i32] }>, ptr addrspace(7) [[TMP0]], i32 0, i32 1
diff --git a/llpc/test/shaderdb/extensions/OpExtInst_TestMixSelectUint_lit.frag b/llpc/test/shaderdb/extensions/OpExtInst_TestMixSelectUint_lit.frag
index 42342ade72..39dbce2bcf 100644
--- a/llpc/test/shaderdb/extensions/OpExtInst_TestMixSelectUint_lit.frag
+++ b/llpc/test/shaderdb/extensions/OpExtInst_TestMixSelectUint_lit.frag
@@ -25,7 +25,7 @@ void main()
// CHECK-LABEL: @lgc.shader.FS.main(
// CHECK-NEXT: .entry:
-// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 0)
+// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.invariant.start.p7(i64 -1, ptr addrspace(7) [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(7) [[TMP0]], align 4
// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds <{ i32, i32, i32, [4 x i8], [3 x i32], [4 x i8], [3 x i32], [4 x i8], [3 x i32] }>, ptr addrspace(7) [[TMP0]], i32 0, i32 1
diff --git a/llpc/test/shaderdb/extensions/PipelineVsFs_TestFetchSingleInput.pipe b/llpc/test/shaderdb/extensions/PipelineVsFs_TestFetchSingleInput.pipe
index 65cfab5c36..e4d2e4dbc3 100644
--- a/llpc/test/shaderdb/extensions/PipelineVsFs_TestFetchSingleInput.pipe
+++ b/llpc/test/shaderdb/extensions/PipelineVsFs_TestFetchSingleInput.pipe
@@ -16,12 +16,13 @@
; SHADERTEST: [[f0:%.*]] = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> [[addr:%[0-9]*]], i32 %VertexIndex, i32 0, i32 0, i32 22, i32 0)
; SHADERTEST: [[f1:%.*]] = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> [[addr:%[0-9]*]], i32 %VertexIndex, i32 4, i32 0, i32 22, i32 0)
; SHADERTEST: [[f2:%.*]] = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> [[addr:%[0-9]*]], i32 %VertexIndex, i32 8, i32 0, i32 22, i32 0)
-; SHADERTEST: [[vectmp0:%.*]] = insertelement <4 x i32> <i32 {{undef|poison}}, i32 {{undef|poison}}, i32 {{undef|poison}}, i32 1065353216>, i32 [[f0]], i{{32|64}} 0
+; SHADERTEST: [[vectmp0:%.*]] = insertelement <4 x i32> poison, i32 [[f0]], i{{32|64}} 0
; SHADERTEST: [[vectmp1:%.*]] = insertelement <4 x i32> [[vectmp0]], i32 [[f1]], i{{32|64}} 1
; SHADERTEST: [[vecf:%.*]] = insertelement <4 x i32> [[vectmp1]], i32 [[f2]], i{{32|64}} 2
; Check that the attribute is cast to float so that it will be placed in a VGPR
-; SHADERTEST: %vertex0.0 = bitcast <4 x i32> [[vecf]] to <4 x float>
+; SHADERTEST: [[vecCast:%.*]] = bitcast <4 x i32> [[vecf]] to <4 x float>
; Check that the attribute is inserted into the return value, and returned.
+; SHADERTEST: %vertex0.0 = insertelement <4 x float> [[vecCast]], float 1.000000e+00, i64 3
; SHADERTEST: [[retval:%.*]] = insertvalue {{.*}}, <4 x float> %vertex0.0
; SHADERTEST: ret {{.*}} [[retval]]
; END_SHADERTEST
diff --git a/llpc/test/shaderdb/general/CallInstAsUserOfGlobalVariable.spvasm b/llpc/test/shaderdb/general/CallInstAsUserOfGlobalVariable.spvasm
index db4b3b778c..004ecc957d 100644
--- a/llpc/test/shaderdb/general/CallInstAsUserOfGlobalVariable.spvasm
+++ b/llpc/test/shaderdb/general/CallInstAsUserOfGlobalVariable.spvasm
@@ -12,7 +12,7 @@
; CHECK: call i32 @lgc.buffer.length(ptr addrspace(7) @_ug_input23, i32 0)
; CHECK-LABEL: {{^// LLPC}} SPIR-V lowering results
-; CHECK: %[[global:[0-9]+]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 2, i32 1, i32 0, i32 2)
+; CHECK: %[[global:[0-9]+]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 2, i32 1, i32 0, i32 2)
; CHECK: call i32 @lgc.buffer.length(ptr addrspace(7) %[[global]], i32 0)
; CHECK-LABEL: {{^}}===== AMDLLPC SUCCESS =====
diff --git a/llpc/test/shaderdb/general/PipelineCs_DebugPrintf.pipe b/llpc/test/shaderdb/general/PipelineCs_DebugPrintf.pipe
index 84bce72fda..ee39f82720 100644
--- a/llpc/test/shaderdb/general/PipelineCs_DebugPrintf.pipe
+++ b/llpc/test/shaderdb/general/PipelineCs_DebugPrintf.pipe
@@ -24,7 +24,7 @@ userDataNode[0].next[0].set = 0xFFFFFFFF
userDataNode[0].next[0].binding = 6
; CHECK-LABEL: @lgc.shader.CS.main(
; CHECK-NEXT: .entry:
-; CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 4294967295, i32 6, i32 0, i32 2)
+; CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 4294967295, i32 6, i32 0, i32 2)
; CHECK-NEXT: [[TMP1:%.*]] = call <3 x i32> (...) @lgc.create.read.builtin.input.v3i32(i32 28, i32 0, i32 poison, i32 poison)
; CHECK-NEXT: [[__LLPC_INPUT_PROXY_GL_GLOBALINVOCATIONID_0_VEC_EXTRACT:%.*]] = extractelement <3 x i32> [[TMP1]], i64 0
; CHECK-NEXT: call void (...) @lgc.debug.printf(ptr addrspace(7) [[TMP0]], ptr addrspace(4) @str, i32 [[__LLPC_INPUT_PROXY_GL_GLOBALINVOCATIONID_0_VEC_EXTRACT]])
diff --git a/llpc/test/shaderdb/general/PipelineCs_MultipleRootInlineBuffer.pipe b/llpc/test/shaderdb/general/PipelineCs_MultipleRootInlineBuffer.pipe
index 406996bdd2..888650934e 100644
--- a/llpc/test/shaderdb/general/PipelineCs_MultipleRootInlineBuffer.pipe
+++ b/llpc/test/shaderdb/general/PipelineCs_MultipleRootInlineBuffer.pipe
@@ -1,11 +1,11 @@
; Test that LLPC can handle multiple inline buffer in the root table.
; BEGIN_SHADERTEST
-; RUN: amdllpc -o %t.elf %gfxip %s -v | FileCheck -check-prefix=SHADERTEST %s
+; RUN: amdllpc -o %t.elf %gfxip %s -v --print-after=lgc-lower-desc 2>&1 | FileCheck -check-prefix=SHADERTEST %s
; SHADERTEST-LABEL: {{^//}} LLPC SPIR-V lowering result
; SHADERTEST: define dllexport spir_func void @main()
-; SHADERTEST-DAG: call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 0)
-; SHADERTEST-DAG: call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 1, i32 0, i32 0)
+; SHADERTEST-DAG: call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 0)
+; SHADERTEST-DAG: call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 1, i32 0, i32 0)
; SHADERTEST: ret void
; SHADERTEST-LABEL: {{^//}} LLPC pipeline before-patching results
; SHADERTEST: define dllexport spir_func void @lgc.shader.CS.main()
diff --git a/llpc/test/shaderdb/general/PipelineCs_TestDynDescNoSpill_lit.pipe b/llpc/test/shaderdb/general/PipelineCs_TestDynDescNoSpill_lit.pipe
index 392c3e6ba0..54612a6a4f 100644
--- a/llpc/test/shaderdb/general/PipelineCs_TestDynDescNoSpill_lit.pipe
+++ b/llpc/test/shaderdb/general/PipelineCs_TestDynDescNoSpill_lit.pipe
@@ -2,7 +2,7 @@
; RUN: amdllpc -v %gfxip %s | FileCheck -check-prefix=SHADERTEST %s
; SHADERTEST-LABEL: {{^// LLPC}} SPIRV-to-LLVM translation results
; SHADERTEST-LABEL: {{^// LLPC}} SPIR-V lowering results
-; SHADERTEST: %{{.*}} = call {{.*}} {{.*}}@lgc.create.load.buffer.desc.{{[0-9a-z.]*}}(i64 0, i32 1, i32 0,
+; SHADERTEST: %{{.*}} = call {{.*}} {{.*}}@lgc.load.buffer.desc(i64 0, i32 1, i32 0,
; SHADERTEST-LABEL: {{^// LLPC}} pipeline patching results
; SHADERTEST: call <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32> %{{.*}}, i32 0, i32 0, i32 0)
; SHADERTEST: AMDLLPC SUCCESS
diff --git a/llpc/test/shaderdb/general/PipelineCs_TestInlineConstDirect_lit.pipe b/llpc/test/shaderdb/general/PipelineCs_TestInlineConstDirect_lit.pipe
index b362f52789..aa04a8b238 100644
--- a/llpc/test/shaderdb/general/PipelineCs_TestInlineConstDirect_lit.pipe
+++ b/llpc/test/shaderdb/general/PipelineCs_TestInlineConstDirect_lit.pipe
@@ -4,7 +4,7 @@
; SHADERTEST-LABEL: {{^// LLPC}} SPIRV-to-LLVM translation results
; SHADERTEST-LABEL: {{^// LLPC}} SPIR-V lowering results
-; SHADERTEST: %{{.*}} = call {{.*}} {{.*}}@lgc.create.load.buffer.desc.{{[0-9a-z.]*}}(i64 0, i32 1, i32 0,
+; SHADERTEST: %{{.*}} = call {{.*}} {{.*}}@lgc.load.buffer.desc(i64 0, i32 1, i32 0,
; SHADERTEST: getelementptr inbounds {{.*}}, ptr addrspace(7) %{{.*}}, i64 0, i32 2
; SHADERTEST: load <2 x double>, ptr addrspace(7) %{{.*}}, align 16
diff --git a/llpc/test/shaderdb/general/PipelineGsTess_TestInOutPacking.pipe b/llpc/test/shaderdb/general/PipelineGsTess_TestInOutPacking.pipe
index 9e253e3a64..a371688436 100644
--- a/llpc/test/shaderdb/general/PipelineGsTess_TestInOutPacking.pipe
+++ b/llpc/test/shaderdb/general/PipelineGsTess_TestInOutPacking.pipe
@@ -6,22 +6,22 @@
; SHADERTEST: <2 x float> (loc = 4, comp = 0), xfbBuffer = 2, xfbStride = 8, xfbOffset = 0, streamID = 0
; SHADERTEST: <2 x double> (loc = 3, comp = 0), xfbBuffer = 0, xfbStride = 16, xfbOffset = 0, streamID = 1
; SHADERTEST: float (loc = 4, comp = 3), xfbBuffer = 3, xfbStride = 4, xfbOffset = 0, streamID = 1
-; SHADERTEST-LABEL: {{^// LLPC}} location input/output mapping results (GS shader)
-; SHADERTEST: (GS) Output: stream = 0, loc = 0, comp = 0 => Mapped = 0, 0
-; SHADERTEST: (GS) Output: stream = 0, loc = 0, comp = 1 => Mapped = 0, 1
-; SHADERTEST: (GS) Output: stream = 0, loc = 1, comp = 0 => Mapped = 0, 2
-; SHADERTEST: (GS) Output: stream = 0, loc = 1, comp = 1 => Mapped = 0, 3
-; SHADERTEST: (GS) Output: stream = 0, loc = 1, comp = 2 => Mapped = 1, 0
-; SHADERTEST: (GS) Output: stream = 0, loc = 1, comp = 3 => Mapped = 1, 1
-; SHADERTEST: (GS) Output: stream = 0, loc = 2, comp = 0 => Mapped = 1, 2
-; SHADERTEST: (GS) Output: stream = 0, loc = 2, comp = 1 => Mapped = 1, 3
-; SHADERTEST: (GS) Output: stream = 0, loc = 4, comp = 0 => Mapped = 2, 0
-; SHADERTEST: (GS) Output: stream = 0, loc = 4, comp = 1 => Mapped = 2, 1
-; SHADERTEST: (GS) Output: stream = 1, loc = 3, comp = 0 => Mapped = 2, 0
-; SHADERTEST: (GS) Output: stream = 1, loc = 3, comp = 1 => Mapped = 2, 1
-; SHADERTEST: (GS) Output: stream = 1, loc = 3, comp = 2 => Mapped = 2, 2
-; SHADERTEST: (GS) Output: stream = 1, loc = 3, comp = 3 => Mapped = 2, 3
-; SHADERTEST: (GS) Output: stream = 1, loc = 4, comp = 3 => Mapped = 3, 0
+; SHADERTEST-LABEL: {{^// LLPC}} location input/output mapping results (GS)
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [0, 0] => Mapped = [0, 0]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [0, 1] => Mapped = [0, 1]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [1, 0] => Mapped = [0, 2]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [1, 1] => Mapped = [0, 3]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [1, 2] => Mapped = [1, 0]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [1, 3] => Mapped = [1, 1]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [2, 0] => Mapped = [1, 2]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [2, 1] => Mapped = [1, 3]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [4, 0] => Mapped = [2, 0]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [4, 1] => Mapped = [2, 1]
+; SHADERTEST: (GS) Output: stream = 1, [location, component] = [3, 0] => Mapped = [2, 0]
+; SHADERTEST: (GS) Output: stream = 1, [location, component] = [3, 1] => Mapped = [2, 1]
+; SHADERTEST: (GS) Output: stream = 1, [location, component] = [3, 2] => Mapped = [2, 2]
+; SHADERTEST: (GS) Output: stream = 1, [location, component] = [3, 3] => Mapped = [2, 3]
+; SHADERTEST: (GS) Output: stream = 1, [location, component] = [4, 3] => Mapped = [3, 0]
; SHADERTEST-LABEL: {{^// LLPC}} pipeline patching results
; SHADERTEST: call void @llvm.amdgcn.exp.f32(i32 32, i32 15
; SHADERTEST: call void @llvm.amdgcn.exp.f32(i32 33, i32 15
diff --git a/llpc/test/shaderdb/general/PipelineTcsTes_OutputComponentNotReadByNextStage.pipe b/llpc/test/shaderdb/general/PipelineTcsTes_OutputComponentNotReadByNextStage.pipe
new file mode 100644
index 0000000000..5548f45a5c
--- /dev/null
+++ b/llpc/test/shaderdb/general/PipelineTcsTes_OutputComponentNotReadByNextStage.pipe
@@ -0,0 +1,78 @@
+; This test is to check location/component mapping of a TCS output which is not used by TES but is treated as active
+; and is kept since it is read by TCS itself.
+
+; BEGIN_SHADERTEST
+; RUN: amdllpc -v %gfxip %s | FileCheck -check-prefix=SHADERTEST %s
+
+; SHADERTEST-LABEL: LLPC location input/output mapping results (TES)
+; SHADERTEST: (TES) Input: [location, component] = [0, 0] => Mapped = [0, 0]
+; SHADERTEST: (TES) Input: [location, component] = [1, 0] => Mapped = [1, 0]
+; SHADERTEST: (TES) Input: [location, component] = [2, 1] => Mapped = [2, 1]
+; SHADERTEST: (TES) Input: locations = 3
+
+; SHADERTEST-LABEL: LLPC location input/output mapping results (TCS)
+; SHADERTEST: (TCS) Output: [location, component] = [0, 0] => Mapped = [0, 0]
+; SHADERTEST: (TCS) Output: [location, component] = [1, 0] => Mapped = [1, 0]
+; SHADERTEST: (TCS) Output: [location, component] = [2, 0] => Mapped = [2, 0]
+; SHADERTEST: (TCS) Output: [location, component] = [2, 1] => Mapped = [2, 1]
+; SHADERTEST: (TCS) Output: locations = 3
+
+; SHADERTEST: AMDLLPC SUCCESS
+; END_SHADERTEST
+
+[TcsGlsl]
+#version 450 core
+
+layout(vertices = 3) out;
+
+layout(location = 0) out vec4 f0[];
+layout(location = 1) out vec4 f1[];
+layout(location = 2, component = 0) out float f2_0[]; // f2_0 is treated as active even if it is not read by TES
+layout(location = 2, component = 1) out float f2_1[];
+
+void main (void)
+{
+ f0[gl_InvocationID] = vec4(0.0);
+ f1[gl_InvocationID] = vec4(1.0);
+
+ f2_0[gl_InvocationID] = 2.0;
+ f2_1[gl_InvocationID] = 3.0;
+
+ barrier();
+
+ f2_0[gl_InvocationID] += f2_0[gl_InvocationID + 1]; // f2_0 is read by TCS
+
+ gl_TessLevelInner[0] = 1.0;
+ gl_TessLevelInner[1] = 1.0;
+ gl_TessLevelOuter[0] = 1.0;
+ gl_TessLevelOuter[1] = 1.0;
+ gl_TessLevelOuter[2] = 1.0;
+ gl_TessLevelOuter[3] = 2.0;
+}
+
+[TcsInfo]
+entryPoint = main
+
+[TesGlsl]
+#version 450 core
+
+layout(triangles) in;
+
+layout(location = 0) in vec4 f0[];
+layout(location = 1) in vec4 f1[];
+layout(location = 2, component = 1) in float f2_1[];
+
+layout(location = 0) out vec4 outColor;
+
+void main()
+{
+ outColor = f0[0];
+ outColor += f1[1];
+ outColor.x += f2_1[2];
+}
+
+[TesInfo]
+entryPoint = main
+
+[GraphicsPipelineState]
+patchControlPoints = 3
diff --git a/llpc/test/shaderdb/general/PipelineTcsTes_TestLocMapLoadBuiltInOutput.pipe b/llpc/test/shaderdb/general/PipelineTcsTes_TestLocMapLoadBuiltInOutput.pipe
index 9f3ee6f4f2..fc1b55ac82 100644
--- a/llpc/test/shaderdb/general/PipelineTcsTes_TestLocMapLoadBuiltInOutput.pipe
+++ b/llpc/test/shaderdb/general/PipelineTcsTes_TestLocMapLoadBuiltInOutput.pipe
@@ -7,7 +7,7 @@
; SHADERTEST: Patch constant total size (in dwords): 0
; SHADERTEST-LABEL: {{^// LLPC}} pipeline patching results
; SHADERTEST: call void @llvm.amdgcn.raw.tbuffer.store.v4f32
-; SHADERTEST-NEXT: ret void
+; SHADERTEST-NEXT: br label %.endHs
; SHADERTEST: AMDLLPC SUCCESS
; END_SHADERTEST
diff --git a/llpc/test/shaderdb/general/PipelineTcsTes_TestLocMapLoadGenericOutput.pipe b/llpc/test/shaderdb/general/PipelineTcsTes_TestLocMapLoadGenericOutput.pipe
index 96e06f575f..84b7c5aaf7 100644
--- a/llpc/test/shaderdb/general/PipelineTcsTes_TestLocMapLoadGenericOutput.pipe
+++ b/llpc/test/shaderdb/general/PipelineTcsTes_TestLocMapLoadGenericOutput.pipe
@@ -1,34 +1,34 @@
; BEGIN_SHADERTEST
; RUN: amdllpc -v %gfxip %s | FileCheck -check-prefix=SHADERTEST %s
-; SHADERTEST-LABEL: LLPC location input/output mapping results (TES shader)
+; SHADERTEST-LABEL: LLPC location input/output mapping results (TES)
-; SHADERTEST: (TES) Input: loc = 2, comp = 0 => Mapped = 0, 0
+; SHADERTEST: (TES) Input: [location, component] = [2, 0] => Mapped = [0, 0]
-; SHADERTEST: (TES) Input (per-patch): loc = 3 => Mapped = 0
-; SHADERTEST: (TES) Input (per-patch): loc = 4 => Mapped = 1
-; SHADERTEST: (TES) Input (per-patch): loc = 5 => Mapped = 2
+; SHADERTEST: (TES) Input (per-patch): location = 3 => Mapped = 0
+; SHADERTEST: (TES) Input (per-patch): location = 4 => Mapped = 1
+; SHADERTEST: (TES) Input (per-patch): location = 5 => Mapped = 2
; SHADERTEST-LABEL: LLPC location count results (after input/output matching)
-; SHADERTEST: (TES) Input: loc count = 1
-; SHADERTEST: (TES) Output: loc count = 0
-; SHADERTEST: (TES) Input (per-patch): loc count = 3
+; SHADERTEST: (TES) Input: locations = 1
+; SHADERTEST: (TES) Output: locations = 0
+; SHADERTEST: (TES) Input (per-patch): locations = 3
-; SHADERTEST-LABEL: LLPC location input/output mapping results (TCS shader)
+; SHADERTEST-LABEL: LLPC location input/output mapping results (TCS)
-; SHADERTEST: (TCS) Output: loc = 1, comp = 0 => Mapped = 1, 0
-; SHADERTEST: (TCS) Output: loc = 2, comp = 0 => Mapped = 0, 0
+; SHADERTEST: (TCS) Output: [location, component] = [1, 0] => Mapped = [1, 0]
+; SHADERTEST: (TCS) Output: [location, component] = [2, 0] => Mapped = [0, 0]
-; SHADERTEST: (TCS) Output (per-patch): loc = 3 => Mapped = 0
-; SHADERTEST: (TCS) Output (per-patch): loc = 4 => Mapped = 1
-; SHADERTEST: (TCS) Output (per-patch): loc = 5 => Mapped = 2
+; SHADERTEST: (TCS) Output (per-patch): location = 3 => Mapped = 0
+; SHADERTEST: (TCS) Output (per-patch): location = 4 => Mapped = 1
+; SHADERTEST: (TCS) Output (per-patch): location = 5 => Mapped = 2
; SHADERTEST-LABEL: LLPC location count results (after input/output matching)
-; SHADERTEST: (TCS) Input: loc count = 0
-; SHADERTEST: (TCS) Output: loc count = 2
-; SHADERTEST: (TCS) Output (per-patch): loc count = 3
+; SHADERTEST: (TCS) Input: locations = 0
+; SHADERTEST: (TCS) Output: locations = 2
+; SHADERTEST: (TCS) Output (per-patch): locations = 3
; SHADERTEST: AMDLLPC SUCCESS
; END_SHADERTEST
diff --git a/llpc/test/shaderdb/general/PipelineTess_TestInOutPacking.pipe b/llpc/test/shaderdb/general/PipelineTess_TestInOutPacking.pipe
index cf581f458b..2d5293e92c 100644
--- a/llpc/test/shaderdb/general/PipelineTess_TestInOutPacking.pipe
+++ b/llpc/test/shaderdb/general/PipelineTess_TestInOutPacking.pipe
@@ -2,8 +2,7 @@
; RUN: amdllpc -enable-part-pipeline=0 -v %gfxip %s | FileCheck -check-prefix=SHADERTEST_PP0 %s
; SHADERTEST_PP0-LABEL: {{^// LLPC}} pipeline patching results
-; SHADERTEST_PP0: define {{.*}} @_amdgpu_ls_main
-; SHADERTEST_PP0: [[VERTEX_BASE:%[0-9a-zA-Z.]+]] = mul i32 %RelVertexId,
+; SHADERTEST_PP0: [[VERTEX_BASE:%[0-9a-zA-Z.]+]] = mul i32 %{{[0-9]*}}, 48
; SHADERTEST_PP0: %{{[0-9]*}} = {{add|or}} {{.*}}i32 [[VERTEX_BASE]], 44
; SHADERTEST_PP0: %{{[0-9]*}} = {{add|or}} {{.*}}i32 [[VERTEX_BASE]], 45
; SHADERTEST_PP0: %{{[0-9]*}} = {{add|or}} {{.*}}i32 [[VERTEX_BASE]], 46
@@ -53,8 +52,7 @@
; SHADERTEST_PP1: call float @llvm.amdgcn.interp.p1(float %{{[^,]*}}, i32 immarg 1, i32 immarg 0, i32 %PrimMask)
; Pre-rasterization part-pipeline:
; SHADERTEST_PP1-LABEL: {{^// LLPC}} pipeline patching results
-; SHADERTEST_PP1: define {{.*}} @_amdgpu_ls_main
-; SHADERTEST_PP1: [[VERTEX_BASE:%[0-9a-zA-Z.]+]] = mul i32 %RelVertexId,
+; SHADERTEST_PP1: [[VERTEX_BASE:%[0-9a-zA-Z.]+]] = mul i32 %{{[0-9]*}}, 48
; SHADERTEST_PP1: %{{[0-9]*}} = {{add|or}} {{.*}}i32 [[VERTEX_BASE]], 44
; SHADERTEST_PP1: %{{[0-9]*}} = {{add|or}} {{.*}}i32 [[VERTEX_BASE]], 45
; SHADERTEST_PP1: %{{[0-9]*}} = {{add|or}} {{.*}}i32 [[VERTEX_BASE]], 46
diff --git a/llpc/test/shaderdb/general/PipelineVsFs_DynamicSampleInfo.pipe b/llpc/test/shaderdb/general/PipelineVsFs_DynamicSampleInfo.pipe
index a55bca8982..ecf1098cf3 100644
--- a/llpc/test/shaderdb/general/PipelineVsFs_DynamicSampleInfo.pipe
+++ b/llpc/test/shaderdb/general/PipelineVsFs_DynamicSampleInfo.pipe
@@ -87,57 +87,52 @@ attribute[1].offset = 16
; SHADERTEST-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr addrspace(4)
; SHADERTEST-NEXT: [[TMP5:%.*]] = getelementptr <4 x i32>, ptr addrspace(4) [[TMP4]], i64 0
; SHADERTEST-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr addrspace(4) [[TMP5]], align 16, !invariant.load !13
-; SHADERTEST-NEXT: [[TMP7:%.*]] = call <2 x i32> @llvm.amdgcn.struct.tbuffer.load.v2i32(<4 x i32> [[TMP6]], i32 [[VERTEXINDEX]], i32 16, i32 0, i32 64, i32 0)
-; SHADERTEST-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> <i32 0, i32 0, i32 0, i32 1065353216>, i32 0
-; SHADERTEST-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> <i32 0, i32 0, i32 0, i32 1065353216>, i32 1
-; SHADERTEST-NEXT: [[TMP10:%.*]] = extractelement <4 x i32> <i32 0, i32 0, i32 0, i32 1065353216>, i32 2
-; SHADERTEST-NEXT: [[TMP11:%.*]] = extractelement <4 x i32> <i32 0, i32 0, i32 0, i32 1065353216>, i32 3
-; SHADERTEST-NEXT: [[TMP12:%.*]] = extractelement <2 x i32> [[TMP7]], i32 0
-; SHADERTEST-NEXT: [[TMP13:%.*]] = extractelement <2 x i32> [[TMP7]], i32 1
-; SHADERTEST-NEXT: [[TMP14:%.*]] = insertelement <2 x i32> poison, i32 [[TMP12]], i32 0
-; SHADERTEST-NEXT: [[TMP15:%.*]] = insertelement <2 x i32> [[TMP14]], i32 [[TMP13]], i32 1
-; SHADERTEST-NEXT: [[VERTEX1_0:%.*]] = bitcast <2 x i32> [[TMP15]] to <2 x float>
-; SHADERTEST-NEXT: [[TMP16:%.*]] = getelementptr <4 x i32>, ptr addrspace(4) [[TMP4]], i64 0
-; SHADERTEST-NEXT: [[TMP17:%.*]] = load <4 x i32>, ptr addrspace(4) [[TMP16]], align 16, !invariant.load !13
-; SHADERTEST-NEXT: [[TMP18:%.*]] = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> [[TMP17]], i32 [[VERTEXINDEX]], i32 0, i32 0, i32 22, i32 0)
-; SHADERTEST-NEXT: [[TMP19:%.*]] = insertelement <4 x i32> poison, i32 [[TMP18]], i64 0
-; SHADERTEST-NEXT: [[TMP20:%.*]] = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> [[TMP17]], i32 [[VERTEXINDEX]], i32 4, i32 0, i32 22, i32 0)
-; SHADERTEST-NEXT: [[TMP21:%.*]] = insertelement <4 x i32> [[TMP19]], i32 [[TMP20]], i64 1
-; SHADERTEST-NEXT: [[TMP22:%.*]] = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> [[TMP17]], i32 [[VERTEXINDEX]], i32 8, i32 0, i32 22, i32 0)
-; SHADERTEST-NEXT: [[TMP23:%.*]] = insertelement <4 x i32> [[TMP21]], i32 [[TMP22]], i64 2
-; SHADERTEST-NEXT: [[TMP24:%.*]] = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> [[TMP17]], i32 [[VERTEXINDEX]], i32 12, i32 0, i32 22, i32 0)
-; SHADERTEST-NEXT: [[TMP25:%.*]] = insertelement <4 x i32> [[TMP23]], i32 [[TMP24]], i64 3
-; SHADERTEST-NEXT: [[TMP26:%.*]] = extractelement <4 x i32> <i32 0, i32 0, i32 0, i32 1065353216>, i32 0
-; SHADERTEST-NEXT: [[TMP27:%.*]] = extractelement <4 x i32> <i32 0, i32 0, i32 0, i32 1065353216>, i32 1
-; SHADERTEST-NEXT: [[TMP28:%.*]] = extractelement <4 x i32> <i32 0, i32 0, i32 0, i32 1065353216>, i32 2
-; SHADERTEST-NEXT: [[TMP29:%.*]] = extractelement <4 x i32> <i32 0, i32 0, i32 0, i32 1065353216>, i32 3
-; SHADERTEST-NEXT: [[TMP30:%.*]] = extractelement <4 x i32> [[TMP25]], i32 0
-; SHADERTEST-NEXT: [[TMP31:%.*]] = extractelement <4 x i32> [[TMP25]], i32 1
-; SHADERTEST-NEXT: [[TMP32:%.*]] = extractelement <4 x i32> [[TMP25]], i32 2
-; SHADERTEST-NEXT: [[TMP33:%.*]] = extractelement <4 x i32> [[TMP25]], i32 3
-; SHADERTEST-NEXT: [[TMP34:%.*]] = insertelement <4 x i32> poison, i32 [[TMP30]], i32 0
-; SHADERTEST-NEXT: [[TMP35:%.*]] = insertelement <4 x i32> [[TMP34]], i32 [[TMP31]], i32 1
-; SHADERTEST-NEXT: [[TMP36:%.*]] = insertelement <4 x i32> [[TMP35]], i32 [[TMP32]], i32 2
-; SHADERTEST-NEXT: [[TMP37:%.*]] = insertelement <4 x i32> [[TMP36]], i32 [[TMP33]], i32 3
-; SHADERTEST-NEXT: [[VERTEX0_0:%.*]] = bitcast <4 x i32> [[TMP37]] to <4 x float>
+; SHADERTEST-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> [[TMP6]], i32 [[VERTEXINDEX]], i32 16, i32 0, i32 22, i32 0)
+; SHADERTEST-NEXT: [[TMP8:%.*]] = insertelement <2 x i32> poison, i32 [[TMP7]], i64 0
+; SHADERTEST-NEXT: [[TMP9:%.*]] = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> [[TMP6]], i32 [[VERTEXINDEX]], i32 20, i32 0, i32 22, i32 0)
+; SHADERTEST-NEXT: [[TMP10:%.*]] = insertelement <2 x i32> [[TMP8]], i32 [[TMP9]], i64 1
+; SHADERTEST-NEXT: [[TMP11:%.*]] = extractelement <2 x i32> [[TMP10]], i32 0
+; SHADERTEST-NEXT: [[TMP12:%.*]] = insertelement <2 x i32> poison, i32 [[TMP11]], i32 0
+; SHADERTEST-NEXT: [[TMP13:%.*]] = extractelement <2 x i32> [[TMP10]], i32 1
+; SHADERTEST-NEXT: [[TMP14:%.*]] = insertelement <2 x i32> [[TMP12]], i32 [[TMP13]], i32 1
+; SHADERTEST-NEXT: [[VERTEX1_0:%.*]] = bitcast <2 x i32> [[TMP14]] to <2 x float>
+; SHADERTEST-NEXT: [[TMP15:%.*]] = getelementptr <4 x i32>, ptr addrspace(4) [[TMP4]], i64 0
+; SHADERTEST-NEXT: [[TMP16:%.*]] = load <4 x i32>, ptr addrspace(4) [[TMP15]], align 16, !invariant.load !13
+; SHADERTEST-NEXT: [[TMP17:%.*]] = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> [[TMP16]], i32 [[VERTEXINDEX]], i32 0, i32 0, i32 22, i32 0)
+; SHADERTEST-NEXT: [[TMP18:%.*]] = insertelement <4 x i32> poison, i32 [[TMP17]], i64 0
+; SHADERTEST-NEXT: [[TMP19:%.*]] = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> [[TMP16]], i32 [[VERTEXINDEX]], i32 4, i32 0, i32 22, i32 0)
+; SHADERTEST-NEXT: [[TMP20:%.*]] = insertelement <4 x i32> [[TMP18]], i32 [[TMP19]], i64 1
+; SHADERTEST-NEXT: [[TMP21:%.*]] = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> [[TMP16]], i32 [[VERTEXINDEX]], i32 8, i32 0, i32 22, i32 0)
+; SHADERTEST-NEXT: [[TMP22:%.*]] = insertelement <4 x i32> [[TMP20]], i32 [[TMP21]], i64 2
+; SHADERTEST-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> [[TMP16]], i32 [[VERTEXINDEX]], i32 12, i32 0, i32 22, i32 0)
+; SHADERTEST-NEXT: [[TMP24:%.*]] = insertelement <4 x i32> [[TMP22]], i32 [[TMP23]], i64 3
+; SHADERTEST-NEXT: [[TMP25:%.*]] = extractelement <4 x i32> [[TMP24]], i32 0
+; SHADERTEST-NEXT: [[TMP26:%.*]] = insertelement <4 x i32> poison, i32 [[TMP25]], i32 0
+; SHADERTEST-NEXT: [[TMP27:%.*]] = extractelement <4 x i32> [[TMP24]], i32 1
+; SHADERTEST-NEXT: [[TMP28:%.*]] = insertelement <4 x i32> [[TMP26]], i32 [[TMP27]], i32 1
+; SHADERTEST-NEXT: [[TMP29:%.*]] = extractelement <4 x i32> [[TMP24]], i32 2
+; SHADERTEST-NEXT: [[TMP30:%.*]] = insertelement <4 x i32> [[TMP28]], i32 [[TMP29]], i32 2
+; SHADERTEST-NEXT: [[TMP31:%.*]] = extractelement <4 x i32> [[TMP24]], i32 3
+; SHADERTEST-NEXT: [[TMP32:%.*]] = insertelement <4 x i32> [[TMP30]], i32 [[TMP31]], i32 3
+; SHADERTEST-NEXT: [[VERTEX0_0:%.*]] = bitcast <4 x i32> [[TMP32]] to <4 x float>
; SHADERTEST-NEXT: call void @lgc.output.export.builtin.Position.i32.v4f32(i32 0, <4 x float> [[VERTEX0_0]]) #[[ATTR7:[0-9]+]]
-; SHADERTEST-NEXT: [[TMP38:%.*]] = extractelement <2 x float> [[VERTEX1_0]], i64 0
-; SHADERTEST-NEXT: [[TMP39:%.*]] = extractelement <2 x float> [[VERTEX1_0]], i64 1
-; SHADERTEST-NEXT: [[TMP40:%.*]] = extractelement <2 x float> [[VERTEX1_0]], i64 0
-; SHADERTEST-NEXT: [[TMP41:%.*]] = extractelement <2 x float> [[VERTEX1_0]], i64 1
-; SHADERTEST-NEXT: [[TMP42:%.*]] = bitcast float [[TMP38]] to i32
-; SHADERTEST-NEXT: [[TMP43:%.*]] = bitcast float [[TMP39]] to i32
-; SHADERTEST-NEXT: [[TMP44:%.*]] = bitcast float [[TMP40]] to i32
-; SHADERTEST-NEXT: [[TMP45:%.*]] = bitcast float [[TMP41]] to i32
-; SHADERTEST-NEXT: [[TMP46:%.*]] = bitcast i32 [[TMP42]] to float
-; SHADERTEST-NEXT: [[TMP47:%.*]] = insertelement <4 x float> poison, float [[TMP46]], i64 0
-; SHADERTEST-NEXT: [[TMP48:%.*]] = bitcast i32 [[TMP43]] to float
-; SHADERTEST-NEXT: [[TMP49:%.*]] = insertelement <4 x float> [[TMP47]], float [[TMP48]], i64 1
-; SHADERTEST-NEXT: [[TMP50:%.*]] = bitcast i32 [[TMP44]] to float
-; SHADERTEST-NEXT: [[TMP51:%.*]] = insertelement <4 x float> [[TMP49]], float [[TMP50]], i64 2
-; SHADERTEST-NEXT: [[TMP52:%.*]] = bitcast i32 [[TMP45]] to float
-; SHADERTEST-NEXT: [[TMP53:%.*]] = insertelement <4 x float> [[TMP51]], float [[TMP52]], i64 3
-; SHADERTEST-NEXT: call void @lgc.output.export.generic.i32.i32.v4f32(i32 0, i32 0, <4 x float> [[TMP53]]) #[[ATTR7]]
+; SHADERTEST-NEXT: [[TMP33:%.*]] = extractelement <2 x float> [[VERTEX1_0]], i64 0
+; SHADERTEST-NEXT: [[TMP34:%.*]] = extractelement <2 x float> [[VERTEX1_0]], i64 1
+; SHADERTEST-NEXT: [[TMP35:%.*]] = extractelement <2 x float> [[VERTEX1_0]], i64 0
+; SHADERTEST-NEXT: [[TMP36:%.*]] = extractelement <2 x float> [[VERTEX1_0]], i64 1
+; SHADERTEST-NEXT: [[TMP37:%.*]] = bitcast float [[TMP33]] to i32
+; SHADERTEST-NEXT: [[TMP38:%.*]] = bitcast float [[TMP34]] to i32
+; SHADERTEST-NEXT: [[TMP39:%.*]] = bitcast float [[TMP35]] to i32
+; SHADERTEST-NEXT: [[TMP40:%.*]] = bitcast float [[TMP36]] to i32
+; SHADERTEST-NEXT: [[TMP41:%.*]] = bitcast i32 [[TMP37]] to float
+; SHADERTEST-NEXT: [[TMP42:%.*]] = insertelement <4 x float> poison, float [[TMP41]], i64 0
+; SHADERTEST-NEXT: [[TMP43:%.*]] = bitcast i32 [[TMP38]] to float
+; SHADERTEST-NEXT: [[TMP44:%.*]] = insertelement <4 x float> [[TMP42]], float [[TMP43]], i64 1
+; SHADERTEST-NEXT: [[TMP45:%.*]] = bitcast i32 [[TMP39]] to float
+; SHADERTEST-NEXT: [[TMP46:%.*]] = insertelement <4 x float> [[TMP44]], float [[TMP45]], i64 2
+; SHADERTEST-NEXT: [[TMP47:%.*]] = bitcast i32 [[TMP40]] to float
+; SHADERTEST-NEXT: [[TMP48:%.*]] = insertelement <4 x float> [[TMP46]], float [[TMP47]], i64 3
+; SHADERTEST-NEXT: call void @lgc.output.export.generic.i32.i32.v4f32(i32 0, i32 0, <4 x float> [[TMP48]]) #[[ATTR7]]
; SHADERTEST-NEXT: ret void
;
;
diff --git a/llpc/test/shaderdb/general/PipelineVsFs_TestInOutPacking.pipe b/llpc/test/shaderdb/general/PipelineVsFs_TestInOutPacking.pipe
index 459b83656d..38dd6a2f9c 100644
--- a/llpc/test/shaderdb/general/PipelineVsFs_TestInOutPacking.pipe
+++ b/llpc/test/shaderdb/general/PipelineVsFs_TestInOutPacking.pipe
@@ -1,168 +1,166 @@
; BEGIN_SHADERTEST
; RUN: amdllpc -enable-part-pipeline=0 -v %gfxip %s | FileCheck -check-prefix=SHADERTEST_PP0 %s
; SHADERTEST_PP0-LABEL: LLPC pipeline before-patching results
-; SHADERTEST_PP0-LABEL: LLPC location input/output mapping results (FS shader)
-; SHADERTEST_PP0: (FS) Input: loc = 7, comp = 0 => Mapped = 0, 0
-; SHADERTEST_PP0: (FS) Input: loc = 7, comp = 1 => Mapped = 0, 1
-; SHADERTEST_PP0: (FS) Input: loc = 8, comp = 0 => Mapped = 0, 2
-; SHADERTEST_PP0: (FS) Input: loc = 8, comp = 1 => Mapped = 0, 3
-; SHADERTEST_PP0: (FS) Input: loc = 9, comp = 0 => Mapped = 1, 0
-; SHADERTEST_PP0: (FS) Input: loc = 9, comp = 1 => Mapped = 1, 0
-; SHADERTEST_PP0: (FS) Input: loc = 9, comp = 2 => Mapped = 1, 1
-; SHADERTEST_PP0: (FS) Input: loc = 9, comp = 3 => Mapped = 1, 1
-; SHADERTEST_PP0: (FS) Input: loc = 10, comp = 0 => Mapped = 1, 2
-; SHADERTEST_PP0: (FS) Input: loc = 10, comp = 1 => Mapped = 1, 2
-; SHADERTEST_PP0: (FS) Input: loc = 10, comp = 2 => Mapped = 1, 3
-; SHADERTEST_PP0: (FS) Input: loc = 10, comp = 3 => Mapped = 1, 3
-; SHADERTEST_PP0: (FS) Input: loc = 11, comp = 0 => Mapped = 2, 0
-; SHADERTEST_PP0: (FS) Input: loc = 11, comp = 1 => Mapped = 2, 1
-; SHADERTEST_PP0: (FS) Input: loc = 11, comp = 2 => Mapped = 2, 2
-; SHADERTEST_PP0: (FS) Input: loc = 11, comp = 3 => Mapped = 2, 3
-; SHADERTEST_PP0: (FS) Input: loc = 12, comp = 0 => Mapped = 3, 0
-; SHADERTEST_PP0: (FS) Input: loc = 12, comp = 1 => Mapped = 3, 1
-; SHADERTEST_PP0: (FS) Input: loc = 13, comp = 0 => Mapped = 3, 2
-; SHADERTEST_PP0: (FS) Input: loc = 14, comp = 0 => Mapped = 4, 0
-; SHADERTEST_PP0: (FS) Input: loc = 14, comp = 1 => Mapped = 4, 0
-; SHADERTEST_PP0: (FS) Input: loc = 15, comp = 0 => Mapped = 4, 1
-; SHADERTEST_PP0: (FS) Input: loc = 15, comp = 1 => Mapped = 4, 1
-; SHADERTEST_PP0: (FS) Input: loc = 16, comp = 0 => Mapped = 4, 2
-; SHADERTEST_PP0: (FS) Input: loc = 16, comp = 1 => Mapped = 4, 2
-; SHADERTEST_PP0: (FS) Input: loc = 16, comp = 2 => Mapped = 4, 3
-; SHADERTEST_PP0: (FS) Input: loc = 16, comp = 3 => Mapped = 4, 3
-; SHADERTEST_PP0: (FS) Input: loc = 17, comp = 0 => Mapped = 5, 0
-; SHADERTEST_PP0: (FS) Input: loc = 17, comp = 1 => Mapped = 5, 1
-; SHADERTEST_PP0: (FS) Input: loc = 17, comp = 2 => Mapped = 5, 2
-; SHADERTEST_PP0-LABEL: LLPC location input/output mapping results (VS shader)
-; SHADERTEST_PP0: (VS) Output: loc = 0, comp = 0 => Mapped = 6, 0
-; SHADERTEST_PP0: (VS) Output: loc = 0, comp = 1 => Mapped = 6, 1
-; SHADERTEST_PP0: (VS) Output: loc = 0, comp = 2 => Mapped = 6, 2
-; SHADERTEST_PP0: (VS) Output: loc = 0, comp = 3 => Mapped = 6, 3
-; SHADERTEST_PP0: (VS) Output: loc = 1, comp = 0 => Mapped = 7, 0
-; SHADERTEST_PP0: (VS) Output: loc = 1, comp = 1 => Mapped = 7, 1
-; SHADERTEST_PP0: (VS) Output: loc = 1, comp = 2 => Mapped = 7, 2
-; SHADERTEST_PP0: (VS) Output: loc = 2, comp = 0 => Mapped = 7, 3
-; SHADERTEST_PP0: (VS) Output: loc = 2, comp = 1 => Mapped = 8, 0
-; SHADERTEST_PP0: (VS) Output: loc = 2, comp = 2 => Mapped = 8, 1
-; SHADERTEST_PP0: (VS) Output: loc = 3, comp = 0 => Mapped = 8, 2
-; SHADERTEST_PP0: (VS) Output: loc = 3, comp = 1 => Mapped = 8, 3
-; SHADERTEST_PP0: (VS) Output: loc = 6, comp = 0 => Mapped = 9, 0
-; SHADERTEST_PP0: (VS) Output: loc = 7, comp = 0 => Mapped = 0, 0
-; SHADERTEST_PP0: (VS) Output: loc = 7, comp = 1 => Mapped = 0, 1
-; SHADERTEST_PP0: (VS) Output: loc = 8, comp = 0 => Mapped = 0, 2
-; SHADERTEST_PP0: (VS) Output: loc = 8, comp = 1 => Mapped = 0, 3
-; SHADERTEST_PP0: (VS) Output: loc = 9, comp = 0 => Mapped = 1, 0
-; SHADERTEST_PP0: (VS) Output: loc = 9, comp = 1 => Mapped = 1, 0
-; SHADERTEST_PP0: (VS) Output: loc = 9, comp = 2 => Mapped = 1, 1
-; SHADERTEST_PP0: (VS) Output: loc = 9, comp = 3 => Mapped = 1, 1
-; SHADERTEST_PP0: (VS) Output: loc = 10, comp = 0 => Mapped = 1, 2
-; SHADERTEST_PP0: (VS) Output: loc = 10, comp = 1 => Mapped = 1, 2
-; SHADERTEST_PP0: (VS) Output: loc = 10, comp = 2 => Mapped = 1, 3
-; SHADERTEST_PP0: (VS) Output: loc = 10, comp = 3 => Mapped = 1, 3
-; SHADERTEST_PP0: (VS) Output: loc = 11, comp = 0 => Mapped = 2, 0
-; SHADERTEST_PP0: (VS) Output: loc = 11, comp = 1 => Mapped = 2, 1
-; SHADERTEST_PP0: (VS) Output: loc = 11, comp = 2 => Mapped = 2, 2
-; SHADERTEST_PP0: (VS) Output: loc = 11, comp = 3 => Mapped = 2, 3
-; SHADERTEST_PP0: (VS) Output: loc = 12, comp = 0 => Mapped = 3, 0
-; SHADERTEST_PP0: (VS) Output: loc = 12, comp = 1 => Mapped = 3, 1
-; SHADERTEST_PP0: (VS) Output: loc = 13, comp = 0 => Mapped = 3, 2
-; SHADERTEST_PP0: (VS) Output: loc = 14, comp = 0 => Mapped = 4, 0
-; SHADERTEST_PP0: (VS) Output: loc = 14, comp = 1 => Mapped = 4, 0
-; SHADERTEST_PP0: (VS) Output: loc = 15, comp = 0 => Mapped = 4, 1
-; SHADERTEST_PP0: (VS) Output: loc = 15, comp = 1 => Mapped = 4, 1
-; SHADERTEST_PP0: (VS) Output: loc = 16, comp = 0 => Mapped = 4, 2
-; SHADERTEST_PP0: (VS) Output: loc = 16, comp = 1 => Mapped = 4, 2
-; SHADERTEST_PP0: (VS) Output: loc = 16, comp = 2 => Mapped = 4, 3
-; SHADERTEST_PP0: (VS) Output: loc = 16, comp = 3 => Mapped = 4, 3
-; SHADERTEST_PP0: (VS) Output: loc = 17, comp = 0 => Mapped = 5, 0
-; SHADERTEST_PP0: (VS) Output: loc = 17, comp = 1 => Mapped = 5, 1
-; SHADERTEST_PP0: (VS) Output: loc = 17, comp = 2 => Mapped = 5, 2
+; SHADERTEST_PP0-LABEL: LLPC location input/output mapping results (FS)
+; SHADERTEST_PP0: (FS) Input: [location, component] = [7, 0] => Mapped = [0, 0]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [7, 1] => Mapped = [0, 1]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [8, 0] => Mapped = [0, 2]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [8, 1] => Mapped = [0, 3]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [9, 0] => Mapped = [1, 0]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [9, 1] => Mapped = [1, 0]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [9, 2] => Mapped = [1, 1]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [9, 3] => Mapped = [1, 1]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [10, 0] => Mapped = [1, 2]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [10, 1] => Mapped = [1, 2]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [10, 2] => Mapped = [1, 3]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [10, 3] => Mapped = [1, 3]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [11, 0] => Mapped = [2, 0]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [11, 1] => Mapped = [2, 1]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [11, 2] => Mapped = [2, 2]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [11, 3] => Mapped = [2, 3]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [12, 0] => Mapped = [3, 0]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [12, 1] => Mapped = [3, 1]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [13, 0] => Mapped = [3, 2]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [14, 0] => Mapped = [4, 0]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [14, 1] => Mapped = [4, 0]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [15, 0] => Mapped = [4, 1]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [15, 1] => Mapped = [4, 1]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [16, 0] => Mapped = [4, 2]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [16, 1] => Mapped = [4, 2]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [16, 2] => Mapped = [4, 3]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [16, 3] => Mapped = [4, 3]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [17, 0] => Mapped = [5, 0]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [17, 1] => Mapped = [5, 1]
+; SHADERTEST_PP0: (FS) Input: [location, component] = [17, 2] => Mapped = [5, 2]
+; SHADERTEST_PP0-LABEL: LLPC location input/output mapping results (VS)
+; SHADERTEST_PP0: (VS) Output: [location, component] = [0, 0] => Mapped = [6, 0]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [0, 1] => Mapped = [6, 1]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [0, 2] => Mapped = [6, 2]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [0, 3] => Mapped = [6, 3]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [1, 0] => Mapped = [7, 0]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [1, 1] => Mapped = [7, 1]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [1, 2] => Mapped = [7, 2]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [2, 0] => Mapped = [7, 3]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [2, 1] => Mapped = [8, 0]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [2, 2] => Mapped = [8, 1]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [3, 0] => Mapped = [8, 2]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [3, 1] => Mapped = [8, 3]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [6, 0] => Mapped = [9, 0]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [7, 0] => Mapped = [0, 0]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [7, 1] => Mapped = [0, 1]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [8, 0] => Mapped = [0, 2]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [8, 1] => Mapped = [0, 3]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [9, 0] => Mapped = [1, 0]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [9, 1] => Mapped = [1, 0]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [9, 2] => Mapped = [1, 1]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [9, 3] => Mapped = [1, 1]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [10, 0] => Mapped = [1, 2]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [10, 1] => Mapped = [1, 2]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [10, 2] => Mapped = [1, 3]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [10, 3] => Mapped = [1, 3]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [11, 0] => Mapped = [2, 0]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [11, 1] => Mapped = [2, 1]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [11, 2] => Mapped = [2, 2]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [11, 3] => Mapped = [2, 3]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [12, 0] => Mapped = [3, 0]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [12, 1] => Mapped = [3, 1]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [13, 0] => Mapped = [3, 2]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [14, 0] => Mapped = [4, 0]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [14, 1] => Mapped = [4, 0]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [15, 0] => Mapped = [4, 1]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [15, 1] => Mapped = [4, 1]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [16, 0] => Mapped = [4, 2]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [16, 1] => Mapped = [4, 2]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [16, 2] => Mapped = [4, 3]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [16, 3] => Mapped = [4, 3]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [17, 0] => Mapped = [5, 0]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [17, 1] => Mapped = [5, 1]
+; SHADERTEST_PP0: (VS) Output: [location, component] = [17, 2] => Mapped = [5, 2]
; SHADERTEST_PP0: AMDLLPC SUCCESS
; END_SHADERTEST
-
-
; BEGIN_SHADERTEST
; RUN: amdllpc -enable-part-pipeline=1 -v %gfxip %s | FileCheck -check-prefix=SHADERTEST_PP1 %s
; Fragment shader part-pipeline:
; SHADERTEST_PP1-LABEL: LLPC pipeline before-patching results
-; SHADERTEST_PP1-LABEL: LLPC location input/output mapping results (FS shader)
-; SHADERTEST_PP1: (FS) Input: loc = 7, comp = 0 => Mapped = 0, 0
-; SHADERTEST_PP1: (FS) Input: loc = 7, comp = 1 => Mapped = 0, 1
-; SHADERTEST_PP1: (FS) Input: loc = 8, comp = 0 => Mapped = 0, 2
-; SHADERTEST_PP1: (FS) Input: loc = 8, comp = 1 => Mapped = 0, 3
-; SHADERTEST_PP1: (FS) Input: loc = 9, comp = 0 => Mapped = 1, 0
-; SHADERTEST_PP1: (FS) Input: loc = 9, comp = 1 => Mapped = 1, 0
-; SHADERTEST_PP1: (FS) Input: loc = 9, comp = 2 => Mapped = 1, 1
-; SHADERTEST_PP1: (FS) Input: loc = 9, comp = 3 => Mapped = 1, 1
-; SHADERTEST_PP1: (FS) Input: loc = 10, comp = 0 => Mapped = 1, 2
-; SHADERTEST_PP1: (FS) Input: loc = 10, comp = 1 => Mapped = 1, 2
-; SHADERTEST_PP1: (FS) Input: loc = 10, comp = 2 => Mapped = 1, 3
-; SHADERTEST_PP1: (FS) Input: loc = 10, comp = 3 => Mapped = 1, 3
-; SHADERTEST_PP1: (FS) Input: loc = 11, comp = 0 => Mapped = 2, 0
-; SHADERTEST_PP1: (FS) Input: loc = 11, comp = 1 => Mapped = 2, 1
-; SHADERTEST_PP1: (FS) Input: loc = 11, comp = 2 => Mapped = 2, 2
-; SHADERTEST_PP1: (FS) Input: loc = 11, comp = 3 => Mapped = 2, 3
-; SHADERTEST_PP1: (FS) Input: loc = 12, comp = 0 => Mapped = 3, 0
-; SHADERTEST_PP1: (FS) Input: loc = 12, comp = 1 => Mapped = 3, 1
-; SHADERTEST_PP1: (FS) Input: loc = 13, comp = 0 => Mapped = 3, 2
-; SHADERTEST_PP1: (FS) Input: loc = 14, comp = 0 => Mapped = 4, 0
-; SHADERTEST_PP1: (FS) Input: loc = 14, comp = 1 => Mapped = 4, 0
-; SHADERTEST_PP1: (FS) Input: loc = 15, comp = 0 => Mapped = 4, 1
-; SHADERTEST_PP1: (FS) Input: loc = 15, comp = 1 => Mapped = 4, 1
-; SHADERTEST_PP1: (FS) Input: loc = 16, comp = 0 => Mapped = 4, 2
-; SHADERTEST_PP1: (FS) Input: loc = 16, comp = 1 => Mapped = 4, 2
-; SHADERTEST_PP1: (FS) Input: loc = 16, comp = 2 => Mapped = 4, 3
-; SHADERTEST_PP1: (FS) Input: loc = 16, comp = 3 => Mapped = 4, 3
-; SHADERTEST_PP1: (FS) Input: loc = 17, comp = 0 => Mapped = 5, 0
-; SHADERTEST_PP1: (FS) Input: loc = 17, comp = 1 => Mapped = 5, 1
-; SHADERTEST_PP1: (FS) Input: loc = 17, comp = 2 => Mapped = 5, 2
+; SHADERTEST_PP1-LABEL: LLPC location input/output mapping results (FS)
+; SHADERTEST_PP1: (FS) Input: [location, component] = [7, 0] => Mapped = [0, 0]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [7, 1] => Mapped = [0, 1]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [8, 0] => Mapped = [0, 2]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [8, 1] => Mapped = [0, 3]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [9, 0] => Mapped = [1, 0]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [9, 1] => Mapped = [1, 0]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [9, 2] => Mapped = [1, 1]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [9, 3] => Mapped = [1, 1]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [10, 0] => Mapped = [1, 2]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [10, 1] => Mapped = [1, 2]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [10, 2] => Mapped = [1, 3]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [10, 3] => Mapped = [1, 3]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [11, 0] => Mapped = [2, 0]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [11, 1] => Mapped = [2, 1]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [11, 2] => Mapped = [2, 2]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [11, 3] => Mapped = [2, 3]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [12, 0] => Mapped = [3, 0]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [12, 1] => Mapped = [3, 1]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [13, 0] => Mapped = [3, 2]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [14, 0] => Mapped = [4, 0]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [14, 1] => Mapped = [4, 0]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [15, 0] => Mapped = [4, 1]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [15, 1] => Mapped = [4, 1]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [16, 0] => Mapped = [4, 2]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [16, 1] => Mapped = [4, 2]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [16, 2] => Mapped = [4, 3]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [16, 3] => Mapped = [4, 3]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [17, 0] => Mapped = [5, 0]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [17, 1] => Mapped = [5, 1]
+; SHADERTEST_PP1: (FS) Input: [location, component] = [17, 2] => Mapped = [5, 2]
; Pre-rasterization part-pipeline:
; SHADERTEST_PP1-LABEL: LLPC pipeline before-patching results
-; SHADERTEST_PP1-LABEL: LLPC location input/output mapping results (VS shader)
-; SHADERTEST_PP1: (VS) Output: loc = 0, comp = 0 => Mapped = 6, 0
-; SHADERTEST_PP1: (VS) Output: loc = 0, comp = 1 => Mapped = 6, 1
-; SHADERTEST_PP1: (VS) Output: loc = 0, comp = 2 => Mapped = 6, 2
-; SHADERTEST_PP1: (VS) Output: loc = 0, comp = 3 => Mapped = 6, 3
-; SHADERTEST_PP1: (VS) Output: loc = 1, comp = 0 => Mapped = 7, 0
-; SHADERTEST_PP1: (VS) Output: loc = 1, comp = 1 => Mapped = 7, 1
-; SHADERTEST_PP1: (VS) Output: loc = 1, comp = 2 => Mapped = 7, 2
-; SHADERTEST_PP1: (VS) Output: loc = 2, comp = 0 => Mapped = 7, 3
-; SHADERTEST_PP1: (VS) Output: loc = 2, comp = 1 => Mapped = 8, 0
-; SHADERTEST_PP1: (VS) Output: loc = 2, comp = 2 => Mapped = 8, 1
-; SHADERTEST_PP1: (VS) Output: loc = 3, comp = 0 => Mapped = 8, 2
-; SHADERTEST_PP1: (VS) Output: loc = 3, comp = 1 => Mapped = 8, 3
-; SHADERTEST_PP1: (VS) Output: loc = 6, comp = 0 => Mapped = 9, 0
-; SHADERTEST_PP1: (VS) Output: loc = 7, comp = 0 => Mapped = 0, 0
-; SHADERTEST_PP1: (VS) Output: loc = 7, comp = 1 => Mapped = 0, 1
-; SHADERTEST_PP1: (VS) Output: loc = 8, comp = 0 => Mapped = 0, 2
-; SHADERTEST_PP1: (VS) Output: loc = 8, comp = 1 => Mapped = 0, 3
-; SHADERTEST_PP1: (VS) Output: loc = 9, comp = 0 => Mapped = 1, 0
-; SHADERTEST_PP1: (VS) Output: loc = 9, comp = 1 => Mapped = 1, 0
-; SHADERTEST_PP1: (VS) Output: loc = 9, comp = 2 => Mapped = 1, 1
-; SHADERTEST_PP1: (VS) Output: loc = 9, comp = 3 => Mapped = 1, 1
-; SHADERTEST_PP1: (VS) Output: loc = 10, comp = 0 => Mapped = 1, 2
-; SHADERTEST_PP1: (VS) Output: loc = 10, comp = 1 => Mapped = 1, 2
-; SHADERTEST_PP1: (VS) Output: loc = 10, comp = 2 => Mapped = 1, 3
-; SHADERTEST_PP1: (VS) Output: loc = 10, comp = 3 => Mapped = 1, 3
-; SHADERTEST_PP1: (VS) Output: loc = 11, comp = 0 => Mapped = 2, 0
-; SHADERTEST_PP1: (VS) Output: loc = 11, comp = 1 => Mapped = 2, 1
-; SHADERTEST_PP1: (VS) Output: loc = 11, comp = 2 => Mapped = 2, 2
-; SHADERTEST_PP1: (VS) Output: loc = 11, comp = 3 => Mapped = 2, 3
-; SHADERTEST_PP1: (VS) Output: loc = 12, comp = 0 => Mapped = 3, 0
-; SHADERTEST_PP1: (VS) Output: loc = 12, comp = 1 => Mapped = 3, 1
-; SHADERTEST_PP1: (VS) Output: loc = 13, comp = 0 => Mapped = 3, 2
-; SHADERTEST_PP1: (VS) Output: loc = 14, comp = 0 => Mapped = 4, 0
-; SHADERTEST_PP1: (VS) Output: loc = 14, comp = 1 => Mapped = 4, 0
-; SHADERTEST_PP1: (VS) Output: loc = 15, comp = 0 => Mapped = 4, 1
-; SHADERTEST_PP1: (VS) Output: loc = 15, comp = 1 => Mapped = 4, 1
-; SHADERTEST_PP1: (VS) Output: loc = 16, comp = 0 => Mapped = 4, 2
-; SHADERTEST_PP1: (VS) Output: loc = 16, comp = 1 => Mapped = 4, 2
-; SHADERTEST_PP1: (VS) Output: loc = 16, comp = 2 => Mapped = 4, 3
-; SHADERTEST_PP1: (VS) Output: loc = 16, comp = 3 => Mapped = 4, 3
-; SHADERTEST_PP1: (VS) Output: loc = 17, comp = 0 => Mapped = 5, 0
-; SHADERTEST_PP1: (VS) Output: loc = 17, comp = 1 => Mapped = 5, 1
-; SHADERTEST_PP1: (VS) Output: loc = 17, comp = 2 => Mapped = 5, 2
+; SHADERTEST_PP1-LABEL: LLPC location input/output mapping results (VS)
+; SHADERTEST_PP1: (VS) Output: [location, component] = [0, 0] => Mapped = [6, 0]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [0, 1] => Mapped = [6, 1]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [0, 2] => Mapped = [6, 2]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [0, 3] => Mapped = [6, 3]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [1, 0] => Mapped = [7, 0]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [1, 1] => Mapped = [7, 1]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [1, 2] => Mapped = [7, 2]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [2, 0] => Mapped = [7, 3]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [2, 1] => Mapped = [8, 0]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [2, 2] => Mapped = [8, 1]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [3, 0] => Mapped = [8, 2]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [3, 1] => Mapped = [8, 3]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [6, 0] => Mapped = [9, 0]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [7, 0] => Mapped = [0, 0]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [7, 1] => Mapped = [0, 1]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [8, 0] => Mapped = [0, 2]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [8, 1] => Mapped = [0, 3]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [9, 0] => Mapped = [1, 0]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [9, 1] => Mapped = [1, 0]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [9, 2] => Mapped = [1, 1]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [9, 3] => Mapped = [1, 1]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [10, 0] => Mapped = [1, 2]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [10, 1] => Mapped = [1, 2]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [10, 2] => Mapped = [1, 3]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [10, 3] => Mapped = [1, 3]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [11, 0] => Mapped = [2, 0]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [11, 1] => Mapped = [2, 1]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [11, 2] => Mapped = [2, 2]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [11, 3] => Mapped = [2, 3]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [12, 0] => Mapped = [3, 0]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [12, 1] => Mapped = [3, 1]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [13, 0] => Mapped = [3, 2]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [14, 0] => Mapped = [4, 0]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [14, 1] => Mapped = [4, 0]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [15, 0] => Mapped = [4, 1]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [15, 1] => Mapped = [4, 1]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [16, 0] => Mapped = [4, 2]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [16, 1] => Mapped = [4, 2]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [16, 2] => Mapped = [4, 3]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [16, 3] => Mapped = [4, 3]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [17, 0] => Mapped = [5, 0]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [17, 1] => Mapped = [5, 1]
+; SHADERTEST_PP1: (VS) Output: [location, component] = [17, 2] => Mapped = [5, 2]
; SHADERTEST_PP1: AMDLLPC SUCCESS
; END_SHADERTEST
diff --git a/llpc/test/shaderdb/general/PipelineVsGsFs_TestDwordPacking.pipe b/llpc/test/shaderdb/general/PipelineVsGsFs_TestDwordPacking.pipe
index 61ce5b0642..39fe50e71c 100644
--- a/llpc/test/shaderdb/general/PipelineVsGsFs_TestDwordPacking.pipe
+++ b/llpc/test/shaderdb/general/PipelineVsGsFs_TestDwordPacking.pipe
@@ -4,36 +4,36 @@
; BEGIN_SHADERTEST
; RUN: amdllpc -enable-part-pipeline=0 -v %gfxip %s | FileCheck -check-prefix=SHADERTEST %s
; RUN: amdllpc -enable-part-pipeline=1 -v %gfxip %s | FileCheck -check-prefix=SHADERTEST %s
-; SHADERTEST-LABEL: LLPC location input/output mapping results (FS shader)
-; SHADERTEST: (FS) Input: loc = 1, comp = 0 => Mapped = 0, 0
-; SHADERTEST: (FS) Input: loc = 1, comp = 1 => Mapped = 0, 1
-; SHADERTEST: (FS) Input: loc = 1, comp = 2 => Mapped = 0, 2
-; SHADERTEST: (FS) Input: loc = 1, comp = 3 => Mapped = 0, 3
-; SHADERTEST: (FS) Input: loc = 2, comp = 0 => Mapped = 2, 0
-; SHADERTEST: (FS) Input: loc = 2, comp = 1 => Mapped = 2, 1
-; SHADERTEST: (FS) Input: loc = 2, comp = 2 => Mapped = 2, 2
-; SHADERTEST: (FS) Input: loc = 2, comp = 3 => Mapped = 2, 3
-; SHADERTEST: (FS) Input: loc = 4, comp = 0 => Mapped = 1, 0
-; SHADERTEST: (FS) Input: loc = 4, comp = 1 => Mapped = 1, 1
+; SHADERTEST-LABEL: LLPC location input/output mapping results (FS)
+; SHADERTEST: (FS) Input: [location, component] = [1, 0] => Mapped = [0, 0]
+; SHADERTEST: (FS) Input: [location, component] = [1, 1] => Mapped = [0, 1]
+; SHADERTEST: (FS) Input: [location, component] = [1, 2] => Mapped = [0, 2]
+; SHADERTEST: (FS) Input: [location, component] = [1, 3] => Mapped = [0, 3]
+; SHADERTEST: (FS) Input: [location, component] = [2, 0] => Mapped = [2, 0]
+; SHADERTEST: (FS) Input: [location, component] = [2, 1] => Mapped = [2, 1]
+; SHADERTEST: (FS) Input: [location, component] = [2, 2] => Mapped = [2, 2]
+; SHADERTEST: (FS) Input: [location, component] = [2, 3] => Mapped = [2, 3]
+; SHADERTEST: (FS) Input: [location, component] = [4, 0] => Mapped = [1, 0]
+; SHADERTEST: (FS) Input: [location, component] = [4, 1] => Mapped = [1, 1]
; SHADERTEST-LABEL: LLPC location count results (after builtin-to-generic mapping)
-; SHADERTEST: (FS) Input: loc count = 3
-; SHADERTEST: (FS) Output: loc count = 2
-; SHADERTEST-LABEL: LLPC location input/output mapping results (GS shader)
-; SHADERTEST: (GS) Output: stream = 0, loc = 1, comp = 0 => Mapped = 0, 0
-; SHADERTEST: (GS) Output: stream = 0, loc = 1, comp = 1 => Mapped = 0, 1
-; SHADERTEST: (GS) Output: stream = 0, loc = 1, comp = 2 => Mapped = 0, 2
-; SHADERTEST: (GS) Output: stream = 0, loc = 1, comp = 3 => Mapped = 0, 3
-; SHADERTEST: (GS) Output: stream = 0, loc = 2, comp = 0 => Mapped = 2, 0
-; SHADERTEST: (GS) Output: stream = 0, loc = 2, comp = 1 => Mapped = 2, 1
-; SHADERTEST: (GS) Output: stream = 0, loc = 2, comp = 2 => Mapped = 2, 2
-; SHADERTEST: (GS) Output: stream = 0, loc = 2, comp = 3 => Mapped = 2, 3
-; SHADERTEST: (GS) Output: stream = 0, loc = 4, comp = 0 => Mapped = 1, 0
-; SHADERTEST: (GS) Output: stream = 0, loc = 4, comp = 1 => Mapped = 1, 1
-; SHADERTEST: (GS) Output: stream = 0, loc = 5, comp = 0 => Mapped = 3, 0
-; SHADERTEST: (GS) Output: stream = 0, loc = 5, comp = 1 => Mapped = 3, 1
+; SHADERTEST: (FS) Input: locations = 3
+; SHADERTEST: (FS) Output: locations = 2
+; SHADERTEST-LABEL: LLPC location input/output mapping results (GS)
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [1, 0] => Mapped = [0, 0]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [1, 1] => Mapped = [0, 1]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [1, 2] => Mapped = [0, 2]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [1, 3] => Mapped = [0, 3]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [2, 0] => Mapped = [2, 0]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [2, 1] => Mapped = [2, 1]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [2, 2] => Mapped = [2, 2]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [2, 3] => Mapped = [2, 3]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [4, 0] => Mapped = [1, 0]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [4, 1] => Mapped = [1, 1]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [5, 0] => Mapped = [3, 0]
+; SHADERTEST: (GS) Output: stream = 0, [location, component] = [5, 1] => Mapped = [3, 1]
; SHADERTEST-LABEL: LLPC location count results (after input/output matching)
-; SHADERTEST: (GS) Input: loc count = 2
-; SHADERTEST: (GS) Output: loc count = 4
+; SHADERTEST: (GS) Input: locations = 2
+; SHADERTEST: (GS) Output: locations = 4
; SHADERTEST: AMDLLPC SUCCESS
; END_SHADERTEST
diff --git a/llpc/test/shaderdb/general/WorkgroupSizeLiteral.spvasm b/llpc/test/shaderdb/general/WorkgroupSizeLiteral.spvasm
index 7daecc64a2..790cb7c648 100644
--- a/llpc/test/shaderdb/general/WorkgroupSizeLiteral.spvasm
+++ b/llpc/test/shaderdb/general/WorkgroupSizeLiteral.spvasm
@@ -1,7 +1,7 @@
; BEGIN_SHADERTEST
; RUN: amdllpc -v %gfxip %s | FileCheck -check-prefix=SHADERTEST %s
; SHADERTEST-LABEL: {{^// LLPC}} pipeline before-patching results
-; SHADERTEST: call <3 x i32> @lgc.shader.input.WorkgroupId(i32 0) #1
+; SHADERTEST: call <3 x i32> @lgc.shader.input.WorkgroupId(i32 0) #{{[0-9]*}}
; SHADERTEST: %{{[0-9]*}} = mul <3 x i32> %{{[0-9]*}}, <i32 1, i32 1, i32 1>
; SHADERTEST: AMDLLPC SUCCESS
; END_SHADERTEST
diff --git a/llpc/test/shaderdb/gfx11/cooperativeMatrix/array-of-matrices.comp b/llpc/test/shaderdb/gfx11/cooperativeMatrix/array-of-matrices.comp
index e0be5057f3..f483594686 100644
--- a/llpc/test/shaderdb/gfx11/cooperativeMatrix/array-of-matrices.comp
+++ b/llpc/test/shaderdb/gfx11/cooperativeMatrix/array-of-matrices.comp
@@ -33,7 +33,7 @@ void main() {
// CHECK-LABEL: @lgc.shader.CS.main(
// CHECK-LABEL: .entry:
// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(4) (...) @lgc.create.load.push.constants.ptr.p4()
-// CHECK-NEXT: [[TMP1:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 2)
+// CHECK-NEXT: [[TMP1:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x float> @lgc.cooperative.matrix.load.v8f32.p7.i32.i1.i32.i32.i32(ptr addrspace(7) [[TMP1]], i32 32, i1 true, i32 1, i32 0, i32 0) #[[ATTR1:[0-9]+]]
// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds <{ [4294967295 x [4 x i32]] }>, ptr addrspace(7) [[TMP1]], i32 0, i32 0, i32 32
// CHECK-NEXT: [[TMP4:%.*]] = call <8 x float> @lgc.cooperative.matrix.load.v8f32.p7.i32.i1.i32.i32.i32(ptr addrspace(7) [[TMP3]], i32 32, i1 true, i32 1, i32 0, i32 0) #[[ATTR1]]
diff --git a/llpc/test/shaderdb/gfx11/cooperativeMatrix/extract-insert.spvasm b/llpc/test/shaderdb/gfx11/cooperativeMatrix/extract-insert.spvasm
index c5fbaac0cc..422ae6f48e 100644
--- a/llpc/test/shaderdb/gfx11/cooperativeMatrix/extract-insert.spvasm
+++ b/llpc/test/shaderdb/gfx11/cooperativeMatrix/extract-insert.spvasm
@@ -121,9 +121,9 @@
; CHECK-LABEL: @lgc.shader.CS.main(
; CHECK-LABEL: .entry:
-; CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 2, i32 0, i32 2)
-; CHECK-NEXT: [[TMP1:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 1, i32 0, i32 2)
-; CHECK-NEXT: [[TMP2:%.*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 2)
+; CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 2, i32 0, i32 2)
+; CHECK-NEXT: [[TMP1:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 1, i32 0, i32 2)
+; CHECK-NEXT: [[TMP2:%.*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
; CHECK-NEXT: [[TMP3:%.*]] = call <8 x float> @lgc.cooperative.matrix.load.v8f32.p7.i32.i1.i32.i32.i32(ptr addrspace(7) [[TMP2]], i32 32, i1 true, i32 1, i32 0, i32 0) #[[ATTR1:[0-9]+]]
; CHECK-NEXT: [[TMP4:%.*]] = call <8 x float> @lgc.cooperative.matrix.load.v8f32.p7.i32.i1.i32.i32.i32(ptr addrspace(7) [[TMP1]], i32 32, i1 true, i32 1, i32 0, i32 0) #[[ATTR1]]
; CHECK-NEXT: br label [[TMP5:%.*]]
diff --git a/llpc/test/shaderdb/gfx11/cooperativeMatrix/loadstore-uvec4.comp b/llpc/test/shaderdb/gfx11/cooperativeMatrix/loadstore-uvec4.comp
index c97078f7ac..df715b16a1 100644
--- a/llpc/test/shaderdb/gfx11/cooperativeMatrix/loadstore-uvec4.comp
+++ b/llpc/test/shaderdb/gfx11/cooperativeMatrix/loadstore-uvec4.comp
@@ -22,8 +22,8 @@ void main() {
// CHECK-LABEL: @lgc.shader.CS.main(
// CHECK-LABEL: .entry:
-// CHECK-NEXT: [[TMP0:%[0-9]*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 1, i32 0, i32 2)
-// CHECK-NEXT: [[TMP1:%[0-9]*]] = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 0, i32 0, i32 2)
+// CHECK-NEXT: [[TMP0:%[0-9]*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 1, i32 0, i32 2)
+// CHECK-NEXT: [[TMP1:%[0-9]*]] = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0, i32 2)
// CHECK-NEXT: [[TMP2:%[0-9]*]] = call <8 x float> @lgc.cooperative.matrix.load.v8f32.p7.i32.i1.i32.i32.i32(ptr addrspace(7) [[TMP1]], i32 64, i1 true, i32 1, i32 0, i32 0) #[[ATTR1:[0-9]+]]
// CHECK-NEXT: call void @lgc.cooperative.matrix.store.p7.i32.i1.i32.i32.i32.v8f32(ptr addrspace(7) [[TMP0]], i32 64, i1 true, i32 1, i32 0, i32 0, <8 x float> [[TMP2]]) #[[ATTR2:[0-9]+]]
// CHECK-NEXT: ret void
diff --git a/llpc/test/shaderdb/object/ObjInput_TestVsDouble_lit.vert b/llpc/test/shaderdb/object/ObjInput_TestVsDouble_lit.vert
index ca977df7bc..1286a9228c 100644
--- a/llpc/test/shaderdb/object/ObjInput_TestVsDouble_lit.vert
+++ b/llpc/test/shaderdb/object/ObjInput_TestVsDouble_lit.vert
@@ -30,7 +30,7 @@ void main()
; SHADERTEST-DAG: call <3 x double> @lgc.input.import.generic.v3f64{{.*}}
; SHADERTEST-DAG: call <3 x double> @lgc.input.import.generic.v3f64{{.*}}
; SHADERTEST-LABEL: {{^// LLPC}} pipeline patching results
-; SHADERTEST-COUNT-3: call <4 x i32> @llvm.amdgcn.struct.tbuffer.load.v4i32
+; SHADERTEST-COUNT-12: call i32 @llvm.amdgcn.struct.tbuffer.load.i32
; SHADERTEST: AMDLLPC SUCCESS
*/
// END_SHADERTEST
diff --git a/llpc/test/shaderdb/object/ObjInput_TestVsVectorArray_lit.vert b/llpc/test/shaderdb/object/ObjInput_TestVsVectorArray_lit.vert
index 2731334b57..6be814bcc5 100644
--- a/llpc/test/shaderdb/object/ObjInput_TestVsVectorArray_lit.vert
+++ b/llpc/test/shaderdb/object/ObjInput_TestVsVectorArray_lit.vert
@@ -18,7 +18,7 @@ void main()
; SHADERTEST-LABEL: {{^// LLPC}} SPIR-V lowering results
; SHADERTEST-COUNT-2: call <4 x float> @lgc.input.import.generic.v4f32{{.*}}
; SHADERTEST-LABEL: {{^// LLPC}} pipeline patching results
-; SHADERTEST: call <4 x i32> @llvm.amdgcn.struct.tbuffer.load.v4i32
+; SHADERTEST-COUNT-4: call i32 @llvm.amdgcn.struct.tbuffer.load.i32
; SHADERTEST: AMDLLPC SUCCESS
*/
// END_SHADERTEST
diff --git a/llpc/test/shaderdb/object/ObjNonUniform_TestMinNonUniform.spvasm b/llpc/test/shaderdb/object/ObjNonUniform_TestMinNonUniform.spvasm
index 87d3782904..735df1edb9 100644
--- a/llpc/test/shaderdb/object/ObjNonUniform_TestMinNonUniform.spvasm
+++ b/llpc/test/shaderdb/object/ObjNonUniform_TestMinNonUniform.spvasm
@@ -1,7 +1,7 @@
; BEGIN_SHADERTEST
; RUN: amdllpc -v %gfxip %s | FileCheck -check-prefix=SHADERTEST %s
; SHADERTEST-LABEL: {{^// LLPC.*}} SPIR-V lowering results
-; SHADERTEST: call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.p7(i64 0, i32 2, i32 {{.*}}, i32 3)
+; SHADERTEST: call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 2, i32 {{.*}}, i32 3)
; SHADERTEST: AMDLLPC SUCCESS
; END_SHADERTEST
diff --git a/llpc/test/shaderdb/object/ObjResource_TestAlias_lit.frag b/llpc/test/shaderdb/object/ObjResource_TestAlias_lit.frag
index 30c6d602b9..c2d76316b4 100644
--- a/llpc/test/shaderdb/object/ObjResource_TestAlias_lit.frag
+++ b/llpc/test/shaderdb/object/ObjResource_TestAlias_lit.frag
@@ -45,7 +45,7 @@ void main()
; SHADERTEST: call reassoc nnan nsz arcp contract afn <4 x float> (...) @lgc.create.image.load.v4f32(i32 1, i32 512, <8 x i32>
; SHADERTEST-LABEL: {{^// LLPC.*}} SPIR-V lowering results
-; SHADERTEST: call {{.*}} {{.*}}@lgc.create.load.buffer.desc.{{[0-9a-z.]*}}{{.*}}(i64 0, i32 1,{{.*}}
+; SHADERTEST: call {{.*}} {{.*}}@lgc.load.buffer.desc{{.*}}(i64 0, i32 1,{{.*}}
; SHADERTEST: load <4 x float>
; SHADERTEST: call reassoc nnan nsz arcp contract afn <4 x float> (...) @lgc.create.image.sample.v4f32(i32 1, i32 512, <8 x i32>
; SHADERTEST: call reassoc nnan nsz arcp contract afn <4 x float> (...) @lgc.create.image.load.v4f32(i32 1, i32 512, <8 x i32>
diff --git a/llpc/test/shaderdb/object/ObjStorageBlock_TestIndirectIndex_lit.frag b/llpc/test/shaderdb/object/ObjStorageBlock_TestIndirectIndex_lit.frag
index 2c7ebe5140..d4cacc188d 100644
--- a/llpc/test/shaderdb/object/ObjStorageBlock_TestIndirectIndex_lit.frag
+++ b/llpc/test/shaderdb/object/ObjStorageBlock_TestIndirectIndex_lit.frag
@@ -35,7 +35,7 @@ void main()
; SHADERTEST: %{{[0-9]*}} = getelementptr [2 x <{ i32, [12 x i8], [4 x float], [2 x [4 x float]] }>], ptr addrspace(7) @{{[a-z0-9]+}}, i32 0, i32 %{{[0-9]*}}, i32 3, i32 %{{[0-9]*}}
; SHADERTEST-LABEL: {{^// LLPC}} SPIR-V lowering results
-; SHADERTEST-COUNT-3: call ptr addrspace(7) {{.*}} @lgc.create.load.buffer.desc.{{[0-9a-z.]*}}(i64 0, i32 0, i32 %{{[0-9]*}},
+; SHADERTEST-COUNT-3: call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 %{{[0-9]*}},
; SHADERTEST: AMDLLPC SUCCESS
*/
diff --git a/llpc/test/shaderdb/object/ObjStorageBlock_TestMemoryQualifier_lit.frag b/llpc/test/shaderdb/object/ObjStorageBlock_TestMemoryQualifier_lit.frag
index 787cc031ac..f630d5d615 100644
--- a/llpc/test/shaderdb/object/ObjStorageBlock_TestMemoryQualifier_lit.frag
+++ b/llpc/test/shaderdb/object/ObjStorageBlock_TestMemoryQualifier_lit.frag
@@ -21,7 +21,7 @@ void main()
; RUN: amdllpc -v %gfxip %s | FileCheck -check-prefix=SHADERTEST %s
; SHADERTEST-LABEL: {{^// LLPC}} SPIR-V lowering results
-; SHADERTEST: %{{[0-9]*}} = call ptr addrspace(7) (...) @lgc.create.load.buffer.desc.{{[0-9a-z]*}}(i64 1, i32 0, i32 0,
+; SHADERTEST: %{{[0-9]*}} = call ptr addrspace(7) @lgc.load.buffer.desc(i64 1, i32 0, i32 0,
; SHADERTEST: %{{[0-9]*}} = load atomic float, ptr addrspace(7) %{{[0-9]*}} unordered, align 4
; SHADERTEST: store atomic float %{{[0-9a-z.]*}}, ptr addrspace(7) %{{[0-9]*}} unordered, align 4
diff --git a/llpc/test/shaderdb/object/ObjStorageBlock_TestStoreBasicDouble_lit.vert b/llpc/test/shaderdb/object/ObjStorageBlock_TestStoreBasicDouble_lit.vert
index 74096f155f..3a3363543d 100644
--- a/llpc/test/shaderdb/object/ObjStorageBlock_TestStoreBasicDouble_lit.vert
+++ b/llpc/test/shaderdb/object/ObjStorageBlock_TestStoreBasicDouble_lit.vert
@@ -32,8 +32,8 @@ void main()
; SHADERTEST: call void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32> {{%[^,]+}}, <4 x i32> {{%[^,]+}}, i32 48, i32 0, i32 0)
; SHADERTEST: call <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32> {{%[^,]+}}, i32 64, i32 0, i32 0)
; SHADERTEST: call <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32> {{%[^,]+}}, i32 80, i32 0, i32 0)
-; SHADERTEST: shufflevector <8 x i32> {{%[^,]+}}, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; SHADERTEST: shufflevector <8 x i32> {{%[^,]+}}, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+; SHADERTEST: shufflevector <8 x i32> {{%[^,]+}}, <8 x i32> {{poison|undef}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; SHADERTEST: shufflevector <8 x i32> {{%[^,]+}}, <8 x i32> {{poison|undef}}, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; SHADERTEST: call void @llvm.amdgcn.raw.buffer.store.v4i32(<4 x i32> {{%[^,]+}}, <4 x i32> {{%[^,]+}}, i32 64, i32 0, i32 0)
; SHADERTEST: call void @llvm.amdgcn.raw.buffer.store.v4i32(<4 x i32> {{%[^,]+}}, <4 x i32> {{%[^,]+}}, i32 80, i32 0, i32 0)
diff --git a/llpc/test/shaderdb/object/ObjStorageBlock_TestVectorComponentStore_lit.comp b/llpc/test/shaderdb/object/ObjStorageBlock_TestVectorComponentStore_lit.comp
index b5a99d7180..8166c511b5 100644
--- a/llpc/test/shaderdb/object/ObjStorageBlock_TestVectorComponentStore_lit.comp
+++ b/llpc/test/shaderdb/object/ObjStorageBlock_TestVectorComponentStore_lit.comp
@@ -16,7 +16,7 @@ void main()
; REQUIRES: do-not-run-me
; SHADERTEST-LABEL: {{^// LLPC}} SPIR-V lowering results
-; SHADERTEST: %{{[0-9]*}} = call ptr addrspace(7) {{.*}} @lgc.create.load.buffer.desc.{{[0-9a-z.]*}}(i64 0, i32 0, i32 0,
+; SHADERTEST: %{{[0-9]*}} = call ptr addrspace(7) @lgc.load.buffer.desc(i64 0, i32 0, i32 0,
; SHADERTEST: %{{[0-9]*}} = load float, ptr addrspace(7) %{{[0-9]*}}, align 4
; SHADERTEST: %{{[0-9]*}} = getelementptr inbounds <{ [4 x float] }>, ptr addrspace(7) %{{[0-9]*}}, i64 0, i32 0, i64 1
; SHADERTEST: store float %{{[0-9]*}}, ptr addrspace(7) %{{[0-9]*}}, align 4
diff --git a/llpc/test/shaderdb/object/ObjUniformBlock_TestDirectIndex_lit.frag b/llpc/test/shaderdb/object/ObjUniformBlock_TestDirectIndex_lit.frag
index a123b31b34..ba1b71735e 100644
--- a/llpc/test/shaderdb/object/ObjUniformBlock_TestDirectIndex_lit.frag
+++ b/llpc/test/shaderdb/object/ObjUniformBlock_TestDirectIndex_lit.frag
@@ -20,8 +20,8 @@ void main()
; SHADERTEST: getelementptr inbounds ([4 x <{ [4 x float], [10 x [4 x float]] }>], ptr addrspace({{.*}}) @{{.*}}, i32 0, i32 3, i32 1, i32 5
; SHADERTEST-LABEL: {{^// LLPC}} SPIR-V lowering results
-; SHADERTEST: call {{.*}} {{.*}}@lgc.create.load.buffer.desc.{{[0-9a-z.]*}}(i64 1, i32 0, i32 0
-; SHADERTEST: call {{.*}} {{.*}}@lgc.create.load.buffer.desc.{{[0-9a-z.]*}}(i64 1, i32 0, i32 3
+; SHADERTEST: call {{.*}} {{.*}}@lgc.load.buffer.desc(i64 1, i32 0, i32 0
+; SHADERTEST: call {{.*}} {{.*}}@lgc.load.buffer.desc(i64 1, i32 0, i32 3
; SHADERTEST-LABEL: {{^// LLPC}} pipeline patching results
; SHADERTEST: call <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32> %{{[0-9]*}}, i32 0, i32 0)
diff --git a/llpc/test/shaderdb/ray_tracing/PipelineRays_Continufy.pipe b/llpc/test/shaderdb/ray_tracing/PipelineRays_Continufy.pipe
index f6c094478b..586e8ec6bc 100644
--- a/llpc/test/shaderdb/ray_tracing/PipelineRays_Continufy.pipe
+++ b/llpc/test/shaderdb/ray_tracing/PipelineRays_Continufy.pipe
@@ -4,6 +4,7 @@
; TODO: Change this to ISA / assembly output checks once the LLVM backend has settled
; RUN: amdllpc -gfxip 11.0 -emit-llvm -o - %s | FileCheck -check-prefixes=CHECK %s
+
; CHECK-LABEL: @_amdgpu_cs_main(
; CHECK: call void {{.*}} @llvm.amdgcn.cs.chain.
diff --git a/llpc/test/shaderdb/ray_tracing/standalone.rmiss b/llpc/test/shaderdb/ray_tracing/standalone.rmiss
index 21c90dc422..f5c8e3af42 100644
--- a/llpc/test/shaderdb/ray_tracing/standalone.rmiss
+++ b/llpc/test/shaderdb/ray_tracing/standalone.rmiss
@@ -1,7 +1,15 @@
// BEGIN_SHADERTEST
/*
; RUN: amdllpc -v %gfxip %s | FileCheck -check-prefix=SHADERTEST %s
-; SHADERTEST: _miss1:
+; SHADERTEST-LABEL: _miss1:
+; SHADERTEST: s_buffer_load_dwordx2 s{{\[}}[[address_lo:[0-9]+]]:[[address_hi:[0-9]+]]{{\]}}, s[0:3], 0x14
+; SHADERTEST: s_buffer_load_dword [[stride:s[0-9]+]], s[0:3], 0x1c
+; add size of shader ids to base address to get the start of the shader record buffer
+; SHADERTEST: s_add_u32 s[[shader_record_lo:[0-9]+]], s[[address_lo]], [[shader_ids_size:32]]
+; SHADERTEST: s_addc_u32 s[[shader_record_hi:[0-9]+]], s[[address_hi]], 0
+; SHADERTEST-NOT: v_mad_u64_u32 v{{[[0-9]+:[0-9]+]}}, null, [[stride]], v4, 32
+; SHADERTEST-NOT: global_load_dword v{{[0-9]}}, v{{[0-9]}}, s[[[address_lo]]:[[address_hi]]]
+; SHADERTEST: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[}}[[shader_record_lo]]:{{[0-9]+\]}}, {{[0-9]+}} idxen
; SHADERTEST: AMDLLPC SUCCESS
*/
// END_SHADERTEST
diff --git a/llpc/test/shaderdb/relocatable_shaders/PipelineGsTess_AllStagesReloc.pipe b/llpc/test/shaderdb/relocatable_shaders/PipelineGsTess_AllStagesReloc.pipe
index 5e562e3b58..78282e4d2f 100644
--- a/llpc/test/shaderdb/relocatable_shaders/PipelineGsTess_AllStagesReloc.pipe
+++ b/llpc/test/shaderdb/relocatable_shaders/PipelineGsTess_AllStagesReloc.pipe
@@ -9,9 +9,6 @@
; Make sure the hs shader comes first and has the vertex attribute as its last parameter.
; SHADERTEST: define dllexport amdgpu_hs void @_amdgpu_hs_main_fetchless({{.*}}, <4 x float> noundef [[vert_attrib:%[0-9]*]])
-; Call the original vertex shader passing in the attribute
-; SHADERTEST: call amdgpu_ls void @_amdgpu_ls_main_fetchless({{.*}}, <4 x float> [[vert_attrib]])
-
; Reach the end of the hs shader
; SHADERTEST: ret void
@@ -26,7 +23,15 @@
; SHADERTEST: define amdgpu_hs { {{.*}} } @_amdgpu_hs_main({{.*}}, float noundef %VertexId
; SHADERTEST: [[vgprAsInt:%[0-9]+]] = bitcast float %VertexId to i32
; SHADERTEST: %VertexIndex = add i32 [[vgprAsInt]], %BaseVertex
-; SHADERTEST: @llvm.amdgcn.struct.tbuffer.load.v4i32(<4 x i32> {{%[0-9]+}}, i32 %VertexIndex,
+; SHADERTEST: [[TMP38:%.*]] = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> [[TMP37:%.*]], i32 %VertexIndex, i32 0, i32 0, i32 22, i32 0)
+; SHADERTEST: [[TMP39:%.*]] = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> [[TMP37]], i32 %VertexIndex, i32 4, i32 0, i32 22, i32 0)
+; SHADERTEST: [[TMP40:%.*]] = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> [[TMP37]], i32 %VertexIndex, i32 8, i32 0, i32 22, i32 0)
+; SHADERTEST: [[TMP41:%.*]] = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> [[TMP37]], i32 %VertexIndex, i32 12, i32 0, i32 22, i32 0)
+; SHADERTEST: [[TMP42:%.*]] = insertelement <4 x i32> poison, i32 [[TMP38]], i64 0
+; SHADERTEST: [[TMP43:%.*]] = insertelement <4 x i32> [[TMP42]], i32 [[TMP39]], i64 1
+; SHADERTEST: [[TMP44:%.*]] = insertelement <4 x i32> [[TMP43]], i32 [[TMP40]], i64 2
+; SHADERTEST: [[TMP45:%.*]] = insertelement <4 x i32> [[TMP44]], i32 [[TMP41]], i64 3
+; SHADERTEST: [[VERTEX0_0:%.*]] = bitcast <4 x i32> [[TMP45]] to <4 x float>
; SHADERTEST: AMDLLPC SUCCESS
; END_SHADERTEST
diff --git a/llpc/test/shaderdb/relocatable_shaders/PipelineGs_VertAttributeShort.pipe b/llpc/test/shaderdb/relocatable_shaders/PipelineGs_VertAttributeShort.pipe
index dc222ee861..fe27bb89da 100644
--- a/llpc/test/shaderdb/relocatable_shaders/PipelineGs_VertAttributeShort.pipe
+++ b/llpc/test/shaderdb/relocatable_shaders/PipelineGs_VertAttributeShort.pipe
@@ -6,7 +6,6 @@
; The i16vec4 fetch comes in as a <2 x float>, and passed on to the vertex shader.
; SHADERTEST: define dllexport amdgpu_gs void @_amdgpu_gs_main_fetchless({{.*}}, <2 x float> noundef [[fetch:%[0-9]*]])
-; SHADERTEST: call amdgpu_es void @_amdgpu_es_main_fetchless({{.*}}, <2 x float> [[fetch]])
; SHADERTEST: ===== AMDLLPC SUCCESS =====
; END_SHADERTEST
diff --git a/llpc/test/shaderdb/relocatable_shaders/PipelineTess_RelocRemoveUnusedTcsOutputs.pipe b/llpc/test/shaderdb/relocatable_shaders/PipelineTess_RelocRemoveUnusedTcsOutputs.pipe
index 636de36801..2db702b63d 100644
--- a/llpc/test/shaderdb/relocatable_shaders/PipelineTess_RelocRemoveUnusedTcsOutputs.pipe
+++ b/llpc/test/shaderdb/relocatable_shaders/PipelineTess_RelocRemoveUnusedTcsOutputs.pipe
@@ -4,10 +4,10 @@
; RUN: -enable-relocatable-shader-elf \
; RUN: -o %t.elf %gfxip %s -v | FileCheck -check-prefix=SHADERTEST %s
; SHADERTEST: {{^}}Building pipeline with relocatable shader elf.
-; SHADERTEST-LABEL: {{^}}// LLPC location input/output mapping results (TES shader)
-; SHADERTEST: {{^}}(TES) Input: loc = 2, comp = 0 => Mapped = 0, 0
-; SHADERTEST-LABEL: {{^}}// LLPC location input/output mapping results (TCS shader)
-; SHADERTEST: {{^}}(TCS) Output: loc = 2, comp = 0 => Mapped = 0, 0
+; SHADERTEST-LABEL: {{^}}// LLPC location input/output mapping results (TES)
+; SHADERTEST: {{^}}(TES) Input: [location, component] = [2, 0] => Mapped = [0, 0]
+; SHADERTEST-LABEL: {{^}}// LLPC location input/output mapping results (TCS)
+; SHADERTEST: {{^}}(TCS) Output: [location, component] = [2, 0] => Mapped = [0, 0]
; END_SHADERTEST
[Version]
diff --git a/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_16BitInput.pipe b/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_16BitInput.pipe
index 167f27a687..b0d986a292 100644
--- a/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_16BitInput.pipe
+++ b/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_16BitInput.pipe
@@ -15,8 +15,8 @@
; corresponds to the vertex shader.
; SHADERTEST-LABEL: // LGC glue shader results
; SHADERTEST: define amdgpu_vs {{.*}}
-; SHADERTEST: [[ld:%[0-9]+]] = call half @llvm.amdgcn.struct.tbuffer.load.f16({{.*}}
-; SHADERTEST: [[cast:%[0-9]+]] = bitcast half [[ld]] to i16
+; SHADERTEST: [[VERTEX2_0:%.*]] = call half @llvm.amdgcn.struct.tbuffer.load.f16({{.*}}
+; SHADERTEST: [[cast:%[0-9]+]] = bitcast half [[VERTEX2_0]] to i16
; SHADERTEST: [[zext:%[0-9]+]] = zext i16 [[cast]] to i32
; SHADERTEST: [[result:%[0-9]+]] = bitcast i32 [[zext]] to float
; SHADERTEST: [[ret:%[0-9]+]] = insertvalue { {{.*}} } {{%[0-9]+}}, float [[result]], 18
diff --git a/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_TestRelocatableInOutMapping.pipe b/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_TestRelocatableInOutMapping.pipe
index 8ebba52f59..cab13841e7 100644
--- a/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_TestRelocatableInOutMapping.pipe
+++ b/llpc/test/shaderdb/relocatable_shaders/PipelineVsFs_TestRelocatableInOutMapping.pipe
@@ -4,23 +4,23 @@
; BEGIN_SHADERTEST
; RUN: amdllpc -enable-relocatable-shader-elf -auto-layout-desc -v %gfxip %s \
; RUN: | FileCheck -check-prefix=SHADERTEST %s
-; SHADERTEST-LABEL: {{^//}} LLPC location input/output mapping results (VS shader){{$}}
+; SHADERTEST-LABEL: {{^//}} LLPC location input/output mapping results (VS){{$}}
;
-; SHADERTEST: (VS) Output: loc = 0, comp = 0 => Mapped = [[loc0:[0-9]+]], 0
-; SHADERTEST-NEXT: (VS) Output: loc = 1, comp = 0 => Mapped = [[loc1:[0-9]+]], 0
-; SHADERTEST-NEXT: (VS) Output: loc = 2, comp = 0 => Mapped = [[loc2:[0-9]+]], 0
-; SHADERTEST-NEXT: (VS) Output: loc = 3, comp = 0 => Mapped = [[loc3:[0-9]+]], 0
-; SHADERTEST-NEXT: (VS) Output: loc = 4, comp = 0 => Mapped = [[loc4:[0-9]+]], 0
+; SHADERTEST: (VS) Output: [location, component] = [0, 0] => Mapped = [[[loc0:[0-9]+]], 0]
+; SHADERTEST-NEXT: (VS) Output: [location, component] = [1, 0] => Mapped = [[[loc1:[0-9]+]], 0]
+; SHADERTEST-NEXT: (VS) Output: [location, component] = [2, 0] => Mapped = [[[loc2:[0-9]+]], 0]
+; SHADERTEST-NEXT: (VS) Output: [location, component] = [3, 0] => Mapped = [[[loc3:[0-9]+]], 0]
+; SHADERTEST-NEXT: (VS) Output: [location, component] = [4, 0] => Mapped = [[[loc4:[0-9]+]], 0]
;
-; SHADERTEST-LABEL: {{^//}} LLPC location input/output mapping results (FS shader){{$}}
+; SHADERTEST-LABEL: {{^//}} LLPC location input/output mapping results (FS){{$}}
;
-; SHADERTEST: (FS) Input: loc = 0, comp = 0 => Mapped = [[loc0]], 0
-; SHADERTEST-NEXT: (FS) Input: loc = 1, comp = 0 => Mapped = [[loc1]], 0
-; SHADERTEST-NEXT: (FS) Input: loc = 2, comp = 0 => Mapped = [[loc2]], 0
-; SHADERTEST-NEXT: (FS) Input: loc = 3, comp = 0 => Mapped = [[loc3]], 0
-; SHADERTEST-NEXT: (FS) Input: loc = 4, comp = 0 => Mapped = [[loc4]], 0
+; SHADERTEST: (FS) Input: [location, component] = [0, 0] => Mapped = [[[loc0]], 0]
+; SHADERTEST-NEXT: (FS) Input: [location, component] = [1, 0] => Mapped = [[[loc1]], 0]
+; SHADERTEST-NEXT: (FS) Input: [location, component] = [2, 0] => Mapped = [[[loc2]], 0]
+; SHADERTEST-NEXT: (FS) Input: [location, component] = [3, 0] => Mapped = [[[loc3]], 0]
+; SHADERTEST-NEXT: (FS) Input: [location, component] = [4, 0] => Mapped = [[[loc4]], 0]
;
-; SHADERTEST: (FS) Output: loc = 0, comp = 0 => Mapped = 0, 0
+; SHADERTEST: (FS) Output: [location, component] = [0, 0] => Mapped = [0, 0]
;
; SHADERTEST: AMDLLPC SUCCESS
; END_SHADERTEST
diff --git a/llpc/tool/amdllpc.cpp b/llpc/tool/amdllpc.cpp
index 4fa506079d..b99d7bca89 100644
--- a/llpc/tool/amdllpc.cpp
+++ b/llpc/tool/amdllpc.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -428,9 +428,9 @@ static Result init(int argc, char *argv[], ICompiler *&compiler, ShaderCacheWrap
// Before we get to LLVM command-line option parsing, we need to find the -gfxip option value.
for (int i = 1; i != argc; ++i) {
StringRef arg = argv[i];
- if (arg.startswith("--gfxip"))
+ if (arg.starts_with("--gfxip"))
arg = arg.drop_front(1);
- if (!arg.startswith("-gfxip"))
+ if (!arg.starts_with("-gfxip"))
continue;
StringRef gfxipStr;
arg = arg.slice(strlen("-gfxip"), StringRef::npos);
@@ -443,9 +443,9 @@ static Result init(int argc, char *argv[], ICompiler *&compiler, ShaderCacheWrap
if (!gfxipStr.consumeInteger(10, ParsedGfxIp.major)) {
ParsedGfxIp.minor = 0;
ParsedGfxIp.stepping = 0;
- if (gfxipStr.startswith(".")) {
+ if (gfxipStr.starts_with(".")) {
gfxipStr = gfxipStr.slice(1, StringRef::npos);
- if (!gfxipStr.consumeInteger(10, ParsedGfxIp.minor) && gfxipStr.startswith(".")) {
+ if (!gfxipStr.consumeInteger(10, ParsedGfxIp.minor) && gfxipStr.starts_with(".")) {
gfxipStr = gfxipStr.slice(1, StringRef::npos);
gfxipStr.consumeInteger(10, ParsedGfxIp.stepping);
}
diff --git a/llpc/tool/llpcAutoLayout.cpp b/llpc/tool/llpcAutoLayout.cpp
index 65d656677a..f079092430 100644
--- a/llpc/tool/llpcAutoLayout.cpp
+++ b/llpc/tool/llpcAutoLayout.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/tool/llpcAutoLayout.h b/llpc/tool/llpcAutoLayout.h
index 33018234ef..93fb3324af 100644
--- a/llpc/tool/llpcAutoLayout.h
+++ b/llpc/tool/llpcAutoLayout.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/tool/llpcCompilationUtils.cpp b/llpc/tool/llpcCompilationUtils.cpp
index 7ead26ea85..d83dc841d2 100644
--- a/llpc/tool/llpcCompilationUtils.cpp
+++ b/llpc/tool/llpcCompilationUtils.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/*
diff --git a/llpc/tool/llpcCompilationUtils.h b/llpc/tool/llpcCompilationUtils.h
index dc22245d57..fa442f521b 100644
--- a/llpc/tool/llpcCompilationUtils.h
+++ b/llpc/tool/llpcCompilationUtils.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/*
diff --git a/llpc/tool/llpcComputePipelineBuilder.cpp b/llpc/tool/llpcComputePipelineBuilder.cpp
index 0c416bb1c3..120b0cccfd 100644
--- a/llpc/tool/llpcComputePipelineBuilder.cpp
+++ b/llpc/tool/llpcComputePipelineBuilder.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/*
diff --git a/llpc/tool/llpcGraphicsPipelineBuilder.cpp b/llpc/tool/llpcGraphicsPipelineBuilder.cpp
index cdbe175080..23b98f27f0 100644
--- a/llpc/tool/llpcGraphicsPipelineBuilder.cpp
+++ b/llpc/tool/llpcGraphicsPipelineBuilder.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/*
diff --git a/llpc/tool/llpcInputUtils.cpp b/llpc/tool/llpcInputUtils.cpp
index 22ae3d4abe..604858e73b 100644
--- a/llpc/tool/llpcInputUtils.cpp
+++ b/llpc/tool/llpcInputUtils.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/*
@@ -219,7 +219,7 @@ bool isIsaText(const void *data, size_t dataSize) {
// @param fileName : File path to check
// @returns : true when fileName is a SPIR-V text file
bool isSpirvTextFile(StringRef fileName) {
- return fileName.endswith(Ext::SpirvText);
+ return fileName.ends_with(Ext::SpirvText);
}
// =====================================================================================================================
@@ -228,7 +228,7 @@ bool isSpirvTextFile(StringRef fileName) {
// @param fileName : File path to check
// @returns : true when fileName is a SPIR-V binary file
bool isSpirvBinaryFile(StringRef fileName) {
- return fileName.endswith(Ext::SpirvBin);
+ return fileName.ends_with(Ext::SpirvBin);
}
// =====================================================================================================================
@@ -237,7 +237,7 @@ bool isSpirvBinaryFile(StringRef fileName) {
// @param fileName : File path to check
// @returns : true when fileName is an LLVM IR file
bool isGlslShaderTextFile(llvm::StringRef fileName) {
- return any_of(Ext::GlslShaders, [fileName](StringLiteral extension) { return fileName.endswith(extension); });
+ return any_of(Ext::GlslShaders, [fileName](StringLiteral extension) { return fileName.ends_with(extension); });
}
// =====================================================================================================================
@@ -246,7 +246,7 @@ bool isGlslShaderTextFile(llvm::StringRef fileName) {
// @param fileName : File path to check
// @returns : true when fileName is an LLVM IR file
bool isLlvmIrFile(StringRef fileName) {
- return fileName.endswith(Ext::LlvmIr);
+ return fileName.ends_with(Ext::LlvmIr);
}
// =====================================================================================================================
@@ -255,7 +255,7 @@ bool isLlvmIrFile(StringRef fileName) {
// @param fileName : File path to check
// @returns : true when `fileName` is a pipeline info file
bool isPipelineInfoFile(StringRef fileName) {
- return fileName.endswith(Ext::PipelineInfo);
+ return fileName.ends_with(Ext::PipelineInfo);
}
// =====================================================================================================================
diff --git a/llpc/tool/llpcInputUtils.h b/llpc/tool/llpcInputUtils.h
index d0f7c93d07..bcf6276d16 100644
--- a/llpc/tool/llpcInputUtils.h
+++ b/llpc/tool/llpcInputUtils.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/*
diff --git a/llpc/tool/llpcPipelineBuilder.cpp b/llpc/tool/llpcPipelineBuilder.cpp
index 32648fac55..f98a8f0c8f 100644
--- a/llpc/tool/llpcPipelineBuilder.cpp
+++ b/llpc/tool/llpcPipelineBuilder.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/*
diff --git a/llpc/tool/llpcRayTracingPipelineBuilder.cpp b/llpc/tool/llpcRayTracingPipelineBuilder.cpp
index fdd398c74a..c2d882927c 100644
--- a/llpc/tool/llpcRayTracingPipelineBuilder.cpp
+++ b/llpc/tool/llpcRayTracingPipelineBuilder.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -115,6 +115,8 @@ Expected<SmallVector<BinaryData>> RayTracingPipelineBuilder::buildRayTracingPipe
Result result = getCompiler().BuildRayTracingPipeline(pipelineInfo, pipelineOut, pipelineDumpHandle);
+ IPipelineDumper::DumpRayTracingLibrarySummary(pipelineDumpHandle, &pipelineOut->librarySummary);
+
SmallVector<BinaryData> pipelines(pipelineOut->pipelineBins,
pipelineOut->pipelineBins + pipelineOut->pipelineBinCount);
runPostBuildActions(pipelineDumpHandle, pipelines);
diff --git a/llpc/tool/llpcRayTracingPipelineBuilder.h b/llpc/tool/llpcRayTracingPipelineBuilder.h
index 38b7053ca9..b3a9840079 100644
--- a/llpc/tool/llpcRayTracingPipelineBuilder.h
+++ b/llpc/tool/llpcRayTracingPipelineBuilder.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/tool/llpcShaderCache.cpp b/llpc/tool/llpcShaderCache.cpp
index 10b46e4259..c4c6e83146 100644
--- a/llpc/tool/llpcShaderCache.cpp
+++ b/llpc/tool/llpcShaderCache.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/tool/llpcShaderCache.h b/llpc/tool/llpcShaderCache.h
index 7f0f7facfb..fa5ffd126f 100644
--- a/llpc/tool/llpcShaderCache.h
+++ b/llpc/tool/llpcShaderCache.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/tool/llpcShaderCacheWrap.cpp b/llpc/tool/llpcShaderCacheWrap.cpp
index ae977561a5..72c794249f 100644
--- a/llpc/tool/llpcShaderCacheWrap.cpp
+++ b/llpc/tool/llpcShaderCacheWrap.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -81,8 +81,8 @@ ShaderCacheWrap *ShaderCacheWrap::Create(unsigned optionCount, const char *const
StringRef option = options[i] + 1; // Skip '-' in options
- if (option.startswith(cl::ShaderCacheMode.ArgStr) || option.startswith(cl::ShaderCacheFileDir.ArgStr) ||
- option.startswith(cl::ExecutableName.ArgStr)) {
+ if (option.starts_with(cl::ShaderCacheMode.ArgStr) || option.starts_with(cl::ShaderCacheFileDir.ArgStr) ||
+ option.starts_with(cl::ExecutableName.ArgStr)) {
createDummyCompiler = true;
break;
}
diff --git a/llpc/tool/llpcShaderCacheWrap.h b/llpc/tool/llpcShaderCacheWrap.h
index 390665a597..fc21c8e77f 100644
--- a/llpc/tool/llpcShaderCacheWrap.h
+++ b/llpc/tool/llpcShaderCacheWrap.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/translator/lib/SPIRV/SPIRVReader.cpp b/llpc/translator/lib/SPIRV/SPIRVReader.cpp
index a19912e44c..75996c6b00 100644
--- a/llpc/translator/lib/SPIRV/SPIRVReader.cpp
+++ b/llpc/translator/lib/SPIRV/SPIRVReader.cpp
@@ -45,6 +45,7 @@
#include "SPIRVType.h"
#include "SPIRVUtil.h"
#include "SPIRVValue.h"
+#include "continuations/ContinuationsUtil.h"
#include "llpcCompiler.h"
#include "llpcContext.h"
#include "llpcDialect.h"
@@ -195,6 +196,8 @@ SPIRVWord getStd430TypeAlignment(SPIRVType *const spvType) {
auto *columnTy = spvType->getMatrixColumnType();
return getStd430TypeAlignment(columnTy);
}
+ case OpTypeSampledImage:
+ return 1;
default:
llvm_unreachable("unexpected type");
break;
@@ -238,6 +241,8 @@ SPIRVWord getStd430AlignedTypeSize(SPIRVType *const spvType) {
SPIRVWord columnCount = spvType->getMatrixColumnCount();
return getStd430TypeAlignment(columnTy) * columnCount;
}
+ case OpTypeSampledImage:
+ return 0;
default:
llvm_unreachable("unexpected type");
break;
@@ -427,6 +432,27 @@ Type *SPIRVToLLVM::transTypeWithOpcode<spv::OpTypeArray>(SPIRVType *const spvTyp
}
Type *const arrayType = ArrayType::get(elementType, spvType->getArrayLength());
+
+ // Setup the replaced array type in case this array is used in default uniform struct:
+ // If the member type could be found in replaced-type map, insert the replaced-type,
+ // If the member type is image type, insert an int8 type. This is used for image array of array
+ SPIRVType *spvElementType = spvType->getArrayElementType();
+ SPIRVTypeContext ctxElementType(spvElementType, matrixStride, isColumnMajor, isParentPointer, layout);
+ Type *imageElementType = nullptr;
+ auto it = m_imageTypeMap.find(ctxElementType.asTuple());
+ if (it != m_imageTypeMap.end()) {
+ imageElementType = static_cast<StructType *>(it->second);
+ } else if (spvElementType->getOpCode() == OpTypeImage || spvElementType->getOpCode() == OpTypeSampler ||
+ spvElementType->getOpCode() == OpTypeSampledImage) {
+ imageElementType = Type::getInt8Ty(*m_context);
+ }
+
+ if (imageElementType) {
+ Type *const imageArrayType = ArrayType::get(imageElementType, spvType->getArrayLength());
+ SPIRVTypeContext ctxArray(spvType, matrixStride, isColumnMajor, isParentPointer, layout);
+ m_imageTypeMap[ctxArray.asTuple()] = imageArrayType;
+ }
+
return paddedArray ? recordTypeWithPad(arrayType) : arrayType;
}
@@ -688,6 +714,27 @@ Type *SPIRVToLLVM::transTypeWithOpcode<OpTypeRuntimeArray>(SPIRVType *const spvT
}
Type *const runtimeArrayType = ArrayType::get(elementType, SPIRVWORD_MAX);
+
+ // Setup the replaced array type in case this array is used in default uniform struct:
+ // If the member type could be found in replaced-type map, insert the replaced-type,
+ // If the member type is image type, insert an int8 type. This is used for image array of array
+ SPIRVType *spvElementType = spvType->getArrayElementType();
+ SPIRVTypeContext ctxElementType(spvElementType, matrixStride, isColumnMajor, isParentPointer, layout);
+ Type *imageElementType = nullptr;
+ auto it = m_imageTypeMap.find(ctxElementType.asTuple());
+ if (it != m_imageTypeMap.end()) {
+ imageElementType = static_cast<StructType *>(it->second);
+ } else if (spvElementType->getOpCode() == OpTypeImage || spvElementType->getOpCode() == OpTypeSampler ||
+ spvElementType->getOpCode() == OpTypeSampledImage) {
+ imageElementType = Type::getInt8Ty(*m_context);
+ }
+
+ if (imageElementType) {
+ Type *const imageArrayType = ArrayType::get(imageElementType, SPIRVWORD_MAX);
+ SPIRVTypeContext ctxArray(spvType, matrixStride, isColumnMajor, isParentPointer, layout);
+ m_imageTypeMap[ctxArray.asTuple()] = imageArrayType;
+ }
+
return paddedArray ? recordTypeWithPad(runtimeArrayType) : runtimeArrayType;
}
@@ -757,6 +804,9 @@ Type *SPIRVToLLVM::transTypeWithOpcode<spv::OpTypeStruct>(SPIRVType *const spvTy
uint64_t lastValidByte = 0;
bool usePadding = (isExplicitlyLaidOut && hasMemberOffset) || layout == LayoutMode::Std430;
SmallVector<Type *, 16> memberTypes;
+ SmallVector<Type *, 16> imageMemberTypes;
+ bool hasSamplerOrNested = false;
+ StructType *emptyStructType = StructType::get(*m_context, {});
for (const StructMember &structMember : structMembers) {
const SPIRVWord index = std::get<0>(structMember);
@@ -809,21 +859,63 @@ Type *SPIRVToLLVM::transTypeWithOpcode<spv::OpTypeStruct>(SPIRVType *const spvTy
if (isExplicitlyLaidOut && memberMatrixStride > 0)
assert(memberIsColumnMajor ^ spvStructType->hasMemberDecorate(index, DecorationRowMajor));
- Type *const memberType = transType(spvMemberType, memberMatrixStride, memberIsColumnMajor, isParentPointer, layout);
-
- lastValidByte = offset + getTypeStoreSize(memberType);
+ Type *memberType = transType(spvMemberType, memberMatrixStride, memberIsColumnMajor, isParentPointer, layout);
+ SPIRVTypeContext ctxMemberType(spvMemberType, matrixStride, isColumnMajor, isParentPointer, layout);
+
+ // Setup the replaced struct type in case this struct is used as default uniform:
+ // 1. If the member type is sampler:
+ // replace the member in origin struct with empty struct type.(member.size = 0)
+ // insert a int8 type in replaced-struct.
+ // 2. If the member type is a struct or an array:
+ // don't modify the member type in origin struct.
+ // if the member type could be found in replaced-type map,
+ // it means the struct contains sampler member, so insert the replaced-type in replaced-struct.
+ // if the member type could not be found,
+ // it means the struct doesn't contains sampler member, so insert an empty struct in replaced-struct.
+ // 3. Other type member
+ // NOT modify the member type in origin struct.
+ // insert an empty struct in replaced-struct.
+ //
+ // For the origin struct, if the member has been replaced with empty struct, NOT insert padding member.
+ // For replaced-struct, always NOT insert padding member.
+ Type *imageMemberType = emptyStructType;
+ if (spvMemberType->getOpCode() == OpTypeImage || spvMemberType->getOpCode() == OpTypeSampler ||
+ spvMemberType->getOpCode() == OpTypeSampledImage) {
+ memberType = emptyStructType;
+ imageMemberType = getBuilder()->getInt8Ty();
+ hasSamplerOrNested = true;
+ } else if (spvMemberType->getOpCode() == OpTypeStruct || spvMemberType->getOpCode() == OpTypeArray ||
+ spvMemberType->getOpCode() == OpTypeRuntimeArray) {
+ auto it = m_imageTypeMap.find(ctxMemberType.asTuple());
+ if (it != m_imageTypeMap.end()) {
+ imageMemberType = static_cast<StructType *>(it->second);
+ hasSamplerOrNested = true;
+ }
+ }
memberTypes.push_back(memberType);
+ imageMemberTypes.push_back(imageMemberType);
+ lastValidByte = offset + getTypeStoreSize(memberType);
lastIndex = index;
}
StructType *structType = nullptr;
- if (spvStructType->isLiteral())
+ StructType *imageStructType = nullptr;
+
+ if (spvStructType->isLiteral()) {
structType = StructType::get(*m_context, memberTypes, isPacked);
- else {
+ imageStructType = StructType::get(*m_context, imageMemberTypes, isPacked);
+ } else {
structType = StructType::create(*m_context, spvStructType->getName());
structType->setBody(memberTypes, isPacked);
+ imageStructType = StructType::create(*m_context, "images." + spvStructType->getName());
+ imageStructType->setBody(imageMemberTypes, isPacked);
+ }
+
+ if (hasSamplerOrNested) {
+ SPIRVTypeContext ctx(spvType, matrixStride, isColumnMajor, isParentPointer, layout);
+ m_imageTypeMap[ctx.asTuple()] = imageStructType;
}
return usePadding ? recordTypeWithPad(structType) : structType;
@@ -902,6 +994,7 @@ Type *SPIRVToLLVM::getPointeeType(SPIRVValue *v, LayoutMode layout) {
if (pointeeType)
return pointeeType;
}
+
if (isStorageClassExplicitlyLaidOut(m_bm, v->getType()->getPointerStorageClass()))
layout = LayoutMode::Explicit;
@@ -1045,11 +1138,6 @@ std::vector<Value *> SPIRVToLLVM::transValue(const std::vector<SPIRVValue *> &bv
return v;
}
-bool SPIRVToLLVM::isSPIRVCmpInstTransToLLVMInst(SPIRVInstruction *bi) const {
- auto oc = bi->getOpCode();
- return isCmpOpCode(oc);
-}
-
void SPIRVToLLVM::setName(ArrayRef<Value *> values, SPIRVValue *bv) {
const auto &name = bv->getName();
@@ -1334,7 +1422,7 @@ void SPIRVToLLVM::setFastMathFlags(Value *val) {
}
}
-Value *SPIRVToLLVM::transShiftLogicalBitwiseInst(SPIRVValue *bv, BasicBlock *bb, Function *f) {
+Value *SPIRVToLLVM::transBinaryShiftBitwiseInst(SPIRVValue *bv, BasicBlock *bb, Function *f) {
SPIRVBinary *bbn = static_cast<SPIRVBinary *>(bv);
assert(bb && "Invalid BB");
if (bbn->getOperand(0)->getType()->isTypeCooperativeMatrixKHR())
@@ -1464,7 +1552,7 @@ bool SPIRVToLLVM::postProcessRowMajorMatrix() {
SmallVector<Function *> functionsToRemove;
for (Function &func : m_m->functions()) {
- if (!func.getName().startswith(SpirvLaunderRowMajor))
+ if (!func.getName().starts_with(SpirvLaunderRowMajor))
continue;
// Remember to remove the function later.
@@ -1679,7 +1767,7 @@ bool SPIRVToLLVM::postProcessRowMajorMatrix() {
// don't add users to worklist
continue;
} else if (auto *const callInst = dyn_cast<CallInst>(inst)) {
- if (callInst->getCalledFunction()->getName().startswith(gSPIRVMD::NonUniform)) {
+ if (callInst->getCalledFunction()->getName().starts_with(gSPIRVMD::NonUniform)) {
// don't add users to worklist
continue;
}
@@ -1805,8 +1893,9 @@ Value *SPIRVToLLVM::addLoadInstRecursively(SPIRVType *const spvType, Value *load
Constant *const zero = getBuilder()->getInt32(0);
if (loadType->isStructTy() && !spvType->isTypeSampledImage() && !spvType->isTypeImage() &&
!spvType->isTypeSampler() && spvType->getOpCode() != OpTypeRayQueryKHR) {
+ // Rewrite this condition to keep consistent with the assert on getStructMemberCount later
// For structs we lookup the mapping of the elements and use it to reverse map the values.
- const bool needsPad = isRemappedTypeElements(spvType);
+ const bool needsPad = isTypeWithPad(loadType);
SmallVector<Value *, 8> memberLoads;
SmallVector<Type *, 8> memberTypes;
@@ -1847,6 +1936,7 @@ Value *SPIRVToLLVM::addLoadInstRecursively(SPIRVType *const spvType, Value *load
return load;
}
if (loadType->isArrayTy() && !spvType->isTypeVector() && !spvType->isTypeImage()) {
+ // Rewrite this condition to keep consistent with the assert on getArrayElementType/getMatrixColumnType later
// Matrix and arrays both get here. For both we need to turn [<{element-type, pad}>] into [element-type].
const bool needsPad = isTypeWithPad(loadType);
@@ -1889,8 +1979,8 @@ Value *SPIRVToLLVM::addLoadInstRecursively(SPIRVType *const spvType, Value *load
return load;
}
- Type *alignmentType = loadType;
+ Type *alignmentType = loadType;
// Vectors are represented as arrays in memory, so we need to cast the array to a vector before loading.
if (spvType->isTypeVector()) {
Type *const vectorType = transType(spvType, 0, false, true, LayoutMode::Native);
@@ -1904,8 +1994,8 @@ Value *SPIRVToLLVM::addLoadInstRecursively(SPIRVType *const spvType, Value *load
alignmentType = vectorType;
}
- LoadInst *const load = getBuilder()->CreateAlignedLoad(
- loadType, loadPointer, m_m->getDataLayout().getABITypeAlign(alignmentType), isVolatile);
+ LoadInst *load = getBuilder()->CreateAlignedLoad(loadType, loadPointer,
+ m_m->getDataLayout().getABITypeAlign(alignmentType), isVolatile);
if (isCoherent)
load->setAtomic(AtomicOrdering::Unordered);
@@ -1965,7 +2055,7 @@ void SPIRVToLLVM::addStoreInstRecursively(SPIRVType *const spvType, Value *store
if (storeType->isStructTy() && !spvType->isTypeSampledImage() && !spvType->isTypeImage() &&
!spvType->isTypeSampler() && spvType->getOpCode() != OpTypeRayQueryKHR) {
// For structs we lookup the mapping of the elements and use it to map the values.
- const bool needsPad = isRemappedTypeElements(spvType);
+ const bool needsPad = isTypeWithPad(storeType);
for (unsigned i = 0, memberCount = spvType->getStructMemberCount(); i < memberCount; i++) {
const unsigned memberIndex = needsPad ? lookupRemappedTypeElements(spvType, i) : i;
@@ -2011,15 +2101,15 @@ void SPIRVToLLVM::addStoreInstRecursively(SPIRVType *const spvType, Value *store
}
} else {
Type *alignmentType = storeType;
-
Type *storeType = nullptr;
// If the store was a bool or vector of bool, need to zext the storing value.
if (spvType->isTypeBool() || (spvType->isTypeVector() && spvType->getVectorComponentType()->isTypeBool())) {
storeValue = getBuilder()->CreateZExtOrBitCast(storeValue, alignmentType);
storeType = storeValue->getType();
- } else
- storeType = transType(spvType);
+ } else {
+ storeType = transType(spvType, 0, false, true, LayoutMode::Native);
+ }
// Vectors are represented as arrays in memory, so we need to cast the array to a vector before storing.
if (spvType->isTypeVector()) {
@@ -2027,7 +2117,6 @@ void SPIRVToLLVM::addStoreInstRecursively(SPIRVType *const spvType, Value *store
storePointer = getBuilder()->CreateBitCast(storePointer, castType);
const bool scalarBlockLayout = getPipelineOptions()->scalarBlockLayout;
-
if (!scalarBlockLayout)
alignmentType = storeType;
}
@@ -2060,7 +2149,7 @@ Constant *SPIRVToLLVM::buildConstStoreRecursively(SPIRVType *const spvType, Type
if (storeType->isStructTy() && spvType->getOpCode() != OpTypeSampledImage && spvType->getOpCode() != OpTypeImage) {
// For structs we lookup the mapping of the elements and use it to map the values.
- const bool needsPad = isRemappedTypeElements(spvType);
+ const bool needsPad = isTypeWithPad(storeType);
SmallVector<Constant *, 8> constMembers(storeType->getStructNumElements(), nullptr);
@@ -2213,7 +2302,9 @@ Value *SPIRVToLLVM::transAtomicRMW(SPIRVValue *const spvValue, const AtomicRMWIn
return getBuilder()->CreateBitCast(atomicRes, getBuilder()->getDoubleTy());
}
- return getBuilder()->CreateAtomicRMW(binOp, atomicPointer, atomicValue, MaybeAlign(), ordering, scope);
+ MaybeAlign align = MaybeAlign();
+
+ return getBuilder()->CreateAtomicRMW(binOp, atomicPointer, atomicValue, align, ordering, scope);
}
// =====================================================================================================================
@@ -2462,8 +2553,12 @@ template <> Value *SPIRVToLLVM::transValueWithOpcode<OpAtomicIIncrement>(SPIRVVa
Value *const atomicPointer = transValue(spvAtomicInst->getOpValue(0), getBuilder()->GetInsertBlock()->getParent(),
getBuilder()->GetInsertBlock());
- Value *const one = ConstantInt::get(transType(spvAtomicInst->getOpValue(0)->getType()->getPointerElementType()), 1);
+ SPIRVType *pointerType = spvAtomicInst->getOpValue(0)->getType();
+ SPIRVType *spvElementType = nullptr;
+ { spvElementType = pointerType->getPointerElementType(); }
+
+ Value *const one = ConstantInt::get(transType(spvElementType), 1);
return getBuilder()->CreateAtomicRMW(AtomicRMWInst::Add, atomicPointer, one, MaybeAlign(), ordering, scope);
}
@@ -2486,7 +2581,12 @@ template <> Value *SPIRVToLLVM::transValueWithOpcode<OpAtomicIDecrement>(SPIRVVa
Value *const atomicPointer = transValue(spvAtomicInst->getOpValue(0), getBuilder()->GetInsertBlock()->getParent(),
getBuilder()->GetInsertBlock());
- Value *const one = ConstantInt::get(transType(spvAtomicInst->getOpValue(0)->getType()->getPointerElementType()), 1);
+ SPIRVType *pointerType = spvAtomicInst->getOpValue(0)->getType();
+ SPIRVType *spvElementType = nullptr;
+
+ { spvElementType = pointerType->getPointerElementType(); }
+
+ Value *const one = ConstantInt::get(transType(spvElementType), 1);
return getBuilder()->CreateAtomicRMW(AtomicRMWInst::Sub, atomicPointer, one, MaybeAlign(), ordering, scope);
}
@@ -2586,36 +2686,51 @@ template <> Value *SPIRVToLLVM::transValueWithOpcode<OpCopyMemory>(SPIRVValue *c
if (spvCopyMemory->getMemoryAccessMask(false) & MemoryAccessNonPrivatePointerKHRMask)
isCoherent = true;
- bool isNonTemporal = spvCopyMemory->SPIRVMemoryAccess::isNonTemporal(true);
-
Value *const loadPointer = transValue(spvCopyMemory->getSource(), getBuilder()->GetInsertBlock()->getParent(),
getBuilder()->GetInsertBlock());
SPIRVType *const spvLoadType = spvCopyMemory->getSource()->getType();
+ SPIRVType *const spvStoreType = spvCopyMemory->getTarget()->getType();
+ SPIRVType *spvCopyMemLoadType = nullptr;
+ SPIRVType *spvCopyMemStoreType = nullptr;
+
+ if (spvLoadType->isTypePointer() && spvStoreType->isTypePointer()) {
+ spvCopyMemLoadType = spvLoadType->getPointerElementType();
+ spvCopyMemStoreType = spvStoreType->getPointerElementType();
+ }
LayoutMode loadLayout = isStorageClassExplicitlyLaidOut(m_bm, spvLoadType->getPointerStorageClass())
? LayoutMode::Explicit
: LayoutMode::Native;
-
- Type *const loadType = transType(spvLoadType->getPointerElementType(), 0, true, true, loadLayout);
-
- Value *const load = addLoadInstRecursively(spvLoadType->getPointerElementType(), loadPointer, loadType, isSrcVolatile,
- isCoherent, isNonTemporal);
+ Type *const loadType = transType(spvCopyMemLoadType, 0, true, true, loadLayout);
+ bool isNonTemporal = spvCopyMemory->SPIRVMemoryAccess::isNonTemporal(true);
+ Value *const load =
+ addLoadInstRecursively(spvCopyMemLoadType, loadPointer, loadType, isSrcVolatile, isCoherent, isNonTemporal);
Value *const storePointer = transValue(spvCopyMemory->getTarget(), getBuilder()->GetInsertBlock()->getParent(),
getBuilder()->GetInsertBlock());
- SPIRVType *const spvStoreType = spvCopyMemory->getTarget()->getType();
LayoutMode storeLayout = isStorageClassExplicitlyLaidOut(m_bm, spvStoreType->getPointerStorageClass())
? LayoutMode::Explicit
: LayoutMode::Native;
- Type *const storeType = transType(spvStoreType->getPointerElementType(), 0, true, true, storeLayout);
+
+ Type *const storeType = transType(spvCopyMemStoreType, 0, true, true, storeLayout);
isNonTemporal = spvCopyMemory->SPIRVMemoryAccess::isNonTemporal(false);
- addStoreInstRecursively(spvStoreType->getPointerElementType(), storePointer, storeType, load, isDestVolatile,
- isCoherent, isNonTemporal);
+ addStoreInstRecursively(spvCopyMemStoreType, storePointer, storeType, load, isDestVolatile, isCoherent,
+ isNonTemporal);
return nullptr;
}
+// =====================================================================================================================
+// Handle OpCopyMemorySized.
+//
+// @param spvValue : A SPIR-V value.
+template <> Value *SPIRVToLLVM::transValueWithOpcode<OpCopyMemorySized>(SPIRVValue *const spvValue) {
+ // Just map OpCopyMemorySized into OpCopyMemory
+ // To do
+ return transValueWithOpcode<OpCopyMemory>(spvValue);
+}
+
// =====================================================================================================================
// Handle OpLoad.
//
@@ -2624,8 +2739,9 @@ template <> Value *SPIRVToLLVM::transValueWithOpcode<OpLoad>(SPIRVValue *const s
SPIRVLoad *const spvLoad = static_cast<SPIRVLoad *>(spvValue);
LayoutMode layout = LayoutMode::Native;
+ const auto storageClassKind = spvLoad->getSrc()->getType()->getPointerStorageClass();
// Handle UniformConstant image/sampler/sampledimage load.
- if (static_cast<SPIRVTypePointer *>(spvLoad->getSrc()->getType())->getStorageClass() == StorageClassUniformConstant) {
+ if (storageClassKind == StorageClassUniformConstant) {
switch (spvLoad->getType()->getOpCode()) {
case OpTypeImage:
case OpTypeSampler:
@@ -2706,11 +2822,13 @@ template <> Value *SPIRVToLLVM::transValueWithOpcode<OpLoad>(SPIRVValue *const s
Instruction *baseNode = getLastInsertedValue();
BasicBlock *currentBlock = getBuilder()->GetInsertBlock();
-
- Type *loadType = getPointeeType(spvLoad->getSrc(), layout);
-
- auto loadInst = addLoadInstRecursively(spvLoadType->getPointerElementType(), loadPointer, loadType, isVolatile,
- isCoherent, isNonTemporal);
+ Type *loadType = nullptr;
+ SPIRVType *spvElemType = nullptr;
+ {
+ spvElemType = spvLoadType->getPointerElementType();
+ loadType = getPointeeType(spvLoad->getSrc(), layout);
+ }
+ Value *loadInst = addLoadInstRecursively(spvElemType, loadPointer, loadType, isVolatile, isCoherent, isNonTemporal);
// Record all load instructions inserted by addLoadInstRecursively.
if (m_scratchBoundsChecksEnabled) {
@@ -2813,10 +2931,17 @@ Value *SPIRVToLLVM::loadImageSampler(Type *elementTy, Value *base) {
// Translate image/sampler/sampledimage pointer to IR value
//
// @param spvImagePtr : The image/sampler/sampledimage pointer
-Value *SPIRVToLLVM::transImagePointer(SPIRVValue *spvImagePtr) {
+Value *SPIRVToLLVM::transImagePointer(SPIRVValue *spvImagePtr, SPIRVType *baseTy) {
+
if (spvImagePtr->getOpCode() != OpVariable ||
- static_cast<SPIRVTypePointer *>(spvImagePtr->getType())->getStorageClass() != StorageClassUniformConstant)
- return transValue(spvImagePtr, getBuilder()->GetInsertBlock()->getParent(), getBuilder()->GetInsertBlock());
+ static_cast<SPIRVTypePointer *>(spvImagePtr->getType())->getStorageClass() != StorageClassUniformConstant) {
+ Value *v = transValue(spvImagePtr, getBuilder()->GetInsertBlock()->getParent(), getBuilder()->GetInsertBlock());
+
+ // For function parameter, if it translated to an pointer type, then, it's a struct with sampler type, we should not
+ // return it.
+ if (!(spvImagePtr->getOpCode() == OpFunctionParameter && v->getType()->isPointerTy()))
+ return v;
+ }
// For an image/sampler/sampledimage pointer that is a UniformConstant OpVariable, we need to materialize it by
// generating the code to get the descriptor pointer(s).
@@ -3040,9 +3165,13 @@ template <> Value *SPIRVToLLVM::transValueWithOpcode<OpStore>(SPIRVValue *const
transValue(spvStore->getSrc(), getBuilder()->GetInsertBlock()->getParent(), getBuilder()->GetInsertBlock());
SPIRVType *const spvStoreType = spvStore->getDst()->getType();
- SPIRVType *pointerElementType = spvStoreType->getPointerElementType();
+ SPIRVType *pointerElementType = nullptr;
+ Type *storeType = nullptr;
- Type *storeType = getPointeeType(spvStore->getDst());
+ {
+ pointerElementType = spvStoreType->getPointerElementType();
+ storeType = getPointeeType(spvStore->getDst());
+ }
Instruction *baseNode = getLastInsertedValue();
BasicBlock *currentBlock = getBuilder()->GetInsertBlock();
@@ -3082,24 +3211,28 @@ template <> Value *SPIRVToLLVM::transValueWithOpcode<OpEndStreamPrimitive>(SPIRV
// Handle OpArrayLength.
//
// @param spvValue : A SPIR-V value.
-template <> Value *SPIRVToLLVM::transValueWithOpcode<OpArrayLength>(SPIRVValue *const spvValue) {
- SPIRVArrayLength *const spvArrayLength = static_cast<SPIRVArrayLength *>(spvValue);
- SPIRVValue *const spvStruct = spvArrayLength->getStruct();
- assert(spvStruct->getType()->isTypePointer());
+Value *SPIRVToLLVM::transArrayLength(SPIRVValue *const spvValue) {
+ SPIRVValue *spvStruct = nullptr;
+ StructType *structType = nullptr;
+ unsigned memberIndex = 0;
+ unsigned remappedMemberIndex = 0;
- Value *const structure =
- transValue(spvStruct, getBuilder()->GetInsertBlock()->getParent(), getBuilder()->GetInsertBlock());
- assert(structure->getType()->isPointerTy());
+ {
+ assert(spvValue->getOpCode() == OpArrayLength);
+ spvStruct = static_cast<SPIRVArrayLength *>(spvValue)->getStruct();
+ assert(spvStruct->getType()->isTypePointer());
+ memberIndex = static_cast<SPIRVArrayLength *>(spvValue)->getMemberIndex();
+ remappedMemberIndex = lookupRemappedTypeElements(spvStruct->getType()->getPointerElementType(), memberIndex);
+ structType = cast<StructType>(getPointeeType(spvStruct));
+ }
- const unsigned memberIndex = spvArrayLength->getMemberIndex();
- const unsigned remappedMemberIndex =
- lookupRemappedTypeElements(spvStruct->getType()->getPointerElementType(), memberIndex);
+ Value *const structurePtr =
+ transValue(spvStruct, getBuilder()->GetInsertBlock()->getParent(), getBuilder()->GetInsertBlock());
- StructType *const structType = cast<StructType>(getPointeeType(spvStruct));
const StructLayout *const structLayout = m_m->getDataLayout().getStructLayout(structType);
const unsigned offset = static_cast<unsigned>(structLayout->getElementOffset(remappedMemberIndex));
Value *const offsetVal = getBuilder()->getInt32(offset);
- Value *const arrayBytes = getBuilder()->create<BufferLengthOp>(structure, offsetVal);
+ Value *const arrayBytes = getBuilder()->create<BufferLengthOp>(structurePtr, offsetVal);
Type *const memberType = structType->getStructElementType(remappedMemberIndex)->getArrayElementType();
const unsigned stride = static_cast<unsigned>(m_m->getDataLayout().getTypeSizeInBits(memberType) / 8);
@@ -3108,17 +3241,46 @@ template <> Value *SPIRVToLLVM::transValueWithOpcode<OpArrayLength>(SPIRVValue *
}
// =====================================================================================================================
-// Handle OpAccessChain.
+// Handle OpArrayLength.
//
// @param spvValue : A SPIR-V value.
-template <> Value *SPIRVToLLVM::transValueWithOpcode<OpAccessChain>(SPIRVValue *const spvValue) {
- SPIRVAccessChainBase *const spvAccessChain = static_cast<SPIRVAccessChainBase *>(spvValue);
+template <> Value *SPIRVToLLVM::transValueWithOpcode<OpArrayLength>(SPIRVValue *const spvValue) {
+ return transArrayLength(spvValue);
+}
+
+// =====================================================================================================================
+// Handle OpAccessChain/OpUntypeAccessChainKHR.
+//
+// @param spvValue : A SPIR-V value.
+SmallVector<Value *> SPIRVToLLVM::transAccessChain(SPIRVValue *const spvValue) {
+ SPIRVType *baseType = nullptr;
+ SPIRVType *spvAccessType = nullptr;
+ SPIRVStorageClassKind storageClass = StorageClassMax;
+ SPIRVValue *baseValue = nullptr;
+ std::vector<SPIRVValue *> indices;
+ bool inBound = false;
+ bool hasPtrIndex = false;
+
+ {
+ assert((spvValue->getOpCode() == OpAccessChain) || (spvValue->getOpCode() == OpInBoundsAccessChain) ||
+ (spvValue->getOpCode() == OpPtrAccessChain) || (spvValue->getOpCode() == OpInBoundsPtrAccessChain));
+ auto spvAccessChain = static_cast<SPIRVAccessChainBase *>(spvValue);
+ baseType = spvAccessChain->getBase()->getType();
+ spvAccessType = spvAccessChain->getBase()->getType()->getPointerElementType();
+ baseValue = spvAccessChain->getBase();
+ indices = spvAccessChain->getIndices();
+ hasPtrIndex = spvAccessChain->hasPtrIndex();
+ inBound = spvAccessChain->isInBounds();
+ }
+
+ if (baseType->isTypePointer() || baseType->isTypeForwardPointer()) {
+ storageClass = static_cast<SPIRVTypePointer *>(baseType)->getStorageClass();
+ }
LayoutMode layout = LayoutMode::Native;
// Special handling for UniformConstant if the ultimate element type is image/sampler/sampledimage.
- if (static_cast<SPIRVTypePointer *>(spvAccessChain->getBase()->getType())->getStorageClass() ==
- StorageClassUniformConstant) {
- SPIRVType *spvUltimateElementType = spvAccessChain->getBase()->getType()->getPointerElementType();
+ if (storageClass == StorageClassUniformConstant) {
+ SPIRVType *spvUltimateElementType = spvAccessType;
while (spvUltimateElementType->getOpCode() == OpTypeArray ||
spvUltimateElementType->getOpCode() == OpTypeRuntimeArray)
spvUltimateElementType = spvUltimateElementType->getArrayElementType();
@@ -3127,7 +3289,7 @@ template <> Value *SPIRVToLLVM::transValueWithOpcode<OpAccessChain>(SPIRVValue *
case OpTypeImage:
case OpTypeSampler:
case OpTypeSampledImage:
- return transOpAccessChainForImage(spvAccessChain);
+ return {transOpAccessChainForImage(static_cast<SPIRVAccessChainBase *>(spvValue))};
default:
layout = isAccelerationStructureType(spvUltimateElementType) ? LayoutMode::Explicit : LayoutMode::Std430;
break;
@@ -3135,30 +3297,32 @@ template <> Value *SPIRVToLLVM::transValueWithOpcode<OpAccessChain>(SPIRVValue *
}
// Non-image-related handling.
- Value *base = transValue(spvAccessChain->getBase(), getBuilder()->GetInsertBlock()->getParent(),
- getBuilder()->GetInsertBlock());
- auto srcIndices = transValue(spvAccessChain->getIndices(), getBuilder()->GetInsertBlock()->getParent(),
- getBuilder()->GetInsertBlock());
+ Value *base = transValue(baseValue, getBuilder()->GetInsertBlock()->getParent(), getBuilder()->GetInsertBlock());
+ auto srcIndices = transValue(indices, getBuilder()->GetInsertBlock()->getParent(), getBuilder()->GetInsertBlock());
truncConstantIndex(srcIndices, getBuilder()->GetInsertBlock());
- if (!spvAccessChain->hasPtrIndex())
+ if (!hasPtrIndex)
srcIndices.insert(srcIndices.begin(), getBuilder()->getInt32(0));
- SPIRVType *spvAccessType = spvAccessChain->getBase()->getType();
- const SPIRVStorageClassKind storageClass = spvAccessType->getPointerStorageClass();
+ const SPIRVStorageClassKind pointerStorageClass = baseType->getPointerStorageClass();
+
const bool typeMaybeRemapped =
- isStorageClassExplicitlyLaidOut(m_bm, storageClass) || storageClass == StorageClassUniformConstant;
+ isStorageClassExplicitlyLaidOut(m_bm, pointerStorageClass) || pointerStorageClass == StorageClassUniformConstant;
- Type *basePointeeType = getPointeeType(spvAccessChain->getBase(), layout);
+ Type *basePointeeType = nullptr;
+ { basePointeeType = getPointeeType(baseValue, layout); }
SmallVector<Value *, 8> gepIndices;
- if (spvAccessType->isTypeForwardPointer())
- spvAccessType = static_cast<SPIRVTypeForwardPointer *>(spvAccessType)->getPointer();
- assert(spvAccessType->isTypePointer());
+ if (baseType->isTypeForwardPointer()) {
+ baseType = static_cast<SPIRVTypeForwardPointer *>(baseType)->getPointer();
+ }
+ assert(baseType->isTypePointer());
gepIndices.push_back(srcIndices[0]);
- spvAccessType = spvAccessType->getPointerElementType();
+
+ if (baseType->isTypePointer())
+ spvAccessType = baseType->getPointerElementType();
auto flushGep = [&]() {
if (gepIndices.size() == 1) {
@@ -3168,7 +3332,7 @@ template <> Value *SPIRVToLLVM::transValueWithOpcode<OpAccessChain>(SPIRVValue *
}
}
- if (spvAccessChain->isInBounds())
+ if (inBound)
base = getBuilder()->CreateInBoundsGEP(basePointeeType, base, gepIndices);
else
base = getBuilder()->CreateGEP(basePointeeType, base, gepIndices);
@@ -3287,14 +3451,22 @@ template <> Value *SPIRVToLLVM::transValueWithOpcode<OpAccessChain>(SPIRVValue *
Type *finalPointeeType = GetElementPtrInst::getIndexedType(basePointeeType, gepIndices);
flushGep();
- tryAddAccessChainRetType(spvAccessChain, finalPointeeType);
- return base;
+ tryAddAccessChainRetType(spvValue, finalPointeeType);
+ return {base};
+}
+
+// =====================================================================================================================
+// Handle OpAccessChain.
+//
+// @param spvValue : A SPIR-V value.
+template <> SmallVector<Value *> SPIRVToLLVM::transValueMultiWithOpcode<OpAccessChain>(SPIRVValue *const spvValue) {
+ return transAccessChain(spvValue);
}
// =====================================================================================================================
-// Handle OpAccessChain for pointer to (array of) image/sampler/sampledimage
+// Handle OpAccessChain/OpUntypedAccessChain for pointer to (array of) image/sampler/sampledimage
//
-// @param spvAccessChain : The OpAccessChain
+// @param spvValue : The spvValue
Value *SPIRVToLLVM::transOpAccessChainForImage(SPIRVAccessChainBase *spvAccessChain) {
SPIRVType *spvElementType = spvAccessChain->getBase()->getType()->getPointerElementType();
std::vector<SPIRVValue *> spvIndicesVec = spvAccessChain->getIndices();
@@ -3382,24 +3554,26 @@ Value *SPIRVToLLVM::indexDescPtr(Type *elementTy, Value *base, Value *index) {
// Handle OpInBoundsAccessChain.
//
// @param spvValue : A SPIR-V value.
-template <> Value *SPIRVToLLVM::transValueWithOpcode<OpInBoundsAccessChain>(SPIRVValue *const spvValue) {
- return transValueWithOpcode<OpAccessChain>(spvValue);
+template <>
+SmallVector<Value *> SPIRVToLLVM::transValueMultiWithOpcode<OpInBoundsAccessChain>(SPIRVValue *const spvValue) {
+ return transAccessChain(spvValue);
}
// =====================================================================================================================
// Handle OpPtrAccessChain.
//
// @param spvValue : A SPIR-V value.
-template <> Value *SPIRVToLLVM::transValueWithOpcode<OpPtrAccessChain>(SPIRVValue *const spvValue) {
- return transValueWithOpcode<OpAccessChain>(spvValue);
+template <> SmallVector<Value *> SPIRVToLLVM::transValueMultiWithOpcode<OpPtrAccessChain>(SPIRVValue *const spvValue) {
+ return transAccessChain(spvValue);
}
// =====================================================================================================================
// Handle OpInBoundsPtrAccessChain.
//
// @param spvValue : A SPIR-V value.
-template <> Value *SPIRVToLLVM::transValueWithOpcode<OpInBoundsPtrAccessChain>(SPIRVValue *const spvValue) {
- return transValueWithOpcode<OpAccessChain>(spvValue);
+template <>
+SmallVector<Value *> SPIRVToLLVM::transValueMultiWithOpcode<OpInBoundsPtrAccessChain>(SPIRVValue *const spvValue) {
+ return transAccessChain(spvValue);
}
// =====================================================================================================================
@@ -4532,13 +4706,19 @@ Constant *SPIRVToLLVM::transInitializer(SPIRVValue *const spvValue, Type *const
//
// @param spvValue : A SPIR-V value.
template <> Value *SPIRVToLLVM::transValueWithOpcode<OpVariable>(SPIRVValue *const spvValue) {
- SPIRVVariable *const spvVar = static_cast<SPIRVVariable *>(spvValue);
+ return transVariable(spvValue);
+}
+
+// =====================================================================================================================
+// Handle OpVariable/OpUntypedVariableKHR.
+//
+// @param spvValue : A SPIR-V value.
+Value *SPIRVToLLVM::transVariable(SPIRVValue *const spvValue) {
+ auto spvVar = static_cast<SPIRVBaseVariable *>(spvValue);
const SPIRVStorageClassKind storageClass = spvVar->getStorageClass();
- SPIRVType *const spvVarType = spvVar->getType()->getPointerElementType();
+ SPIRVType *spvVarType = spvVar->getMemObjType();
- LayoutMode layout = isStorageClassExplicitlyLaidOut(m_bm, spvVar->getType()->getPointerStorageClass())
- ? LayoutMode::Explicit
- : LayoutMode::Native;
+ LayoutMode layout = isStorageClassExplicitlyLaidOut(m_bm, storageClass) ? LayoutMode::Explicit : LayoutMode::Native;
if (storageClass == StorageClassUniformConstant) {
SPIRVType *spvElementType = spvVarType;
while (spvElementType->getOpCode() == OpTypeArray || spvElementType->getOpCode() == OpTypeRuntimeArray)
@@ -4559,10 +4739,9 @@ template <> Value *SPIRVToLLVM::transValueWithOpcode<OpVariable>(SPIRVValue *con
Type *const ptrType = transType(spvVar->getType());
unsigned addrSpace = ptrType->getPointerAddressSpace();
- Type *const varType = transType(spvVar->getType()->getPointerElementType(), 0, true, true, layout);
+ Type *const varType = transType(spvVarType, 0, true, true, layout);
SPIRVValue *const spvInitializer = spvVar->getInitializer();
-
Constant *initializer = nullptr;
// If the type has an initializer, re-create the SPIR-V initializer in LLVM.
@@ -6085,8 +6264,10 @@ SmallVector<Value *> SPIRVToLLVM::transValueWithoutDecoration(SPIRVValue *bv, Fu
transValue(bi->getOpValue(0), getBuilder()->GetInsertBlock()->getParent(), getBuilder()->GetInsertBlock());
Value *const op2 =
transValue(bi->getOpValue(1), getBuilder()->GetInsertBlock()->getParent(), getBuilder()->GetInsertBlock());
- Type *ty = transType(bi->getOpValue(0)->getType()->getPointerElementType());
+ Type *ty = nullptr;
+ SPIRVType *ptrTy = bi->getOpValue(0)->getType();
+ { ty = transType(ptrTy->getPointerElementType()); }
Value *ptrDiff = getBuilder()->CreatePtrDiff(ty, op1, op2);
auto destType = cast<IntegerType>(transType(bv->getType()));
@@ -6136,6 +6317,8 @@ SmallVector<Value *> SPIRVToLLVM::transValueWithoutDecoration(SPIRVValue *bv, Fu
return mapValue(bv, transValueWithOpcode<OpAtomicFAddEXT>(bv));
case OpCopyMemory:
return mapValue(bv, transValueWithOpcode<OpCopyMemory>(bv));
+ case OpCopyMemorySized:
+ return mapValue(bv, transValueWithOpcode<OpCopyMemorySized>(bv));
case OpLoad:
return mapValue(bv, transValueWithOpcode<OpLoad>(bv));
case OpStore:
@@ -6145,15 +6328,15 @@ SmallVector<Value *> SPIRVToLLVM::transValueWithoutDecoration(SPIRVValue *bv, Fu
case OpEndStreamPrimitive:
return mapValue(bv, transValueWithOpcode<OpEndStreamPrimitive>(bv));
case OpAccessChain:
- return mapValue(bv, transValueWithOpcode<OpAccessChain>(bv));
+ return mapValue(bv, transValueMultiWithOpcode<OpAccessChain>(bv));
case OpArrayLength:
return mapValue(bv, transValueWithOpcode<OpArrayLength>(bv));
case OpInBoundsAccessChain:
- return mapValue(bv, transValueWithOpcode<OpInBoundsAccessChain>(bv));
+ return mapValue(bv, transValueMultiWithOpcode<OpInBoundsAccessChain>(bv));
case OpPtrAccessChain:
- return mapValue(bv, transValueWithOpcode<OpPtrAccessChain>(bv));
+ return mapValue(bv, transValueMultiWithOpcode<OpPtrAccessChain>(bv));
case OpInBoundsPtrAccessChain:
- return mapValue(bv, transValueWithOpcode<OpInBoundsPtrAccessChain>(bv));
+ return mapValue(bv, transValueMultiWithOpcode<OpInBoundsPtrAccessChain>(bv));
case OpImage:
return mapValue(bv, transValueWithOpcode<OpImage>(bv));
case OpSampledImage:
@@ -6338,14 +6521,12 @@ SmallVector<Value *> SPIRVToLLVM::transValueWithoutDecoration(SPIRVValue *bv, Fu
return mapValue(bv, transValueWithOpcode<OpCooperativeMatrixMulAddKHR>(bv));
default: {
auto oc = bv->getOpCode();
- if (isSPIRVCmpInstTransToLLVMInst(static_cast<SPIRVInstruction *>(bv)))
+ if (isCmpOpCode(oc))
return mapValue(bv, transCmpInst(bv, bb, f));
- if (isBinaryShiftLogicalBitwiseOpCode(oc) || isLogicalOpCode(oc))
- return mapValue(bv, transShiftLogicalBitwiseInst(bv, bb, f));
- if (isCvtOpCode(oc)) {
- Value *inst = transConvertInst(bv, f, bb);
- return mapValue(bv, inst);
- }
+ if (isBinaryShiftBitwiseOpCode(oc) || isLogicalOpCode(oc))
+ return mapValue(bv, transBinaryShiftBitwiseInst(bv, bb, f));
+ if (isCvtOpCode(oc))
+ return mapValue(bv, transConvertInst(bv, f, bb));
return mapValue(bv, transSPIRVBuiltinFromInst(static_cast<SPIRVInstruction *>(bv), bb));
}
}
@@ -6471,12 +6652,28 @@ Function *SPIRVToLLVM::transFunction(SPIRVFunction *bf) {
m_blockPredecessorToCount.clear();
- // Special handling for GPURT intrinsic function _AmdContStackStore* to rescue the stored pointee type
- if (f->getName().startswith("_AmdContStackStore")) {
- assert(f->arg_size() == 2);
- Type *pointeeType = getPointeeType(bf->getArgument(1));
- Metadata *MD = ConstantAsMetadata::get(PoisonValue::get(pointeeType));
- f->setMetadata(gSPIRVMD::ContStackStoreType, MDNode::get(*m_context, MD));
+ auto getContArgTy = [&](SPIRVType *argTy) {
+ if (argTy->isTypePointer()) {
+ auto storageClass = argTy->getPointerStorageClass();
+ const unsigned addrSpace = SPIRSPIRVAddrSpaceMap::rmap(storageClass);
+ Type *pointeeType = transType(argTy->getPointerElementType());
+ Type *ptrTy = PointerType::get(*m_context, addrSpace);
+ return ContArgTy(ptrTy, pointeeType);
+ }
+ return ContArgTy(transType(argTy));
+ };
+
+ // Special handling for GPURT intrinsic function _Amd* and _cont_
+ if (f->getName().starts_with("_Amd") || f->getName().starts_with("_cont_")) {
+ SmallVector<ContArgTy> argTys;
+
+ for (unsigned i = 0; i < bf->getNumArguments(); ++i) {
+ auto argTy = bf->getArgument(i)->getType();
+ argTys.push_back(getContArgTy(argTy));
+ }
+
+ ContFuncTy funcTys(getContArgTy(bf->getType()), argTys);
+ funcTys.writeMetadata(f);
}
return f;
@@ -6674,7 +6871,7 @@ void SPIRVToLLVM::getImageDesc(SPIRVValue *bImageInst, ExtractedImageInfo *info)
// Extract image descriptor from possible array of multi-plane image descriptors.
info->imageDesc = getBuilder()->CreateExtractValue(info->imageDesc, 0);
}
- // We also need to trace back to the OpVariable or OpFunctionParam to find
+ // We also need to trace back to the OpVariable/OpUntypedVariableKHR or OpFunctionParam to find
// the coherent and volatile decorations.
SPIRVValue *imageAccessChain = nullptr;
while (bImagePtr->getOpCode() == OpAccessChain || bImagePtr->getOpCode() == OpInBoundsAccessChain) {
@@ -7830,7 +8027,7 @@ bool SPIRVToLLVM::translate(ExecutionModel entryExecModel, const char *entryName
pipelineContext->getPipelineType() == PipelineType::RayTracing ? subgroupSizeUsage : shaderMode.useSubgroupSize;
if (pipelineContext->getPipelineType() == PipelineType::Graphics && subgroupSizeUsage) {
- for (lgc::ShaderStage stage : lgc::enumRange<lgc::ShaderStage>()) {
+ for (lgc::ShaderStageEnum stage : lgc::enumRange<lgc::ShaderStageEnum>()) {
if (subgroupSizeUsage & (1 << stage)) {
Pipeline::setSubgroupSizeUsage(*m_m, stage, true);
}
@@ -7838,28 +8035,28 @@ bool SPIRVToLLVM::translate(ExecutionModel entryExecModel, const char *entryName
}
// Figure out the LGC shader stage so we can use it in the setCommonShaderMode call.
- lgc::ShaderStage shaderStage = lgc::ShaderStageCompute;
+ lgc::ShaderStageEnum shaderStage = lgc::ShaderStage::Compute;
switch (entryExecModel) {
case ExecutionModelTaskEXT:
- shaderStage = lgc::ShaderStageTask;
+ shaderStage = lgc::ShaderStage::Task;
break;
case ExecutionModelVertex:
- shaderStage = lgc::ShaderStageVertex;
+ shaderStage = lgc::ShaderStage::Vertex;
break;
case ExecutionModelTessellationControl:
- shaderStage = lgc::ShaderStageTessControl;
+ shaderStage = lgc::ShaderStage::TessControl;
break;
case ExecutionModelTessellationEvaluation:
- shaderStage = lgc::ShaderStageTessEval;
+ shaderStage = lgc::ShaderStage::TessEval;
break;
case ExecutionModelGeometry:
- shaderStage = lgc::ShaderStageGeometry;
+ shaderStage = lgc::ShaderStage::Geometry;
break;
case ExecutionModelMeshEXT:
- shaderStage = lgc::ShaderStageMesh;
+ shaderStage = lgc::ShaderStage::Mesh;
break;
case ExecutionModelFragment:
- shaderStage = lgc::ShaderStageFragment;
+ shaderStage = lgc::ShaderStage::Fragment;
break;
default:
break;
@@ -8038,8 +8235,8 @@ bool SPIRVToLLVM::transMetadata() {
if (auto em = bf->getExecutionMode(ExecutionModeOutputVertices))
tessellationMode.outputVertices = em->getLiterals()[0];
- lgc::ShaderStage shaderStage =
- execModel == ExecutionModelTessellationControl ? lgc::ShaderStageTessControl : lgc::ShaderStageTessEval;
+ lgc::ShaderStageEnum shaderStage =
+ execModel == ExecutionModelTessellationControl ? lgc::ShaderStage::TessControl : lgc::ShaderStage::TessEval;
Pipeline::setTessellationMode(*m_m, shaderStage, tessellationMode);
} else if (execModel == ExecutionModelGeometry) {
@@ -8290,9 +8487,9 @@ bool SPIRVToLLVM::transDecoration(SPIRVValue *bv, ArrayRef<Value *> values) {
// Some SPIR-V instructions (e.g. OpAccessChain) can become no-ops in LLVM IR,
// so we must explicitly check both the SPIR-V opcode and the LLVM type.
if (gv && bv->getOpCode() == OpVariable) {
+ auto spvTy = static_cast<SPIRVBaseVariable *>(bv)->getMemObjType();
auto as = gv->getType()->getAddressSpace();
- auto spvTy = bv->getType()->getPointerElementType();
while (spvTy->getOpCode() == OpTypeArray || spvTy->getOpCode() == OpTypeRuntimeArray)
spvTy = spvTy->getArrayElementType();
if (isAccelerationStructureType(spvTy)) {
@@ -8430,7 +8627,7 @@ bool SPIRVToLLVM::transDecoration(SPIRVValue *bv, ArrayRef<Value *> values) {
} else if (as == SPIRAS_Uniform) {
// Translate decorations of blocks
- SPIRVType *blockTy = bv->getType()->getPointerElementType();
+ SPIRVType *blockTy = static_cast<SPIRVBaseVariable *>(bv)->getMemObjType();
// If not task payload, try to remove block array dimensions. Note that task
// payload doesn't have such dimensions.
if (bv->getType()->getPointerStorageClass() != StorageClassTaskPayloadWorkgroupEXT) {
@@ -8535,10 +8732,11 @@ bool SPIRVToLLVM::transDecoration(SPIRVValue *bv, ArrayRef<Value *> values) {
auto mdNode = MDNode::get(*m_context, mDs);
gv->addMetadata(gSPIRVMD::UniformConstant, *mdNode);
}
- } else if (bv->getType()->isTypePointer() && bv->getType()->getPointerStorageClass() == StorageClassPushConstant) {
+ } else if ((bv->getType()->isTypePointer()) &&
+ bv->getType()->getPointerStorageClass() == StorageClassPushConstant) {
// Translate decorations of push constants
- SPIRVType *pushConstTy = bv->getType()->getPointerElementType();
+ SPIRVType *pushConstTy = static_cast<SPIRVBaseVariable *>(bv)->getMemObjType();
assert(pushConstTy->isTypeStruct());
// Build push constant specific metadata
@@ -9913,8 +10111,7 @@ Instruction *SPIRVToLLVM::transBarrierFence(SPIRVInstruction *mb, BasicBlock *bb
llvm::GlobalValue::LinkageTypes SPIRVToLLVM::transLinkageType(const SPIRVValue *v) {
if (v->getLinkageType() == LinkageTypeInternal) {
if (v->getOpCode() == OpVariable) {
- // Variable declaration
- SPIRVStorageClassKind storageClass = static_cast<const SPIRVVariable *>(v)->getStorageClass();
+ SPIRVStorageClassKind storageClass = static_cast<const SPIRVBaseVariable *>(v)->getStorageClass();
if (storageClass == StorageClassUniformConstant || storageClass == StorageClassInput ||
storageClass == StorageClassUniform || storageClass == StorageClassPushConstant ||
storageClass == StorageClassStorageBuffer || storageClass == StorageClassAtomicCounter)
@@ -9940,7 +10137,7 @@ llvm::GlobalValue::LinkageTypes SPIRVToLLVM::transLinkageType(const SPIRVValue *
}
// LinkageTypeExport
if (v->getOpCode() == OpVariable) {
- if (static_cast<const SPIRVVariable *>(v)->getInitializer() == 0)
+ if (static_cast<const SPIRVBaseVariable *>(v)->getInitializer() == 0)
// Tentative definition
return GlobalValue::CommonLinkage;
}
@@ -9986,6 +10183,7 @@ bool SPIRVToLLVM::shouldInsertScratchBoundsCheck(SPIRVValue *memOp, SPIRVToLLVM:
assert(m_scratchBoundsChecksEnabled);
const auto accessChain = deriveAccessChain(memOp, instructionType);
+
if (!accessChain || accessChain->getOpCode() != OpAccessChain)
return false;
@@ -10235,13 +10433,25 @@ void SPIRVToLLVM::createXfbMetadata(bool hasXfbOuts) {
SPIRVWord xfbBuffer = InvalidValue;
// NOTE: XFbBuffer may be decorated on the pointer element
SPIRVType *pointerElemTy = bv->getType()->getPointerElementType();
+ while (pointerElemTy->isTypeArray())
+ pointerElemTy = pointerElemTy->getArrayElementType();
SPIRVEntry *entries[2] = {bv, pointerElemTy};
unsigned memberCount = 0;
if (pointerElemTy->isTypeStruct())
memberCount = pointerElemTy->getStructMemberCount();
+
+ // If a variable has xfb_buffer assigned to them but without xfb_offset, This does nothing and will be
+ // ignored. For struct type, the Offset will be assigned in the element member of the struct, not the struct
+ // type itself. So, need to travels every element member of the struct, to check if they has Offset decoration
+ bool hasXfbOffset = bv->hasDecorate(DecorationOffset, 0, nullptr);
+ for (unsigned i = 0; i < memberCount && !hasXfbOffset; ++i)
+ hasXfbOffset |= pointerElemTy->hasMemberDecorate(i, DecorationOffset, 0, nullptr);
+ if (!hasXfbOffset)
+ continue;
+
for (unsigned id = 0; id < 2; ++id) {
auto entry = entries[id];
- if (entry->hasDecorate(DecorationXfbBuffer, 0, &xfbBuffer)) {
+ if (entry->hasDecorate(DecorationXfbBuffer, 0, &xfbBuffer) && hasXfbOffset) {
const unsigned indexOfBuffer = 2 * xfbBuffer;
xfbState[indexOfBuffer] = 0;
SPIRVWord streamId = InvalidValue;
@@ -10255,7 +10465,8 @@ void SPIRVToLLVM::createXfbMetadata(bool hasXfbOuts) {
}
} else if (id == 1) {
for (unsigned i = 0; i < memberCount; ++i) {
- if (entry->hasMemberDecorate(i, DecorationXfbBuffer, 0, &xfbBuffer)) {
+ if (entry->hasMemberDecorate(i, DecorationXfbBuffer, 0, &xfbBuffer) &&
+ entry->hasMemberDecorate(i, DecorationOffset, 0, nullptr)) {
const unsigned indexOfBuffer = 2 * xfbBuffer;
xfbState[indexOfBuffer] = 0;
SPIRVWord streamId = InvalidValue;
@@ -10425,44 +10636,12 @@ Value *SPIRVToLLVM::transCooperativeMatrixArithInst(SPIRVValue *spvVal, BasicBlo
// Translate cooperative matrix construction instructions to LLVM IR
Value *SPIRVToLLVM::transCooperativeMatrixKHRFromConstruct(SPIRVType *spvCoopMatTy,
const std::vector<Value *> &constituents) {
- auto vecTy = transType(spvCoopMatTy);
- Value *matrixResult = PoisonValue::get(vecTy);
- unsigned subElemNums = 0;
- unsigned elemNums = 0;
- lgc::Builder::CooperativeMatrixElementType componentType =
+ lgc::Builder::CooperativeMatrixElementType elemType =
mapToBasicType(spvCoopMatTy->getCooperativeMatrixKHRComponentType());
- unsigned duplicateFoldFactor = 1;
-
- switch (componentType) {
- case lgc::Builder::CooperativeMatrixElementType::Int8: // A/B
- subElemNums = 4;
- elemNums = 4 / duplicateFoldFactor;
- break;
- case lgc::Builder::CooperativeMatrixElementType::Int32: // C/D
- case lgc::Builder::CooperativeMatrixElementType::Float32:
- subElemNums = 1;
- elemNums = 8; // label:changewaveSize
- break;
- case lgc::Builder::CooperativeMatrixElementType::Int16: // A/B
- case lgc::Builder::CooperativeMatrixElementType::Float16:
- subElemNums = 2;
- elemNums = 8 / duplicateFoldFactor;
- break;
- default:
- llvm_unreachable("The component type is not be supported.");
- }
-
- for (unsigned idx = 0; idx < elemNums; ++idx) {
- Type *subElemTy = transType(spvCoopMatTy->getCooperativeMatrixKHRComponentType());
- Type *subVecTy = FixedVectorType::get(subElemTy, subElemNums);
- Value *elem = PoisonValue::get(subVecTy);
- for (unsigned subIdx = 0; subIdx < subElemNums; ++subIdx)
- elem = getBuilder()->CreateInsertElement(elem, constituents[0], subIdx); // The value to initialize all members
-
- elem = getBuilder()->CreateBitCast(elem, cast<FixedVectorType>(vecTy)->getElementType());
- matrixResult = getBuilder()->CreateInsertElement(matrixResult, elem, idx);
- }
- return matrixResult;
+ lgc::Builder::CooperativeMatrixLayout layout = getCooperativeMatrixKHRLayout(
+ static_cast<CooperativeMatrixUse>(spvCoopMatTy->getCooperativeMatrixKHRUse()), elemType,
+ spvCoopMatTy->getCooperativeMatrixKHRRows(), spvCoopMatTy->getCooperativeMatrixKHRColumns());
+ return getBuilder()->CreateCooperativeMatrixFill(constituents[0], elemType, layout);
}
} // namespace SPIRV
diff --git a/llpc/translator/lib/SPIRV/SPIRVReader.h b/llpc/translator/lib/SPIRV/SPIRVReader.h
index a9be457be3..7f1699f265 100644
--- a/llpc/translator/lib/SPIRV/SPIRVReader.h
+++ b/llpc/translator/lib/SPIRV/SPIRVReader.h
@@ -99,9 +99,10 @@ class SPIRVToLLVM {
Value *transAtomicRMW(SPIRVValue *, const AtomicRMWInst::BinOp);
Constant *transInitializer(SPIRVValue *, Type *);
template <spv::Op> Value *transValueWithOpcode(SPIRVValue *);
+ template <spv::Op> SmallVector<Value *> transValueMultiWithOpcode(SPIRVValue *);
Value *transLoadImage(SPIRVValue *spvImageLoadPtr);
Value *loadImageSampler(Type *elementTy, Value *base);
- Value *transImagePointer(SPIRVValue *spvImagePtr);
+ Value *transImagePointer(SPIRVValue *spvImagePtr, SPIRVType *elementTy = nullptr);
Value *getDescPointerAndStride(lgc::ResourceNodeType resType, unsigned descriptorSet, unsigned binding,
lgc::ResourceNodeType searchType);
Value *transOpAccessChainForImage(SPIRVAccessChainBase *spvAccessChain);
@@ -128,7 +129,9 @@ class SPIRVToLLVM {
Instruction *transBarrierFence(SPIRVInstruction *bi, BasicBlock *bb);
Value *transString(const SPIRVString *spvValue);
Value *transDebugPrintf(SPIRVInstruction *bi, const ArrayRef<SPIRVValue *> spvValues, Function *func, BasicBlock *bb);
-
+ Value *transVariable(SPIRVValue *const spvValue);
+ SmallVector<Value *> transAccessChain(SPIRVValue *const spvValue);
+ Value *transArrayLength(SPIRVValue *const spvValue);
// Struct used to pass information in and out of getImageDesc.
struct ExtractedImageInfo {
BasicBlock *bb;
@@ -253,6 +256,7 @@ class SPIRVToLLVM {
llvm::ArrayRef<ConvertingSampler> m_convertingSamplers;
SPIRVToLLVMTypeMap m_typeMap;
SPIRVToLLVMFullTypeMap m_fullTypeMap;
+ SPIRVToLLVMFullTypeMap m_imageTypeMap; // Map to store struct/array with sampler type
SPIRVToLLVMValueMap m_valueMap;
SPIRVToLLVMEntryMap m_entryMap;
SPIRVToLLVMFunctionMap m_funcMap;
@@ -381,7 +385,6 @@ class SPIRVToLLVM {
// Change this if it is no longer true.
bool isFuncNoUnwind() const { return true; }
- bool isSPIRVCmpInstTransToLLVMInst(SPIRVInstruction *bi) const;
Value *mapFunction(SPIRVFunction *bf, Function *f) {
m_funcMap[bf] = f;
@@ -401,7 +404,7 @@ class SPIRVToLLVM {
FastMathFlags getFastMathFlags(SPIRVValue *bv);
void setFastMathFlags(SPIRVValue *bv);
void setFastMathFlags(Value *val);
- llvm::Value *transShiftLogicalBitwiseInst(SPIRVValue *bv, BasicBlock *bb, Function *f);
+ llvm::Value *transBinaryShiftBitwiseInst(SPIRVValue *bv, BasicBlock *bb, Function *f);
llvm::Value *transCmpInst(SPIRVValue *bv, BasicBlock *bb, Function *f);
void setName(ArrayRef<Value *> values, SPIRVValue *bv);
diff --git a/llpc/translator/lib/SPIRV/libSPIRV/SPIRVDecorate.h b/llpc/translator/lib/SPIRV/libSPIRV/SPIRVDecorate.h
index 1c9b800e0a..d384108727 100644
--- a/llpc/translator/lib/SPIRV/libSPIRV/SPIRVDecorate.h
+++ b/llpc/translator/lib/SPIRV/libSPIRV/SPIRVDecorate.h
@@ -189,10 +189,15 @@ class SPIRVDecorationGroup : public SPIRVEntry {
_SPIRV_DCL_DECODE
// Move the given decorates to the decoration group
void takeDecorates(SPIRVDecorateVec &Decs) {
- Decorations = std::move(Decs);
- for (auto &I : Decorations)
- const_cast<SPIRVDecorateGeneric *>(I)->setOwner(this);
- Decs.clear();
+ for (SPIRVDecorateVec::const_iterator Dec = Decs.begin(); Dec != Decs.end();) {
+ if ((*Dec)->getTargetId() == Id) {
+ (*Dec)->setOwner(this);
+ Decorations.push_back(*Dec);
+ Dec = Decs.erase(Dec); // Remove the decoration from original collection
+ } else {
+ ++Dec;
+ }
+ }
}
SPIRVDecorateVec &getDecorations() { return Decorations; }
diff --git a/llpc/translator/lib/SPIRV/libSPIRV/SPIRVEntry.h b/llpc/translator/lib/SPIRV/libSPIRV/SPIRVEntry.h
index 6d35557df8..d51f519c77 100644
--- a/llpc/translator/lib/SPIRV/libSPIRV/SPIRVEntry.h
+++ b/llpc/translator/lib/SPIRV/libSPIRV/SPIRVEntry.h
@@ -214,6 +214,7 @@ class SPIRVEntry {
const char *getDecorateString(Decoration kind) const;
bool hasMemberDecorate(SPIRVWord MemberIndex, Decoration Kind, size_t Index = 0, SPIRVWord *Result = 0) const;
std::set<SPIRVWord> getDecorate(Decoration Kind, size_t Index = 0) const;
+
bool hasId() const { return !(Attrib & SPIRVEA_NOID); }
bool hasLine() const { return Line != nullptr; }
bool hasLinkageType() const;
@@ -230,6 +231,7 @@ class SPIRVEntry {
bool isControlBarrier() const { return OpCode == OpControlBarrier; }
bool isMemoryBarrier() const { return OpCode == OpMemoryBarrier; }
bool isVariable() const { return OpCode == OpVariable; }
+
bool isEndOfBlock() const;
virtual bool isInst() const { return false; }
virtual bool isOperandLiteral(unsigned Index) const {
diff --git a/llpc/translator/lib/SPIRV/libSPIRV/SPIRVInstruction.h b/llpc/translator/lib/SPIRV/libSPIRV/SPIRVInstruction.h
index adb656f363..2f2780b527 100644
--- a/llpc/translator/lib/SPIRV/libSPIRV/SPIRVInstruction.h
+++ b/llpc/translator/lib/SPIRV/libSPIRV/SPIRVInstruction.h
@@ -413,20 +413,20 @@ class SPIRVMemoryAccess {
} MemoryAccess[2]; // [0]:destination, [1]:source
};
-class SPIRVVariable : public SPIRVInstruction {
+class SPIRVBaseVariable : public SPIRVInstruction {
public:
// Complete constructor for integer constant
- SPIRVVariable(SPIRVType *TheType, SPIRVId TheId, SPIRVValue *TheInitializer, const std::string &TheName,
- SPIRVStorageClassKind TheStorageClass, SPIRVBasicBlock *TheBB, SPIRVModule *TheM)
- : SPIRVInstruction(TheInitializer ? 5 : 4, OpVariable, TheType, TheId, TheBB, TheM),
- StorageClass(TheStorageClass) {
+ SPIRVBaseVariable(Op OC, SPIRVWord FixedWordCount, SPIRVType *TheType, SPIRVId TheId, SPIRVValue *TheInitializer,
+ const std::string &TheName, SPIRVStorageClassKind TheStorageClass, SPIRVId TheMemObjId,
+ SPIRVBasicBlock *TheBB, SPIRVModule *TheM)
+ : SPIRVInstruction(TheInitializer ? (FixedWordCount + 1) : FixedWordCount, OC, TheType, TheId, TheBB, TheM),
+ StorageClass(TheStorageClass), MemObjId(TheMemObjId) {
if (TheInitializer)
Initializer.push_back(TheInitializer->getId());
Name = TheName;
- validate();
}
// Incomplete constructor
- SPIRVVariable() : SPIRVInstruction(OpVariable), StorageClass(StorageClassFunction) {}
+ SPIRVBaseVariable(Op OC) : SPIRVInstruction(OC), StorageClass(StorageClassFunction) {}
SPIRVStorageClassKind getStorageClass() const { return StorageClass; }
SPIRVValue *getInitializer() const {
@@ -435,6 +435,7 @@ class SPIRVVariable : public SPIRVInstruction {
assert(Initializer.size() == 1);
return getValue(Initializer[0]);
}
+
bool isBuiltin(SPIRVBuiltinVariableKind *BuiltinKind = nullptr) const {
SPIRVWord Kind;
bool Found = hasDecorate(DecorationBuiltIn, 0, &Kind);
@@ -454,8 +455,39 @@ class SPIRVVariable : public SPIRVInstruction {
return std::vector<SPIRVEntry *>();
}
+ virtual void validate() const {};
+ SPIRVType *getMemObjType() const {
+ SPIRVType *spvMemType = nullptr;
+ if (getOpCode() == OpVariable) {
+ spvMemType = getType()->getPointerElementType();
+ }
+ return spvMemType;
+ }
+
protected:
- void validate() const override {
+ SPIRVStorageClassKind StorageClass;
+ std::vector<SPIRVId> Initializer;
+ SPIRVId MemObjId;
+};
+
+class SPIRVVariable : public SPIRVBaseVariable {
+ const static Op OC = OpVariable;
+ const static SPIRVWord FixedWords = 4;
+
+public:
+ // Complete constructor for integer constant
+ SPIRVVariable(SPIRVType *TheType, SPIRVId TheId, SPIRVValue *TheInitializer, const std::string &TheName,
+ SPIRVStorageClassKind TheStorageClass, SPIRVBasicBlock *TheBB, SPIRVModule *TheM)
+ : SPIRVBaseVariable(OC, FixedWords, TheType, TheId, TheInitializer, TheName, TheStorageClass, SPIRVID_INVALID,
+ TheBB, TheM) {
+ validate();
+ };
+
+ // Incomplete constructor
+ SPIRVVariable() : SPIRVBaseVariable(OC){};
+
+protected:
+ virtual void validate() const override {
SPIRVValue::validate();
assert(isValid(StorageClass));
assert(Initializer.size() == 1 || Initializer.empty());
@@ -466,9 +498,6 @@ class SPIRVVariable : public SPIRVInstruction {
Initializer.resize(WordCount - 4);
}
_SPIRV_DEF_DECODE4(Type, Id, StorageClass, Initializer)
-
- SPIRVStorageClassKind StorageClass;
- std::vector<SPIRVId> Initializer;
};
class SPIRVImageTexelPointer : public SPIRVInstruction {
@@ -688,9 +717,11 @@ class SPIRVBinary : public SPIRVInstTemplateBase {
assert((Op1Ty->getBitWidth() == Op2Ty->getBitWidth()) && "Inconsistent BitWidth");
} else if (OpCode == OpPtrDiff) {
assert(Op1Ty->isTypePointer() && Op2Ty->isTypePointer() && "Invalid type for ptr diff instruction");
- Op1Ty = Op1Ty->getPointerElementType();
- Op2Ty = Op2Ty->getPointerElementType();
- assert(Op1Ty == Op2Ty && "Inconsistent type");
+ if (Op1Ty->isTypePointer() && Op2Ty->isTypePointer()) {
+ Op1Ty = Op1Ty->getPointerElementType();
+ Op2Ty = Op2Ty->getPointerElementType();
+ assert(Op1Ty == Op2Ty && "Inconsistent type");
+ }
} else {
assert(0 && "Invalid op code!");
}
diff --git a/llpc/translator/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h b/llpc/translator/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h
index 4439a4a4db..41242df7cc 100644
--- a/llpc/translator/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h
+++ b/llpc/translator/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h
@@ -927,6 +927,11 @@ inline bool isValid(spv::Op V) {
case OpRayQueryGetIntersectionObjectToWorldKHR:
case OpRayQueryGetIntersectionWorldToObjectKHR:
case OpRayQueryGetIntersectionTriangleVertexPositionsKHR:
+ case OpTypeCooperativeMatrixKHR:
+ case OpCooperativeMatrixLoadKHR:
+ case OpCooperativeMatrixStoreKHR:
+ case OpCooperativeMatrixMulAddKHR:
+ case OpCooperativeMatrixLengthKHR:
return true;
default:
return false;
diff --git a/llpc/translator/lib/SPIRV/libSPIRV/SPIRVModule.cpp b/llpc/translator/lib/SPIRV/libSPIRV/SPIRVModule.cpp
index 062feca63e..2531347b91 100644
--- a/llpc/translator/lib/SPIRV/libSPIRV/SPIRVModule.cpp
+++ b/llpc/translator/lib/SPIRV/libSPIRV/SPIRVModule.cpp
@@ -558,7 +558,7 @@ bool SPIRVModuleImpl::importBuiltinSet(const std::string &BuiltinSetName, SPIRVI
}
bool SPIRVModuleImpl::isNonSemanticInfoInstSet(llvm::StringRef setName) const {
- return setName.startswith("NonSemantic.");
+ return setName.starts_with("NonSemantic.");
}
bool SPIRVModuleImpl::importBuiltinSetWithId(const std::string &BuiltinSetName, SPIRVId BuiltinSetId) {
diff --git a/llpc/translator/lib/SPIRV/libSPIRV/SPIRVOpCode.h b/llpc/translator/lib/SPIRV/libSPIRV/SPIRVOpCode.h
index 027daa4a78..3bd057d2d3 100644
--- a/llpc/translator/lib/SPIRV/libSPIRV/SPIRVOpCode.h
+++ b/llpc/translator/lib/SPIRV/libSPIRV/SPIRVOpCode.h
@@ -75,7 +75,7 @@ inline bool isBitwiseOpCode(Op OpCode) {
return (unsigned)OpCode >= OpBitwiseOr && (unsigned)OpCode <= OpBitwiseAnd;
}
-inline bool isBinaryShiftLogicalBitwiseOpCode(Op OpCode) {
+inline bool isBinaryShiftBitwiseOpCode(Op OpCode) {
return (((unsigned)OpCode >= OpShiftRightLogical && (unsigned)OpCode <= OpBitwiseAnd) || isBinaryOpCode(OpCode));
}
@@ -104,6 +104,10 @@ inline bool isAccessChainOpCode(Op OpCode) {
return OpCode == OpAccessChain || OpCode == OpInBoundsAccessChain;
}
+inline bool isPtrAccessChainOpCode(Op OpCode) {
+ return OpCode == OpPtrAccessChain || OpCode == OpInBoundsPtrAccessChain;
+}
+
inline bool hasExecScope(Op OpCode) {
unsigned OC = OpCode;
return (OpGroupAll <= OC && OC <= OpGroupSMax);
diff --git a/llpc/unittests/context/testOptLevel.cpp b/llpc/unittests/context/testOptLevel.cpp
index fae1433c1c..48acfdd5bd 100644
--- a/llpc/unittests/context/testOptLevel.cpp
+++ b/llpc/unittests/context/testOptLevel.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/llpc/util/llpcDebug.cpp b/llpc/util/llpcDebug.cpp
index 0677f76521..98348beee1 100644
--- a/llpc/util/llpcDebug.cpp
+++ b/llpc/util/llpcDebug.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -121,7 +121,7 @@ void redirectLogOutput(bool restoreToDefault, unsigned optionCount, const char *
bool needDebugOut = ::llvm::DebugFlag;
for (unsigned i = 1; !needDebugOut && i < optionCount; ++i) {
StringRef option = options[i];
- if (option.startswith("-debug") || option.startswith("-print"))
+ if (option.starts_with("-debug") || option.starts_with("-print"))
needDebugOut = true;
}
diff --git a/llpc/util/llpcDebug.h b/llpc/util/llpcDebug.h
index dbb427b3cc..f406c1794d 100644
--- a/llpc/util/llpcDebug.h
+++ b/llpc/util/llpcDebug.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2016-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2016-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/util/llpcElfWriter.cpp b/llpc/util/llpcElfWriter.cpp
index 8681fdc1ba..b844a41867 100644
--- a/llpc/util/llpcElfWriter.cpp
+++ b/llpc/util/llpcElfWriter.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/util/llpcElfWriter.h b/llpc/util/llpcElfWriter.h
index 4f2605fc90..b51e1bd5db 100644
--- a/llpc/util/llpcElfWriter.h
+++ b/llpc/util/llpcElfWriter.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/util/llpcFile.cpp b/llpc/util/llpcFile.cpp
index 12926b24b6..8555a6d861 100644
--- a/llpc/util/llpcFile.cpp
+++ b/llpc/util/llpcFile.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/util/llpcFile.h b/llpc/util/llpcFile.h
index 009e35abe4..c9305494bb 100644
--- a/llpc/util/llpcFile.h
+++ b/llpc/util/llpcFile.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/util/llpcShaderModuleHelper.cpp b/llpc/util/llpcShaderModuleHelper.cpp
index bc59cd049e..b4ff1027a2 100644
--- a/llpc/util/llpcShaderModuleHelper.cpp
+++ b/llpc/util/llpcShaderModuleHelper.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -169,6 +169,14 @@ ShaderModuleUsage ShaderModuleHelper::getShaderModuleUsageInfo(const BinaryData
auto location = (opCode == OpDecorate) ? codePos[3] : codePos[4];
if (location == static_cast<unsigned>(Vkgc::GlCompatibilityInOutLocation::ClipVertex))
shaderModuleUsage.useClipVertex = true;
+ if (location == static_cast<unsigned>(Vkgc::GlCompatibilityInOutLocation::FrontColor))
+ shaderModuleUsage.useFrontColor = true;
+ if (location == static_cast<unsigned>(Vkgc::GlCompatibilityInOutLocation::BackColor))
+ shaderModuleUsage.useBackColor = true;
+ if (location == static_cast<unsigned>(Vkgc::GlCompatibilityInOutLocation::FrontSecondaryColor))
+ shaderModuleUsage.useFrontSecondaryColor = true;
+ if (location == static_cast<unsigned>(Vkgc::GlCompatibilityInOutLocation::BackSecondaryColor))
+ shaderModuleUsage.useBackSecondaryColor = true;
} else if (decoration == DecorationPerVertexKHR) {
shaderModuleUsage.useBarycentric = true;
}
@@ -520,6 +528,7 @@ Result ShaderModuleHelper::getModuleData(const ShaderModuleBuildInfo *shaderInfo
memcpy(moduleData.cacheHash, cacheHash.dwords, sizeof(cacheHash));
} else {
moduleData.binCode = shaderBinary;
+ memcpy(codeBuffer.data(), shaderBinary.pCode, shaderBinary.codeSize);
}
return Result::Success;
@@ -556,7 +565,14 @@ Expected<BinaryData> ShaderModuleHelper::getShaderCode(const ShaderModuleBuildIn
// @return : The number of bytes need to hold the code for this shader module.
Expected<unsigned> ShaderModuleHelper::getCodeSize(const ShaderModuleBuildInfo *shaderInfo) {
const BinaryData &shaderBinary = shaderInfo->shaderBin;
- bool trimDebugInfo = cl::TrimDebugInfo && !(shaderInfo->options.pipelineOptions.internalRtShaders);
+ BinaryType binaryType;
+ Result result = ShaderModuleHelper::getShaderBinaryType(shaderBinary, binaryType);
+ if (result != Result::Success)
+ return createResultError(Result::ErrorInvalidShader);
+
+ bool trimDebugInfo =
+ binaryType != BinaryType::LlvmBc && cl::TrimDebugInfo && !(shaderInfo->options.pipelineOptions.internalRtShaders);
+
if (!trimDebugInfo)
return shaderBinary.codeSize;
return ShaderModuleHelper::trimSpirvDebugInfo(&shaderBinary, {});
diff --git a/llpc/util/llpcShaderModuleHelper.h b/llpc/util/llpcShaderModuleHelper.h
index 07a0a9424d..5282f38fd1 100644
--- a/llpc/util/llpcShaderModuleHelper.h
+++ b/llpc/util/llpcShaderModuleHelper.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/util/llpcTimerProfiler.cpp b/llpc/util/llpcTimerProfiler.cpp
index ec9ed71b54..ee7ff99610 100644
--- a/llpc/util/llpcTimerProfiler.cpp
+++ b/llpc/util/llpcTimerProfiler.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/util/llpcTimerProfiler.h b/llpc/util/llpcTimerProfiler.h
index 40a3dac8b8..bc7c8e598e 100644
--- a/llpc/util/llpcTimerProfiler.h
+++ b/llpc/util/llpcTimerProfiler.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/util/llpcUtil.cpp b/llpc/util/llpcUtil.cpp
index d30cbfcd29..645ed0d7e2 100644
--- a/llpc/util/llpcUtil.cpp
+++ b/llpc/util/llpcUtil.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/llpc/util/llpcUtil.h b/llpc/util/llpcUtil.h
index a614509a98..0fbcae5663 100644
--- a/llpc/util/llpcUtil.h
+++ b/llpc/util/llpcUtil.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/script/switch-coding-style.sh b/script/switch-coding-style.sh
index 920b299f16..94756811e4 100755
--- a/script/switch-coding-style.sh
+++ b/script/switch-coding-style.sh
@@ -2,13 +2,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -18,9 +18,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/shared/continuations/CMakeLists.txt b/shared/continuations/CMakeLists.txt
index 26eff9d596..f8b9ee8a9e 100644
--- a/shared/continuations/CMakeLists.txt
+++ b/shared/continuations/CMakeLists.txt
@@ -15,14 +15,12 @@ option(CONTINUATIONS_BUILD_TESTS "Build continuation tests")
add_llvm_library(LLVMContinuations
lib/CleanupContinuations.cpp
+ lib/Continuations.cpp
lib/ContinuationsDialect.cpp
- lib/ContinuationsUtil.cpp
lib/CpsStackLowering.cpp
- lib/DXILCont.cpp
lib/DXILContIntrinsicPrepare.cpp
lib/DXILContLgcRtOpConverter.cpp
lib/DXILContPostProcess.cpp
- lib/DXILMetadata.cpp
lib/DXILSupport.cpp
lib/GpurtDialect.cpp
lib/LegacyCleanupContinuations.cpp
@@ -35,6 +33,7 @@ add_llvm_library(LLVMContinuations
lib/RegisterBuffer.cpp
lib/RemoveTypesMetadata.cpp
lib/SaveContinuationState.cpp
+ lib/TypesMetadata.cpp
DEPENDS
intrinsics_gen
diff --git a/shared/continuations/include/continuations/Continuations.h b/shared/continuations/include/continuations/Continuations.h
index 875dcf0dc9..ca01437def 100644
--- a/shared/continuations/include/continuations/Continuations.h
+++ b/shared/continuations/include/continuations/Continuations.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -66,9 +66,9 @@
// argument. All these intrinsics cannot modify system data, otherwise we could
// not rematerialize them.
//
-// At the start of a function, the alloca is initialized from
-// getSystemData, which is itself initialized from either an argument or
-// SetupRayGen.
+// At the start of a function, the alloca is initialized from an argument. In
+// the case of RayGen, this argument is removed and replaced with a proper call
+// to SetupRayGen in the DXILContPostProcess pass.
#ifndef CONTINUATIONS_CONTINUATIONS_H
#define CONTINUATIONS_CONTINUATIONS_H
@@ -96,10 +96,6 @@ class Builder;
class DialectContext;
} // namespace llvm_dialects
-namespace continuations {
-class GetSystemDataOp;
-} // namespace continuations
-
namespace llvm {
class PassBuilder;
@@ -123,10 +119,11 @@ Value *continuationStackOffsetToPtr(IRBuilder<> &B, Value *Offset,
CompilerUtils::CrossModuleInliner &Inliner);
/// Create a new function, as cloneFunctionHeader, but include types metadata.
-Function *cloneFunctionHeaderWithTypes(Function &F, DXILContFuncTy &NewType,
+Function *cloneFunctionHeaderWithTypes(Function &F, ContFuncTy &NewType,
ArrayRef<AttributeSet> ArgAttrs);
/// Remove bitcasts of function pointers in metadata.
+/// This also removes the DXIL payload metadata from functions.
/// Returns true if something changed.
bool fixupDxilMetadata(Module &M);
@@ -212,16 +209,6 @@ uint64_t computeNeededStackSizeForRegisterBuffer(uint64_t NumI32s,
// of individual bytes at the end if NumBytes is not a multiple of 4.
void copyBytes(IRBuilder<> &B, Value *Dst, Value *Src, uint64_t NumBytes);
-/// Return element type of a function argument resolving opaque pointers
-/// via !types metadata where appropriate.
-/// Returns nullptr for non-pointers.
-Type *getFuncArgPtrElementType(const Function *F, const Argument *Arg);
-
-/// Return element type of a function argument resolving opaque pointers
-/// via !types metadata where appropriate.
-/// Returns nullptr for non-pointers.
-Type *getFuncArgPtrElementType(const Function *F, int ArgNo);
-
class DialectContextAnalysisResult {
public:
DialectContextAnalysisResult() {}
@@ -266,7 +253,8 @@ class LegacyCleanupContinuationsPass
class CleanupContinuationsPass
: public llvm::PassInfoMixin<CleanupContinuationsPass> {
public:
- CleanupContinuationsPass();
+ CleanupContinuationsPass(llvm::Module *GpurtLibrary = nullptr)
+ : GpurtLibrary(GpurtLibrary) {}
llvm::PreservedAnalyses run(llvm::Module &Module,
llvm::ModuleAnalysisManager &AnalysisManager);
@@ -285,9 +273,10 @@ class CleanupContinuationsPass
};
void removeContFreeCall(Function *F, Function *ContFree);
- Value *getContinuationFramePtr(Function *F, bool IsStart,
- const ContinuationData &ContinuationInfo,
- SmallVector<Instruction *> &InstsToRemove);
+ Value *
+ getContinuationFramePtr(Function *F, bool IsStart,
+ const ContinuationData &ContinuationInfo,
+ SmallVector<Instruction *> *InstsToRemove = nullptr);
void freeCpsStack(Function *F, ContinuationData &CpsInfo);
void updateCpsStack(Function *F, Function *NewFunc, bool IsStart,
ContinuationData &CpsInfo);
@@ -296,12 +285,14 @@ class CleanupContinuationsPass
void handleContinue(ContinuationData &Data, Instruction *Ret);
void handleSingleContinue(ContinuationData &Data, CallInst *Call,
Value *ResumeFun);
+ void lowerIntrinsicCall(Module &Mod);
llvm_dialects::Builder *Builder;
Function *ContMalloc;
Function *ContFree;
MapVector<Function *, ContinuationData> ToProcess;
uint32_t MaxContStateBytes;
+ llvm::Module *GpurtLibrary;
};
class LowerRaytracingPipelinePass
: public llvm::PassInfoMixin<LowerRaytracingPipelinePass> {
@@ -481,7 +472,7 @@ class DXILContLgcRtOpConverterPass
Module *M = nullptr;
const llvm::DataLayout *DL = nullptr;
- bool processFunction(llvm::Function &Func);
+ bool convertDxOp(llvm::Function &Func);
using OpCallbackType = std::function<llvm::Value *(
llvm::CallInst &, DXILContLgcRtOpConverterPass *)>;
std::optional<OpCallbackType> getCallbackByOpName(StringRef OpName);
@@ -496,7 +487,8 @@ class DXILContLgcRtOpConverterPass
Value *handleMatrixResult(CallInst &CI);
Value *createVec3(Value *X, Value *Y, Value *Z);
void addDXILPayloadTypeToCall(Function &DXILFunc, CallInst &CI);
- void applyPayloadMetadataTypesOnShaders();
+ bool prepareEntryPointShaders();
+ void setupLocalRootIndex(Function *F);
};
/// Add necessary continuation transform passes for LGC.
diff --git a/shared/continuations/include/continuations/ContinuationsDialect.h b/shared/continuations/include/continuations/ContinuationsDialect.h
index 515d4fb12c..206044c7a2 100644
--- a/shared/continuations/include/continuations/ContinuationsDialect.h
+++ b/shared/continuations/include/continuations/ContinuationsDialect.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/shared/continuations/include/continuations/ContinuationsDialect.td b/shared/continuations/include/continuations/ContinuationsDialect.td
index b58d4a5b34..d4173142eb 100644
--- a/shared/continuations/include/continuations/ContinuationsDialect.td
+++ b/shared/continuations/include/continuations/ContinuationsDialect.td
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -52,15 +52,3 @@ def GetReturnValueOp : ContinuationsOp<"getReturnValue", [NoUnwind, WillReturn]>
coroutine.
}];
}
-
-def GetSystemDataOp : ContinuationsOp<"getSystemData", [NoUnwind, WillReturn]> {
- let arguments = (ins);
- let results = (outs value:$result);
-
- let defaultBuilderHasExplicitResultType = true;
-
- let summary = "get the system data";
- let description = [{
- See the system data documentation in Continuations.h for more info.
- }];
-}
diff --git a/shared/continuations/include/continuations/ContinuationsUtil.h b/shared/continuations/include/continuations/ContinuationsUtil.h
index c4d1362a1b..84fb70b163 100644
--- a/shared/continuations/include/continuations/ContinuationsUtil.h
+++ b/shared/continuations/include/continuations/ContinuationsUtil.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -34,11 +34,13 @@
#include "lgc/LgcCpsDialect.h"
#include "lgc/LgcRtDialect.h"
+#include "llpc/GpurtEnums.h"
#include "llvm-dialects/Dialect/OpMap.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/IR/Constants.h"
+#include "llvm/IR/Dominators.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/Module.h"
@@ -50,14 +52,6 @@
#include <optional>
#include <type_traits>
-namespace DialectUtils {
-
-llvm::StringRef getLgcRtDialectOpName(llvm::StringRef FullName);
-
-bool isLgcRtOp(const llvm::Function *F);
-
-} // namespace DialectUtils
-
namespace llvm {
class Argument;
@@ -93,6 +87,12 @@ const unsigned GlobalMaxHitAttributeBytes = 32;
/// this pessimism.
const unsigned MinimumContinuationStateBytes = 8;
+constexpr uint32_t CpsArgIdxContState = 0;
+constexpr uint32_t CpsArgIdxReturnAddr = 1;
+constexpr uint32_t CpsArgIdxShaderIndex = 2;
+constexpr uint32_t CpsArgIdxSystemData = 3;
+constexpr uint32_t CpsArgIdxHitAttributes = 4;
+
struct DxRayIntrinsic {
unsigned int Id;
StringRef Name;
@@ -105,29 +105,6 @@ struct GpuRtIntrinsicEntry {
extern const llvm_dialects::OpMap<GpuRtIntrinsicEntry> LgcRtGpuRtMap;
-// This must match DXIL::ShaderKind from DxilConstants.h, and also
-// DXILShaderKind in a matching definition in GPURT, because it is used
-// as return type of an intrinsic.
-enum class DXILShaderKind : uint32_t {
- Pixel = 0,
- Vertex,
- Geometry,
- Hull,
- Domain,
- Compute,
- Library,
- RayGeneration,
- Intersection,
- AnyHit,
- ClosestHit,
- Miss,
- Callable,
- Mesh,
- Amplification,
- Node,
- Invalid
-};
-
llvm::raw_ostream &operator<<(llvm::raw_ostream &, DXILShaderKind);
enum class AnyHitExitKind {
@@ -151,19 +128,19 @@ struct RegisterBufferMD {
// Helper class to abstract over function argument types.
// Derives types from custom metadata when available, allowing pointer
// element types to be derives even with opaque pointers.
-class DXILContArgTy {
+class ContArgTy {
private:
Type *ArgTy;
Type *ElemTy;
public:
- DXILContArgTy() : ArgTy(nullptr), ElemTy(nullptr) {}
- DXILContArgTy(Type *Arg, Type *Elem) : ArgTy(Arg), ElemTy(Elem) {}
- DXILContArgTy(Type *Arg);
+ ContArgTy() : ArgTy(nullptr), ElemTy(nullptr) {}
+ ContArgTy(Type *Arg, Type *Elem) : ArgTy(Arg), ElemTy(Elem) {}
+ ContArgTy(Type *Arg);
- static DXILContArgTy get(const Function *F, const Argument *Arg);
- static DXILContArgTy get(const Function *F, const unsigned ArgNo);
- static DXILContArgTy get(const Metadata *MD, LLVMContext &Context);
+ static ContArgTy get(const Function *F, const Argument *Arg);
+ static ContArgTy get(const Function *F, const unsigned ArgNo);
+ static ContArgTy get(const Metadata *MD, LLVMContext &Context);
Type *asType(LLVMContext &Context);
Type *getPointerElementType() const;
@@ -172,33 +149,43 @@ class DXILContArgTy {
bool isVoidTy() const;
Metadata *getTypeMetadata(LLVMContext &Context);
- bool operator==(const DXILContArgTy &RHS) const {
+ bool operator==(const ContArgTy &RHS) const {
return (ArgTy == RHS.ArgTy) && (ElemTy == RHS.ElemTy);
}
};
// Helper class to abstract over function types.
-// Uses DXILContArgTy to derive types from and encode types to custom metadata.
-class DXILContFuncTy {
+// Uses ContArgTy to derive types from and encode types to custom metadata.
+class ContFuncTy {
public:
- DXILContFuncTy() {}
- DXILContFuncTy(DXILContArgTy Return) : ReturnTy(Return) {}
- DXILContFuncTy(DXILContArgTy Return, ArrayRef<DXILContArgTy> Args)
+ ContFuncTy() {}
+ ContFuncTy(ContArgTy Return) : ReturnTy(Return) {}
+ ContFuncTy(ContArgTy Return, ArrayRef<ContArgTy> Args)
: ReturnTy(Return), ArgTys(Args) {}
- DXILContArgTy ReturnTy;
- SmallVector<DXILContArgTy> ArgTys;
+ ContArgTy ReturnTy;
+ SmallVector<ContArgTy> ArgTys;
- static DXILContFuncTy get(const Function *F);
- static DXILContFuncTy get(const Metadata *MD, LLVMContext &Context);
+ static ContFuncTy get(const Function *F);
+ static ContFuncTy get(const Metadata *MD, LLVMContext &Context);
FunctionType *asFunctionType(LLVMContext &Context);
void writeMetadata(Function *F);
};
-// Helper class to access data specific to DXIL continuation passes, e.g.
+/// Return element type of a function argument resolving opaque pointers
+/// via !types metadata where appropriate.
+/// Returns nullptr for non-pointers.
+Type *getFuncArgPtrElementType(const Argument *Arg);
+
+/// Return element type of a function argument resolving opaque pointers
+/// via !types metadata where appropriate.
+/// Returns nullptr for non-pointers.
+Type *getFuncArgPtrElementType(const Function *F, int ArgNo);
+
+// Helper class to access data specific to continuation passes, e.g.
// metadata or globals.
-class DXILContHelper {
+class ContHelper {
private:
// Private metadata node names
// These are private because we provide dedicated utilities to get and set
@@ -310,7 +297,7 @@ class DXILContHelper {
static constexpr const char *MDTypesName = "types";
static constexpr const char *MDTypesFunctionName = "function";
static constexpr const char *MDTypesVoidName = "void";
- static constexpr const char *MDDXILPayloadTyName = "dxil.payload.type";
+ static constexpr const char *MDContPayloadTyName = "cont.payload.type";
static constexpr const char *MDLgcCpsModuleName = "lgc.cps.module";
// Global variable names
@@ -425,15 +412,10 @@ class DXILContHelper {
return NumPayloadRegistersI32s;
}
+ // TODO: Remove this once dxcp calls the lgc::rt function directly.
static void setMaxHitAttributeByteCount(Function &F,
uint32_t MaxHitAttributeByteCount) {
- F.setMetadata(MDMaxHitAttributeBytesName,
- getI32MDConstant(F.getContext(), MaxHitAttributeByteCount));
- }
-
- static std::optional<uint32_t>
- tryGetMaxHitAttributeByteCount(const Function &F) {
- return extractZExtI32Constant(F.getMetadata(MDMaxHitAttributeBytesName));
+ lgc::rt::setShaderHitAttributeSize(&F, MaxHitAttributeByteCount);
}
static void setMaxPayloadByteCount(Function &F,
@@ -523,19 +505,19 @@ class DXILContHelper {
}
static Type *getPayloadTypeFromMetadata(const Function &Func) {
- if (MDNode *Node = Func.getMetadata(MDDXILPayloadTyName))
+ if (MDNode *Node = Func.getMetadata(MDContPayloadTyName))
return getPayloadTypeFromMetadata(Node);
- report_fatal_error(Twine(MDDXILPayloadTyName) +
+ report_fatal_error(Twine(MDContPayloadTyName) +
" metadata not found on function " + Func.getName() +
"!");
}
static Type *getPayloadTypeFromMetadata(const CallInst &CI) {
- if (MDNode *Node = CI.getMetadata(MDDXILPayloadTyName))
+ if (MDNode *Node = CI.getMetadata(MDContPayloadTyName))
return getPayloadTypeFromMetadata(Node);
- report_fatal_error(Twine(MDDXILPayloadTyName) +
+ report_fatal_error(Twine(MDContPayloadTyName) +
" metadata not found on CallInst!");
}
@@ -545,7 +527,7 @@ class DXILContHelper {
// Specifies that an awaited call should wait on a wait mask.
static void setIsWaitAwaitCall(CallInst &CI) {
- CI.setMetadata(DXILContHelper::MDIsWaitAwaitName,
+ CI.setMetadata(ContHelper::MDIsWaitAwaitName,
MDTuple::get(CI.getContext(), {}));
}
@@ -555,9 +537,20 @@ class DXILContHelper {
}
static void removeIsWaitAwaitMetadata(CallInst &CI) {
- CI.setMetadata(DXILContHelper::MDIsWaitAwaitName, nullptr);
+ CI.setMetadata(ContHelper::MDIsWaitAwaitName, nullptr);
}
+ /// Returns true if a call to the given function should be rematerialized
+ /// in a shader of the specified kind.
+ ///
+ /// If no shader kind is specified, return false.
+ static bool
+ isRematerializableLgcRtOp(CallInst &CInst,
+ std::optional<DXILShaderKind> Kind = std::nullopt);
+};
+
+class ShaderStageHelper final {
+public:
static DXILShaderKind
shaderStageToDxilShaderKind(lgc::rt::RayTracingShaderStage Stage) {
switch (Stage) {
@@ -573,9 +566,15 @@ class DXILContHelper {
return DXILShaderKind::Miss;
case lgc::rt::RayTracingShaderStage::Callable:
return DXILShaderKind::Callable;
+ case lgc::rt::RayTracingShaderStage::KernelEntry:
case lgc::rt::RayTracingShaderStage::Traversal:
+ // TODO: Migrate to an enum shared by GpuRt HLSL and the compiler C++
+ // source that explicitly supports KernelEntry and Traversal,
+ // eliminate most uses of DXILShaderKind except for initial
+ // conversions to the shared enum.
return DXILShaderKind::Compute;
}
+ llvm_unreachable("invalid stage!");
}
static std::optional<lgc::rt::RayTracingShaderStage>
@@ -597,16 +596,11 @@ class DXILContHelper {
return std::nullopt;
}
}
-
- /// Returns true if a call to the given function should be rematerialized
- /// in a shader of the specified kind.
- ///
- /// If no shader kind is specified, return false.
- static bool
- isRematerializableLgcRtOp(CallInst &CInst,
- std::optional<DXILShaderKind> Kind = std::nullopt);
};
+// Until all users have been migrated, provide old name as well:
+class DXILContHelper : public ContHelper {};
+
/// Free-standing helpers.
// Helper to visit all calls of a function.
@@ -622,6 +616,8 @@ void forEachCall(Function &F, CallbackTy Callback) {
}
}
+bool isLgcRtOp(const llvm::Function *F);
+
// Move all basic blocks of OldFunc to NewFunc.
void moveFunctionBody(Function &OldFunc, Function &NewFunc);
@@ -656,10 +652,20 @@ void forEachTerminator(Function *Func, ArrayRef<unsigned> TerminatorOpcodes,
// Essentially RAUW for pointers for the case that these use different address
// spaces, rewriting all derived pointers to also use the new address space.
+// Writes instructions which are redundant after the replacement into
+// the given ToBeRemoved vector.
+// The caller has to handle the erasure afterwards.
void replaceAllPointerUses(IRBuilder<> *Builder, Value *OldPointerValue,
Value *NewPointerValue,
SmallVectorImpl<Instruction *> &ToBeRemoved);
+// Do store-to-load forwarding for memory access to continuation stack. This is
+// helpful to mitigate the issue that coroutine passes in some cases still load
+// state from the in-memory continuation state when it is still available in SSA
+// variables. The implementation is assuming there is no other pointers in the
+// program that may alias the pointer argument.
+void forwardContinuationFrameStoreToLoad(DominatorTree &DT, Value *FramePtr);
+
// Replacement for PointerType::getWithSamePointeeType that works with new LLVM.
// Returns a typed pointer type if the pointer type is typed.
PointerType *getWithSamePointeeType(PointerType *PtrTy, unsigned AddressSpace);
diff --git a/shared/continuations/include/continuations/CpsStackLowering.h b/shared/continuations/include/continuations/CpsStackLowering.h
index a0f65207ee..f0b5eab9c1 100644
--- a/shared/continuations/include/continuations/CpsStackLowering.h
+++ b/shared/continuations/include/continuations/CpsStackLowering.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -33,10 +33,12 @@
#include "compilerutils/TypeLowering.h"
#include "lgc/LgcCpsDialect.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/IR/IRBuilder.h"
namespace llvm {
class LLVMContext;
class Function;
+class BitCastInst;
class GetElementPtrInst;
class PtrToIntInst;
class IntToPtrInst;
@@ -48,8 +50,6 @@ class Type;
class DataLayout;
} // namespace llvm
-using namespace lgc::cps;
-
constexpr unsigned ContinuationStackAlignment = 4;
class CpsStackLowering {
@@ -57,8 +57,10 @@ class CpsStackLowering {
CpsStackLowering(llvm::LLVMContext &Context,
unsigned LoweredCpsStackAddrSpace)
: TypeLower(Context), LoweredCpsStackAddrSpace{LoweredCpsStackAddrSpace} {
+ BasePointer = llvm::ConstantPointerNull::get(llvm::PointerType::get(
+ llvm::Type::getInt8Ty(Context), LoweredCpsStackAddrSpace));
}
- void lowerCpsStackOps(llvm::Function &, llvm::Value *);
+ llvm::Function *lowerCpsStackOps(llvm::Function &, llvm::Value *);
// Get continuation stack size (in bytes).
unsigned getStackSizeInBytes() { return StackSizeInBytes; }
@@ -71,24 +73,39 @@ class CpsStackLowering {
return Layout.getPointerSize(LoweredCpsStackAddrSpace);
}
+ // Register a base pointer in the CpsStackLowering.
+ // This is used to set the base address when using a stack residing in global
+ // memory. BasePointer is by default a zero pointer in the
+ // @LoweredCpsStackAddrSpace. During the lowering of load / store
+ // instructions, a GEP will be constructed that uses the base pointer and the
+ // corresponding CSP as offset for the source / dest addresses. In case
+ // @setRealBasePointer never was called, this just creates a pointer out of an
+ // offset.
+ void setRealBasePointer(llvm::Value *BasePointer) {
+ this->BasePointer = BasePointer;
+ }
+
TypeLowering TypeLower;
private:
- llvm::SmallVector<llvm::Type *> convertCpsStackPointer(TypeLowering &,
- llvm::Type *);
- void visitCpsAlloc(AllocOp &);
- void visitCpsFree(FreeOp &);
- void visitCpsPeek(PeekOp &);
- void visitSetVsp(SetVspOp &);
- void visitGetVsp(GetVspOp &);
+ llvm::SmallVector<llvm::Type *> convertStackPtrToI32(TypeLowering &,
+ llvm::Type *);
+ void visitCpsAlloc(lgc::cps::AllocOp &);
+ void visitCpsFree(lgc::cps::FreeOp &);
+ void visitCpsPeek(lgc::cps::PeekOp &);
+ void visitSetVsp(lgc::cps::SetVspOp &);
+ void visitGetVsp(lgc::cps::GetVspOp &);
void visitGetElementPtr(llvm::GetElementPtrInst &);
void visitPtrToIntInst(llvm::PtrToIntInst &);
void visitIntToPtrInst(llvm::IntToPtrInst &);
+ void visitBitCastInst(llvm::BitCastInst &);
void visitLoad(llvm::LoadInst &);
void visitStore(llvm::StoreInst &);
+ llvm::Value *getRealMemoryAddress(llvm::IRBuilder<> &, llvm::Value *);
llvm::Module *Mod;
- llvm::Value *CpsStackAlloca;
+ llvm::AllocaInst *CpsStackAlloca;
unsigned LoweredCpsStackAddrSpace;
unsigned StackSizeInBytes = 0;
+ llvm::Value *BasePointer = nullptr;
};
diff --git a/shared/continuations/include/continuations/PayloadAccessQualifiers.h b/shared/continuations/include/continuations/PayloadAccessQualifiers.h
index 7b6dda331f..79b58e9996 100644
--- a/shared/continuations/include/continuations/PayloadAccessQualifiers.h
+++ b/shared/continuations/include/continuations/PayloadAccessQualifiers.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/shared/continuations/include/lgc/GpurtDialect.h b/shared/continuations/include/lgc/GpurtDialect.h
index 03b13c58bd..e25d2dd529 100644
--- a/shared/continuations/include/lgc/GpurtDialect.h
+++ b/shared/continuations/include/lgc/GpurtDialect.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/shared/continuations/include/lgc/GpurtDialect.td b/shared/continuations/include/lgc/GpurtDialect.td
index 6ad1435cea..4c4f6fb563 100644
--- a/shared/continuations/include/lgc/GpurtDialect.td
+++ b/shared/continuations/include/lgc/GpurtDialect.td
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -96,6 +96,12 @@ def GpurtLdsStackStoreOp : GpurtOp<"lds.stack.store", [Memory<[(write)]>, WillRe
}];
}
+def GpurtFloatWithRoundModeOp : GpurtOp<"rt.floatop.roundmode", [Memory<[]>, WillReturn]> {
+ let arguments = (ins I32:$roundMode, I32:$operation, (ScalarOrFixedVector F32):$src0, (eq $src0):$src1);
+ let results = (outs (eq $src0):$result);
+ let summary = "return result of floatOp with roundmode";
+}
+
def GpurtGetBoxSortHeuristicModeOp : GpurtOp<"get.box.sort.heuristic.mode", [Memory<[]>, WillReturn]> {
let arguments = (ins);
let results = (outs I32:$result);
diff --git a/shared/continuations/include/lgc/LgcCpsDialect.h b/shared/continuations/include/lgc/LgcCpsDialect.h
index e2c2134c10..d276e3c9d3 100644
--- a/shared/continuations/include/lgc/LgcCpsDialect.h
+++ b/shared/continuations/include/lgc/LgcCpsDialect.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/shared/continuations/include/lgc/LgcCpsDialect.td b/shared/continuations/include/lgc/LgcCpsDialect.td
index 5dd9c5d72c..3da4c56f3d 100644
--- a/shared/continuations/include/lgc/LgcCpsDialect.td
+++ b/shared/continuations/include/lgc/LgcCpsDialect.td
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/shared/continuations/include/lgc/LgcRtDialect.h b/shared/continuations/include/lgc/LgcRtDialect.h
index 1cd8c181c2..76ab2b2775 100644
--- a/shared/continuations/include/lgc/LgcRtDialect.h
+++ b/shared/continuations/include/lgc/LgcRtDialect.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -49,7 +49,8 @@ enum class RayTracingShaderStage {
Miss,
Callable,
// Not an input shader stage but we need to annotate it as well
- Traversal
+ Traversal,
+ KernelEntry
};
// Set shader stage metadata on a LLVM function and erase it by setting
@@ -87,7 +88,7 @@ void setShaderArgSize(llvm::Function *func, size_t size);
// Get attribute size (in bytes) metadata for a ray-tracing shader
// function.
-size_t getShaderHitAttributeSize(llvm::Function *func);
+size_t getShaderHitAttributeSize(const llvm::Function *func);
// Set attribute size (in bytes) metadata for a ray-tracing shader
// function.
diff --git a/shared/continuations/include/lgc/LgcRtDialect.td b/shared/continuations/include/lgc/LgcRtDialect.td
index c39514963e..2f88c5440e 100644
--- a/shared/continuations/include/lgc/LgcRtDialect.td
+++ b/shared/continuations/include/lgc/LgcRtDialect.td
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -304,9 +304,9 @@ def ShaderRecordBufferOp : LgcRtOp<"shader.record.buffer", [Memory<[]>, WillRetu
// =========================================================================================================
def BaseTraceRayOp : OpClass<LgcRtDialect> {
- let arguments = (ins I64:$accelStruct, I32:$rayFlags, I32:$instanceInclusionMask,
- I32:$rayContributionToHitGroupIndex, I32:$multiplierForGeometryContribution, I32:$missShaderIndex,
- V3F32:$origin, F32:$tMin, V3F32:$direction, F32:$tMax, PointerType:$payload, value:$paq);
+ let arguments = (ins I64:$accel_struct, I32:$ray_flags, I32:$instance_inclusion_mask,
+ I32:$ray_contribution_to_hit_group_index, I32:$multiplier_for_geometry_contribution, I32:$miss_shader_index,
+ V3F32:$origin, F32:$t_min, V3F32:$direction, F32:$t_max, PointerType:$payload, value:$paq);
let summary = "Trace a ray";
let description = [{
diff --git a/shared/continuations/lib/CleanupContinuations.cpp b/shared/continuations/lib/CleanupContinuations.cpp
index d5e2f67590..4efb803a97 100644
--- a/shared/continuations/lib/CleanupContinuations.cpp
+++ b/shared/continuations/lib/CleanupContinuations.cpp
@@ -3,13 +3,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -20,8 +20,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
//
@@ -64,6 +64,7 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
+#include "llvm/IR/Dominators.h"
#include "llvm/IR/InstIterator.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/Type.h"
@@ -76,8 +77,6 @@ using namespace lgc;
#define DEBUG_TYPE "cleanup-continuations"
-CleanupContinuationsPass::CleanupContinuationsPass() {}
-
/// Find the original call that created the continuation token and the matching
/// resume function for a return value.
///
@@ -200,8 +199,7 @@ void CleanupContinuationsPass::updateCpsStack(Function *F, Function *NewFunc,
}
SmallVector<Instruction *> ToBeRemoved;
- Value *OldBase = getContinuationFramePtr(F, IsStart, CpsInfo, ToBeRemoved);
-
+ Value *OldBase = getContinuationFramePtr(F, IsStart, CpsInfo, &ToBeRemoved);
replaceAllPointerUses(Builder, OldBase, CpsStack, ToBeRemoved);
for (auto *I : reverse(ToBeRemoved))
@@ -243,12 +241,15 @@ static void buildCpsArgInfos(Function *F, bool IsStart,
ArgNo++;
}
} else {
- // Add extra arguments ({} %state, i32 %rcr) for resume part. But for now,
- // we always use continuation stack to pass continuation state.
+ // Add extra arguments ({} %state, i32 %rcr, i32 %shader-index) for resume
+ // part. But for now, we always use continuation stack to pass continuation
+ // state.
AllArgTypes.push_back(StructType::get(Context, {}));
AllArgValues.push_back(nullptr);
AllArgTypes.push_back(IntegerType::get(Context, 32));
AllArgValues.push_back(nullptr);
+ AllArgTypes.push_back(IntegerType::get(Context, 32));
+ AllArgValues.push_back(nullptr);
// Find arguments from continuation.returnvalue calls
for (auto &I : F->getEntryBlock()) {
@@ -265,23 +266,20 @@ static void buildCpsArgInfos(Function *F, bool IsStart,
/// given as an argument
Value *CleanupContinuationsPass::getContinuationFramePtr(
Function *F, bool IsStart, const ContinuationData &ContinuationInfo,
- SmallVector<Instruction *> &InstsToRemove) {
+ SmallVector<Instruction *> *InstsToRemove) {
if (!ContinuationInfo.MallocCall)
return IsStart ? F->getArg(F->arg_size() - 1) : F->getArg(0);
if (IsStart) {
- InstsToRemove.push_back(ContinuationInfo.MallocCall);
-
- auto *BufferArg = F->getArg(F->arg_size() - 1);
- auto *Store = cast<Instruction>(BufferArg->getUniqueUndroppableUser());
- // Erase immediately to make later continuation stack setup easy.
- Store->eraseFromParent();
+ if (InstsToRemove)
+ InstsToRemove->push_back(ContinuationInfo.MallocCall);
return ContinuationInfo.MallocCall;
}
// Look for the load of the allocated pointer
Instruction *Load =
cast<Instruction>(F->getArg(0)->getUniqueUndroppableUser());
- InstsToRemove.push_back(Load); // Load needs to be eliminated
+ if (InstsToRemove)
+ InstsToRemove->push_back(Load); // Load needs to be eliminated
return Load;
}
@@ -331,7 +329,7 @@ void CleanupContinuationsPass::processContinuations() {
// b.) change the address space for cps stack to 32.
// 2. prepare arguments passed to cps.jump and insert the call at the exit of
// start part.
- // 3. Edit resume signature to add the state/rcr/returnvalues.
+ // 3. Edit resume signature to add the state/rcr/shader-indxe/returnvalues.
for (auto &FuncData : ToProcess) {
LLVM_DEBUG(dbgs() << "Processing function: " << FuncData.first->getName()
<< "\n");
@@ -414,6 +412,9 @@ void CleanupContinuationsPass::processContinuations() {
// Replace the old function with the new one.
F->replaceAllUsesWith(NewFunc);
+ // Update the `ToProcess` for later processing.
+ if (IsStart)
+ FuncData.first = NewFunc;
}
}
@@ -507,11 +508,61 @@ void CleanupContinuationsPass::handleSingleContinue(ContinuationData &Data,
}
}
+/// Lower lgc.rt calls inside cps functions.
+void CleanupContinuationsPass::lowerIntrinsicCall(Module &Mod) {
+ DenseMap<Function *, SmallVector<CallInst *>> CpsIntrinsicCalls;
+
+ // We only care about lgc.rt here.
+ for (auto &F : Mod.functions()) {
+ auto Name = F.getName();
+ if (!Name.starts_with("lgc.rt"))
+ continue;
+
+ llvm::forEachCall(F, [&](CallInst &CInst) {
+ auto IntrImplEntry = llvm::findIntrImplEntryByIntrinsicCall(&CInst);
+ if (IntrImplEntry == std::nullopt)
+ return;
+
+ auto *Caller = CInst.getFunction();
+ CpsIntrinsicCalls[Caller].push_back(&CInst);
+ });
+ }
+
+ CompilerUtils::CrossModuleInliner CrossInliner;
+ for (const auto &[Caller, IntrinsicCalls] : CpsIntrinsicCalls) {
+ // No need to insert system data alloca if no intrinsic call.
+ if (IntrinsicCalls.empty())
+ continue;
+
+ auto Stage = lgc::rt::getLgcRtShaderStage(Caller);
+ if (!Stage)
+ continue;
+ DXILShaderKind ShaderKind =
+ ShaderStageHelper::shaderStageToDxilShaderKind(*Stage);
+
+ // Signature of cps function: { state, rcr, shader-index, system-data}
+ auto *SystemDataArg = Caller->getArg(CpsArgIdxSystemData);
+ assert(SystemDataArg->getType()->isStructTy() &&
+ "SystemData should be struct type");
+ auto *AllocaInsertPt =
+ &*Caller->getEntryBlock().getFirstNonPHIOrDbgOrAlloca();
+ Builder->SetInsertPoint(AllocaInsertPt);
+ auto *SystemData = Builder->CreateAlloca(SystemDataArg->getType());
+ Builder->CreateStore(SystemDataArg, SystemData);
+ for (auto *Call : IntrinsicCalls)
+ replaceIntrinsicCall(*Builder, SystemDataArg->getType(), SystemData,
+ ShaderKind, Call, GpurtLibrary ? GpurtLibrary : &Mod,
+ CrossInliner);
+ }
+}
+
llvm::PreservedAnalyses
CleanupContinuationsPass::run(llvm::Module &Mod,
llvm::ModuleAnalysisManager &AnalysisManager) {
LLVM_DEBUG(dbgs() << "Run the lgc-cleanup-continuations pass\n");
AnalysisManager.getResult<DialectContextAnalysis>(Mod);
+ auto &FAM = AnalysisManager.getResult<FunctionAnalysisManagerModuleProxy>(Mod)
+ .getManager();
ToProcess.clear();
MaxContStateBytes = 0;
@@ -524,7 +575,7 @@ CleanupContinuationsPass::run(llvm::Module &Mod,
for (auto &F : Mod.functions()) {
if (F.empty())
continue;
- if (auto *MD = F.getMetadata(DXILContHelper::MDContinuationName))
+ if (auto *MD = F.getMetadata(ContHelper::MDContinuationName))
analyzeContinuation(F, MD);
}
@@ -548,8 +599,33 @@ CleanupContinuationsPass::run(llvm::Module &Mod,
}
}
+ // Erase store coroutine frame to make later continuation stack traversal
+ // easy.
+ for (auto &FuncData : ToProcess) {
+ if (!FuncData.second.MallocCall)
+ continue;
+ auto *StartF = FuncData.first;
+ auto *BufferArg = StartF->getArg(StartF->arg_size() - 1);
+ auto *Store = cast<Instruction>(BufferArg->getUniqueUndroppableUser());
+ Store->eraseFromParent();
+ }
+
+ // Try to do store->load forwarding here.
+ for (auto &FuncData : ToProcess) {
+ for (auto *F : FuncData.second.Functions) {
+ auto &DT = FAM.getResult<DominatorTreeAnalysis>(*F);
+ // If this is the continuation start part.
+ bool IsStart = (F == FuncData.first);
+ Value *ContFrame = getContinuationFramePtr(F, IsStart, FuncData.second);
+ // Traversal the users to forward store to load instruction.
+ forwardContinuationFrameStoreToLoad(DT, ContFrame);
+ }
+ }
+
if (!ToProcess.empty()) {
processContinuations();
+ // Lower lgc.rt intrinsics
+ lowerIntrinsicCall(Mod);
return PreservedAnalyses::none();
}
return PreservedAnalyses::all();
diff --git a/shared/continuations/lib/DXILCont.cpp b/shared/continuations/lib/Continuations.cpp
similarity index 63%
rename from shared/continuations/lib/DXILCont.cpp
rename to shared/continuations/lib/Continuations.cpp
index 077e6be5b1..3b22bec31f 100644
--- a/shared/continuations/lib/DXILCont.cpp
+++ b/shared/continuations/lib/Continuations.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,25 +18,31 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
-//===- DXILCont.cpp - Insert await calls and prepare DXIL -----------------===//
-//
-// This file serves as a caller for the LowerRaytracingPipelineImpl.
+//===- Continuations.cpp - Continuations utilities ------------------------===//
//
+// This file defines implementations for helper functions for continuation
+// passes.
//===----------------------------------------------------------------------===//
-#include "compilerutils/CompilerUtils.h"
#include "continuations/Continuations.h"
+#include "compilerutils/CompilerUtils.h"
#include "continuations/ContinuationsDialect.h"
#include "continuations/ContinuationsUtil.h"
#include "lgc/LgcCpsDialect.h"
#include "lgc/LgcRtDialect.h"
#include "llvm-dialects/Dialect/Builder.h"
#include "llvm-dialects/Dialect/Dialect.h"
+#include "llvm-dialects/Dialect/OpSet.h"
+#include "llvm/ADT/IntervalTree.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/IR/Function.h"
+#include "llvm/IR/Instructions.h"
+#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/IR/PassManager.h"
#include "llvm/Passes/PassBuilder.h"
#include "llvm/Support/ErrorHandling.h"
@@ -49,11 +55,389 @@
#include "llvm/Transforms/Scalar/SROA.h"
#include "llvm/Transforms/Scalar/SimplifyCFG.h"
#include "llvm/Transforms/Utils/FixIrreducible.h"
+#include "llvm/Transforms/Utils/LowerSwitch.h"
-#define DEBUG_TYPE "lower-raytracing-pipeline"
+#define DEBUG_TYPE "continuations"
using namespace llvm;
+#define GPURTMAP_ENTRY(Op, GpurtName, AccessesHitData) \
+ { \
+ llvm_dialects::OpDescription::get<lgc::rt::Op>(), { \
+ GpurtName, AccessesHitData \
+ } \
+ }
+
+const llvm_dialects::OpMap<llvm::GpuRtIntrinsicEntry> llvm::LgcRtGpuRtMap = {{
+ GPURTMAP_ENTRY(InstanceIdOp, "InstanceID", true),
+ GPURTMAP_ENTRY(InstanceIndexOp, "InstanceIndex", true),
+ GPURTMAP_ENTRY(HitKindOp, "HitKind", true),
+ GPURTMAP_ENTRY(RayFlagsOp, "RayFlags", false),
+ GPURTMAP_ENTRY(DispatchRaysIndexOp, "DispatchRaysIndex3", false),
+ GPURTMAP_ENTRY(DispatchRaysDimensionsOp, "DispatchRaysDimensions3", false),
+ GPURTMAP_ENTRY(WorldRayOriginOp, "WorldRayOrigin3", false),
+ GPURTMAP_ENTRY(WorldRayDirectionOp, "WorldRayDirection3", false),
+ GPURTMAP_ENTRY(ObjectRayOriginOp, "ObjectRayOrigin3", true),
+ GPURTMAP_ENTRY(ObjectRayDirectionOp, "ObjectRayDirection3", true),
+ GPURTMAP_ENTRY(ObjectToWorldOp, "ObjectToWorld4x3", true),
+ GPURTMAP_ENTRY(WorldToObjectOp, "WorldToObject4x3", true),
+ GPURTMAP_ENTRY(RayTminOp, "RayTMin", false),
+ GPURTMAP_ENTRY(RayTcurrentOp, "RayTCurrent", true),
+ GPURTMAP_ENTRY(IgnoreHitOp, "IgnoreHit", false),
+ GPURTMAP_ENTRY(AcceptHitAndEndSearchOp, "AcceptHitAndEndSearch", false),
+ GPURTMAP_ENTRY(TraceRayOp, "TraceRay", false),
+ GPURTMAP_ENTRY(ReportHitOp, "ReportHit", false),
+ GPURTMAP_ENTRY(CallCallableShaderOp, "CallShader", false),
+ GPURTMAP_ENTRY(PrimitiveIndexOp, "PrimitiveIndex", true),
+ GPURTMAP_ENTRY(GeometryIndexOp, "GeometryIndex", true),
+}};
+
+#undef GPURTMAP_ENTRY
+
+bool llvm::isLgcRtOp(const llvm::Function *F) {
+ return F && F->getName().starts_with("lgc.rt");
+}
+
+void llvm::moveFunctionBody(Function &OldFunc, Function &NewFunc) {
+ while (!OldFunc.empty()) {
+ BasicBlock *BB = &OldFunc.front();
+ BB->removeFromParent();
+ BB->insertInto(&NewFunc);
+ }
+}
+
+std::optional<llvm::GpuRtIntrinsicEntry>
+llvm::findIntrImplEntryByIntrinsicCall(CallInst *Call) {
+ if (!isLgcRtOp(Call->getCalledFunction()))
+ return std::nullopt;
+
+ auto ImplEntry = LgcRtGpuRtMap.find(*Call);
+ if (ImplEntry == LgcRtGpuRtMap.end())
+ report_fatal_error("Unhandled lgc.rt op!");
+
+ return *ImplEntry.val();
+}
+
+bool llvm::removeUnusedFunctionDecls(Module *Mod, bool OnlyIntrinsics) {
+ bool DidChange = false;
+
+ for (Function &F : make_early_inc_range(*Mod)) {
+ if (F.isDeclaration() && F.user_empty()) {
+ if (!OnlyIntrinsics ||
+ (isLgcRtOp(&F) || F.getName().starts_with("dx.op."))) {
+ F.eraseFromParent();
+ DidChange = true;
+ }
+ }
+ }
+
+ return DidChange;
+}
+
+bool ContHelper::isRematerializableLgcRtOp(CallInst &CInst,
+ std::optional<DXILShaderKind> Kind) {
+ using namespace lgc::rt;
+ Function *Callee = CInst.getCalledFunction();
+ if (!llvm::isLgcRtOp(Callee))
+ return false;
+
+ // Always rematerialize
+ static const llvm_dialects::OpSet RematerializableDialectOps =
+ llvm_dialects::OpSet::get<DispatchRaysDimensionsOp,
+ DispatchRaysIndexOp>();
+ if (RematerializableDialectOps.contains(*Callee))
+ return true;
+
+ // Rematerialize for Intersection that can only call ReportHit, which keeps
+ // the largest system data struct. These cannot be rematerialized in
+ // ClosestHit, because if ClosestHit calls TraceRay or CallShader, that
+ // information is lost from the system data struct. Also exclude rayTCurrent
+ // because ReportHit calls can change that.
+ if (!Kind || *Kind == DXILShaderKind::Intersection) {
+ static const llvm_dialects::OpSet RematerializableIntersectionDialectOps =
+ llvm_dialects::OpSet::get<
+ InstanceIdOp, InstanceIndexOp, GeometryIndexOp,
+ ObjectRayDirectionOp, ObjectRayOriginOp, ObjectToWorldOp,
+ PrimitiveIndexOp, RayFlagsOp, RayTminOp, WorldRayDirectionOp,
+ WorldRayOriginOp, WorldToObjectOp>();
+ if (RematerializableIntersectionDialectOps.contains(*Callee))
+ return true;
+ }
+
+ return false;
+}
+
+void llvm::replaceAllPointerUses(IRBuilder<> *Builder, Value *OldPointerValue,
+ Value *NewPointerValue,
+ SmallVectorImpl<Instruction *> &ToBeRemoved) {
+ // Note: The implementation explicitly supports typed pointers, which
+ // complicates some of the code below.
+
+ // Assert that both types are pointers that only differ in the address space.
+ PointerType *OldPtrTy = cast<PointerType>(OldPointerValue->getType());
+ PointerType *NewPtrTy = cast<PointerType>(NewPointerValue->getType());
+ unsigned NewAS = NewPtrTy->getAddressSpace();
+ assert(NewAS != OldPtrTy->getAddressSpace());
+ assert(getWithSamePointeeType(OldPtrTy, NewAS) == NewPtrTy);
+
+ OldPointerValue->mutateType(NewPtrTy);
+
+ // Traverse through the users and setup the addrspace
+ SmallVector<Value *> Worklist(OldPointerValue->users());
+ OldPointerValue->replaceAllUsesWith(NewPointerValue);
+
+ // Given a pointer type, get a pointer with the same pointee type (possibly
+ // opaque) as the given type that uses the NewAS address space.
+ auto GetMutatedPtrTy = [NewAS](Type *Ty) {
+ PointerType *PtrTy = cast<PointerType>(Ty);
+ // Support typed pointers:
+ return getWithSamePointeeType(PtrTy, NewAS);
+ };
+
+ while (!Worklist.empty()) {
+ Value *Ptr = Worklist.pop_back_val();
+ Instruction *Inst = cast<Instruction>(Ptr);
+ LLVM_DEBUG(dbgs() << "Visiting " << *Inst << '\n');
+ // In the switch below, "break" means to continue with replacing
+ // the users of the current value, while "continue" means to stop at
+ // the current value, and proceed with next one from the work list.
+ switch (Inst->getOpcode()) {
+ default:
+ LLVM_DEBUG(Inst->dump());
+ llvm_unreachable("Unhandled instruction\n");
+ break;
+ case Instruction::Call: {
+ if (Inst->isLifetimeStartOrEnd()) {
+ // The lifetime marker is not useful anymore.
+ Inst->eraseFromParent();
+ } else {
+ LLVM_DEBUG(Inst->dump());
+ llvm_unreachable("Unhandled call instruction\n");
+ }
+ // No further processing needed for the users.
+ continue;
+ }
+ case Instruction::Load:
+ case Instruction::Store:
+ // No further processing needed for the users.
+ continue;
+ case Instruction::And:
+ case Instruction::Add:
+ case Instruction::PtrToInt:
+ break;
+ case Instruction::BitCast: {
+ // This can happen with typed pointers
+ auto *BC = cast<BitCastOperator>(Inst);
+ assert(cast<BitCastOperator>(Inst)->getSrcTy()->isPointerTy() &&
+ BC->getDestTy()->isPointerTy());
+ Inst->mutateType(GetMutatedPtrTy(Inst->getType()));
+ break;
+ }
+ case Instruction::AddrSpaceCast:
+ // Check that the pointer operand has already been fixed
+ assert(Inst->getOperand(0)->getType()->getPointerAddressSpace() == NewAS);
+ // Push the correct users before RAUW.
+ Worklist.append(Ptr->users().begin(), Ptr->users().end());
+ Inst->mutateType(GetMutatedPtrTy(Inst->getType()));
+ // Since we are mutating the address spaces of users as well,
+ // we can just use the (already mutated) cast operand.
+ Inst->replaceAllUsesWith(Inst->getOperand(0));
+ ToBeRemoved.push_back(Inst);
+ continue;
+ case Instruction::IntToPtr:
+ case Instruction::GetElementPtr: {
+ Inst->mutateType(GetMutatedPtrTy(Inst->getType()));
+ break;
+ }
+ case Instruction::Select: {
+ auto *OldType = Inst->getType();
+ if (OldType->isPointerTy()) {
+ Type *NewType = GetMutatedPtrTy(OldType);
+ // No further processing if the type has the correct pointer type
+ if (NewType == OldType)
+ continue;
+
+ Inst->mutateType(NewType);
+ }
+ break;
+ }
+ }
+
+ Worklist.append(Ptr->users().begin(), Ptr->users().end());
+ }
+}
+
+void llvm::forwardContinuationFrameStoreToLoad(DominatorTree &DT,
+ Value *FramePtr) {
+ assert(FramePtr);
+
+ DenseMap<int64_t, SmallVector<LoadInst *>> OffsetLoadMap;
+ using StoreIntervalTree = IntervalTree<int64_t, StoreInst *>;
+ using IntervalTreeData = StoreIntervalTree::DataType;
+ StoreIntervalTree::Allocator Allocator;
+ StoreIntervalTree StoreIntervals(Allocator);
+ // While IntervalTree is efficient at answering which store would write to
+ // memory that fully cover the memory range that will be loaded [load_begin,
+ // load_end] by detecting the intervals that have intersection with both
+ // `load_begin` and `load_end`, but it is not good at answering whether there
+ // are stores that are strictly within the range (load_begin, load_end). So
+ // we introduce a sorted array to help detecting if there is conflicting
+ // store within the range (load_begin, load_end).
+ struct OffsetStorePair {
+ OffsetStorePair(int64_t Offset, StoreInst *Store)
+ : Offset(Offset), Store(Store) {}
+ int64_t Offset;
+ StoreInst *Store;
+ };
+ SmallVector<OffsetStorePair> SortedStores;
+
+ struct PointerUse {
+ PointerUse(Use *P, int64_t O) : Ptr(P), Offset(O) {}
+ // The Use of a particular pointer to be visited.
+ Use *Ptr;
+ // The byte offset to the base pointer.
+ int64_t Offset;
+ };
+ SmallVector<PointerUse> Worklist;
+ for (auto &U : FramePtr->uses())
+ Worklist.push_back(PointerUse(&U, 0));
+
+ while (!Worklist.empty()) {
+ PointerUse PtrUse = Worklist.pop_back_val();
+ User *U = PtrUse.Ptr->getUser();
+ switch (cast<Instruction>(U)->getOpcode()) {
+ case Instruction::GetElementPtr: {
+ auto *Gep = cast<GetElementPtrInst>(U);
+ const DataLayout &DL = Gep->getModule()->getDataLayout();
+ unsigned OffsetBitWidth = DL.getIndexSizeInBits(Gep->getAddressSpace());
+ APInt Offset(OffsetBitWidth, 0);
+ bool ConstantOffset = Gep->accumulateConstantOffset(
+ Gep->getModule()->getDataLayout(), Offset);
+ // Give up on dynamic indexes for simplicity.
+ if (!ConstantOffset)
+ return;
+
+ for (auto &UU : Gep->uses())
+ Worklist.push_back(
+ PointerUse(&UU, Offset.getSExtValue() + PtrUse.Offset));
+ break;
+ }
+ case Instruction::Load: {
+ auto *Load = cast<LoadInst>(U);
+ if (!Load->isSimple())
+ return;
+ SmallVector<LoadInst *> &Instrs = OffsetLoadMap[PtrUse.Offset];
+ Instrs.push_back(cast<LoadInst>(U));
+ break;
+ }
+ case Instruction::Store: {
+ auto *Store = cast<StoreInst>(U);
+ if (!Store->isSimple() || Store->getValueOperand() == PtrUse.Ptr->get())
+ return;
+
+ assert(Store->getPointerOperand() == PtrUse.Ptr->get());
+ const DataLayout &DL = Store->getModule()->getDataLayout();
+ unsigned StoredBytes =
+ DL.getTypeStoreSize(Store->getValueOperand()->getType());
+
+ SortedStores.push_back(OffsetStorePair(PtrUse.Offset, Store));
+ StoreIntervals.insert(PtrUse.Offset, PtrUse.Offset + StoredBytes - 1,
+ Store);
+ break;
+ }
+ case Instruction::BitCast:
+ case Instruction::AddrSpaceCast: {
+ for (auto &UU : cast<Instruction>(U)->uses())
+ Worklist.push_back(PointerUse(&UU, PtrUse.Offset));
+ break;
+ }
+ default:
+ LLVM_DEBUG(dbgs() << "Unhandled user of continuation frame pointer: "
+ << *U << '\n');
+ return;
+ }
+ }
+
+ StoreIntervals.create();
+ llvm::sort(SortedStores,
+ [](const OffsetStorePair &Left, const OffsetStorePair &Right) {
+ return Left.Offset < Right.Offset;
+ });
+
+ // Nothing to do if there is no store.
+ if (StoreIntervals.empty())
+ return;
+
+ for (const auto &[Offset, Loads] : OffsetLoadMap) {
+ assert(!Loads.empty());
+ auto IntersectionsLeft = StoreIntervals.getContaining(Offset);
+ // Nothing to do if there is no store or more than one store.
+ if (IntersectionsLeft.size() != 1)
+ continue;
+
+ const IntervalTreeData &StoreInfo = *IntersectionsLeft.front();
+ // The load and store are at different addresses, abort. This can be
+ // improved later.
+ if (Offset != StoreInfo.left())
+ continue;
+
+ for (auto *Load : Loads) {
+ const DataLayout &DL = Load->getModule()->getDataLayout();
+ unsigned LoadBytes = DL.getTypeStoreSize(Load->getType());
+ auto IntersectionsRight =
+ StoreIntervals.getContaining(Offset + LoadBytes - 1);
+ assert(!IntersectionsRight.empty());
+ // Make sure the store we found fully covers the loaded range and is the
+ // only one.
+ if (IntersectionsRight.size() != 1 ||
+ IntersectionsRight.front()->value() != StoreInfo.value())
+ continue;
+
+ StoreInst *Store = StoreInfo.value();
+ // Get the first iterator pointing to a value that is strictly greater
+ // than Offset.
+ auto *MaybeConflict = llvm::upper_bound(
+ SortedStores, Offset, [](int64_t V, const OffsetStorePair &Elem) {
+ return V < Elem.Offset;
+ });
+ // Abort if there is another store which write to the memory region
+ // strictly within the loaded region.
+ if (MaybeConflict != SortedStores.end() &&
+ MaybeConflict->Offset < StoreInfo.right())
+ continue;
+
+ // Currently we only forward if the value types are the same. This can
+ // be improved.
+ Type *StoredTy = Store->getValueOperand()->getType();
+ if (Load->getType() != StoredTy)
+ continue;
+ if (!DT.dominates(Store, Load))
+ continue;
+
+ auto *LoadPtr = Load->getPointerOperand();
+ Load->replaceAllUsesWith(Store->getValueOperand());
+ Load->eraseFromParent();
+
+ // Erase the possibly dead instruction which defines the pointer.
+ if (!LoadPtr->use_empty())
+ continue;
+ if (auto *PtrInstr = dyn_cast<Instruction>(LoadPtr))
+ PtrInstr->eraseFromParent();
+ }
+ }
+}
+
+PointerType *llvm::getWithSamePointeeType(PointerType *PtrTy,
+ unsigned AddressSpace) {
+#if LLVM_MAIN_REVISION && LLVM_MAIN_REVISION < 482880
+ return PointerType::getWithSamePointeeType(PtrTy, AddressSpace);
+#else
+ // New version of the code (also handles unknown version, which we treat as
+ // latest)
+ return PointerType::get(PtrTy->getContext(), AddressSpace);
+#endif
+}
+
static const char *toString(DXILShaderKind ShaderKind) {
switch (ShaderKind) {
case DXILShaderKind::Pixel:
@@ -100,7 +484,7 @@ llvm::raw_ostream &llvm::operator<<(llvm::raw_ostream &Str,
return Str;
}
-void DXILContHelper::RegisterPasses(PassBuilder &PB, bool NeedDialectContext) {
+void ContHelper::RegisterPasses(PassBuilder &PB, bool NeedDialectContext) {
#define HANDLE_PASS(NAME, CREATE_PASS) \
if (innerPipeline.empty() && name == NAME) { \
passMgr.addPass(CREATE_PASS); \
@@ -189,8 +573,8 @@ void DXILContHelper::RegisterPasses(PassBuilder &PB, bool NeedDialectContext) {
}
}
-void DXILContHelper::addContinuationPasses(ModulePassManager &MPM,
- Module *GpurtLibrary) {
+void ContHelper::addContinuationPasses(ModulePassManager &MPM,
+ Module *GpurtLibrary) {
// Inline functions into shaders, so everything is in a shader
MPM.addPass(AlwaysInlinerPass(/*InsertLifetimeIntrinsics=*/false));
@@ -214,6 +598,10 @@ void DXILContHelper::addContinuationPasses(ModulePassManager &MPM,
MPM.addPass(RemoveTypesMetadataPass());
+ // The FixIrreducible pass does not cope with switch instructions, so lower
+ // them before.
+ MPM.addPass(createModuleToFunctionPassAdaptor(LowerSwitchPass()));
+
// Splitting functions as part of LLVM's coroutine transformation can lead
// to irreducible resume functions in some cases. Use the FixIrreduciblePass
// to resolve the irreducibility with a dynamic dispatch block. In the future
@@ -224,8 +612,8 @@ void DXILContHelper::addContinuationPasses(ModulePassManager &MPM,
MPM.addPass(createModuleToFunctionPassAdaptor(FixIrreduciblePass()));
}
-void DXILContHelper::addDxilContinuationPasses(ModulePassManager &MPM,
- Module *GpurtLibrary) {
+void ContHelper::addDxilContinuationPasses(ModulePassManager &MPM,
+ Module *GpurtLibrary) {
MPM.addPass(DXILContPreHookPass());
// Translate dx.op intrinsic calls to lgc.rt dialect intrinsic calls
@@ -244,7 +632,7 @@ void DXILContHelper::addDxilContinuationPasses(ModulePassManager &MPM,
MPM.addPass(DXILContPostHookPass());
}
-void DXILContHelper::addDxilGpurtLibraryPasses(ModulePassManager &MPM) {
+void ContHelper::addDxilGpurtLibraryPasses(ModulePassManager &MPM) {
MPM.addPass(llvm::DXILContIntrinsicPreparePass());
MPM.addPass(AlwaysInlinerPass(/*InsertLifetimeIntrinsics=*/false));
@@ -300,7 +688,7 @@ llvm::continuationStackOffsetToPtr(IRBuilder<> &B, Value *Offset,
"Stack offset is expected to be an i32");
Module *M = B.GetInsertPoint()->getModule();
std::optional<ContStackAddrspace> StackAddrspace =
- DXILContHelper::tryGetStackAddrspace(*M);
+ ContHelper::tryGetStackAddrspace(*M);
if (!StackAddrspace)
report_fatal_error("Missing stack addrspace metadata!");
if (*StackAddrspace == ContStackAddrspace::Scratch)
@@ -321,8 +709,7 @@ llvm::continuationStackOffsetToPtr(IRBuilder<> &B, Value *Offset,
return B.CreateGEP(B.getInt8Ty(), BaseAddrPtr, Offset);
}
-Function *llvm::cloneFunctionHeaderWithTypes(Function &F,
- DXILContFuncTy &NewType,
+Function *llvm::cloneFunctionHeaderWithTypes(Function &F, ContFuncTy &NewType,
ArrayRef<AttributeSet> ArgAttrs) {
FunctionType *FuncTy = NewType.asFunctionType(F.getContext());
Function *NewFunc = CompilerUtils::cloneFunctionHeader(F, FuncTy, ArgAttrs);
@@ -370,10 +757,15 @@ bool llvm::fixupDxilMetadata(Module &M) {
}
for (auto &F : M.functions()) {
- if (auto *MD = F.getMetadata(DXILContHelper::MDContinuationName)) {
+ if (auto *MD = F.getMetadata(ContHelper::MDContinuationName)) {
if (auto *MDTup = dyn_cast_or_null<MDTuple>(MD))
Changed |= stripMDCasts(MDTup);
}
+
+ if (F.hasMetadata(ContHelper::MDContPayloadTyName)) {
+ F.setMetadata(ContHelper::MDContPayloadTyName, nullptr);
+ Changed = true;
+ }
}
return Changed;
@@ -720,13 +1112,13 @@ static void handleGetUninitialized(Function &Func) {
bool llvm::earlyDriverTransform(Module &M) {
// Import StackAddrspace from metadata if set, otherwise from default
- auto StackAddrspaceMD = DXILContHelper::tryGetStackAddrspace(M);
+ auto StackAddrspaceMD = ContHelper::tryGetStackAddrspace(M);
auto StackAddrspace =
- StackAddrspaceMD.value_or(DXILContHelper::DefaultStackAddrspace);
+ StackAddrspaceMD.value_or(ContHelper::DefaultStackAddrspace);
// Import from metadata if set
- auto RtipLevel = DXILContHelper::tryGetRtip(M);
- auto Flags = DXILContHelper::tryGetFlags(M);
+ auto RtipLevel = ContHelper::tryGetRtip(M);
+ auto Flags = ContHelper::tryGetFlags(M);
bool Changed = false;
// Replace Enqueue and Complete intrinsics
@@ -760,7 +1152,7 @@ bool llvm::earlyDriverTransform(Module &M) {
report_fatal_error(
"Tried to get rtip level but it is not available on the module");
handleGetRtip(F, *RtipLevel);
- } else if (Name.startswith("_AmdGetUninitialized")) {
+ } else if (Name.starts_with("_AmdGetUninitialized")) {
Changed = true;
handleGetUninitialized(F);
}
@@ -779,16 +1171,16 @@ llvm::computeNeededStackSizeForRegisterBuffer(uint64_t NumI32s,
return NumStackI32s * RegisterBytes;
}
-Type *llvm::getFuncArgPtrElementType(const Function *F, const Argument *Arg) {
+Type *llvm::getFuncArgPtrElementType(const Argument *Arg) {
auto *ArgTy = Arg->getType();
if (!ArgTy->isPointerTy())
return nullptr;
- return DXILContArgTy::get(F, Arg).getPointerElementType();
+ return ContArgTy::get(Arg->getParent(), Arg).getPointerElementType();
}
Type *llvm::getFuncArgPtrElementType(const Function *F, int ArgNo) {
- return getFuncArgPtrElementType(F, F->getArg(ArgNo));
+ return getFuncArgPtrElementType(F->getArg(ArgNo));
}
namespace llvm {
@@ -819,6 +1211,12 @@ bool llvm::LgcMaterializable(Instruction &OrigI) {
if (coro::defaultMaterializable(*V))
return true;
+ // Insert into constant.
+ if (isa<InsertElementInst, InsertValueInst>(V) &&
+ isa<Constant>(V->getOperand(0))) {
+ return true;
+ }
+
if (auto *LI = dyn_cast<LoadInst>(V)) {
// load from constant address space
if (LI->getPointerAddressSpace() == 4)
@@ -831,13 +1229,26 @@ bool llvm::LgcMaterializable(Instruction &OrigI) {
// be rematerialized are replaced by their implementation, so that the
// necessary values can be put into the coroutine frame. Therefore, we
// can assume all left-over intrinsics can be rematerialized.
- if (DXILContHelper::isRematerializableLgcRtOp(*CInst))
+ if (ContHelper::isRematerializableLgcRtOp(*CInst))
return true;
+ if (auto *Intrinsic = dyn_cast<IntrinsicInst>(CInst)) {
+ switch (Intrinsic->getIntrinsicID()) {
+ // Note: s_getpc will return a different value if rematerialized into a
+ // different place, but assuming we only care about the high 32bit for
+ // all the use cases we have now, it should be ok to do so.
+ case Intrinsic::amdgcn_s_getpc:
+ return true;
+ default:
+ break;
+ }
+ }
+
auto CalledName = CalledFunc->getName();
// FIXME: switch to dialectOp check.
- if (CalledName.startswith("lgc.user.data") ||
- CalledName.startswith("lgc.load.user.data"))
+ if (CalledName.starts_with("lgc.user.data") ||
+ CalledName.starts_with("lgc.shader.input") ||
+ CalledName.starts_with("lgc.load.user.data"))
return true;
}
}
diff --git a/shared/continuations/lib/ContinuationsDialect.cpp b/shared/continuations/lib/ContinuationsDialect.cpp
index cc788d500f..1d56d90af9 100644
--- a/shared/continuations/lib/ContinuationsDialect.cpp
+++ b/shared/continuations/lib/ContinuationsDialect.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/shared/continuations/lib/ContinuationsUtil.cpp b/shared/continuations/lib/ContinuationsUtil.cpp
deleted file mode 100644
index 2f50b6b57e..0000000000
--- a/shared/continuations/lib/ContinuationsUtil.cpp
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- ***********************************************************************************************************************
- *
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- *all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
- *
- **********************************************************************************************************************/
-
-//===- ContinuationsUtil.cpp - Continuations utilities -----------------===//
-//
-// This file defines implementations for helper functions for continuation
-// passes.
-//
-//===----------------------------------------------------------------------===//
-
-#include "continuations/ContinuationsUtil.h"
-#include "lgc/LgcRtDialect.h"
-#include "llvm-dialects/Dialect/OpSet.h"
-#include "llvm/ADT/STLExtras.h"
-#include "llvm/IR/Function.h"
-#include "llvm/IR/Instructions.h"
-
-#define DEBUG_TYPE "continuations-util"
-
-#define GPURTMAP_ENTRY(Op, GpurtName, AccessesHitData) \
- { \
- OpDescription::get<lgc::rt::Op>(), { GpurtName, AccessesHitData } \
- }
-
-const OpMap<llvm::GpuRtIntrinsicEntry> llvm::LgcRtGpuRtMap = {{
- GPURTMAP_ENTRY(InstanceIdOp, "InstanceID", true),
- GPURTMAP_ENTRY(InstanceIndexOp, "InstanceIndex", true),
- GPURTMAP_ENTRY(HitKindOp, "HitKind", true),
- GPURTMAP_ENTRY(RayFlagsOp, "RayFlags", false),
- GPURTMAP_ENTRY(DispatchRaysIndexOp, "DispatchRaysIndex3", false),
- GPURTMAP_ENTRY(DispatchRaysDimensionsOp, "DispatchRaysDimensions3", false),
- GPURTMAP_ENTRY(WorldRayOriginOp, "WorldRayOrigin3", false),
- GPURTMAP_ENTRY(WorldRayDirectionOp, "WorldRayDirection3", false),
- GPURTMAP_ENTRY(ObjectRayOriginOp, "ObjectRayOrigin3", true),
- GPURTMAP_ENTRY(ObjectRayDirectionOp, "ObjectRayDirection3", true),
- GPURTMAP_ENTRY(ObjectToWorldOp, "ObjectToWorld4x3", true),
- GPURTMAP_ENTRY(WorldToObjectOp, "WorldToObject4x3", true),
- GPURTMAP_ENTRY(RayTminOp, "RayTMin", false),
- GPURTMAP_ENTRY(RayTcurrentOp, "RayTCurrent", true),
- GPURTMAP_ENTRY(IgnoreHitOp, "IgnoreHit", false),
- GPURTMAP_ENTRY(AcceptHitAndEndSearchOp, "AcceptHitAndEndSearch", false),
- GPURTMAP_ENTRY(TraceRayOp, "TraceRay", false),
- GPURTMAP_ENTRY(ReportHitOp, "ReportHit", false),
- GPURTMAP_ENTRY(CallCallableShaderOp, "CallShader", false),
- GPURTMAP_ENTRY(PrimitiveIndexOp, "PrimitiveIndex", true),
- GPURTMAP_ENTRY(GeometryIndexOp, "GeometryIndex", true),
-}};
-
-#undef GPURTMAP_ENTRY
-
-llvm::StringRef DialectUtils::getLgcRtDialectOpName(llvm::StringRef FullName) {
- return FullName.substr(std::strlen("lgc.rt."));
-}
-
-bool DialectUtils::isLgcRtOp(const llvm::Function *F) {
- return F && F->getName().starts_with("lgc.rt");
-}
-
-void llvm::moveFunctionBody(Function &OldFunc, Function &NewFunc) {
- while (!OldFunc.empty()) {
- BasicBlock *BB = &OldFunc.front();
- BB->removeFromParent();
- BB->insertInto(&NewFunc);
- }
-}
-
-std::optional<llvm::GpuRtIntrinsicEntry>
-llvm::findIntrImplEntryByIntrinsicCall(CallInst *Call) {
- if (!DialectUtils::isLgcRtOp(Call->getCalledFunction()))
- return std::nullopt;
-
- auto ImplEntry = LgcRtGpuRtMap.find(*Call);
- if (ImplEntry == LgcRtGpuRtMap.end())
- report_fatal_error("Unhandled lgc.rt op!");
-
- return *ImplEntry.val();
-}
-
-bool llvm::removeUnusedFunctionDecls(Module *Mod, bool OnlyIntrinsics) {
- bool DidChange = false;
-
- for (Function &F : make_early_inc_range(*Mod)) {
- if (F.isDeclaration() && F.user_empty()) {
- if (!OnlyIntrinsics ||
- (DialectUtils::isLgcRtOp(&F) || F.getName().starts_with("dx.op."))) {
- F.eraseFromParent();
- DidChange = true;
- }
- }
- }
-
- return DidChange;
-}
-
-bool DXILContHelper::isRematerializableLgcRtOp(
- CallInst &CInst, std::optional<DXILShaderKind> Kind) {
- using namespace lgc::rt;
- Function *Callee = CInst.getCalledFunction();
- if (!DialectUtils::isLgcRtOp(Callee))
- return false;
-
- // Always rematerialize
- static const OpSet RematerializableDialectOps =
- OpSet::get<DispatchRaysDimensionsOp, DispatchRaysIndexOp>();
- if (RematerializableDialectOps.contains(*Callee))
- return true;
-
- // Rematerialize for Intersection that can only call ReportHit, which keeps
- // the largest system data struct. These cannot be rematerialized in
- // ClosestHit, because if ClosestHit calls TraceRay or CallShader, that
- // information is lost from the system data struct. Also exclude rayTCurrent
- // because ReportHit calls can change that.
- if (!Kind || *Kind == DXILShaderKind::Intersection) {
- static const OpSet RematerializableIntersectionDialectOps =
- OpSet::get<InstanceIdOp, InstanceIndexOp, GeometryIndexOp,
- ObjectRayDirectionOp, ObjectRayOriginOp, ObjectToWorldOp,
- PrimitiveIndexOp, RayFlagsOp, RayTminOp, WorldRayDirectionOp,
- WorldRayOriginOp, WorldToObjectOp>();
- if (RematerializableIntersectionDialectOps.contains(*Callee))
- return true;
- }
-
- return false;
-}
-
-void llvm::replaceAllPointerUses(IRBuilder<> *Builder, Value *OldPointerValue,
- Value *NewPointerValue,
- SmallVectorImpl<Instruction *> &ToBeRemoved) {
- // Note: The implementation explicitly supports typed pointers, which
- // complicates some of the code below.
-
- // Assert that both types are pointers that only differ in the address space.
- PointerType *OldPtrTy = cast<PointerType>(OldPointerValue->getType());
- PointerType *NewPtrTy = cast<PointerType>(NewPointerValue->getType());
- unsigned NewAS = NewPtrTy->getAddressSpace();
- assert(NewAS != OldPtrTy->getAddressSpace());
- assert(getWithSamePointeeType(OldPtrTy, NewAS) == NewPtrTy);
-
- OldPointerValue->mutateType(NewPtrTy);
-
- // Traverse through the users and setup the addrspace
- SmallVector<Value *> Worklist(OldPointerValue->users());
- OldPointerValue->replaceAllUsesWith(NewPointerValue);
-
- // Given a pointer type, get a pointer with the same pointee type (possibly
- // opaque) as the given type that uses the NewAS address space.
- auto GetMutatedPtrTy = [NewAS](Type *Ty) {
- PointerType *PtrTy = cast<PointerType>(Ty);
- // Support typed pointers:
- return getWithSamePointeeType(PtrTy, NewAS);
- };
-
- while (!Worklist.empty()) {
- Value *Ptr = Worklist.pop_back_val();
- Instruction *Inst = cast<Instruction>(Ptr);
- LLVM_DEBUG(dbgs() << "Visiting " << *Inst << '\n');
- // In the switch below, "break" means to continue with replacing
- // the users of the current value, while "continue" means to stop at
- // the current value, and proceed with next one from the work list.
- switch (Inst->getOpcode()) {
- default:
- LLVM_DEBUG(Inst->dump());
- llvm_unreachable("Unhandled instruction\n");
- break;
- case Instruction::Call: {
- if (Inst->isLifetimeStartOrEnd()) {
- // The lifetime marker is not useful anymore.
- Inst->eraseFromParent();
- } else {
- LLVM_DEBUG(Inst->dump());
- llvm_unreachable("Unhandled call instruction\n");
- }
- // No further processing needed for the users.
- continue;
- }
- case Instruction::Load:
- case Instruction::Store:
- // No further processing needed for the users.
- continue;
- case Instruction::And:
- case Instruction::Add:
- case Instruction::PtrToInt:
- break;
- case Instruction::BitCast: {
- // This can happen with typed pointers
- auto *BC = cast<BitCastOperator>(Inst);
- assert(cast<BitCastOperator>(Inst)->getSrcTy()->isPointerTy() &&
- BC->getDestTy()->isPointerTy());
- Inst->mutateType(GetMutatedPtrTy(Inst->getType()));
- break;
- }
- case Instruction::AddrSpaceCast:
- // Check that the pointer operand has already been fixed
- assert(Inst->getOperand(0)->getType()->getPointerAddressSpace() == NewAS);
- // Push the correct users before RAUW.
- Worklist.append(Ptr->users().begin(), Ptr->users().end());
- Inst->mutateType(GetMutatedPtrTy(Inst->getType()));
- // Since we are mutating the address spaces of users as well,
- // we can just use the (already mutated) cast operand.
- Inst->replaceAllUsesWith(Inst->getOperand(0));
- ToBeRemoved.push_back(Inst);
- continue;
- case Instruction::IntToPtr:
- case Instruction::GetElementPtr: {
- Inst->mutateType(GetMutatedPtrTy(Inst->getType()));
- break;
- }
- case Instruction::Select: {
- auto *OldType = Inst->getType();
- if (OldType->isPointerTy()) {
- Type *NewType = GetMutatedPtrTy(OldType);
- // No further processing if the type has the correct pointer type
- if (NewType == OldType)
- continue;
-
- Inst->mutateType(NewType);
- }
- break;
- }
- }
-
- Worklist.append(Ptr->users().begin(), Ptr->users().end());
- }
-}
-
-PointerType *llvm::getWithSamePointeeType(PointerType *PtrTy,
- unsigned AddressSpace) {
-#if LLVM_MAIN_REVISION && LLVM_MAIN_REVISION < 482880
- return PointerType::getWithSamePointeeType(PtrTy, AddressSpace);
-#else
- // New version of the code (also handles unknown version, which we treat as
- // latest)
- return PointerType::get(PtrTy->getContext(), AddressSpace);
-#endif
-}
diff --git a/shared/continuations/lib/CpsStackLowering.cpp b/shared/continuations/lib/CpsStackLowering.cpp
index 5cfddfc4ec..ecb5b4bac7 100644
--- a/shared/continuations/lib/CpsStackLowering.cpp
+++ b/shared/continuations/lib/CpsStackLowering.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,36 +18,31 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
#include "continuations/CpsStackLowering.h"
+#include "continuations/ContinuationsUtil.h"
+#include "lgc/LgcCpsDialect.h"
#include "llvm-dialects/Dialect/Visitor.h"
#include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/Instructions.h"
#include "llvm/IR/Type.h"
-#include <functional>
using namespace llvm;
using namespace lgc::cps;
LLVM_DIALECTS_VISITOR_PAYLOAD_PROJECT_FIELD(CpsStackLowering, TypeLower)
-// =====================================================================================================================
-// Type lowering rule that lowers cps stack pointer type to corresponding
-// backend pointer type.
-//
-// @param typeLowering : the calling TypeLowering object
-// @param type : the type to be converted
SmallVector<Type *>
-CpsStackLowering::convertCpsStackPointer(TypeLowering &TypeLower, Type *Ty) {
+CpsStackLowering::convertStackPtrToI32(TypeLowering &TypeLower, Type *Ty) {
SmallVector<Type *> Types;
if (auto *PtrTy = dyn_cast<PointerType>(Ty)) {
if (PtrTy->getAddressSpace() == lgc::cps::stackAddrSpace)
- Types.push_back(
- PointerType::get(Ty->getContext(), LoweredCpsStackAddrSpace));
+ Types.push_back(Type::getInt32Ty(TypeLower.getContext()));
}
return Types;
@@ -59,11 +54,15 @@ CpsStackLowering::convertCpsStackPointer(TypeLowering &TypeLower, Type *Ty) {
// @param Function : the function to be processed
// @param CpsStorage : the alloca used for the holding the latest continuation
// stack pointer
-void CpsStackLowering::lowerCpsStackOps(Function &Function, Value *CpsStorage) {
+// @return: The new function, if Function was mutated, or the Function argument.
+Function *CpsStackLowering::lowerCpsStackOps(Function &Function,
+ Value *CpsStorage) {
+ assert(cast<AllocaInst>(CpsStorage)->getAllocatedType()->isIntegerTy());
+
Mod = Function.getParent();
StackSizeInBytes = 0;
- CpsStackAlloca = CpsStorage;
- TypeLower.addRule(std::bind(&CpsStackLowering::convertCpsStackPointer, this,
+ CpsStackAlloca = cast<AllocaInst>(CpsStorage);
+ TypeLower.addRule(std::bind(&CpsStackLowering::convertStackPtrToI32, this,
std::placeholders::_1, std::placeholders::_2));
auto *NewFunc = &Function;
if (lgc::cps::isCpsFunction(Function))
@@ -79,110 +78,152 @@ void CpsStackLowering::lowerCpsStackOps(Function &Function, Value *CpsStorage) {
.add(&CpsStackLowering::visitGetElementPtr)
.add(&CpsStackLowering::visitPtrToIntInst)
.add(&CpsStackLowering::visitIntToPtrInst)
+ .add(&CpsStackLowering::visitBitCastInst)
.add(&CpsStackLowering::visitLoad)
.add(&CpsStackLowering::visitStore)
.build();
Visitor.visit(*this, *NewFunc);
TypeLower.finishPhis();
TypeLower.finishCleanup();
+
+ return NewFunc;
}
// =====================================================================================================================
// Lower getelementptr instruction
//
-// @param function : the instruction
+// @param GEP: the instruction
void CpsStackLowering::visitGetElementPtr(GetElementPtrInst &GEP) {
if (GEP.getAddressSpace() != lgc::cps::stackAddrSpace)
return;
IRBuilder<> Builder(&GEP);
- SmallVector<Value *, 8> Indices(GEP.idx_begin(), GEP.idx_end());
-
- Value *NewGEP = nullptr;
auto Values = TypeLower.getValue(GEP.getPointerOperand());
- auto *GEPVal = Values[0];
- auto *GEPTy = GEP.getSourceElementType();
+ Value *AddChain = Values[0];
- if (GEP.isInBounds())
- NewGEP = Builder.CreateInBoundsGEP(GEPTy, GEPVal, Indices);
- else
- NewGEP = Builder.CreateGEP(GEPTy, GEPVal, Indices);
+ const DataLayout &DL = GEP.getFunction()->getParent()->getDataLayout();
+ unsigned BitWidth = DL.getIndexSizeInBits(GEP.getPointerAddressSpace());
- cast<Instruction>(NewGEP)->copyMetadata(GEP);
+ APInt ConstantOffset{BitWidth, 0};
+ MapVector<Value *, APInt> VariableOffsets;
+
+ [[maybe_unused]] bool Success =
+ GEP.collectOffset(DL, BitWidth, VariableOffsets, ConstantOffset);
+ assert(Success && "CpsStackLowering::visitGetElementPtr: GEP.collectOffset "
+ "did not succeed!");
+
+ if (ConstantOffset.getSExtValue() != 0)
+ AddChain = Builder.CreateAdd(
+ AddChain, Builder.getInt32(ConstantOffset.getSExtValue()));
+
+ for (const auto &[Index, Scaling] : VariableOffsets) {
+ Value *ScaledVal = Index;
+
+ if (Scaling.getSExtValue() != 1)
+ ScaledVal =
+ Builder.CreateMul(Index, Builder.getInt32(Scaling.getSExtValue()));
+
+ AddChain = Builder.CreateAdd(AddChain, ScaledVal);
+ }
- TypeLower.replaceInstruction(&GEP, {NewGEP});
+ TypeLower.replaceInstruction(&GEP, {AddChain});
}
// =====================================================================================================================
// Lower load instruction
//
-// @param function : the instruction
+// @param Load: the instruction
void CpsStackLowering::visitLoad(LoadInst &Load) {
if (Load.getPointerAddressSpace() != lgc::cps::stackAddrSpace)
return;
auto Values = TypeLower.getValue(Load.getPointerOperand());
+
+ IRBuilder<> Builder(&Load);
+ Values[0] = getRealMemoryAddress(Builder, Values[0]);
+
Load.replaceUsesOfWith(Load.getPointerOperand(), Values[0]);
}
// =====================================================================================================================
// Lower store instruction
//
-// @param function : the instruction
+// @param Store: the instruction
void CpsStackLowering::visitStore(llvm::StoreInst &Store) {
if (Store.getPointerAddressSpace() != lgc::cps::stackAddrSpace)
return;
auto Values = TypeLower.getValue(Store.getPointerOperand());
+
+ IRBuilder<> Builder(&Store);
+ Values[0] = getRealMemoryAddress(Builder, Values[0]);
+
Store.replaceUsesOfWith(Store.getPointerOperand(), Values[0]);
}
// =====================================================================================================================
// Lower ptrtoint instruction
//
-// @param function : the instruction
+// @param Ptr2Int: the instruction
void CpsStackLowering::visitPtrToIntInst(llvm::PtrToIntInst &Ptr2Int) {
if (Ptr2Int.getPointerAddressSpace() != lgc::cps::stackAddrSpace)
return;
auto Values = TypeLower.getValue(Ptr2Int.getOperand(0));
- Ptr2Int.replaceUsesOfWith(Ptr2Int.getOperand(0), Values[0]);
+ Ptr2Int.replaceAllUsesWith(Values[0]);
+ TypeLower.eraseInstruction(&Ptr2Int);
}
// =====================================================================================================================
// Lower inttoptr instruction
//
-// @param function : the instruction
+// @param Int2Ptr: the instruction
void CpsStackLowering::visitIntToPtrInst(llvm::IntToPtrInst &Int2Ptr) {
if (Int2Ptr.getAddressSpace() != lgc::cps::stackAddrSpace)
return;
- IRBuilder<> Builder(&Int2Ptr);
- auto *NewPtr = Builder.CreateIntToPtr(
- Int2Ptr.getOperand(0),
- PointerType::get(Builder.getContext(), LoweredCpsStackAddrSpace));
- TypeLower.replaceInstruction(&Int2Ptr, NewPtr);
+ TypeLower.replaceInstruction(&Int2Ptr, Int2Ptr.getOperand(0));
+}
+
+// =====================================================================================================================
+// Lower bitcast instruction
+//
+// @param BC: the instruction
+void CpsStackLowering::visitBitCastInst(llvm::BitCastInst &BC) {
+ Type *SrcTy = BC.getOperand(0)->getType();
+ if (!SrcTy->isPointerTy() ||
+ cast<PointerType>(SrcTy)->getAddressSpace() != lgc::cps::stackAddrSpace)
+ return;
+
+ Type *DstTy = BC.getType();
+ if (!DstTy->isPointerTy() ||
+ cast<PointerType>(DstTy)->getAddressSpace() != lgc::cps::stackAddrSpace)
+ return;
+
+ auto Values = TypeLower.getValue(BC.getOperand(0));
+ TypeLower.replaceInstruction(&BC, {Values[0]});
}
// =====================================================================================================================
// Lower lgc.cps.alloc instruction
//
-// @param function : the instruction
+// @param AllocOp: the instruction
void CpsStackLowering::visitCpsAlloc(lgc::cps::AllocOp &AllocOp) {
IRBuilder<> Builder(&AllocOp);
+ Value *VSP =
+ Builder.CreateLoad(CpsStackAlloca->getAllocatedType(), CpsStackAlloca);
+
Value *Size = AllocOp.getSize();
- Value *VSP = Builder.CreateLoad(Builder.getPtrTy(LoweredCpsStackAddrSpace),
- CpsStackAlloca);
- unsigned AlignedSize = alignTo(cast<ConstantInt>(Size)->getZExtValue(),
- ContinuationStackAlignment);
+ int AlignedSize = cast<ConstantInt>(Size)->getSExtValue();
+ assert(AlignedSize >= 0);
+ AlignedSize = alignTo(AlignedSize, ContinuationStackAlignment);
StackSizeInBytes += AlignedSize;
// update stack pointer
- Value *Ptr =
- Builder.CreateConstGEP1_32(Builder.getInt8Ty(), VSP, AlignedSize);
- Builder.CreateStore(Ptr, CpsStackAlloca);
+ Value *NewVSP = Builder.CreateAdd(VSP, Builder.getInt32(AlignedSize));
+ Builder.CreateStore(NewVSP, CpsStackAlloca);
TypeLower.replaceInstruction(&AllocOp, {VSP});
}
@@ -190,17 +231,19 @@ void CpsStackLowering::visitCpsAlloc(lgc::cps::AllocOp &AllocOp) {
// =====================================================================================================================
// Lower lgc.cps.free instruction
//
-// @param function : the instruction
+// @param FreeOp: the instruction
void CpsStackLowering::visitCpsFree(lgc::cps::FreeOp &FreeOp) {
IRBuilder<> Builder(&FreeOp);
- Value *VSP = Builder.CreateLoad(Builder.getPtrTy(LoweredCpsStackAddrSpace),
- CpsStackAlloca);
+ Value *VSP =
+ Builder.CreateLoad(CpsStackAlloca->getAllocatedType(), CpsStackAlloca);
+
Value *Size = FreeOp.getSize();
- unsigned AlignedSize = alignTo(cast<ConstantInt>(Size)->getZExtValue(),
- ContinuationStackAlignment);
- Value *Ptr =
- Builder.CreateConstGEP1_32(Builder.getInt8Ty(), VSP, -AlignedSize);
+ int AlignedSize = cast<ConstantInt>(Size)->getSExtValue();
+ assert(AlignedSize >= 0);
+ AlignedSize = alignTo(AlignedSize, ContinuationStackAlignment);
+ Value *Ptr = Builder.CreateAdd(VSP, Builder.getInt32(-AlignedSize));
+
// Assuming continuation stack grows upward.
Builder.CreateStore(Ptr, CpsStackAlloca);
TypeLower.replaceInstruction(&FreeOp, {});
@@ -209,18 +252,19 @@ void CpsStackLowering::visitCpsFree(lgc::cps::FreeOp &FreeOp) {
// =====================================================================================================================
// Lower lgc.cps.peek instruction
//
-// @param function : the instruction
+// @param PeekOp: the instruction
void CpsStackLowering::visitCpsPeek(lgc::cps::PeekOp &PeekOp) {
IRBuilder<> Builder(&PeekOp);
- auto *Ptr = Builder.CreateLoad(Builder.getPtrTy(LoweredCpsStackAddrSpace),
- CpsStackAlloca);
+ auto *Ptr =
+ Builder.CreateLoad(CpsStackAlloca->getAllocatedType(), CpsStackAlloca);
auto *Size = PeekOp.getSize();
- unsigned ImmSize = cast<ConstantInt>(Size)->getZExtValue();
+ int ImmSize = cast<ConstantInt>(Size)->getSExtValue();
+ assert(ImmSize >= 0);
ImmSize = alignTo(ImmSize, ContinuationStackAlignment);
// Assuming continuation stack grows upward.
- auto *Result =
- Builder.CreateGEP(Builder.getInt8Ty(), Ptr, {Builder.getInt32(-ImmSize)});
+ auto *Result = Builder.CreateAdd(Ptr, Builder.getInt32(-ImmSize));
+
TypeLower.replaceInstruction(&PeekOp, {Result});
}
@@ -229,22 +273,41 @@ void CpsStackLowering::visitCpsPeek(lgc::cps::PeekOp &PeekOp) {
//
// @param function : the instruction
void CpsStackLowering::visitSetVsp(lgc::cps::SetVspOp &SetVsp) {
+ auto *Ptr = SetVsp.getPtr();
+
IRBuilder<> B(&SetVsp);
- auto *Ptr = SetVsp.getPtr();
- auto Converted = TypeLower.getValue(Ptr);
- B.CreateStore(Converted[0], CpsStackAlloca);
+ auto Values = TypeLower.getValue(Ptr);
+ B.CreateStore(Values[0], CpsStackAlloca);
TypeLower.replaceInstruction(&SetVsp, {});
}
// =====================================================================================================================
// Lower lgc.cps.get.VSP instruction
//
-// @param function : the instruction
+// @param GetVsp: the instruction
void CpsStackLowering::visitGetVsp(lgc::cps::GetVspOp &GetVsp) {
IRBuilder<> B(&GetVsp);
- auto *Ptr =
- B.CreateLoad(B.getPtrTy(LoweredCpsStackAddrSpace), CpsStackAlloca);
+ auto *Ptr = B.CreateLoad(CpsStackAlloca->getAllocatedType(), CpsStackAlloca);
TypeLower.replaceInstruction(&GetVsp, {Ptr});
}
+
+// =====================================================================================================================
+// Create a target address space-specific pointer based on an offset pointer
+// (@Val) and a given base pointer, that is either the default null base pointer
+// or a base pointer injected by calling @setRealBasePointer.
+//
+// @param Builder: the builder to use.
+// @param Val: The offset to the base address, given as integer with bitwidth
+// <= 32.
+//
+Value *CpsStackLowering::getRealMemoryAddress(IRBuilder<> &Builder,
+ Value *Val) {
+ // Since we are using at most 32-bit offsets, assert that we don't put in any
+ // offset larger 32 bit.
+ assert(Val->getType()->isIntegerTy() &&
+ Val->getType()->getIntegerBitWidth() <= 32);
+ return Builder.CreateGEP(Type::getInt8Ty(Builder.getContext()), BasePointer,
+ {Val});
+}
diff --git a/shared/continuations/lib/DXILContIntrinsicPrepare.cpp b/shared/continuations/lib/DXILContIntrinsicPrepare.cpp
index a58d91f53c..8598d7a081 100644
--- a/shared/continuations/lib/DXILContIntrinsicPrepare.cpp
+++ b/shared/continuations/lib/DXILContIntrinsicPrepare.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -78,7 +78,7 @@ static Function *transformFunction(Function &F) {
LLVM_DEBUG(dbgs() << " Set new name " << NewName << "\n");
// Change the return type and arguments
- SmallVector<DXILContArgTy> AllArgTypes;
+ SmallVector<ContArgTy> AllArgTypes;
Type *NewRetTy = F.getReturnType();
@@ -93,9 +93,11 @@ static Function *transformFunction(Function &F) {
}
}
- // TODO Remove old name when possible
- if (NewName == "_cont_Traversal" || Name == "amd.dx.TraversalImpl")
+ if (NewName == "_cont_Traversal")
lgc::rt::setLgcRtShaderStage(&F, lgc::rt::RayTracingShaderStage::Traversal);
+ else if (NewName == "_cont_KernelEntry")
+ lgc::rt::setLgcRtShaderStage(&F,
+ lgc::rt::RayTracingShaderStage::KernelEntry);
Argument *RetArg = nullptr;
AttributeList FAttrs = F.getAttributes();
@@ -103,7 +105,7 @@ static Function *transformFunction(Function &F) {
unsigned ArgNo = 0;
for (auto &Arg : F.args()) {
- DXILContArgTy ArgTy = DXILContArgTy::get(&F, &Arg);
+ ContArgTy ArgTy = ContArgTy::get(&F, &Arg);
bool DidHandleArg = false;
@@ -138,7 +140,7 @@ static Function *transformFunction(Function &F) {
}
// Create new empty function
- DXILContFuncTy NewFuncTy(NewRetTy, AllArgTypes);
+ ContFuncTy NewFuncTy(NewRetTy, AllArgTypes);
Function *NewFunc = cloneFunctionHeaderWithTypes(F, NewFuncTy, ParamAttrs);
// Remove old name for the case that the new name is the same
@@ -300,6 +302,7 @@ static bool isUtilFunction(StringRef Name) {
"GetUninitialized",
"I32Count",
"IsEndSearch",
+ "KernelEntry",
"ReportHit",
"RestoreSystemData",
"SetI32",
@@ -325,7 +328,7 @@ llvm::PreservedAnalyses DXILContIntrinsicPreparePass::run(
for (auto *F : Funcs) {
auto Name = F->getName();
- bool IsContImpl = Name.contains("_cont_") || Name.contains("amd.dx.");
+ bool IsContImpl = Name.contains("_cont_");
bool ShouldTransform = false;
if (IsContImpl) {
diff --git a/shared/continuations/lib/DXILContLgcRtOpConverter.cpp b/shared/continuations/lib/DXILContLgcRtOpConverter.cpp
index 993a38bde1..75d246066b 100644
--- a/shared/continuations/lib/DXILContLgcRtOpConverter.cpp
+++ b/shared/continuations/lib/DXILContLgcRtOpConverter.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -441,16 +441,16 @@ void DXILContLgcRtOpConverterPass::addDXILPayloadTypeToCall(Function &DXILFunc,
auto *PayloadPtr = DXILFunc.getArg(DXILFunc.arg_size() - 1);
auto *PayloadPtrTy =
- DXILContArgTy::get(&DXILFunc, PayloadPtr).getPointerElementType();
+ ContArgTy::get(&DXILFunc, PayloadPtr).getPointerElementType();
// Store a poison value as metadata with the given type.
CI.setMetadata(
- DXILContHelper::MDDXILPayloadTyName,
+ ContHelper::MDContPayloadTyName,
MDNode::get(CI.getContext(),
{ConstantAsMetadata::get(PoisonValue::get(PayloadPtrTy))}));
}
-bool DXILContLgcRtOpConverterPass::processFunction(Function &Func) {
+bool DXILContLgcRtOpConverterPass::convertDxOp(Function &Func) {
auto FuncName = Func.getName();
constexpr const char CalleePrefix[] = "dx.op.";
if (!FuncName.starts_with(CalleePrefix))
@@ -493,19 +493,32 @@ bool DXILContLgcRtOpConverterPass::processFunction(Function &Func) {
return Changed;
}
-void DXILContLgcRtOpConverterPass::applyPayloadMetadataTypesOnShaders() {
+void DXILContLgcRtOpConverterPass::setupLocalRootIndex(Function *F) {
+ Builder->SetInsertPointPastAllocas(F);
+ auto *LocalIndex = Builder->create<lgc::rt::ShaderIndexOp>();
+ auto *SetLocalRootIndex = llvm::getSetLocalRootIndex(*F->getParent());
+ Builder->CreateCall(SetLocalRootIndex, LocalIndex);
+}
+
+// Do preparation transformations to entry-point shaders.
+bool DXILContLgcRtOpConverterPass::prepareEntryPointShaders() {
+ bool Changed = false;
MapVector<Function *, DXILShaderKind> ShaderKinds;
analyzeShaderKinds(*M, ShaderKinds);
for (auto &[Func, Kind] : ShaderKinds) {
- auto Stage = DXILContHelper::dxilShaderKindToShaderStage(Kind);
+ auto Stage = ShaderStageHelper::dxilShaderKindToShaderStage(Kind);
// Ignore non-raytracing shader stages
if (!Stage.has_value())
continue;
+ Changed = true;
+ // Set lgc.rt shader stage metadata.
lgc::rt::setLgcRtShaderStage(Func, Stage);
-
+ // Set local root index in entry block.
+ setupLocalRootIndex(Func);
+ // Set payload type metadata.
switch (Kind) {
case DXILShaderKind::AnyHit:
case DXILShaderKind::ClosestHit:
@@ -514,7 +527,7 @@ void DXILContLgcRtOpConverterPass::applyPayloadMetadataTypesOnShaders() {
Type *PayloadTy = getFuncArgPtrElementType(Func, 0);
assert(PayloadTy && "Shader must have a payload argument");
Func->setMetadata(
- DXILContHelper::MDDXILPayloadTyName,
+ ContHelper::MDContPayloadTyName,
MDNode::get(Func->getContext(),
{ConstantAsMetadata::get(PoisonValue::get(PayloadTy))}));
break;
@@ -523,6 +536,7 @@ void DXILContLgcRtOpConverterPass::applyPayloadMetadataTypesOnShaders() {
break;
}
}
+ return Changed;
}
PreservedAnalyses
@@ -536,13 +550,13 @@ DXILContLgcRtOpConverterPass::run(Module &Module,
M = &Module;
DL = &M->getDataLayout();
- applyPayloadMetadataTypesOnShaders();
+ Changed |= prepareEntryPointShaders();
for (Function &F : Module.functions()) {
if (!F.isDeclaration())
continue;
- Changed |= processFunction(F);
+ Changed |= convertDxOp(F);
}
return Changed ? PreservedAnalyses::all() : PreservedAnalyses::none();
diff --git a/shared/continuations/lib/DXILContPostProcess.cpp b/shared/continuations/lib/DXILContPostProcess.cpp
index 0925f614cb..30bb282404 100644
--- a/shared/continuations/lib/DXILContPostProcess.cpp
+++ b/shared/continuations/lib/DXILContPostProcess.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -85,18 +85,19 @@ class DXILContPostProcessPassImpl final {
DXILContPostProcessPassImpl(Module &M, Module &GpurtLibrary);
bool run(llvm::ModuleAnalysisManager &AnalysisManager);
+ static constexpr unsigned SystemDataArgumentIndexStart = 2;
+ static constexpr unsigned SystemDataArgumentIndexContinuation = 1;
+ static constexpr unsigned SystemDataArgumentIndexRayGen = 0;
+
struct FunctionData {
DXILShaderKind Kind = DXILShaderKind::Invalid;
/// Calls to hlsl intrinsics
SmallVector<CallInst *> IntrinsicCalls;
- /// Calls to get the system data pointer
- SmallVector<continuations::GetSystemDataOp *> GetSystemDataCalls;
/// If this is the start function part of a split function
bool IsStart = true;
- /// Pointer to the alloca'd system data object in this function
- Value *SystemData = nullptr;
Type *SystemDataTy = nullptr;
+ unsigned SystemDataArgumentIndex = std::numeric_limits<unsigned>::max();
};
private:
@@ -115,9 +116,13 @@ class DXILContPostProcessPassImpl final {
void handleContPayloadRegistersSetI32(Function &F);
void handleContStackAlloc(FunctionAnalysisManager &FAM, Function &F);
+ bool replaceIntrinsicCalls(Function &F, const FunctionData &Data);
+ [[nodiscard]] std::pair<bool, Function *>
+ insertSetupRayGen(Function &F, const FunctionData &Data);
+
void collectProcessableFunctions();
bool handleIntrinsicCalls();
- bool handleGetSystemDataCalls();
+ bool replaceIntrinsicCallsAndSetupRayGen();
bool unfoldGlobals();
bool handleAmdInternals(llvm::ModuleAnalysisManager &AnalysisManager);
@@ -153,7 +158,7 @@ static void reportContStateSizes(Module &M) {
if (F.isDeclaration())
continue;
if (auto *MD = dyn_cast_or_null<MDTuple>(
- F.getMetadata(DXILContHelper::MDContinuationName))) {
+ F.getMetadata(ContHelper::MDContinuationName))) {
auto *EntryF = extractFunctionOrNull(MD->getOperand(0));
if (EntryF != &F)
EntriesWithContinuationFunctions.insert(EntryF);
@@ -167,12 +172,12 @@ static void reportContStateSizes(Module &M) {
if (!EntriesWithContinuationFunctions.contains(&F))
continue;
- auto OptStateSize = DXILContHelper::tryGetContinuationStateByteCount(F);
+ auto OptStateSize = ContHelper::tryGetContinuationStateByteCount(F);
if (!OptStateSize.has_value())
continue;
DXILShaderKind ShaderKind =
- DXILContHelper::shaderStageToDxilShaderKind(*Stage);
+ ShaderStageHelper::shaderStageToDxilShaderKind(*Stage);
dbgs() << "Continuation state size of \"" << F.getName() << "\" ("
<< ShaderKind << "): " << OptStateSize.value() << " bytes\n";
}
@@ -188,8 +193,7 @@ static void reportPayloadSizes(Module &M) {
collectContinueCalls(M, ContinueCalls);
for (auto *CallInst : ContinueCalls) {
- auto RegCount =
- DXILContHelper::tryGetOutgoingRegisterCount(CallInst).value();
+ auto RegCount = ContHelper::tryGetOutgoingRegisterCount(CallInst).value();
MaxOutgoingRegisterCounts[CallInst->getFunction()] =
std::max(MaxOutgoingRegisterCounts[CallInst->getFunction()], RegCount);
}
@@ -200,9 +204,9 @@ static void reportPayloadSizes(Module &M) {
continue;
DXILShaderKind ShaderKind =
- DXILContHelper::shaderStageToDxilShaderKind(*Stage);
+ ShaderStageHelper::shaderStageToDxilShaderKind(*Stage);
auto OptIncomingPayloadRegisterCount =
- DXILContHelper::tryGetIncomingRegisterCount(&F);
+ ContHelper::tryGetIncomingRegisterCount(&F);
bool HasIncomingPayload = OptIncomingPayloadRegisterCount.has_value();
auto It = MaxOutgoingRegisterCounts.find(&F);
bool HasOutgoingPayload = (It != MaxOutgoingRegisterCounts.end());
@@ -313,7 +317,7 @@ static bool addGetAddrAndMDIntrinsicCalls(Module &M) {
while (!CEWorkList.empty()) {
auto *CE = CEWorkList.pop_back_val();
- assert((isa<BitCastOperator>(CE) || isa<PtrToIntOperator>(CE)) &&
+ assert((isa<BitCastOperator, PtrToIntOperator>(CE)) &&
"Unexpected use of function!");
// Copy the users of CE into a local SmallVector before traversing it,
@@ -365,7 +369,7 @@ static bool addGetAddrAndMDIntrinsicCalls(Module &M) {
SmallVector<CallInst *> CallInsts;
collectContinueCalls(M, CallInsts);
for (auto *CallInst : CallInsts) {
- if (!DXILContHelper::tryGetOutgoingRegisterCount(CallInst))
+ if (!ContHelper::tryGetOutgoingRegisterCount(CallInst))
report_fatal_error("Missing registercount metadata on continue call!");
}
@@ -520,7 +524,7 @@ void DXILContPostProcessPassImpl::lowerGetResumePointAddr(Function &F) {
unsigned ReturnAddrArgNum = HasWaitMask ? 3 : 2;
// Move up computation of the resume address
auto *ReturnAddr = ContinueCall->getArgOperand(ReturnAddrArgNum);
- assert((ReturnAddr->getType() == Builder.getInt64Ty()) &&
+ assert(ReturnAddr->getType() == Builder.getInt64Ty() &&
"Unexpected return addr type!");
SmallVector<Instruction *> MoveInstrs;
@@ -784,7 +788,7 @@ void DXILContPostProcessPassImpl::handleContStackAlloc(
CInst.eraseFromParent();
// Add allocation to the stack size of this function
- DXILContHelper::addStackSize(Func, Size);
+ ContHelper::addStackSize(Func, Size);
});
}
@@ -799,7 +803,7 @@ void DXILContPostProcessPassImpl::collectProcessableFunctions() {
// Handle entry functions first
if (auto *MD = dyn_cast_or_null<MDTuple>(
- F.getMetadata(DXILContHelper::MDContinuationName))) {
+ F.getMetadata(ContHelper::MDContinuationName))) {
auto *EntryF = extractFunctionOrNull(MD->getOperand(0));
if (&F != EntryF)
continue;
@@ -807,9 +811,20 @@ void DXILContPostProcessPassImpl::collectProcessableFunctions() {
continue;
}
- DXILShaderKind Kind = DXILContHelper::shaderStageToDxilShaderKind(*Stage);
+ DXILShaderKind Kind =
+ ShaderStageHelper::shaderStageToDxilShaderKind(*Stage);
switch (Kind) {
- case DXILShaderKind::RayGeneration:
+ case DXILShaderKind::RayGeneration: {
+ FunctionData Data;
+ Data.Kind = Kind;
+ Data.SystemDataArgumentIndex = SystemDataArgumentIndexRayGen;
+ Data.SystemDataTy =
+ F.getFunctionType()->getParamType(SystemDataArgumentIndexRayGen);
+ [[maybe_unused]] bool DidInsert =
+ ToProcess.insert({&F, std::move(Data)}).second;
+ assert(DidInsert);
+ break;
+ }
case DXILShaderKind::Intersection:
case DXILShaderKind::AnyHit:
case DXILShaderKind::ClosestHit:
@@ -817,13 +832,12 @@ void DXILContPostProcessPassImpl::collectProcessableFunctions() {
case DXILShaderKind::Callable: {
FunctionData Data;
Data.Kind = Kind;
- if (Data.Kind == DXILShaderKind::RayGeneration) {
- assert(SetupRayGen && "Could not find SetupRayGen function");
- Data.SystemDataTy = SetupRayGen->getReturnType();
- } else {
- Data.SystemDataTy = F.getFunctionType()->getParamType(2);
- }
- ToProcess[&F] = Data;
+ Data.SystemDataArgumentIndex = SystemDataArgumentIndexStart;
+ Data.SystemDataTy =
+ F.getFunctionType()->getParamType(SystemDataArgumentIndexStart);
+ [[maybe_unused]] bool DidInsert =
+ ToProcess.insert({&F, std::move(Data)}).second;
+ assert(DidInsert);
break;
}
default:
@@ -836,14 +850,18 @@ void DXILContPostProcessPassImpl::collectProcessableFunctions() {
if (F.isDeclaration())
continue;
if (auto *MD = dyn_cast_or_null<MDTuple>(
- F.getMetadata(DXILContHelper::MDContinuationName))) {
+ F.getMetadata(ContHelper::MDContinuationName))) {
auto *EntryF = extractFunctionOrNull(MD->getOperand(0));
auto Stage = lgc::rt::getLgcRtShaderStage(EntryF);
if (Stage && &F != EntryF) {
FunctionData Data = ToProcess[EntryF];
Data.IsStart = false;
- Data.SystemDataTy = F.getArg(1)->getType();
- ToProcess[&F] = Data;
+ Data.SystemDataArgumentIndex = SystemDataArgumentIndexContinuation;
+ Data.SystemDataTy =
+ F.getArg(SystemDataArgumentIndexContinuation)->getType();
+ [[maybe_unused]] bool DidInsert =
+ ToProcess.insert({&F, std::move(Data)}).second;
+ assert(DidInsert);
}
}
}
@@ -851,7 +869,7 @@ void DXILContPostProcessPassImpl::collectProcessableFunctions() {
bool DXILContPostProcessPassImpl::handleIntrinsicCalls() {
bool Changed = false;
- auto *Payload = Mod->getGlobalVariable(DXILContHelper::GlobalPayloadName);
+ auto *Payload = Mod->getGlobalVariable(ContHelper::GlobalPayloadName);
// TODO: Dialectify.
for (auto &F : Mod->functions()) {
@@ -859,13 +877,13 @@ bool DXILContPostProcessPassImpl::handleIntrinsicCalls() {
if (Name == "continuation.initialContinuationStackPtr") {
Changed = true;
handleInitialContinuationStackPtr(F);
- } else if (Name.startswith("lgc.rt")) {
+ } else if (Name.starts_with("lgc.rt")) {
Changed = true;
handleLgcRtIntrinsic(F);
- } else if (Name.startswith("registerbuffer.setpointerbarrier")) {
+ } else if (Name.starts_with("registerbuffer.setpointerbarrier")) {
Changed = true;
handleRegisterBufferSetPointerBarrier(F, Payload);
- } else if (Name.startswith("registerbuffer.getpointer")) {
+ } else if (Name.starts_with("registerbuffer.getpointer")) {
Changed = true;
handleRegisterBufferGetPointer(F, Payload);
}
@@ -874,68 +892,101 @@ bool DXILContPostProcessPassImpl::handleIntrinsicCalls() {
return Changed;
}
-bool DXILContPostProcessPassImpl::handleGetSystemDataCalls() {
- const static auto Visitor =
- llvm_dialects::VisitorBuilder<MapVector<Function *, FunctionData>>()
- .setStrategy(llvm_dialects::VisitorStrategy::ByFunctionDeclaration)
- .add<continuations::GetSystemDataOp>([](auto &ToProcess, auto &Op) {
- // See also the system data documentation at the top of
- // Continuations.h.
- auto Data = ToProcess.find(Op.getFunction());
- if (Data != ToProcess.end())
- Data->second.GetSystemDataCalls.push_back(&Op);
- })
- .build();
-
- Visitor.visit(ToProcess, *Mod);
-
- for (auto &FuncData : ToProcess) {
- auto &Data = FuncData.second;
- // Transform SystemData to alloca and load on every use
- Builder.SetInsertPoint(FuncData.first->getEntryBlock().getFirstNonPHI());
- Data.SystemData = Builder.CreateAlloca(Data.SystemDataTy);
-
- // Replace intrinsic calls
- for (auto *Call : Data.IntrinsicCalls)
- replaceIntrinsicCall(Builder, Data.SystemDataTy, Data.SystemData,
- Data.Kind, Call, GpurtLibrary, CrossInliner);
-
- // Replace calls to getSystemData
- for (auto *Call : Data.GetSystemDataCalls) {
- Builder.SetInsertPoint(Call);
- auto *SystemDataTy = Call->getFunctionType()->getReturnType();
- auto *SystemDataPtr = getDXILSystemData(Builder, Data.SystemData,
- Data.SystemDataTy, SystemDataTy);
- auto *SystemData = Builder.CreateLoad(SystemDataTy, SystemDataPtr);
- Call->replaceAllUsesWith(SystemData);
- Call->eraseFromParent();
- }
+bool DXILContPostProcessPassImpl::replaceIntrinsicCalls(
+ Function &F, const FunctionData &Data) {
+ if (Data.IntrinsicCalls.empty())
+ return false;
- Builder.SetInsertPoint(
- &*FuncData.first->getEntryBlock().getFirstNonPHIOrDbgOrAlloca());
- if (FuncData.first->hasMetadata(DXILContHelper::MDEntryName)) {
- // Initialize system data for the start part of the entry shader
- auto *TmpSystemData = Builder.CreateCall(SetupRayGen);
- Builder.CreateStore(TmpSystemData, Data.SystemData);
- CrossInliner.inlineCall(*TmpSystemData);
- Builder.SetInsertPoint(&*Builder.GetInsertPoint());
- } else {
- // Initialize the new system data alloca with the passed argument.
- Builder.CreateStore(FuncData.first->getArg(Data.IsStart ? 2 : 1),
- Data.SystemData);
- }
+ auto *FuncTy = F.getFunctionType();
+
+ assert(FuncTy->getNumParams() > Data.SystemDataArgumentIndex &&
+ "Missing system data argument");
+ Builder.SetInsertPointPastAllocas(&F);
+
+ // Intrinsics need a pointer, so allocate and store the system data argument
+ Argument *SystemDataArgument = F.getArg(Data.SystemDataArgumentIndex);
+ Value *SystemDataPtr = Builder.CreateAlloca(Data.SystemDataTy);
+ SystemDataPtr->setName("system.data.alloca");
+ Builder.CreateStore(SystemDataArgument, SystemDataPtr);
+
+ for (auto *Call : Data.IntrinsicCalls)
+ replaceIntrinsicCall(Builder, Data.SystemDataTy, SystemDataPtr, Data.Kind,
+ Call, GpurtLibrary, CrossInliner);
+
+ return true;
+}
+
+std::pair<bool, Function *>
+DXILContPostProcessPassImpl::insertSetupRayGen(Function &F,
+ const FunctionData &Data) {
+ // The start part of the RayGen shader is the only occurrence where we need to
+ // call SetupRayGen
+ if (Data.Kind != DXILShaderKind::RayGeneration || !Data.IsStart)
+ return {false, &F};
- Data.SystemData->setName("system.data");
+ auto *FuncTy = F.getFunctionType();
+ assert(FuncTy->getNumParams() > Data.SystemDataArgumentIndex &&
+ "Missing system data argument");
+
+ Argument *const SystemDataArgument = F.getArg(Data.SystemDataArgumentIndex);
+
+ // Replace usages of the system data argument with the result of SetupRayGen
+ Builder.SetInsertPointPastAllocas(&F);
+
+ auto *SystemDataInit = Builder.CreateCall(SetupRayGen);
+ assert(SystemDataInit->getType() == Data.SystemDataTy &&
+ "SetupRayGen return type does not match system data type");
+ SystemDataInit->setName("system.data");
+ SystemDataArgument->replaceAllUsesWith(SystemDataInit);
+ CrossInliner.inlineCall(*SystemDataInit);
+
+ // Change function signature to remove the system data argument
+ SmallVector<Type *> ArgTypes;
+ ArgTypes.append(FuncTy->param_begin(),
+ FuncTy->param_begin() + Data.SystemDataArgumentIndex);
+ ArgTypes.append(FuncTy->param_begin() + (Data.SystemDataArgumentIndex + 1),
+ FuncTy->param_end());
+ auto *NewFuncTy = FunctionType::get(FuncTy->getReturnType(), ArgTypes, false);
+
+ Function *NewFunc = CompilerUtils::cloneFunctionHeader(
+ F, NewFuncTy, ArrayRef<AttributeSet>{});
+ NewFunc->takeName(&F);
+
+ llvm::moveFunctionBody(F, *NewFunc);
+
+ F.replaceAllUsesWith(ConstantExpr::getBitCast(NewFunc, F.getType()));
+ F.eraseFromParent();
+
+ return {true, NewFunc};
+}
+
+bool DXILContPostProcessPassImpl::replaceIntrinsicCallsAndSetupRayGen() {
+ bool Changed = false;
+
+ // We will change some function signatures and populate a new MapVector as we
+ // go, to then replace ToProcess
+ MapVector<Function *, FunctionData> ToProcessNew;
+ ToProcessNew.reserve(ToProcess.size());
+
+ for (auto &[Func, Data] : ToProcess) {
+ Changed |= replaceIntrinsicCalls(*Func, Data);
+
+ auto const [DidInsert, NewFunc] = insertSetupRayGen(*Func, Data);
+ Changed |= DidInsert;
+
+ // Func could have been changed, but Data is the same
+ ToProcessNew.insert({NewFunc, std::move(Data)});
}
- return !ToProcess.empty();
+ ToProcess = std::move(ToProcessNew);
+ return Changed;
}
bool DXILContPostProcessPassImpl::unfoldGlobals() {
// Replace register globals with indices into a bigger global
const auto &DL = Mod->getDataLayout();
GlobalVariable *PayloadGlobal =
- Mod->getGlobalVariable(DXILContHelper::GlobalPayloadName);
+ Mod->getGlobalVariable(ContHelper::GlobalPayloadName);
if (PayloadGlobal) {
// We use the maximum size for the continuation state and the actual size
@@ -950,10 +1001,10 @@ bool DXILContPostProcessPassImpl::unfoldGlobals() {
auto *I32 = Type::getInt32Ty(Mod->getContext());
auto *RegistersTy = ArrayType::get(I32, RequiredSize / RegisterBytes);
Registers = cast<GlobalVariable>(Mod->getOrInsertGlobal(
- DXILContHelper::GlobalRegistersName, RegistersTy, [&] {
+ ContHelper::GlobalRegistersName, RegistersTy, [&] {
return new GlobalVariable(
*Mod, RegistersTy, false, GlobalVariable::ExternalLinkage,
- nullptr, DXILContHelper::GlobalRegistersName, nullptr,
+ nullptr, ContHelper::GlobalRegistersName, nullptr,
GlobalVariable::NotThreadLocal, GlobalRegisterAddrspace);
}));
@@ -972,13 +1023,13 @@ bool DXILContPostProcessPassImpl::handleAmdInternals(
for (auto &F : Mod->functions()) {
auto Name = F.getName();
- if (Name.startswith("_AmdValueI32Count")) {
+ if (Name.starts_with("_AmdValueI32Count")) {
Changed = true;
handleValueI32Count(F);
- } else if (Name.startswith("_AmdValueGetI32")) {
+ } else if (Name.starts_with("_AmdValueGetI32")) {
Changed = true;
handleValueGetI32(F);
- } else if (Name.startswith("_AmdValueSetI32")) {
+ } else if (Name.starts_with("_AmdValueSetI32")) {
Changed = true;
handleValueSetI32(F);
} else if (Name.starts_with("_AmdContPayloadRegistersI32Count")) {
@@ -1020,7 +1071,7 @@ bool DXILContPostProcessPassImpl::run(
collectProcessableFunctions();
Changed |= handleIntrinsicCalls();
- Changed |= handleGetSystemDataCalls();
+ Changed |= replaceIntrinsicCallsAndSetupRayGen();
for (auto &F : make_early_inc_range(*Mod)) {
if (F.getName().starts_with("_AmdGetResumePointAddr")) {
Changed = true;
diff --git a/shared/continuations/lib/DXILSupport.cpp b/shared/continuations/lib/DXILSupport.cpp
index 4678f6694e..d3c62a18a1 100644
--- a/shared/continuations/lib/DXILSupport.cpp
+++ b/shared/continuations/lib/DXILSupport.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -91,7 +91,7 @@ static bool isRematerializableDxilLoad(CallInst *CInst, StringRef CalledName) {
bool IsLoad = false;
for (const auto *LoadFunc : LoadFunctions) {
- if (CalledName.startswith(LoadFunc)) {
+ if (CalledName.starts_with(LoadFunc)) {
IsLoad = true;
break;
}
@@ -104,9 +104,9 @@ static bool isRematerializableDxilLoad(CallInst *CInst, StringRef CalledName) {
// Unwrap dx.op.annotateHandle and dx.op.createHandleForLib calls.
while (auto *Call = dyn_cast<CallInst>(Handle)) {
assert(
- Call->getCalledFunction()->getName().startswith(
+ Call->getCalledFunction()->getName().starts_with(
"dx.op.annotateHandle") ||
- Call->getCalledFunction()->getName().startswith("dx.op.createHandle"));
+ Call->getCalledFunction()->getName().starts_with("dx.op.createHandle"));
Handle = Call->getArgOperand(1);
}
@@ -159,12 +159,18 @@ bool llvm::DXILMaterializable(Instruction &OrigI) {
if (coro::defaultMaterializable(*V))
return true;
+ // Insert into constant.
+ if (isa<InsertElementInst, InsertValueInst>(V) &&
+ isa<Constant>(V->getOperand(0))) {
+ return true;
+ }
+
// Loads associated with dx.op.createHandle calls
if (auto *LI = dyn_cast<LoadInst>(V)) {
for (auto *LIUse : LI->users()) {
if (auto *CallI = dyn_cast<CallInst>(LIUse)) {
auto *CalledF = CallI->getCalledFunction();
- if (!CalledF || !CalledF->getName().startswith("dx.op.createHandle"))
+ if (!CalledF || !CalledF->getName().starts_with("dx.op.createHandle"))
return false;
} else {
return false;
@@ -179,13 +185,13 @@ bool llvm::DXILMaterializable(Instruction &OrigI) {
// be rematerialized are replaced by their implementation, so that the
// necessary values can be put into the coroutine frame. Therefore, we
// can assume all left-over intrinsics can be rematerialized.
- if (DXILContHelper::isRematerializableLgcRtOp(*CInst))
+ if (ContHelper::isRematerializableLgcRtOp(*CInst))
return true;
auto CalledName = CalledFunc->getName();
- if (CalledName.startswith("dx.op.")) {
+ if (CalledName.starts_with("dx.op.")) {
// createHandle and createHandleForLib
- if (CalledName.startswith("dx.op.createHandle"))
+ if (CalledName.starts_with("dx.op.createHandle"))
return true;
// Match by id
diff --git a/shared/continuations/lib/GpurtDialect.cpp b/shared/continuations/lib/GpurtDialect.cpp
index eb39ad54e3..6db1bde69f 100644
--- a/shared/continuations/lib/GpurtDialect.cpp
+++ b/shared/continuations/lib/GpurtDialect.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/shared/continuations/lib/LegacyCleanupContinuations.cpp b/shared/continuations/lib/LegacyCleanupContinuations.cpp
index 2713fd1889..64abd9c279 100644
--- a/shared/continuations/lib/LegacyCleanupContinuations.cpp
+++ b/shared/continuations/lib/LegacyCleanupContinuations.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -73,7 +73,8 @@ class LegacyCleanupContinuationsPassImpl {
uint32_t ContStateBytes = 0;
CallInst *MallocCall = nullptr;
MDNode *MD = nullptr;
- AllocaInst *NewContState = nullptr;
+ // The continuation state on the CPS stack
+ Value *NewContState = nullptr;
SmallVector<CallInst *> NewReturnContinues;
/// Cleaned entry function, used to replace metadata
Function *NewStart = nullptr;
@@ -98,6 +99,7 @@ class LegacyCleanupContinuationsPassImpl {
Module &M;
LLVMContext &Context;
+ llvm::FunctionAnalysisManager &FAM;
IRBuilder<> B;
Type *I32 = nullptr;
Type *I64 = nullptr;
@@ -184,17 +186,6 @@ findTokenOrigin(BasicBlock *BB, Value *V,
return Result;
}
-/// Create a memcopy of an array, which the translator understands
-void createCopy(IRBuilder<> &B, Value *Dst, Value *Src, Type *Ty) {
- assert(Ty->isArrayTy() && "Can only copy arrays");
- for (unsigned I = 0; I < Ty->getArrayNumElements(); I++) {
- auto *SrcGep = B.CreateConstInBoundsGEP2_32(Ty, Src, 0, I);
- auto *DstGep = B.CreateConstInBoundsGEP2_32(Ty, Dst, 0, I);
- auto *Load = B.CreateLoad(Ty->getArrayElementType(), SrcGep);
- B.CreateStore(Load, DstGep);
- }
-}
-
void LegacyCleanupContinuationsPassImpl::analyzeContinuation(Function &F,
MDNode *MD) {
// Only analyze main continuation
@@ -271,7 +262,7 @@ uint32_t getIncomingRegisterCount(Function *ResumeFunc) {
assert(isa<CallInst>(U) &&
"User of a resume function should be a call to continue");
auto *Inst = cast<CallInst>(U);
- if (auto Count = DXILContHelper::tryGetReturnedRegisterCount(Inst)) {
+ if (auto Count = ContHelper::tryGetReturnedRegisterCount(Inst)) {
assert((!RegCount || *RegCount == *Count) &&
"Got different returned registercounts in continues to "
"the same resume function");
@@ -330,7 +321,7 @@ void LegacyCleanupContinuationsPassImpl::processContinuation(
Function *StartFunc, ContinuationData &FuncData) {
auto *Void = Type::getVoidTy(Context);
LLVM_DEBUG(dbgs() << "Processing function: " << StartFunc->getName() << "\n");
- bool IsEntry = StartFunc->hasMetadata(DXILContHelper::MDEntryName);
+ bool IsEntry = StartFunc->hasMetadata(ContHelper::MDEntryName);
// The start function must come first to setup FuncData.NewStart and
// ContMDTuple which is used by processing the resume functions.
assert(StartFunc == FuncData.Functions[0]);
@@ -346,9 +337,9 @@ void LegacyCleanupContinuationsPassImpl::processContinuation(
for (auto *F : FuncData.Functions) {
if (F != StartFunc) {
// Entry marker should only be on the start and not on resume functions
- F->eraseMetadata(Context.getMDKindID(DXILContHelper::MDEntryName));
+ F->eraseMetadata(Context.getMDKindID(ContHelper::MDEntryName));
// Same for stacksize
- F->eraseMetadata(Context.getMDKindID(DXILContHelper::MDStackSizeName));
+ F->eraseMetadata(Context.getMDKindID(ContHelper::MDStackSizeName));
// Set same linkage as for start function
F->setLinkage(StartFunc->getLinkage());
}
@@ -405,6 +396,14 @@ void LegacyCleanupContinuationsPassImpl::processContinuation(
Value *ContFrame =
getContFrame(FuncData.MallocCall, F, IsStart, InstsToRemove);
+ // Try to eliminate unnecessary continuation state accesses
+ // of values that are still available as SSA values by a simple
+ // store-to-load forwarding routine.
+ // Ideally, LLVM coro passes should do better and not emit these
+ // loads to begin with.
+ auto &DT = FAM.getResult<DominatorTreeAnalysis>(*F);
+ forwardContinuationFrameStoreToLoad(DT, ContFrame);
+
// Create new empty function
F->eraseMetadata(FuncData.MD->getMetadataID());
auto *NewFuncTy = FunctionType::get(Void, AllArgTypes, false);
@@ -444,9 +443,24 @@ void LegacyCleanupContinuationsPassImpl::processContinuation(
handleFunctionEntry(FuncData, NewFunc, IsEntry);
// Handle the function body
- // Use the global continuation state
- ContFrame->replaceAllUsesWith(
- B.CreateBitOrPointerCast(FuncData.NewContState, ContFrame->getType()));
+
+ if (FuncData.NewContState) {
+ // Bitcast new cont state to the pointer type used by coro passes, but
+ // preserve the address space. Uses of the pointer are then fixed to also
+ // use the correct address space.
+ PointerType *UsedContFrameTy = cast<PointerType>(ContFrame->getType());
+ Value *CastNewContState = B.CreateBitCast(
+ FuncData.NewContState,
+ getWithSamePointeeType(
+ UsedContFrameTy,
+ FuncData.NewContState->getType()->getPointerAddressSpace()));
+ replaceAllPointerUses(&B, ContFrame, CastNewContState, InstsToRemove);
+ } else {
+ // If there is no continuation state, replace it with a poison
+ // value instead of a zero-sized stack allocation.
+ // This leads to nicer tests.
+ ContFrame->replaceAllUsesWith(PoisonValue::get(ContFrame->getType()));
+ }
// Handle the function returns
for (auto &BB : make_early_inc_range(*NewFunc)) {
@@ -472,7 +486,7 @@ void LegacyCleanupContinuationsPassImpl::processContinuation(
// Update metadata
assert(ContMDTuple != nullptr);
- NewFunc->setMetadata(DXILContHelper::MDContinuationName, ContMDTuple);
+ NewFunc->setMetadata(ContHelper::MDContinuationName, ContMDTuple);
}
// Register count analysis needs to wait until all functions have been
@@ -480,7 +494,7 @@ void LegacyCleanupContinuationsPassImpl::processContinuation(
for (auto [NewFunc, IsStart] : NewFuncs) {
if (!IsStart) {
uint32_t IncomingRegisterCount = getIncomingRegisterCount(NewFunc);
- DXILContHelper::setIncomingRegisterCount(NewFunc, IncomingRegisterCount);
+ ContHelper::setIncomingRegisterCount(NewFunc, IncomingRegisterCount);
}
}
@@ -490,46 +504,53 @@ void LegacyCleanupContinuationsPassImpl::processContinuation(
void LegacyCleanupContinuationsPassImpl::handleFunctionEntry(
ContinuationData &Data, Function *F, bool IsEntry) {
+ uint64_t NeededStackSize = Data.getContStateStackBytes();
bool IsStart = F == Data.NewStart;
- // Create alloca to keep the continuation state
- uint64_t ContStateNumI32s = divideCeil(Data.ContStateBytes, RegisterBytes);
- uint64_t NeededStackSize = Data.getContStateStackBytes();
- auto *ContStateTy = ArrayType::get(I32, ContStateNumI32s);
- Data.NewContState = B.CreateAlloca(ContStateTy, nullptr, "cont.state");
+ // We allocate continuation state on top of the payload.
+ // We plan to change this, but until we have done that,
+ // we need to "reverse peek" on top of the payload allocation
+ // that is going to be allocated later (also on function entry).
+ int64_t StackOffsetForPayloadSpill = 0;
if (IsStart) {
// Add function metadata that stores how big the continuation state is in
// bytes
- DXILContHelper::setContinuationStateByteCount(*F, Data.ContStateBytes);
+ ContHelper::setContinuationStateByteCount(*F, Data.ContStateBytes);
+ // At this point, stack size is exactly the payload spill size.
+ StackOffsetForPayloadSpill = ContHelper::tryGetStackSize(F).value_or(0);
if (NeededStackSize) {
// Add to continuation stack size metadata
- DXILContHelper::addStackSize(F, NeededStackSize);
+ ContHelper::addStackSize(F, NeededStackSize);
}
- } else if (NeededStackSize) {
+ } else {
+ // Deallocate
+ if (NeededStackSize)
+ moveContinuationStackOffset(B, -NeededStackSize);
+ }
+
+ if (NeededStackSize) {
+ uint64_t ContStateNumI32s = divideCeil(Data.ContStateBytes, RegisterBytes);
+ auto *ContStateTy = ArrayType::get(I32, ContStateNumI32s);
+
+ // Peek into CSP stack to obtain continuation state.
+ // This can be handled in the same way for start and resume functions,
+ // because for start functions we already allocated space above.
+ //
// Obtain current CSP
auto *CspOffsetPtr = B.CreateCall(getContinuationStackOffset(M));
auto *CspType = getContinuationStackOffsetType(M.getContext());
- auto *Offset = B.CreateLoad(CspType, CspOffsetPtr);
- auto *Ptr = continuationStackOffsetToPtr(
- B, Offset, *(GpurtLibrary ? GpurtLibrary : &M), CrossInliner);
-
- // Obtain ptr to continuation state on stack,
- // and copy continuation state from global into local variable
- Value *ContStateOnStack =
- B.CreateGEP(B.getInt8Ty(), Ptr, B.getInt64(-NeededStackSize));
- createCopy(
- B, Data.NewContState,
- B.CreateBitOrPointerCast(ContStateOnStack,
- ContStateTy->getPointerTo(
- Ptr->getType()->getPointerAddressSpace())),
- ContStateTy);
-
- // Deallocate continuation stack space.
- // The generated IR is partially redundant with the above,
- // as the new CSP is just ContStateOnStack from above.
- // However, we need to do the copy first and only then deallocate.
- moveContinuationStackOffset(B, -NeededStackSize);
+ auto *CspAsOffset = B.CreateLoad(CspType, CspOffsetPtr);
+ auto *CspAsPtr = continuationStackOffsetToPtr(
+ B, CspAsOffset, *(GpurtLibrary ? GpurtLibrary : &M), CrossInliner);
+ Value *ContStateOnStack = B.CreateGEP(
+ B.getInt8Ty(), CspAsPtr, B.getInt64(StackOffsetForPayloadSpill));
+
+ Data.NewContState = B.CreateBitOrPointerCast(
+ ContStateOnStack,
+ ContStateTy->getPointerTo(
+ ContStateOnStack->getType()->getPointerAddressSpace()),
+ "cont.state");
}
}
@@ -580,34 +601,18 @@ void LegacyCleanupContinuationsPassImpl::handleSingleContinue(
ContinuationData &Data, CallInst *Call, Value *ResumeFun) {
// Pass resume address as argument
B.SetInsertPoint(Call);
+ // Allocate CSP storage
+ uint64_t NeededStackSize = Data.getContStateStackBytes();
+ if (NeededStackSize)
+ moveContinuationStackOffset(B, NeededStackSize);
auto *ReturnAddrInt = B.CreatePtrToInt(ResumeFun, I64);
auto *CpsType = getContinuationStackOffsetType(Call->getContext());
auto *CspFun = getContinuationStackOffset(*Call->getModule());
- // Write local continuation state to stack and registers
- uint64_t NeededStackSize = Data.getContStateStackBytes();
- if (NeededStackSize) {
- // Allocate continuation stack space
- Value *ContStateOnStackOffset =
- moveContinuationStackOffset(B, NeededStackSize).first;
- auto *ContStateOnStackPtr = continuationStackOffsetToPtr(
- B, ContStateOnStackOffset, *(GpurtLibrary ? GpurtLibrary : &M),
- CrossInliner);
- // Copy continuation state from local variable into global
- auto *ContStateTy = Data.NewContState->getAllocatedType();
- createCopy(
- B,
- B.CreateBitOrPointerCast(
- ContStateOnStackPtr,
- ContStateTy->getPointerTo(
- ContStateOnStackPtr->getType()->getPointerAddressSpace())),
- Data.NewContState, ContStateTy);
- }
-
auto *Csp = B.CreateLoad(CpsType, B.CreateCall(CspFun));
- bool IsWait = DXILContHelper::isWaitAwaitCall(*Call);
+ bool IsWait = ContHelper::isWaitAwaitCall(*Call);
Function *ContinueFunction = IsWait ? WaitContinue : Continue;
// Replace this instruction with a call to continuation.[wait]continue
@@ -623,8 +628,8 @@ void LegacyCleanupContinuationsPassImpl::handleSingleContinue(
// Copy metadata, except for the wait flag, which is no longer needed.
ContinueCall->copyMetadata(*Call);
if (IsWait)
- DXILContHelper::removeIsWaitAwaitMetadata(*ContinueCall);
- assert(DXILContHelper::tryGetOutgoingRegisterCount(ContinueCall) &&
+ ContHelper::removeIsWaitAwaitMetadata(*ContinueCall);
+ assert(ContHelper::tryGetOutgoingRegisterCount(ContinueCall) &&
"Missing registercount metadata!");
// Remove instructions at the end of the block
@@ -665,7 +670,7 @@ void LegacyCleanupContinuationsPassImpl::handleReturn(ContinuationData &Data,
Data.NewReturnContinues.push_back(ContinueCall);
ContinueCall->copyMetadata(*ContRet);
- assert(DXILContHelper::tryGetOutgoingRegisterCount(ContinueCall) &&
+ assert(ContHelper::tryGetOutgoingRegisterCount(ContinueCall) &&
"Missing registercount metadata!");
}
@@ -675,7 +680,10 @@ void LegacyCleanupContinuationsPassImpl::handleReturn(ContinuationData &Data,
LegacyCleanupContinuationsPassImpl::LegacyCleanupContinuationsPassImpl(
llvm::Module &Mod, llvm::Module *GpurtLibrary,
llvm::ModuleAnalysisManager &AnalysisManager)
- : M{Mod}, Context{M.getContext()}, B{Context}, GpurtLibrary{GpurtLibrary} {
+ : M{Mod}, Context{M.getContext()},
+ FAM{AnalysisManager.getResult<FunctionAnalysisManagerModuleProxy>(Mod)
+ .getManager()},
+ B{Context}, GpurtLibrary{GpurtLibrary} {
AnalysisManager.getResult<DialectContextAnalysis>(M);
ContMalloc = M.getFunction("continuation.malloc");
ContFree = M.getFunction("continuation.free");
@@ -689,16 +697,16 @@ llvm::PreservedAnalyses LegacyCleanupContinuationsPassImpl::run() {
if (F.empty())
continue;
- if (auto *MD = F.getMetadata(DXILContHelper::MDContinuationName)) {
+ if (auto *MD = F.getMetadata(ContHelper::MDContinuationName)) {
analyzeContinuation(F, MD);
- } else if (auto Stage = lgc::rt::getLgcRtShaderStage(&F);
- Stage && *Stage == lgc::rt::RayTracingShaderStage::Traversal) {
+ } else if (lgc::rt::getLgcRtShaderStage(&F) ==
+ lgc::rt::RayTracingShaderStage::Traversal) {
Changed = true;
// Add !continuation metadata to Traversal after coroutine passes.
// The traversal loop is written as like the coroutine passes were applied
// manually.
MDTuple *ContMDTuple = MDTuple::get(Context, {ValueAsMetadata::get(&F)});
- F.setMetadata(DXILContHelper::MDContinuationName, ContMDTuple);
+ F.setMetadata(ContHelper::MDContinuationName, ContMDTuple);
}
}
diff --git a/shared/continuations/lib/LgcCpsDialect.cpp b/shared/continuations/lib/LgcCpsDialect.cpp
index 73ae2823e0..c84e7d93ec 100644
--- a/shared/continuations/lib/LgcCpsDialect.cpp
+++ b/shared/continuations/lib/LgcCpsDialect.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/shared/continuations/lib/LgcRtDialect.cpp b/shared/continuations/lib/LgcRtDialect.cpp
index 691269540e..c73f40059e 100644
--- a/shared/continuations/lib/LgcRtDialect.cpp
+++ b/shared/continuations/lib/LgcRtDialect.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -173,7 +173,7 @@ void lgc::rt::setShaderArgSize(Function *func, size_t size) {
// ==============================================================================================
// Get attribute size (in bytes) metadata for a ray-tracing shader function.
-size_t lgc::rt::getShaderHitAttributeSize(Function *func) {
+size_t lgc::rt::getShaderHitAttributeSize(const Function *func) {
MDNode *node = func->getMetadata(AttributeSizeMetadata);
if (!node)
return 0;
diff --git a/shared/continuations/lib/LowerAwait.cpp b/shared/continuations/lib/LowerAwait.cpp
index 41d1de649e..e9a422b26e 100644
--- a/shared/continuations/lib/LowerAwait.cpp
+++ b/shared/continuations/lib/LowerAwait.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -170,7 +170,7 @@ static void processContinuations(
// Lgc.cps dialect will handle stack pointer and return address in other
// places.
bool IsLegacyNonEntry =
- !F->hasMetadata(DXILContHelper::MDEntryName) && !LowerLgcAwait;
+ !F->hasMetadata(ContHelper::MDEntryName) && !LowerLgcAwait;
// Add continuation stack pointer and passed return address.
if (IsLegacyNonEntry) {
AllArgTypes.push_back(getContinuationStackOffsetType(Context));
@@ -230,8 +230,8 @@ static void processContinuations(
// Add metadata, marking it as a continuation function
MDTuple *ContMDTuple =
MDTuple::get(Context, {ValueAsMetadata::get(NewFunc)});
- NewFunc->setMetadata(DXILContHelper::MDContinuationName, ContMDTuple);
- ContProtoFunc->setMetadata(DXILContHelper::MDContinuationName, ContMDTuple);
+ NewFunc->setMetadata(ContHelper::MDContinuationName, ContMDTuple);
+ ContProtoFunc->setMetadata(ContHelper::MDContinuationName, ContMDTuple);
auto *ContProtoFuncPtr = ConstantExpr::getBitCast(ContProtoFunc, I8Ptr);
@@ -347,10 +347,10 @@ LowerAwaitPass::run(llvm::Module &M,
bool LowerLgcAwait = !ToProcess.empty();
if (!LowerLgcAwait) {
for (auto &F : M.functions()) {
- if (!F.getName().startswith("await.")) {
+ if (!F.getName().starts_with("await.")) {
// Force processing annotated functions, even if they don't have await
// calls
- if (F.hasMetadata(DXILContHelper::MDContinuationName))
+ if (F.hasMetadata(ContHelper::MDContinuationName))
ToProcess[&F].size();
continue;
}
diff --git a/shared/continuations/lib/LowerRaytracingPipeline.cpp b/shared/continuations/lib/LowerRaytracingPipeline.cpp
index 9354dacfb5..3ed308566e 100644
--- a/shared/continuations/lib/LowerRaytracingPipeline.cpp
+++ b/shared/continuations/lib/LowerRaytracingPipeline.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -240,6 +240,8 @@ class ModuleMetadataState final {
ContStackAddrspace getContStackAddrspace() const { return StackAddrspace; }
+ bool isInLgcCpsMode() const { return IsInLgcCpsMode; }
+
void updateModuleMetadata() const;
private:
@@ -253,25 +255,10 @@ class ModuleMetadataState final {
uint32_t MinPayloadRegisterCount = 0;
/// The address space used for the continuations stack.
/// Either stack or global memory.
- ContStackAddrspace StackAddrspace = DXILContHelper::DefaultStackAddrspace;
-};
-
-class CpsMutator final {
-public:
- explicit CpsMutator(Module &Mod)
- : Mod{Mod}, IsModuleInCpsMode{DXILContHelper::isLgcCpsModule(Mod)},
- Builder{std::make_unique<llvm_dialects::Builder>(Mod.getContext())} {}
-
- Value *insertCpsAwait(Type *ReturnTy, Value *ShaderAddr, Instruction *Call,
- ArrayRef<Value *> Args, ContinuationCallType CallType,
- lgc::cps::CpsShaderStage ShaderStage);
+ ContStackAddrspace StackAddrspace = ContHelper::DefaultStackAddrspace;
- bool shouldRun() const { return IsModuleInCpsMode; }
-
-private:
- Module &Mod;
- bool IsModuleInCpsMode = false;
- std::unique_ptr<llvm_dialects::Builder> Builder;
+ /// If the module has lgc.cps.module metadata attached.
+ bool IsInLgcCpsMode = false;
};
class LowerRaytracingPipelinePassImpl final {
@@ -303,6 +290,8 @@ class LowerRaytracingPipelinePassImpl final {
/// Pointer to the alloca'd system data object in this function
AllocaInst *SystemData = nullptr;
StructType *SystemDataTy = nullptr;
+ /// The first store to the alloca'd system data.
+ Instruction *SystemDataFirstStore = nullptr;
Type *ReturnTy = nullptr;
/// Maximum number of I32s required to store the outgoing payload in all
/// CallShader or TraceRay (maximum over all TraceRay formats) calls
@@ -333,8 +322,6 @@ class LowerRaytracingPipelinePassImpl final {
Type *NewRetTy = nullptr;
};
- static DXILShaderKind callTypeToShaderKind(ContinuationCallType CallType);
-
void replaceCall(FunctionData &Data, CallInst *Call, Function *Func,
ContinuationCallType CallType);
void handleRestoreSystemData(CallInst *Call);
@@ -343,8 +330,6 @@ class LowerRaytracingPipelinePassImpl final {
Type *PayloadOrAttrsTy);
void replaceReportHitCall(FunctionData &Data, CallInst *Call);
- void handleReportHit(FunctionData &Data, Function &F);
-
void replaceShaderIndexCall(FunctionData &Data, CallInst *Call);
void handleGetFuncAddr(Function &Func);
@@ -357,7 +342,7 @@ class LowerRaytracingPipelinePassImpl final {
void handleUnrematerializableCandidates();
- void collectDriverFunctions();
+ void collectGpuRtFunctions();
// Copy the payload content between global payload and local payload.
// Excludes the stack pointer or hit attributes which may also reside in
@@ -398,26 +383,24 @@ class LowerRaytracingPipelinePassImpl final {
void createPayloadGlobal();
- void setTraversalRegisterCountMetadata();
+ // Sets register count metadata (incoming on entry functions, outgoing on
+ // continue calls) in GpuRt entries (Traversal and launch kernel).
+ void setGpurtEntryRegisterCountMetadata();
void copyHitAttributes(FunctionData &Data, Value *SystemData,
Type *SystemDataTy, Value *LocalHitAttributes,
bool GlobalToLocal,
const PAQSerializationLayout *Layout);
void processContinuations();
- void processFunctionEntry(Function *F, FunctionData &Data);
+ void processFunctionEntry(FunctionData &Data, Argument *SystemDataArgument);
void processFunctionEnd(FunctionData &Data, FunctionEndData &EData);
void processFunction(Function *F, FunctionData &FuncData);
void collectProcessableFunctions();
- void handleDriverFuncAssertions();
-
- constexpr static uint32_t ArgContState = 0;
- constexpr static uint32_t ArgReturnAddr = 1;
- constexpr static uint32_t ArgShaderIndex = 2;
- [[maybe_unused]] constexpr static uint32_t ArgSystemData = 3;
- [[maybe_unused]] constexpr static uint32_t ArgHitAttributes = 4;
+ Value *insertCpsAwait(Type *ReturnTy, Value *ShaderAddr, Instruction *Call,
+ ArrayRef<Value *> Args, ContinuationCallType CallType,
+ lgc::cps::CpsShaderStage ShaderStage);
MapVector<Function *, FunctionData> ToProcess;
Module *Mod;
@@ -426,7 +409,6 @@ class LowerRaytracingPipelinePassImpl final {
const DataLayout *DL;
llvm_dialects::Builder Builder;
ModuleMetadataState MetadataState;
- CpsMutator Mutator;
PAQSerializationInfoManager PAQManager;
CompilerUtils::CrossModuleInliner CrossInliner;
Type *I32;
@@ -462,30 +444,30 @@ constexpr unsigned ModuleMetadataState::DefaultPayloadRegisterCount;
ModuleMetadataState::ModuleMetadataState(Module &Module) : Mod{Module} {
// Import PayloadRegisterCount from metadata if set,
// otherwise from default
- auto RegisterCountFromMD =
- DXILContHelper::tryGetMaxPayloadRegisterCount(Module);
+ auto RegisterCountFromMD = ContHelper::tryGetMaxPayloadRegisterCount(Module);
MaxPayloadRegisterCount =
RegisterCountFromMD.value_or(DefaultPayloadRegisterCount);
// Check that if there is a required minimum number of payload registers,
// it is compatible
auto MinRegisterCountFromMD =
- DXILContHelper::tryGetMinPayloadRegisterCount(Module);
+ ContHelper::tryGetMinPayloadRegisterCount(Module);
MinPayloadRegisterCount =
MinRegisterCountFromMD.value_or(MaxPayloadRegisterCount);
assert(MinPayloadRegisterCount <= MaxPayloadRegisterCount);
// Import StackAddrspace from metadata if set, otherwise from default
- auto StackAddrspaceMD = DXILContHelper::tryGetStackAddrspace(Module);
- StackAddrspace =
- StackAddrspaceMD.value_or(DXILContHelper::DefaultStackAddrspace);
+ auto StackAddrspaceMD = ContHelper::tryGetStackAddrspace(Module);
+ StackAddrspace = StackAddrspaceMD.value_or(ContHelper::DefaultStackAddrspace);
+
+ IsInLgcCpsMode = ContHelper::isLgcCpsModule(Mod);
}
/// Write the previously derived information about max payload registers and
/// stack address space that was derived by metadata as global state.
void ModuleMetadataState::updateModuleMetadata() const {
- DXILContHelper::setMaxPayloadRegisterCount(Mod, MaxPayloadRegisterCount);
- DXILContHelper::setStackAddrspace(Mod, StackAddrspace);
+ ContHelper::setMaxPayloadRegisterCount(Mod, MaxPayloadRegisterCount);
+ ContHelper::setStackAddrspace(Mod, StackAddrspace);
}
lgc::cps::CpsShaderStage
@@ -511,15 +493,15 @@ convertShaderKindToCpsShaderStage(DXILShaderKind Kind) {
}
// Create a lgc.cps.await operation for a given shader address.
-Value *CpsMutator::insertCpsAwait(Type *ReturnTy, Value *ShaderAddr,
- Instruction *Call, ArrayRef<Value *> Args,
- ContinuationCallType CallType,
- CpsShaderStage ShaderStage) {
- Builder->SetInsertPoint(Call);
+Value *LowerRaytracingPipelinePassImpl::insertCpsAwait(
+ Type *ReturnTy, Value *ShaderAddr, Instruction *Call,
+ ArrayRef<Value *> Args, ContinuationCallType CallType,
+ CpsShaderStage ShaderStage) {
+ Builder.SetInsertPoint(Call);
Value *CR = nullptr;
if (ShaderAddr->getType()->getIntegerBitWidth() == 64)
- CR = Builder->CreateTrunc(ShaderAddr, Type::getInt32Ty(Mod.getContext()));
+ CR = Builder.CreateTrunc(ShaderAddr, Type::getInt32Ty(Mod->getContext()));
else
CR = ShaderAddr;
@@ -532,10 +514,10 @@ Value *CpsMutator::insertCpsAwait(Type *ReturnTy, Value *ShaderAddr,
CallStage = CpsShaderStage::AnyHit;
assert(CallStage != CpsShaderStage::Count &&
- "LowerRaytracingPipelinePassImpl::CpsMutator::insertCpsAwait: Invalid "
+ "LowerRaytracingPipelinePassImpl::insertCpsAwait: Invalid "
"call stage before inserting lgc.cps.await operation!");
- return Builder->create<AwaitOp>(
+ return Builder.create<AwaitOp>(
ReturnTy, CR,
1 << static_cast<uint8_t>(getCpsLevelForShaderStage(CallStage)), Args);
}
@@ -556,9 +538,9 @@ Function *llvm::getSetLocalRootIndex(Module &M) {
// Set maximum continuation stack size metadata
static void setStacksizeMetadata(Function &F, uint64_t NeededStackSize) {
- uint64_t CurStackSize = DXILContHelper::tryGetStackSize(&F).value_or(0);
+ uint64_t CurStackSize = ContHelper::tryGetStackSize(&F).value_or(0);
if (NeededStackSize > CurStackSize)
- DXILContHelper::setStackSize(&F, NeededStackSize);
+ ContHelper::setStackSize(&F, NeededStackSize);
}
// Create an ExtractElement instruction for each index of a FixedVector @Vector
@@ -595,20 +577,6 @@ static bool flattenVectorArgument(IRBuilder<> &B, Value *Arg,
return false;
}
-/// Convert the called shader type to the ShaderKind of the called function.
-DXILShaderKind LowerRaytracingPipelinePassImpl::callTypeToShaderKind(
- ContinuationCallType CallType) {
- switch (CallType) {
- case ContinuationCallType::AnyHit:
- return DXILShaderKind::AnyHit;
- case ContinuationCallType::CallShader:
- return DXILShaderKind::Callable;
- case ContinuationCallType::Traversal:
- return DXILShaderKind::RayGeneration;
- }
- llvm_unreachable("Unhandled enum value");
-}
-
/// Clone a function and replace a call with a call to the cloned function
void LowerRaytracingPipelinePassImpl::replaceCall(
FunctionData &Data, CallInst *Call, Function *Func,
@@ -657,7 +625,7 @@ void LowerRaytracingPipelinePassImpl::replaceCall(
}
// Get payload argument
- Type *PayloadOrAttrsTy = DXILContHelper::getPayloadTypeFromMetadata(*Call);
+ Type *PayloadOrAttrsTy = ContHelper::getPayloadTypeFromMetadata(*Call);
auto *NewCall = Builder.CreateCall(Func, Arguments);
if (!Call->getType()->isVoidTy())
@@ -720,9 +688,16 @@ void LowerRaytracingPipelinePassImpl::handleRestoreSystemData(CallInst *Call) {
cast<StructType>(getFuncArgPtrElementType(GetLocalRootIndex, 0));
auto *LocalIndexSystemData = getDXILSystemData(
Builder, SystemData, SystemDataTy, LocalIndexSystemDataTy);
- auto *LocalIndex =
- CrossInliner.inlineCall(Builder, GetLocalRootIndex, LocalIndexSystemData)
- .returnValue;
+
+ auto Stage = lgc::rt::getLgcRtShaderStage(Call->getFunction());
+ Value *LocalIndex = nullptr;
+ if (Stage == lgc::rt::RayTracingShaderStage::RayGeneration)
+ LocalIndex = Builder.getInt32(0);
+ else
+ LocalIndex =
+ CrossInliner
+ .inlineCall(Builder, GetLocalRootIndex, LocalIndexSystemData)
+ .returnValue;
LocalIndex->setName("local.root.index");
Builder.CreateCall(SetLocalRootIndex, LocalIndex);
}
@@ -750,19 +725,25 @@ void LowerRaytracingPipelinePassImpl::replaceReportHitCall(FunctionData &Data,
cast<StructType>(Data.ReturnTy));
Value *RetSystemData = Builder.CreateLoad(Data.ReturnTy, SystemData);
- if (Mutator.shouldRun()) {
+ if (MetadataState.isInLgcCpsMode()) {
uint32_t CpsRetLevel = getPotentialCpsReturnLevels(
convertShaderKindToCpsShaderStage(Data.Kind));
+ // When jumping to the ReturnAddress of parent function (i.e. the resume
+ // part of the caller of the parent function), the RCR and ShaderIndex
+ // are not important anymore, just pass Poison.
+ // Argument list: %rcr, %shader-index, %system-data.
+ SmallVector<Value *> TailArgs = {PoisonValue::get(I32),
+ PoisonValue::get(I32), RetSystemData};
Builder.create<JumpOp>(
- F->getArg(ArgReturnAddr), CpsRetLevel,
- PoisonValue::get(StructType::get(Builder.getContext())), RetSystemData);
+ F->getArg(CpsArgIdxReturnAddr), CpsRetLevel,
+ PoisonValue::get(StructType::get(Builder.getContext())), TailArgs);
Builder.CreateUnreachable();
} else {
auto *Ret = Builder.CreateRet(RetSystemData);
// Assume worst-case payload size for Intersection. See the note on the
// incoming payload size.
- DXILContHelper::setOutgoingRegisterCount(
+ ContHelper::setOutgoingRegisterCount(
Ret, MetadataState.getMaxPayloadRegisterCount());
}
@@ -834,7 +815,7 @@ void LowerRaytracingPipelinePassImpl::replaceContinuationCall(
// If we have a mem pointer, then we need to allocate stack storage
// The reverse does not hold, as a different payload type in the same
// shader could require the allocation.
- assert((Data.PayloadSpillSize != 0) && "Inconsistent payload stack size");
+ assert(Data.PayloadSpillSize != 0 && "Inconsistent payload stack size");
// Peek into the stack. This eventually will become lgc.cps.peek
auto *CspType = getContinuationStackOffsetType(Builder.getContext());
@@ -878,9 +859,28 @@ void LowerRaytracingPipelinePassImpl::replaceContinuationCall(
SmallVector<Type *, 2> ArgTys;
SmallVector<Value *, 2> Args;
- // Pass the given arguments, skipping the function address
- ArgTys.append(FTy->param_begin() + 1, FTy->param_end());
- Args.append(Call->arg_begin() + 1, Call->arg_end());
+ if (MetadataState.isInLgcCpsMode()) {
+ // For LgcCps, skip function-addr and also return-addr/wait-mask, the
+ // return-addr will be filled at late stage of continuation transform. Add
+ // shader-index so that the callee cps function get correct shader-index
+ // being passed in.
+ ArgTys.push_back(I32);
+ auto *ShaderIndex =
+ CrossInliner
+ .inlineCall(Builder, GetLocalRootIndex,
+ getDXILSystemData(
+ Builder, Data.SystemData, Data.SystemDataTy,
+ getFuncArgPtrElementType(GetLocalRootIndex, 0)))
+ .returnValue;
+ Args.push_back(ShaderIndex);
+
+ ArgTys.append(FTy->param_begin() + 2, FTy->param_end());
+ Args.append(Call->arg_begin() + 2, Call->arg_end());
+ } else {
+ // Pass the given arguments, skipping the function address
+ ArgTys.append(FTy->param_begin() + 1, FTy->param_end());
+ Args.append(Call->arg_begin() + 1, Call->arg_end());
+ }
auto *SystemDataTy = SetupRayGen->getReturnType();
if (CallType == ContinuationCallType::AnyHit) {
@@ -893,10 +893,9 @@ void LowerRaytracingPipelinePassImpl::replaceContinuationCall(
}
Value *NewCall = nullptr;
- if (Mutator.shouldRun()) {
- NewCall = Mutator.insertCpsAwait(
- Call->getType(), ShaderAddr, Call, Args, CallType,
- convertShaderKindToCpsShaderStage(Data.Kind));
+ if (MetadataState.isInLgcCpsMode()) {
+ NewCall = insertCpsAwait(Call->getType(), ShaderAddr, Call, Args, CallType,
+ convertShaderKindToCpsShaderStage(Data.Kind));
} else {
auto *ShaderTy = FunctionType::get(TokenTy, ArgTys, false);
auto *ShaderFun =
@@ -908,18 +907,17 @@ void LowerRaytracingPipelinePassImpl::replaceContinuationCall(
NewCall = Builder.CreateCall(Await, {Token});
// Annotate call with the number of registers used for payload
- DXILContHelper::setOutgoingRegisterCount(
+ ContHelper::setOutgoingRegisterCount(
Token, std::min(OutgoingSerializationLayout
? OutgoingSerializationLayout->NumStorageI32s
: MetadataState.getMaxPayloadRegisterCount(),
MetadataState.getMaxPayloadRegisterCount()));
- DXILContHelper::setReturnedRegisterCount(Token,
- ReturnedRegisterCount.value());
+ ContHelper::setReturnedRegisterCount(Token, ReturnedRegisterCount.value());
// For WaitAwait, add metadata indicating that we wait. After coroutine
// passes, we then generate a waitContinue on the awaited function.
- if (Call->getCalledFunction()->getName().startswith("_AmdWaitAwait"))
- DXILContHelper::setIsWaitAwaitCall(*Token);
+ if (Call->getCalledFunction()->getName().starts_with("_AmdWaitAwait"))
+ ContHelper::setIsWaitAwaitCall(*Token);
}
if (CallType != ContinuationCallType::AnyHit) {
@@ -945,42 +943,27 @@ void LowerRaytracingPipelinePassImpl::replaceContinuationCall(
Call->eraseFromParent();
}
-// If ReportHit is called for opaque geometry or if there is no AnyHit shader,
-// ReportHit has to store the passed hit attributes to the payload global.
-void LowerRaytracingPipelinePassImpl::handleReportHit(FunctionData &Data,
- Function &F) {
- auto *HitAttrsArg = F.getArg(F.arg_size() - 1);
-
- // Look for accept hit calls
- for (auto &BB : F) {
- for (auto &I : make_early_inc_range(BB)) {
- if (auto *Call = dyn_cast<CallInst>(&I)) {
- if (Call->getCalledFunction()->getName().starts_with(
- "_AmdAcceptHitAttributes")) {
- // Commit hit attributes
- Builder.SetInsertPoint(Call);
- assert(TraversalDataTy != 0 && "Missing traversal system data!");
- copyHitAttributes(Data, Call->getArgOperand(0), TraversalDataTy,
- HitAttrsArg, false, nullptr);
- // Make sure that we store the hit attributes into the correct system
- // data (just in case dxc copied them around).
- assert(Call->getArgOperand(0) == F.getArg(0) &&
- "AcceptHitAttributes does not take the correct system data as "
- "argument!");
- Call->eraseFromParent();
- }
- }
- }
- }
-}
-
-/// Replace a call to lgc.rt.shader.index with the passed shader index argument.
+/// Replace a call to lgc.rt.shader.index with the passed shader index argument
+/// for LgcCps mode or get the value from system data for non-LgcCps mode.
void LowerRaytracingPipelinePassImpl::replaceShaderIndexCall(FunctionData &Data,
CallInst *Call) {
if (Data.Kind == DXILShaderKind::RayGeneration) {
Call->replaceAllUsesWith(Builder.getInt32(0));
} else {
- auto *ShaderIndex = Call->getFunction()->getArg(ArgShaderIndex);
+ Value *ShaderIndex = nullptr;
+ if (MetadataState.isInLgcCpsMode()) {
+ ShaderIndex = Call->getFunction()->getArg(CpsArgIdxShaderIndex);
+ } else {
+ assert(Data.SystemDataFirstStore != nullptr);
+ Builder.SetInsertPoint(&*++Data.SystemDataFirstStore->getIterator());
+ ShaderIndex =
+ CrossInliner
+ .inlineCall(Builder, GetLocalRootIndex,
+ getDXILSystemData(
+ Builder, Data.SystemData, Data.SystemDataTy,
+ getFuncArgPtrElementType(GetLocalRootIndex, 0)))
+ .returnValue;
+ }
Call->replaceAllUsesWith(ShaderIndex);
}
Call->eraseFromParent();
@@ -1022,7 +1005,7 @@ void LowerRaytracingPipelinePassImpl::handleGetShaderKind(Function &Func) {
return;
DXILShaderKind ShaderKind =
- DXILContHelper::shaderStageToDxilShaderKind(*Stage);
+ ShaderStageHelper::shaderStageToDxilShaderKind(*Stage);
auto *ShaderKindVal = ConstantInt::get(Func.getReturnType(),
static_cast<uint64_t>(ShaderKind));
CInst.replaceAllUsesWith(ShaderKindVal);
@@ -1347,10 +1330,10 @@ void LowerRaytracingPipelinePassImpl::createPayloadGlobal() {
auto *PayloadTy = ArrayType::get(I32, MaxPayloadI32s);
Payload = cast<GlobalVariable>(
- Mod->getOrInsertGlobal(DXILContHelper::GlobalPayloadName, PayloadTy, [&] {
+ Mod->getOrInsertGlobal(ContHelper::GlobalPayloadName, PayloadTy, [&] {
auto *Payload = new GlobalVariable(
*Mod, PayloadTy, false, GlobalVariable::ExternalLinkage, nullptr,
- DXILContHelper::GlobalPayloadName, nullptr,
+ ContHelper::GlobalPayloadName, nullptr,
GlobalVariable::NotThreadLocal);
// Add registerbuffer metadata unconditionally to split all accesses
@@ -1366,13 +1349,11 @@ void LowerRaytracingPipelinePassImpl::createPayloadGlobal() {
}));
}
-void LowerRaytracingPipelinePassImpl::setTraversalRegisterCountMetadata() {
- const uint32_t NumI32s = std::min(
+void LowerRaytracingPipelinePassImpl::setGpurtEntryRegisterCountMetadata() {
+ const uint32_t MaxRegisterCount = std::min(
static_cast<uint32_t>(Payload->getValueType()->getArrayNumElements()),
MetadataState.getMaxPayloadRegisterCount());
- // Find traversal functions without walking over all functions by checking
- // uses of the `continuation.[wait]continue` intrinsics.
for (const auto &Name :
{"continuation.continue", "continuation.waitContinue"}) {
auto *Func = Mod->getFunction(Name);
@@ -1383,19 +1364,35 @@ void LowerRaytracingPipelinePassImpl::setTraversalRegisterCountMetadata() {
if (!isa<CallInst>(User) || CI->getCalledFunction() != Func)
continue;
- auto *TraversalVariant = CI->getFunction();
- auto Stage = lgc::rt::getLgcRtShaderStage(TraversalVariant);
- if (!Stage || *Stage != lgc::rt::RayTracingShaderStage::Traversal)
+ uint32_t InRegisterCount = 0;
+ uint32_t OutRegisterCount = 0;
+ auto *Func = CI->getFunction();
+ switch (lgc::rt::getLgcRtShaderStage(Func).value()) {
+ case lgc::rt::RayTracingShaderStage::Traversal:
+ InRegisterCount = MaxRegisterCount;
+ OutRegisterCount = MaxRegisterCount;
+ break;
+ case lgc::rt::RayTracingShaderStage::KernelEntry:
+ InRegisterCount = 0;
+ // Technically, we could likely use zero registers instead, but it
+ // shouldn't make a difference for performance, and assuming the
+ // worst-case avoids nasty errors in case we do use payload registers
+ // for some reason. Longer term, we'll get rid of the REGISTERS global
+ // and register count metadata anyways.
+ OutRegisterCount = MaxRegisterCount;
+ break;
+ default:
continue;
+ }
- assert(!DXILContHelper::tryGetOutgoingRegisterCount(CI).has_value() &&
+ assert(!ContHelper::tryGetOutgoingRegisterCount(CI).has_value() &&
"Unexpected register count metadata");
- DXILContHelper::setOutgoingRegisterCount(CI, NumI32s);
+ ContHelper::setOutgoingRegisterCount(CI, OutRegisterCount);
- assert(DXILContHelper::tryGetIncomingRegisterCount(TraversalVariant)
- .value_or(NumI32s) == NumI32s &&
+ assert(ContHelper::tryGetIncomingRegisterCount(Func).value_or(
+ InRegisterCount) == InRegisterCount &&
"Unexpected incoming register count on Traversal");
- DXILContHelper::setIncomingRegisterCount(TraversalVariant, NumI32s);
+ ContHelper::setIncomingRegisterCount(Func, InRegisterCount);
}
}
}
@@ -1409,28 +1406,14 @@ void LowerRaytracingPipelinePassImpl::processContinuations() {
}
}
-void LowerRaytracingPipelinePassImpl::processFunctionEntry(Function *F,
- FunctionData &Data) {
- // Create system data
+void LowerRaytracingPipelinePassImpl::processFunctionEntry(
+ FunctionData &Data, Argument *SystemDataArgument) {
// See also the system data documentation at the top of Continuations.h.
Data.SystemData = Builder.CreateAlloca(Data.SystemDataTy);
Data.SystemData->setName("system.data.alloca");
- // Initialize system data by calling the getSystemData intrinsic
- auto *SystemDataIntr =
- Builder.create<continuations::GetSystemDataOp>(Data.SystemDataTy);
- Builder.CreateStore(SystemDataIntr, Data.SystemData);
-
- // Set local root signature on entry
- assert(GetLocalRootIndex && "Could not find GetLocalRootIndex function");
- auto *LocalIndex =
- CrossInliner
- .inlineCall(
- Builder, GetLocalRootIndex,
- getDXILSystemData(Builder, Data.SystemData, Data.SystemDataTy,
- getFuncArgPtrElementType(GetLocalRootIndex, 0)))
- .returnValue;
- LocalIndex->setName("local.root.index");
- Builder.CreateCall(SetLocalRootIndex, LocalIndex);
+ // Initialize system data by copying the argument
+ Data.SystemDataFirstStore =
+ Builder.CreateStore(SystemDataArgument, Data.SystemData);
// Allocate payload spilling space
if (Data.PayloadSpillSize > 0)
@@ -1450,14 +1433,10 @@ void LowerRaytracingPipelinePassImpl::processFunctionEnd(
// acceptHitAndEndSearch or ignoreHit.
if (EData.Terminator != EData.Terminator->getParent()->getFirstNonPHI()) {
auto Before = --EData.Terminator->getIterator();
- if (auto *Call = dyn_cast<CallInst>(Before)) {
- if (auto *Callee = Call->getCalledFunction()) {
- if (isa<AcceptHitAndEndSearchOp>(Call))
- AHExitKind = AnyHitExitKind::AcceptHitAndEndSearch;
- else if (isa<IgnoreHitOp>(Call))
- AHExitKind = AnyHitExitKind::IgnoreHit;
- }
- }
+ if (isa<AcceptHitAndEndSearchOp>(Before))
+ AHExitKind = AnyHitExitKind::AcceptHitAndEndSearch;
+ else if (isa<IgnoreHitOp>(Before))
+ AHExitKind = AnyHitExitKind::IgnoreHit;
}
}
@@ -1528,21 +1507,25 @@ void LowerRaytracingPipelinePassImpl::processFunctionEnd(
RetValue = Builder.CreateLoad(Data.ReturnTy, SystemData);
}
- if (Mutator.shouldRun()) {
+ if (MetadataState.isInLgcCpsMode()) {
uint32_t CpsRetLevel = getPotentialCpsReturnLevels(
convertShaderKindToCpsShaderStage(Data.Kind));
- SmallVector<Value *> RetArgs;
-
- if (RetValue)
- RetArgs.push_back(RetValue);
if (Data.Kind == DXILShaderKind::RayGeneration) {
- assert(RetArgs.empty() && "RayGen cannot return anything");
+ assert(!RetValue && "RayGen cannot return anything");
Builder.CreateRetVoid();
} else {
+ // Jump to resume point of caller, pass Poison Rcr and ShaderIndex as they
+ // are not meaningful for the case.
+ SmallVector<Value *> TailArgs = {PoisonValue::get(I32),
+ PoisonValue::get(I32)};
+ if (RetValue)
+ TailArgs.push_back(RetValue);
+
Builder.create<JumpOp>(
- EData.Terminator->getFunction()->getArg(ArgReturnAddr), CpsRetLevel,
- PoisonValue::get(StructType::get(Builder.getContext())), RetArgs);
+ EData.Terminator->getFunction()->getArg(CpsArgIdxReturnAddr),
+ CpsRetLevel, PoisonValue::get(StructType::get(Builder.getContext())),
+ TailArgs);
Builder.CreateUnreachable();
}
} else {
@@ -1557,7 +1540,7 @@ void LowerRaytracingPipelinePassImpl::processFunctionEnd(
? std::min(EData.OutgoingSerializationLayout->NumStorageI32s,
MetadataState.getMaxPayloadRegisterCount())
: MetadataState.getMaxPayloadRegisterCount();
- DXILContHelper::setOutgoingRegisterCount(Ret, OutgoingRegisterCount);
+ ContHelper::setOutgoingRegisterCount(Ret, OutgoingRegisterCount);
}
EData.Terminator->eraseFromParent();
@@ -1572,7 +1555,7 @@ void LowerRaytracingPipelinePassImpl::processFunction(Function *F,
Type *NewRetTy;
Type *SystemDataTy = nullptr;
- if (Mutator.shouldRun()) {
+ if (MetadataState.isInLgcCpsMode()) {
// Create the CPS function header.
// A CPS function signature consists of:
@@ -1586,57 +1569,58 @@ void LowerRaytracingPipelinePassImpl::processFunction(Function *F,
AllArgTypes.push_back(Builder.getInt32Ty());
}
- if (Data.Kind == DXILShaderKind::RayGeneration) {
+ const auto SystemDataArgumentIndex = AllArgTypes.size();
+
+ switch (Data.Kind) {
+ case DXILShaderKind::RayGeneration: {
assert(SetupRayGen && "Could not find SetupRayGen function");
SystemDataTy = SetupRayGen->getReturnType();
+ AllArgTypes.push_back(SystemDataTy);
NewRetTy = Builder.getVoidTy();
- } else {
- switch (Data.Kind) {
- case DXILShaderKind::Intersection: {
- assert(TraversalDataTy && "Failed to detect traversal system data type");
- SystemDataTy = TraversalDataTy;
- AllArgTypes.push_back(SystemDataTy);
- NewRetTy = SystemDataTy;
- break;
- }
- case DXILShaderKind::AnyHit: {
- assert(TraversalDataTy && "Failed to detect traversal system data type");
- SystemDataTy = TraversalDataTy;
- AllArgTypes.push_back(SystemDataTy);
- AllArgTypes.push_back(Data.HitAttributes);
- NewRetTy = SystemDataTy;
- break;
- }
- case DXILShaderKind::ClosestHit:
- case DXILShaderKind::Miss: {
- assert(HitMissDataTy && "Failed to detect hit/miss system data type");
- assert(SetupRayGen && "Could not find SetupRayGen function");
- SystemDataTy = HitMissDataTy;
- AllArgTypes.push_back(SystemDataTy);
- NewRetTy = SetupRayGen->getReturnType();
- break;
- }
- case DXILShaderKind::Callable: {
- assert(SetupRayGen && "Could not find SetupRayGen function");
- SystemDataTy = SetupRayGen->getReturnType();
- AllArgTypes.push_back(SystemDataTy);
- NewRetTy = SystemDataTy;
- break;
- }
- default:
- llvm_unreachable("Unhandled ShaderKind");
- }
+ break;
+ }
+ case DXILShaderKind::Intersection: {
+ assert(TraversalDataTy && "Failed to detect traversal system data type");
+ SystemDataTy = TraversalDataTy;
+ AllArgTypes.push_back(SystemDataTy);
+ NewRetTy = SystemDataTy;
+ break;
+ }
+ case DXILShaderKind::AnyHit: {
+ assert(TraversalDataTy && "Failed to detect traversal system data type");
+ SystemDataTy = TraversalDataTy;
+ AllArgTypes.push_back(SystemDataTy);
+ AllArgTypes.push_back(Data.HitAttributes);
+ NewRetTy = SystemDataTy;
+ break;
+ }
+ case DXILShaderKind::ClosestHit:
+ case DXILShaderKind::Miss: {
+ assert(HitMissDataTy && "Failed to detect hit/miss system data type");
+ assert(SetupRayGen && "Could not find SetupRayGen function");
+ SystemDataTy = HitMissDataTy;
+ AllArgTypes.push_back(SystemDataTy);
+ NewRetTy = SetupRayGen->getReturnType();
+ break;
+ }
+ case DXILShaderKind::Callable: {
+ assert(SetupRayGen && "Could not find SetupRayGen function");
+ SystemDataTy = SetupRayGen->getReturnType();
+ AllArgTypes.push_back(SystemDataTy);
+ NewRetTy = SystemDataTy;
+ break;
+ }
+ default:
+ llvm_unreachable("Unhandled ShaderKind");
}
Data.PayloadSpillSize = computeNeededStackSizeForRegisterBuffer(
Data.MaxOutgoingPayloadI32s, MetadataState.getMaxPayloadRegisterCount());
- assert((Data.PayloadSpillSize == 0) ||
- (Data.Kind != DXILShaderKind::Intersection));
- Data.SystemDataTy = cast<StructType>(SystemDataTy);
- processFunctionEntry(F, Data);
+ assert(Data.PayloadSpillSize == 0 ||
+ Data.Kind != DXILShaderKind::Intersection);
auto *FunctionTypeRetTy =
- Mutator.shouldRun() ? Builder.getVoidTy() : NewRetTy;
+ MetadataState.isInLgcCpsMode() ? Builder.getVoidTy() : NewRetTy;
// Create new function to change signature
auto *NewFuncTy = FunctionType::get(FunctionTypeRetTy, AllArgTypes, false);
Function *NewFunc = CompilerUtils::cloneFunctionHeader(
@@ -1645,10 +1629,13 @@ void LowerRaytracingPipelinePassImpl::processFunction(Function *F,
llvm::moveFunctionBody(*F, *NewFunc);
- if (Mutator.shouldRun()) {
- NewFunc->getArg(ArgContState)->setName("cont.state");
- NewFunc->getArg(ArgReturnAddr)->setName("return.addr");
- NewFunc->getArg(ArgShaderIndex)->setName("shader.index");
+ Data.SystemDataTy = cast<StructType>(SystemDataTy);
+ processFunctionEntry(Data, NewFunc->getArg(SystemDataArgumentIndex));
+
+ if (MetadataState.isInLgcCpsMode()) {
+ NewFunc->getArg(CpsArgIdxContState)->setName("cont.state");
+ NewFunc->getArg(CpsArgIdxReturnAddr)->setName("return.addr");
+ NewFunc->getArg(CpsArgIdxShaderIndex)->setName("shader.index");
// Mark as CPS function with the corresponding level.
CpsLevel Level =
@@ -1658,12 +1645,11 @@ void LowerRaytracingPipelinePassImpl::processFunction(Function *F,
FunctionEndData EData;
if (Data.Kind == DXILShaderKind::RayGeneration) {
- if (!Mutator.shouldRun()) {
- NewFunc->setMetadata(DXILContHelper::MDEntryName,
- MDTuple::get(*Context, {}));
+ if (!MetadataState.isInLgcCpsMode()) {
+ NewFunc->setMetadata(ContHelper::MDEntryName, MDTuple::get(*Context, {}));
// Entry functions have no incoming payload or continuation state
- DXILContHelper::setIncomingRegisterCount(NewFunc, 0);
+ ContHelper::setIncomingRegisterCount(NewFunc, 0);
}
} else {
// Ignore payload for intersection shaders, they don't touch payload
@@ -1713,11 +1699,11 @@ void LowerRaytracingPipelinePassImpl::processFunction(Function *F,
FPayload->replaceAllUsesWith(NewPayload);
}
- if (Mutator.shouldRun()) {
+ if (MetadataState.isInLgcCpsMode()) {
// TODO Read payload argument for lgc continuations
} else {
// Annotate function with the number of registers for incoming payload
- DXILContHelper::setIncomingRegisterCount(
+ ContHelper::setIncomingRegisterCount(
NewFunc, std::min(IncomingSerializationLayout.NumStorageI32s,
MetadataState.getMaxPayloadRegisterCount()));
@@ -1785,14 +1771,14 @@ void LowerRaytracingPipelinePassImpl::processFunction(Function *F,
true, &IncomingSerializationLayout);
}
} else {
- if (!Mutator.shouldRun()) {
+ if (!MetadataState.isInLgcCpsMode()) {
// Annotate intersection shader with the maximum number of registers
// used for payload
// TODO: When compiling a pipeline and not a library, we could figure
// out the pipeline-wide max (on a higher level than here) and use
// that instead. For a library compile, we can't know the max
// payload size of shaders in pipelines this shader is used in.
- DXILContHelper::setIncomingRegisterCount(
+ ContHelper::setIncomingRegisterCount(
NewFunc, MetadataState.getMaxPayloadRegisterCount());
}
}
@@ -1828,7 +1814,7 @@ void LowerRaytracingPipelinePassImpl::processFunction(Function *F,
F = NewFunc;
MDTuple *ContMDTuple = MDTuple::get(*Context, {ValueAsMetadata::get(F)});
- F->setMetadata(DXILContHelper::MDContinuationName, ContMDTuple);
+ F->setMetadata(ContHelper::MDContinuationName, ContMDTuple);
// Replace TraceRay calls
for (auto *Call : Data.TraceRayCalls) {
@@ -1851,10 +1837,8 @@ void LowerRaytracingPipelinePassImpl::processFunction(Function *F,
}
// Replace ShaderIndexOp calls
- for (auto *Call : Data.ShaderIndexCalls) {
- Builder.SetInsertPoint(&*++Call->getIterator());
+ for (auto *Call : Data.ShaderIndexCalls)
replaceShaderIndexCall(Data, Call);
- }
// Replace non-rematerializable intrinsic calls
for (auto *Call : Data.IntrinsicCalls)
@@ -1862,12 +1846,13 @@ void LowerRaytracingPipelinePassImpl::processFunction(Function *F,
Call, GpurtLibrary, CrossInliner);
#ifndef NDEBUG
- if (!Mutator.shouldRun() && Data.Kind != DXILShaderKind::RayGeneration) {
+ if (!MetadataState.isInLgcCpsMode() &&
+ Data.Kind != DXILShaderKind::RayGeneration) {
// Check that all returns have registercount metadata
for (const auto &BB : *F) {
auto *Terminator = BB.getTerminator();
if (Terminator->getOpcode() == Instruction::Ret &&
- !DXILContHelper::tryGetOutgoingRegisterCount(Terminator))
+ !ContHelper::tryGetOutgoingRegisterCount(Terminator))
report_fatal_error("Missing registercount metadata!");
}
}
@@ -1877,8 +1862,10 @@ void LowerRaytracingPipelinePassImpl::processFunction(Function *F,
static uint32_t getMaxHitAttributeByteCount(const Function &F) {
// Use max hit attribute size from metadata, or use globally max allowed
// value for the max if metadata is not set
- uint32_t Result = DXILContHelper::tryGetMaxHitAttributeByteCount(F).value_or(
- GlobalMaxHitAttributeBytes);
+ uint32_t Result = lgc::rt::getShaderHitAttributeSize(&F);
+ if (Result == 0)
+ Result = GlobalMaxHitAttributeBytes;
+
if (Result % RegisterBytes != 0) {
auto AlignedSize = alignTo(Result, RegisterBytes);
LLVM_DEBUG(dbgs() << "Aligning misaligned max hit attribute size " << Result
@@ -1894,7 +1881,8 @@ void LowerRaytracingPipelinePassImpl::collectProcessableFunctions() {
if (!Stage || Func.isDeclaration())
continue;
- DXILShaderKind Kind = DXILContHelper::shaderStageToDxilShaderKind(*Stage);
+ DXILShaderKind Kind =
+ ShaderStageHelper::shaderStageToDxilShaderKind(*Stage);
switch (Kind) {
case DXILShaderKind::RayGeneration:
case DXILShaderKind::Intersection:
@@ -1941,76 +1929,6 @@ void LowerRaytracingPipelinePassImpl::collectProcessableFunctions() {
}
}
-// Assert that the types of the different driver functions are as expected
-void LowerRaytracingPipelinePassImpl::handleDriverFuncAssertions() {
- if (IsEndSearch)
- assert(IsEndSearch->getReturnType() == Type::getInt1Ty(*Context) &&
- IsEndSearch->arg_size() == 1
- // Traversal data
- && IsEndSearch->getFunctionType()->getParamType(0)->isPointerTy());
-
- if (GetTriangleHitAttributes)
- assert(GetTriangleHitAttributes->getReturnType()
- ->isStructTy() // BuiltinTriangleIntersectionAttributes
- && GetTriangleHitAttributes->arg_size() == 1
- // System data
- && GetTriangleHitAttributes->getFunctionType()
- ->getParamType(0)
- ->isPointerTy());
-
- if (SetTriangleHitAttributes)
- assert(SetTriangleHitAttributes->getReturnType()->isVoidTy() &&
- SetTriangleHitAttributes->arg_size() == 2
- // System data
- && SetTriangleHitAttributes->getFunctionType()
- ->getParamType(0)
- ->isPointerTy()
- // BuiltinTriangleIntersectionAttributes
- && SetTriangleHitAttributes->getFunctionType()
- ->getParamType(1)
- ->isStructTy());
-
- if (GetLocalRootIndex)
- assert(
- GetLocalRootIndex->getReturnType() ==
- Type::getInt32Ty(Mod->getContext()) &&
- GetLocalRootIndex->arg_size() == 1
- // Dispatch data
- &&
- GetLocalRootIndex->getFunctionType()->getParamType(0)->isPointerTy());
-
- if (SetupRayGen)
- assert(SetupRayGen->getReturnType()->isStructTy() &&
- SetupRayGen->arg_empty());
-
- if (TraceRay)
- assert(TraceRay->getReturnType()->isVoidTy() &&
- TraceRay->arg_size() == 15
- // Dispatch data
- && TraceRay->getFunctionType()->getParamType(0)->isPointerTy());
-
- if (CallShader)
- assert(CallShader->getReturnType()->isVoidTy() &&
- CallShader->arg_size() == 2
- // Dispatch data
- && CallShader->getFunctionType()->getParamType(0)->isPointerTy()
- // Shader id
- && CallShader->getFunctionType()->getParamType(1) ==
- Type::getInt32Ty(*Context));
-
- if (ReportHit)
- assert(ReportHit->getReturnType()->isIntegerTy(1) &&
- ReportHit->arg_size() == 3
- // Traversal data
- && ReportHit->getFunctionType()->getParamType(0)->isPointerTy());
-
- if (AcceptHit)
- assert(AcceptHit->getReturnType()->isVoidTy() &&
- AcceptHit->arg_size() == 1
- // Traversal data
- && AcceptHit->getFunctionType()->getParamType(0)->isPointerTy());
-}
-
void LowerRaytracingPipelinePassImpl::handleAmdInternalFunc(Function &Func) {
StringRef FuncName = Func.getName();
@@ -2040,7 +1958,7 @@ void LowerRaytracingPipelinePassImpl::handleAmdInternalFunc(Function &Func) {
// argument.
void LowerRaytracingPipelinePassImpl::splitRestoreBB() {
for (auto &F : *Mod) {
- if (F.getName().startswith("_AmdRestoreSystemData")) {
+ if (F.getName().starts_with("_AmdRestoreSystemData")) {
llvm::forEachCall(F, [](llvm::CallInst &CInst) {
auto *Next = &*++CInst.getIterator();
CInst.eraseFromParent();
@@ -2054,7 +1972,7 @@ void LowerRaytracingPipelinePassImpl::splitRestoreBB() {
// Search for known intrinsics that cannot be rematerialized
void LowerRaytracingPipelinePassImpl::handleUnrematerializableCandidates() {
for (auto &Func : *Mod) {
- if (!DialectUtils::isLgcRtOp(&Func))
+ if (!llvm::isLgcRtOp(&Func))
continue;
static const llvm_dialects::OpSet NonRematerializableDialectOps =
@@ -2064,8 +1982,7 @@ void LowerRaytracingPipelinePassImpl::handleUnrematerializableCandidates() {
llvm::forEachCall(Func, [&](llvm::CallInst &CInst) {
auto Data = ToProcess.find(CInst.getFunction());
if (Data != ToProcess.end()) {
- if (!DXILContHelper::isRematerializableLgcRtOp(CInst,
- Data->second.Kind))
+ if (!ContHelper::isRematerializableLgcRtOp(CInst, Data->second.Kind))
Data->second.IntrinsicCalls.push_back(&CInst);
}
});
@@ -2073,32 +1990,100 @@ void LowerRaytracingPipelinePassImpl::handleUnrematerializableCandidates() {
}
}
-void LowerRaytracingPipelinePassImpl::collectDriverFunctions() {
+// Collect GPURT functions and do precondition checks on the fly.
+void LowerRaytracingPipelinePassImpl::collectGpuRtFunctions() {
IsEndSearch = GpurtLibrary->getFunction("_cont_IsEndSearch");
+ if (IsEndSearch)
+ assert(IsEndSearch->getReturnType() == Type::getInt1Ty(*Context) &&
+ IsEndSearch->arg_size() == 1
+ // Traversal data
+ && IsEndSearch->getFunctionType()->getParamType(0)->isPointerTy());
+
GetTriangleHitAttributes =
GpurtLibrary->getFunction("_cont_GetTriangleHitAttributes");
+ if (GetTriangleHitAttributes)
+ assert(GetTriangleHitAttributes->getReturnType()
+ ->isStructTy() // BuiltinTriangleIntersectionAttributes
+ && GetTriangleHitAttributes->arg_size() == 1
+ // System data
+ && GetTriangleHitAttributes->getFunctionType()
+ ->getParamType(0)
+ ->isPointerTy());
+
SetTriangleHitAttributes =
GpurtLibrary->getFunction("_cont_SetTriangleHitAttributes");
+ if (SetTriangleHitAttributes)
+ assert(SetTriangleHitAttributes->getReturnType()->isVoidTy() &&
+ SetTriangleHitAttributes->arg_size() == 2
+ // System data
+ && SetTriangleHitAttributes->getFunctionType()
+ ->getParamType(0)
+ ->isPointerTy()
+ // BuiltinTriangleIntersectionAttributes
+ && SetTriangleHitAttributes->getFunctionType()
+ ->getParamType(1)
+ ->isStructTy());
+
GetLocalRootIndex = GpurtLibrary->getFunction("_cont_GetLocalRootIndex");
+ if (GetLocalRootIndex)
+ assert(
+ GetLocalRootIndex->getReturnType() ==
+ Type::getInt32Ty(Mod->getContext()) &&
+ GetLocalRootIndex->arg_size() == 1
+ // Dispatch data
+ &&
+ GetLocalRootIndex->getFunctionType()->getParamType(0)->isPointerTy());
+
SetLocalRootIndex = getSetLocalRootIndex(*Mod);
+
SetupRayGen = GpurtLibrary->getFunction("_cont_SetupRayGen");
+ if (SetupRayGen)
+ assert(SetupRayGen->getReturnType()->isStructTy() &&
+ SetupRayGen->arg_empty());
+
TraceRay = GpurtLibrary->getFunction("_cont_TraceRay");
+ if (TraceRay)
+ assert(TraceRay->getReturnType()->isVoidTy() &&
+ TraceRay->arg_size() == 15
+ // Dispatch data
+ && TraceRay->getFunctionType()->getParamType(0)->isPointerTy());
+
CallShader = GpurtLibrary->getFunction("_cont_CallShader");
+ if (CallShader)
+ assert(CallShader->getReturnType()->isVoidTy() &&
+ CallShader->arg_size() == 2
+ // Dispatch data
+ && CallShader->getFunctionType()->getParamType(0)->isPointerTy()
+ // Shader id
+ && CallShader->getFunctionType()->getParamType(1) ==
+ Type::getInt32Ty(*Context));
+
ReportHit = GpurtLibrary->getFunction("_cont_ReportHit");
+ if (ReportHit)
+ assert(ReportHit->getReturnType()->isIntegerTy(1) &&
+ ReportHit->arg_size() == 3
+ // Traversal data
+ && ReportHit->getFunctionType()->getParamType(0)->isPointerTy());
+
AcceptHit = GpurtLibrary->getFunction("_cont_AcceptHit");
+ if (AcceptHit)
+ assert(AcceptHit->getReturnType()->isVoidTy() &&
+ AcceptHit->arg_size() == 1
+ // Traversal data
+ && AcceptHit->getFunctionType()->getParamType(0)->isPointerTy());
}
LowerRaytracingPipelinePassImpl::LowerRaytracingPipelinePassImpl(
llvm::Module &M, Module &GpurtLibrary)
: Mod{&M}, GpurtLibrary{&GpurtLibrary}, Context{&M.getContext()},
DL{&M.getDataLayout()}, Builder{Mod->getContext()}, MetadataState{*Mod},
- Mutator{*Mod}, PAQManager{Mod, &GpurtLibrary,
- MetadataState.getMaxPayloadRegisterCount()} {}
+ PAQManager{Mod, &GpurtLibrary,
+ MetadataState.getMaxPayloadRegisterCount()} {}
bool LowerRaytracingPipelinePassImpl::run() {
MetadataState.updateModuleMetadata();
- collectDriverFunctions();
+ collectGpuRtFunctions();
collectProcessableFunctions();
@@ -2122,8 +2107,7 @@ bool LowerRaytracingPipelinePassImpl::run() {
return;
}
- Type *PayloadTy =
- DXILContHelper::getPayloadTypeFromMetadata(*CInst);
+ Type *PayloadTy = ContHelper::getPayloadTypeFromMetadata(*CInst);
if (!isa<ReportHitOp>(Op)) {
PAQPayloadConfig PAQPayload = {
@@ -2163,7 +2147,6 @@ bool LowerRaytracingPipelinePassImpl::run() {
Visitor.visit(S, *Mod);
handleUnrematerializableCandidates();
- handleDriverFuncAssertions();
// Find the traversal system data type by looking at the argument to
// ReportHit.
@@ -2178,7 +2161,7 @@ bool LowerRaytracingPipelinePassImpl::run() {
}
createPayloadGlobal();
- setTraversalRegisterCountMetadata();
+ setGpurtEntryRegisterCountMetadata();
processContinuations();
@@ -2194,21 +2177,18 @@ bool LowerRaytracingPipelinePassImpl::run() {
// For tests, remove intrinsic implementations from the module
for (auto &F : make_early_inc_range(*Mod)) {
auto Name = F.getName();
- if (Name.startswith("_cont_TraceRay") ||
- Name.startswith("_cont_CallShader") ||
- Name.startswith("_cont_ReportHit")) {
+ if (Name.starts_with("_cont_TraceRay") ||
+ Name.starts_with("_cont_CallShader") ||
+ Name.starts_with("_cont_ReportHit")) {
F.eraseFromParent();
}
}
}
+ // Remove bitcasts and the DXIL Payload Type metadata in one step to save one
+ // full iteration over all functions.
fixupDxilMetadata(*Mod);
- for (Function &F : *Mod) {
- // Remove the DXIL Payload Type metadata
- F.setMetadata(DXILContHelper::MDDXILPayloadTyName, nullptr);
- }
-
llvm::removeUnusedFunctionDecls(Mod);
return true;
diff --git a/shared/continuations/lib/PassRegistry.inc b/shared/continuations/lib/PassRegistry.inc
index ce65a5559e..3c010e88a5 100644
--- a/shared/continuations/lib/PassRegistry.inc
+++ b/shared/continuations/lib/PassRegistry.inc
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/shared/continuations/lib/PayloadAccessQualifiers.cpp b/shared/continuations/lib/PayloadAccessQualifiers.cpp
index 35fa424736..84c3ac40b7 100644
--- a/shared/continuations/lib/PayloadAccessQualifiers.cpp
+++ b/shared/continuations/lib/PayloadAccessQualifiers.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -141,7 +141,8 @@ static std::string
determineSerializationInfoPrefix(const PAQPayloadConfig &PAQConfig) {
std::string Result;
raw_string_ostream Str{Result};
- Str << PAQConfig.PayloadTy->getStructName();
+ if (cast<StructType>(PAQConfig.PayloadTy)->hasName())
+ Str << PAQConfig.PayloadTy->getStructName();
if (PAQConfig.MaxHitAttributeByteCount != 0) {
assert(PAQConfig.MaxHitAttributeByteCount % RegisterBytes == 0);
Str << ".attr_max_" << PAQConfig.MaxHitAttributeByteCount / RegisterBytes
@@ -273,7 +274,7 @@ static void printPAQNodeImpl(llvm::raw_ostream &Stream, const PAQNode &Node,
Stream << "<no lifetime class>";
}
- if (Node.Ty->isStructTy()) {
+ if (Node.Ty->isStructTy() && cast<StructType>(Node.Ty)->hasName()) {
Stream << ", Type: " << Node.Ty->getStructName();
}
Stream << "\n";
@@ -331,8 +332,10 @@ void PAQSerializationLayout::print(raw_ostream &O, bool SingleLine) const {
assert(PayloadRootNode);
auto *Indent = " ";
- O << "Serialization layout for type " << PayloadRootNode->Ty->getStructName()
- << "\n";
+ auto TypeName = cast<StructType>(PayloadRootNode->Ty)->hasName()
+ ? PayloadRootNode->Ty->getStructName()
+ : "unnamed";
+ O << "Serialization layout for type " << TypeName << "\n";
// Print type with body
O << Indent << "Serialization struct type: " << *SerializationTy << "\n";
diff --git a/shared/continuations/lib/RegisterBuffer.cpp b/shared/continuations/lib/RegisterBuffer.cpp
index 2164a839a6..d59457b04a 100644
--- a/shared/continuations/lib/RegisterBuffer.cpp
+++ b/shared/continuations/lib/RegisterBuffer.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -719,8 +719,7 @@ RegisterBufferPass::run(llvm::Module &M,
OpCode == Instruction::AddrSpaceCast;
}
- if (isa<GetElementPtrInst>(Use) || isa<BitCastInst>(Use) ||
- IsConstExprCast) {
+ if (isa<GetElementPtrInst, BitCastInst>(Use) || IsConstExprCast) {
for (auto *U : Use->users()) {
if (!UseList.count(U)) {
UseList.insert(U);
@@ -729,8 +728,7 @@ RegisterBufferPass::run(llvm::Module &M,
LLVM_DEBUG(dbgs() << "Already there " << *U << "\n");
}
}
- } else if (isa<LoadInst>(Use) || isa<StoreInst>(Use) ||
- isa<CallInst>(Use)) {
+ } else if (isa<LoadInst, StoreInst, CallInst>(Use)) {
Uses.push_back(Use);
} else {
LLVM_DEBUG(dbgs() << "Failed to handle use of global: " << *Use
@@ -753,10 +751,10 @@ RegisterBufferPass::run(llvm::Module &M,
auto Name = Intr->getName();
// Ignore registerbuffer.setpointerbarrier barriers but leave them in
// the code
- if (Name.startswith("registerbuffer.setpointerbarrier"))
+ if (Name.starts_with("registerbuffer.setpointerbarrier"))
continue;
- if (Name.startswith("llvm.lifetime.")) {
+ if (Name.starts_with("llvm.lifetime.")) {
// Remove lifetime intrinsics, these are an optimization only
} else {
LLVM_DEBUG(dbgs() << "Failed to handle call taking global address: "
diff --git a/shared/continuations/lib/RemoveTypesMetadata.cpp b/shared/continuations/lib/RemoveTypesMetadata.cpp
index 712796a157..b0c569ac1f 100644
--- a/shared/continuations/lib/RemoveTypesMetadata.cpp
+++ b/shared/continuations/lib/RemoveTypesMetadata.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/shared/continuations/lib/SaveContinuationState.cpp b/shared/continuations/lib/SaveContinuationState.cpp
index cf5787fa74..a350484fb7 100644
--- a/shared/continuations/lib/SaveContinuationState.cpp
+++ b/shared/continuations/lib/SaveContinuationState.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -64,7 +64,7 @@ void SaveContinuationStatePass::lowerCsp(Function *Intr) {
auto *CspType = getContinuationStackOffsetType(F->getContext());
auto *Csp = B->CreateAlloca(CspType);
Csp->setName("csp");
- bool IsEntry = F->hasMetadata(DXILContHelper::MDEntryName);
+ bool IsEntry = F->hasMetadata(ContHelper::MDEntryName);
if (IsEntry) {
// Init csp through intrinsic
auto *Init = getContinuationCspInit(*F->getParent());
diff --git a/shared/continuations/lib/DXILMetadata.cpp b/shared/continuations/lib/TypesMetadata.cpp
similarity index 75%
rename from shared/continuations/lib/DXILMetadata.cpp
rename to shared/continuations/lib/TypesMetadata.cpp
index 1652e8c4dc..b17d2c52a4 100644
--- a/shared/continuations/lib/DXILMetadata.cpp
+++ b/shared/continuations/lib/TypesMetadata.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,12 +18,12 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
-//===- DXILMetadata.cpp - Generators, decoders and wrappers for metadata --===//
+//===- TypesMetadata.cpp - Generators, decoders and wrappers for metadata --==//
//
// This file implements metadata functions for the DXIL continuations
//
@@ -33,28 +33,28 @@
namespace llvm {
-DXILContArgTy::DXILContArgTy(Type *Arg) {
+ContArgTy::ContArgTy(Type *Arg) {
assert(!Arg->isPointerTy() &&
"pointers are not supported by this constructor");
ArgTy = Arg;
ElemTy = nullptr;
}
-DXILContArgTy DXILContArgTy::get(const Function *F, const Argument *Arg) {
+ContArgTy ContArgTy::get(const Function *F, const Argument *Arg) {
// only consult metadata for pointer types
Type *ArgTy = Arg->getType();
if (!ArgTy->isPointerTy())
- return DXILContArgTy(ArgTy, nullptr);
+ return ContArgTy(ArgTy, nullptr);
// types metadata of the form { !"function", <return-type>,
// <argument-0-type>, ... }
- auto *TypesMD = F->getMetadata(DXILContHelper::MDTypesName);
+ auto *TypesMD = F->getMetadata(ContHelper::MDTypesName);
if (TypesMD) {
unsigned ArgNo = Arg->getArgNo() + 2;
assert(ArgNo < TypesMD->getNumOperands() &&
"insufficient operands in types metadata");
- DXILContArgTy Result = get(&*TypesMD->getOperand(ArgNo), F->getContext());
+ ContArgTy Result = get(&*TypesMD->getOperand(ArgNo), F->getContext());
return Result;
}
@@ -62,18 +62,18 @@ DXILContArgTy DXILContArgTy::get(const Function *F, const Argument *Arg) {
report_fatal_error("Missing metadata for pointer type!");
}
-DXILContArgTy DXILContArgTy::get(const Function *F, const unsigned ArgNo) {
+ContArgTy ContArgTy::get(const Function *F, const unsigned ArgNo) {
return get(F, F->getArg(ArgNo));
}
-DXILContArgTy DXILContArgTy::get(const Metadata *MD, LLVMContext &Context) {
+ContArgTy ContArgTy::get(const Metadata *MD, LLVMContext &Context) {
if (const auto *ConstantMD = dyn_cast<ConstantAsMetadata>(MD)) {
- return DXILContArgTy(ConstantMD->getType(), nullptr);
+ return ContArgTy(ConstantMD->getType(), nullptr);
}
if (const auto *StringMD = dyn_cast<MDString>(MD)) {
- assert(StringMD->getString() == DXILContHelper::MDTypesVoidName &&
+ assert(StringMD->getString() == ContHelper::MDTypesVoidName &&
"unknown string in types metadata");
- return DXILContArgTy(Type::getVoidTy(Context));
+ return ContArgTy(Type::getVoidTy(Context));
}
if (const auto *PointerMD = dyn_cast<MDNode>(MD)) {
assert(PointerMD && PointerMD->getNumOperands() == 2 &&
@@ -90,28 +90,28 @@ DXILContArgTy DXILContArgTy::get(const Metadata *MD, LLVMContext &Context) {
Type *ElemTy = ValueMD->getType();
Type *PtrTy =
ElemTy->getPointerTo((unsigned)AddressSpace->getZExtValue());
- return DXILContArgTy(PtrTy, ElemTy);
+ return ContArgTy(PtrTy, ElemTy);
}
}
assert(false && "unknown node type in types metadata");
- return DXILContArgTy(Type::getVoidTy(Context));
+ return ContArgTy(Type::getVoidTy(Context));
}
-Type *DXILContArgTy::asType(LLVMContext &Context) { return ArgTy; }
+Type *ContArgTy::asType(LLVMContext &Context) { return ArgTy; }
-Type *DXILContArgTy::getPointerElementType() const {
+Type *ContArgTy::getPointerElementType() const {
assert(ElemTy && "cannot get element type of non-pointer");
return ElemTy;
}
-bool DXILContArgTy::isPointerTy() const { return !!ElemTy; }
+bool ContArgTy::isPointerTy() const { return !!ElemTy; }
-bool DXILContArgTy::isVoidTy() const { return (!ArgTy || ArgTy->isVoidTy()); }
+bool ContArgTy::isVoidTy() const { return (!ArgTy || ArgTy->isVoidTy()); }
-Metadata *DXILContArgTy::getTypeMetadata(LLVMContext &Context) {
+Metadata *ContArgTy::getTypeMetadata(LLVMContext &Context) {
if (isVoidTy())
- return MDString::get(Context, DXILContHelper::MDTypesVoidName);
+ return MDString::get(Context, ContHelper::MDTypesVoidName);
if (!ElemTy) {
assert(ArgTy && !ArgTy->isPointerTy());
@@ -128,14 +128,14 @@ Metadata *DXILContArgTy::getTypeMetadata(LLVMContext &Context) {
return MDTuple::get(Context, MD);
}
-DXILContFuncTy DXILContFuncTy::get(const Function *F) {
- auto *TypesMD = F->getMetadata(DXILContHelper::MDTypesName);
+ContFuncTy ContFuncTy::get(const Function *F) {
+ auto *TypesMD = F->getMetadata(ContHelper::MDTypesName);
assert(TypesMD);
return get(TypesMD, F->getContext());
}
-DXILContFuncTy DXILContFuncTy::get(const Metadata *MD, LLVMContext &Context) {
+ContFuncTy ContFuncTy::get(const Metadata *MD, LLVMContext &Context) {
// Decode types metadata of the form { !"function", <return-type>,
// <argument-0-type>, ... }
const MDNode *TypesMD = dyn_cast<MDNode>(MD);
@@ -145,13 +145,13 @@ DXILContFuncTy DXILContFuncTy::get(const Metadata *MD, LLVMContext &Context) {
assert(TypesMD->getNumOperands() >= 2 && "invalid function metadata");
assert(isa<MDString>(TypesMD->getOperand(0)) &&
dyn_cast<MDString>(TypesMD->getOperand(0))->getString() ==
- DXILContHelper::MDTypesFunctionName &&
+ ContHelper::MDTypesFunctionName &&
"metadata is not a function type");
- DXILContFuncTy FuncTy;
+ ContFuncTy FuncTy;
for (unsigned OpNo = 1; OpNo < TypesMD->getNumOperands(); ++OpNo) {
Metadata *Arg = TypesMD->getOperand(OpNo);
- FuncTy.ArgTys.push_back(DXILContArgTy::get(Arg, Context));
+ FuncTy.ArgTys.push_back(ContArgTy::get(Arg, Context));
}
// FIXME: do something more efficient
assert(FuncTy.ArgTys.size() >= 1);
@@ -160,18 +160,18 @@ DXILContFuncTy DXILContFuncTy::get(const Metadata *MD, LLVMContext &Context) {
return FuncTy;
}
-FunctionType *DXILContFuncTy::asFunctionType(LLVMContext &Context) {
+FunctionType *ContFuncTy::asFunctionType(LLVMContext &Context) {
SmallVector<Type *> FuncArgTys;
for (auto Arg : ArgTys)
FuncArgTys.push_back(Arg.asType(Context));
return FunctionType::get(ReturnTy.asType(Context), FuncArgTys, false);
}
-void DXILContFuncTy::writeMetadata(Function *F) {
+void ContFuncTy::writeMetadata(Function *F) {
// Don't generate metadata if there are no pointers
if (!ReturnTy.isPointerTy() &&
llvm::none_of(ArgTys,
- [](const DXILContArgTy &Arg) { return Arg.isPointerTy(); }))
+ [](const ContArgTy &Arg) { return Arg.isPointerTy(); }))
return;
LLVMContext &Context = F->getContext();
@@ -180,14 +180,13 @@ void DXILContFuncTy::writeMetadata(Function *F) {
// Encode types metadata of the form { !"function", <return-type>,
// <argument-0-type>, ... }
SignatureMD.push_back(
- MDString::get(Context, DXILContHelper::MDTypesFunctionName));
+ MDString::get(Context, ContHelper::MDTypesFunctionName));
SignatureMD.push_back(ReturnTy.getTypeMetadata(Context));
for (auto ArgTy : ArgTys)
SignatureMD.push_back(ArgTy.getTypeMetadata(Context));
assert(SignatureMD.size() >= 2 && "return type must be specified");
- F->setMetadata(DXILContHelper::MDTypesName,
- MDTuple::get(Context, SignatureMD));
+ F->setMetadata(ContHelper::MDTypesName, MDTuple::get(Context, SignatureMD));
}
static Metadata *getTypeMetadataEntry(unsigned TypeID, LLVMContext &Context,
@@ -214,11 +213,11 @@ getTypeMetadataEntryImpl(Type *Ty, unsigned TypeID, LLVMContext &Context,
// Save the function signature as metadata
SmallVector<Metadata *> SignatureMD;
SignatureMD.push_back(
- MDString::get(Context, DXILContHelper::MDTypesFunctionName));
+ MDString::get(Context, ContHelper::MDTypesFunctionName));
// Return type
if (FTy->getReturnType()->isVoidTy()) {
SignatureMD.push_back(
- MDString::get(Context, DXILContHelper::MDTypesVoidName));
+ MDString::get(Context, ContHelper::MDTypesVoidName));
} else {
SignatureMD.push_back(getTypeMetadataEntry(GetContainedTypeID(TypeID, 0),
Context, GetTypeByID,
@@ -257,9 +256,9 @@ static Metadata *getTypeMetadataEntry(unsigned TypeID, LLVMContext &Context,
return nullptr;
assert(((Ty->isFunctionTy() &&
- DXILContFuncTy::get(MD, Context).asFunctionType(Context) == Ty) ||
+ ContFuncTy::get(MD, Context).asFunctionType(Context) == Ty) ||
(!Ty->isFunctionTy() &&
- DXILContArgTy::get(MD, Context).asType(Context) == Ty)) &&
+ ContArgTy::get(MD, Context).asType(Context) == Ty)) &&
"MD Type mismatch");
return MD;
}
@@ -271,7 +270,7 @@ void DXILValueTypeMetadataCallback(Value *V, unsigned TypeID,
auto *MD = getTypeMetadataEntry(TypeID, F->getContext(), GetTypeByID,
GetContainedTypeID);
if (MD)
- F->setMetadata(DXILContHelper::MDTypesName, llvm::cast<llvm::MDNode>(MD));
+ F->setMetadata(ContHelper::MDTypesName, llvm::cast<llvm::MDNode>(MD));
}
}
diff --git a/shared/continuations/plugin/Plugin.cpp b/shared/continuations/plugin/Plugin.cpp
index 4b9a87e508..757f573966 100644
--- a/shared/continuations/plugin/Plugin.cpp
+++ b/shared/continuations/plugin/Plugin.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
@@ -37,7 +37,7 @@
llvm::PassPluginLibraryInfo getContinuationsPluginPluginInfo() {
return {LLVM_PLUGIN_API_VERSION, "Continuations", LLVM_VERSION_STRING,
[](llvm::PassBuilder &PB) {
- llvm::DXILContHelper::RegisterPasses(PB, true);
+ llvm::ContHelper::RegisterPasses(PB, true);
}};
}
diff --git a/shared/continuations/test/dx/cleanup-continuations-malloc.ll b/shared/continuations/test/dx/cleanup-continuations-malloc.ll
index 88c6a6f413..c878e8f543 100644
--- a/shared/continuations/test/dx/cleanup-continuations-malloc.ll
+++ b/shared/continuations/test/dx/cleanup-continuations-malloc.ll
@@ -11,45 +11,23 @@ declare %continuation.token* @async_fun()
define <4 x i32> @simple_await(<4 x i32> %arg) !continuation.registercount !1 {
; CHECK-LABEL: define void @simple_await(
-; CHECK-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], <4 x i32> [[ARG:%.*]]) !continuation.registercount !1 !continuation !2 !continuation.state !3 !continuation.stacksize !3 {
+; CHECK-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], <4 x i32> [[ARG:%.*]]) !continuation.registercount [[META1:![0-9]+]] !continuation [[META2:![0-9]+]] !continuation.state [[META3:![0-9]+]] !continuation.stacksize [[META3]] {
; CHECK-NEXT: AllocaSpillBB:
-; CHECK-NEXT: [[CONT_STATE:%.*]] = alloca [6 x i32], align 4
-; CHECK-NEXT: [[ARG_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; CHECK-NEXT: store <4 x i32> [[ARG]], ptr [[ARG_SPILL_ADDR]], align 4
-; CHECK-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME]], ptr [[CONT_STATE]], i32 0, i32 1
-; CHECK-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
; CHECK-NEXT: [[TMP0:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 24
-; CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP0]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
-; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP4]], align 4
-; CHECK-NEXT: store i32 [[TMP6]], ptr addrspace(21) [[TMP5]], align 4
-; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 1
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4
-; CHECK-NEXT: store i32 [[TMP9]], ptr addrspace(21) [[TMP8]], align 4
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 2
-; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP12]], ptr addrspace(21) [[TMP11]], align 4
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 3
-; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 3
-; CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP13]], align 4
-; CHECK-NEXT: store i32 [[TMP15]], ptr addrspace(21) [[TMP14]], align 4
-; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 4
-; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 4
-; CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4
-; CHECK-NEXT: store i32 [[TMP18]], ptr addrspace(21) [[TMP17]], align 4
-; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 5
-; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 5
-; CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP19]], align 4
-; CHECK-NEXT: store i32 [[TMP21]], ptr addrspace(21) [[TMP20]], align 4
-; CHECK-NEXT: [[TMP22:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
-; CHECK-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP23]], i64 ptrtoint (ptr @simple_await.resume.0 to i64)), !continuation.registercount !1, !continuation.returnedRegistercount !1
+; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP2]], i64 0
+; CHECK-NEXT: [[ARG_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME:%.*]], ptr addrspace(21) [[TMP3]], i32 0, i32 0
+; CHECK-NEXT: store <4 x i32> [[ARG]], ptr addrspace(21) [[ARG_SPILL_ADDR]], align 4
+; CHECK-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME]], ptr addrspace(21) [[TMP3]], i32 0, i32 1
+; CHECK-NEXT: store i64 [[RETURNADDR]], ptr addrspace(21) [[RETURNADDR_SPILL_ADDR]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 24
+; CHECK-NEXT: store i32 [[TMP6]], ptr [[TMP4]], align 4
+; CHECK-NEXT: [[TMP7:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+; CHECK-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP8]], i64 ptrtoint (ptr @simple_await.resume.0 to i64)), !continuation.registercount [[META1]], !continuation.returnedRegistercount !1
; CHECK-NEXT: unreachable
;
%tok = call %continuation.token* @async_fun(), !continuation.registercount !1, !continuation.returnedRegistercount !1
@@ -59,45 +37,23 @@ define <4 x i32> @simple_await(<4 x i32> %arg) !continuation.registercount !1 {
define void @simple_await_entry(<4 x i32> %arg, <4 x i32> addrspace(1)* %mem) !continuation.entry !0 !continuation.registercount !1 {
; CHECK-LABEL: define void @simple_await_entry(
-; CHECK-SAME: <4 x i32> [[ARG:%.*]], ptr addrspace(1) [[MEM:%.*]]) !continuation.registercount !1 !continuation.entry !4 !continuation !5 !continuation.state !3 !continuation.stacksize !3 {
+; CHECK-SAME: <4 x i32> [[ARG:%.*]], ptr addrspace(1) [[MEM:%.*]]) !continuation.registercount [[META1]] !continuation.entry [[META4:![0-9]+]] !continuation [[META5:![0-9]+]] !continuation.state [[META3]] !continuation.stacksize [[META3]] {
; CHECK-NEXT: AllocaSpillBB:
-; CHECK-NEXT: [[CONT_STATE:%.*]] = alloca [6 x i32], align 4
-; CHECK-NEXT: [[MEM_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 1
-; CHECK-NEXT: store ptr addrspace(1) [[MEM]], ptr [[MEM_SPILL_ADDR]], align 4
-; CHECK-NEXT: [[ARG_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME]], ptr [[CONT_STATE]], i32 0, i32 0
-; CHECK-NEXT: store <4 x i32> [[ARG]], ptr [[ARG_SPILL_ADDR]], align 4
; CHECK-NEXT: [[TMP0:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 24
-; CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP0]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
-; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP4]], align 4
-; CHECK-NEXT: store i32 [[TMP6]], ptr addrspace(21) [[TMP5]], align 4
-; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 1
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4
-; CHECK-NEXT: store i32 [[TMP9]], ptr addrspace(21) [[TMP8]], align 4
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 2
-; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP12]], ptr addrspace(21) [[TMP11]], align 4
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 3
-; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 3
-; CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP13]], align 4
-; CHECK-NEXT: store i32 [[TMP15]], ptr addrspace(21) [[TMP14]], align 4
-; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 4
-; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 4
-; CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4
-; CHECK-NEXT: store i32 [[TMP18]], ptr addrspace(21) [[TMP17]], align 4
-; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 5
-; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 5
-; CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP19]], align 4
-; CHECK-NEXT: store i32 [[TMP21]], ptr addrspace(21) [[TMP20]], align 4
-; CHECK-NEXT: [[TMP22:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
-; CHECK-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP23]], i64 ptrtoint (ptr @simple_await_entry.resume.0 to i64)), !continuation.registercount !1, !continuation.returnedRegistercount !1
+; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP2]], i64 0
+; CHECK-NEXT: [[MEM_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME:%.*]], ptr addrspace(21) [[TMP3]], i32 0, i32 1
+; CHECK-NEXT: store ptr addrspace(1) [[MEM]], ptr addrspace(21) [[MEM_SPILL_ADDR]], align 4
+; CHECK-NEXT: [[ARG_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME]], ptr addrspace(21) [[TMP3]], i32 0, i32 0
+; CHECK-NEXT: store <4 x i32> [[ARG]], ptr addrspace(21) [[ARG_SPILL_ADDR]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 24
+; CHECK-NEXT: store i32 [[TMP6]], ptr [[TMP4]], align 4
+; CHECK-NEXT: [[TMP7:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+; CHECK-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP8]], i64 ptrtoint (ptr @simple_await_entry.resume.0 to i64)), !continuation.registercount [[META1]], !continuation.returnedRegistercount !1
; CHECK-NEXT: unreachable
;
%tok = call %continuation.token* @async_fun(), !continuation.registercount !1, !continuation.returnedRegistercount !1
diff --git a/shared/continuations/test/dx/cleanup-continuations.ll b/shared/continuations/test/dx/cleanup-continuations.ll
index b300343f54..50c5dc0cd9 100644
--- a/shared/continuations/test/dx/cleanup-continuations.ll
+++ b/shared/continuations/test/dx/cleanup-continuations.ll
@@ -14,28 +14,23 @@ declare i32 @continuations.getReturnValue.i32() #0
declare void @continuation.return(i64, ...)
define { i8*, %continuation.token* } @simple_await(i8* %0) !continuation !0 !continuation.registercount !4 {
-; CHECK-LABEL: define void @simple_await() !continuation !1 !continuation.registercount !2 !continuation.state !3 !continuation.stacksize !3 {
+; CHECK-LABEL: define void @simple_await(
+; CHECK-SAME: ) !continuation [[META1:![0-9]+]] !continuation.registercount [[META2:![0-9]+]] !continuation.state [[META3:![0-9]+]] !continuation.stacksize [[META3]] {
; CHECK-NEXT: AllocaSpillBB:
-; CHECK-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
-; CHECK-NEXT: [[FRAMEPTR:%.*]] = bitcast ptr [[CONT_STATE]] to ptr
-; CHECK-NEXT: [[DOTSPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME:%.*]], ptr [[FRAMEPTR]], i32 0, i32 0
-; CHECK-NEXT: store i64 -1, ptr [[DOTSPILL_ADDR]], align 4
; CHECK-NEXT: [[TMP0:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 8
-; CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP0]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
-; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP4]], align 4
-; CHECK-NEXT: store i32 [[TMP6]], ptr addrspace(21) [[TMP5]], align 4
-; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 1
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4
-; CHECK-NEXT: store i32 [[TMP9]], ptr addrspace(21) [[TMP8]], align 4
-; CHECK-NEXT: [[TMP10:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-; CHECK-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP11]], i64 ptrtoint (ptr @simple_await.resume.0 to i64)), !continuation.registercount !2, !continuation.returnedRegistercount !2
+; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP2]], i64 0
+; CHECK-NEXT: [[FRAMEPTR:%.*]] = bitcast ptr addrspace(21) [[TMP3]] to ptr addrspace(21)
+; CHECK-NEXT: [[DOTSPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME:%.*]], ptr addrspace(21) [[FRAMEPTR]], i32 0, i32 0
+; CHECK-NEXT: store i64 -1, ptr addrspace(21) [[DOTSPILL_ADDR]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 8
+; CHECK-NEXT: store i32 [[TMP6]], ptr [[TMP4]], align 4
+; CHECK-NEXT: [[TMP7:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+; CHECK-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP8]], i64 ptrtoint (ptr @simple_await.resume.0 to i64)), !continuation.registercount [[META2]], !continuation.returnedRegistercount !2
; CHECK-NEXT: unreachable
;
AllocaSpillBB:
@@ -49,32 +44,23 @@ AllocaSpillBB:
define internal { i8*, %continuation.token* } @simple_await.resume.0(i8* noalias nonnull align 16 dereferenceable(8) %0, i1 %1) !continuation !0 {
; CHECK-LABEL: define dso_local void @simple_await.resume.0(
-; CHECK-SAME: i32 [[TMP0:%.*]]) !continuation !1 !continuation.registercount !2 {
+; CHECK-SAME: i32 [[TMP0:%.*]]) !continuation [[META1]] !continuation.registercount [[META2]] {
; CHECK-NEXT: entryresume.0:
-; CHECK-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
; CHECK-NEXT: [[TMP1:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(21)
-; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP3]], i64 -8
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(21) [[TMP5]], align 4
-; CHECK-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 1
-; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(21) [[TMP8]], align 4
-; CHECK-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4
-; CHECK-NEXT: [[TMP11:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
-; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[TMP12]], -8
-; CHECK-NEXT: store i32 [[TMP13]], ptr [[TMP11]], align 4
-; CHECK-NEXT: [[FRAMEPTR:%.*]] = bitcast ptr [[CONT_STATE]] to ptr
-; CHECK-NEXT: [[VFRAME:%.*]] = bitcast ptr [[FRAMEPTR]] to ptr
-; CHECK-NEXT: [[DOTRELOAD_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME:%.*]], ptr [[FRAMEPTR]], i32 0, i32 0
-; CHECK-NEXT: [[DOTRELOAD:%.*]] = load i64, ptr [[DOTRELOAD_ADDR]], align 4
-; CHECK-NEXT: [[TMP14:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
-; CHECK-NEXT: call void (i64, ...) @continuation.continue(i64 [[DOTRELOAD]], i32 [[TMP15]]), !continuation.registercount !2
+; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], -8
+; CHECK-NEXT: store i32 [[TMP3]], ptr [[TMP1]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i32 [[TMP5]] to ptr addrspace(21)
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP6]], i64 0
+; CHECK-NEXT: [[FRAMEPTR:%.*]] = bitcast ptr addrspace(21) [[TMP7]] to ptr addrspace(21)
+; CHECK-NEXT: [[VFRAME:%.*]] = bitcast ptr addrspace(21) [[FRAMEPTR]] to ptr addrspace(21)
+; CHECK-NEXT: [[DOTRELOAD_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME:%.*]], ptr addrspace(21) [[FRAMEPTR]], i32 0, i32 0
+; CHECK-NEXT: [[DOTRELOAD:%.*]] = load i64, ptr addrspace(21) [[DOTRELOAD_ADDR]], align 4
+; CHECK-NEXT: [[TMP8:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+; CHECK-NEXT: call void (i64, ...) @continuation.continue(i64 [[DOTRELOAD]], i32 [[TMP9]]), !continuation.registercount [[META2]]
; CHECK-NEXT: unreachable
;
entryresume.0:
@@ -87,26 +73,21 @@ entryresume.0:
}
define { i8*, %continuation.token* } @simple_await_entry(i8* %0) !continuation.entry !2 !continuation !3 !continuation.registercount !4 {
-; CHECK-LABEL: define void @simple_await_entry() !continuation !4 !continuation.registercount !2 !continuation.entry !5 !continuation.state !3 !continuation.stacksize !3 {
+; CHECK-LABEL: define void @simple_await_entry(
+; CHECK-SAME: ) !continuation [[META4:![0-9]+]] !continuation.registercount [[META2]] !continuation.entry [[META5:![0-9]+]] !continuation.state [[META3]] !continuation.stacksize [[META3]] {
; CHECK-NEXT: AllocaSpillBB:
-; CHECK-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
-; CHECK-NEXT: [[FRAMEPTR:%.*]] = bitcast ptr [[CONT_STATE]] to ptr
; CHECK-NEXT: [[TMP0:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 8
-; CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP0]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
-; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP4]], align 4
-; CHECK-NEXT: store i32 [[TMP6]], ptr addrspace(21) [[TMP5]], align 4
-; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 1
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4
-; CHECK-NEXT: store i32 [[TMP9]], ptr addrspace(21) [[TMP8]], align 4
-; CHECK-NEXT: [[TMP10:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-; CHECK-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP11]], i64 ptrtoint (ptr @simple_await_entry.resume.0 to i64)), !continuation.registercount !2, !continuation.returnedRegistercount !2
+; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP2]], i64 0
+; CHECK-NEXT: [[FRAMEPTR:%.*]] = bitcast ptr addrspace(21) [[TMP3]] to ptr addrspace(21)
+; CHECK-NEXT: [[TMP4:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 8
+; CHECK-NEXT: store i32 [[TMP6]], ptr [[TMP4]], align 4
+; CHECK-NEXT: [[TMP7:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+; CHECK-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP8]], i64 ptrtoint (ptr @simple_await_entry.resume.0 to i64)), !continuation.registercount [[META2]], !continuation.returnedRegistercount !2
; CHECK-NEXT: unreachable
;
AllocaSpillBB:
@@ -120,27 +101,18 @@ AllocaSpillBB:
define internal { i8*, %continuation.token* } @simple_await_entry.resume.0(i8* noalias nonnull align 16 dereferenceable(8) %0, i1 %1) !continuation.entry !2 !continuation !3 {
; CHECK-LABEL: define dso_local void @simple_await_entry.resume.0(
-; CHECK-SAME: i32 [[TMP0:%.*]]) !continuation !4 !continuation.registercount !2 {
+; CHECK-SAME: i32 [[TMP0:%.*]]) !continuation [[META4]] !continuation.registercount [[META2]] {
; CHECK-NEXT: entryresume.0:
-; CHECK-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
; CHECK-NEXT: [[TMP1:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(21)
-; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP3]], i64 -8
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(21) [[TMP5]], align 4
-; CHECK-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 1
-; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(21) [[TMP8]], align 4
-; CHECK-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4
-; CHECK-NEXT: [[TMP11:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
-; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[TMP12]], -8
-; CHECK-NEXT: store i32 [[TMP13]], ptr [[TMP11]], align 4
-; CHECK-NEXT: [[FRAMEPTR:%.*]] = bitcast ptr [[CONT_STATE]] to ptr
-; CHECK-NEXT: [[VFRAME:%.*]] = bitcast ptr [[FRAMEPTR]] to ptr
+; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], -8
+; CHECK-NEXT: store i32 [[TMP3]], ptr [[TMP1]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i32 [[TMP5]] to ptr addrspace(21)
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP6]], i64 0
+; CHECK-NEXT: [[FRAMEPTR:%.*]] = bitcast ptr addrspace(21) [[TMP7]] to ptr addrspace(21)
+; CHECK-NEXT: [[VFRAME:%.*]] = bitcast ptr addrspace(21) [[FRAMEPTR]] to ptr addrspace(21)
; CHECK-NEXT: call void @continuation.complete()
; CHECK-NEXT: unreachable
;
@@ -152,27 +124,22 @@ entryresume.0:
}
define { i8*, %continuation.token* } @await_with_ret_value(i8* %0) !continuation !1 !continuation.registercount !4 {
-; CHECK-LABEL: define void @await_with_ret_value() !continuation !6 !continuation.registercount !2 !continuation.state !3 !continuation.stacksize !3 {
-; CHECK-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
-; CHECK-NEXT: [[FRAMEPTR:%.*]] = bitcast ptr [[CONT_STATE]] to ptr
-; CHECK-NEXT: [[DOTSPILL_ADDR:%.*]] = getelementptr inbounds [[AWAIT_WITH_RET_VALUE_FRAME:%.*]], ptr [[FRAMEPTR]], i32 0, i32 0
-; CHECK-NEXT: store i64 -1, ptr [[DOTSPILL_ADDR]], align 4
+; CHECK-LABEL: define void @await_with_ret_value(
+; CHECK-SAME: ) !continuation [[META6:![0-9]+]] !continuation.registercount [[META2]] !continuation.state [[META3]] !continuation.stacksize [[META3]] {
; CHECK-NEXT: [[TMP1:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], 8
-; CHECK-NEXT: store i32 [[TMP3]], ptr [[TMP1]], align 4
-; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(21)
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 0
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP5]], align 4
-; CHECK-NEXT: store i32 [[TMP7]], ptr addrspace(21) [[TMP6]], align 4
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 1
-; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP8]], align 4
-; CHECK-NEXT: store i32 [[TMP10]], ptr addrspace(21) [[TMP9]], align 4
-; CHECK-NEXT: [[TMP11:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
-; CHECK-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP12]], i64 ptrtoint (ptr @await_with_ret_value.resume.0 to i64)), !continuation.registercount !2, !continuation.returnedRegistercount !2
+; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(21)
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP3]], i64 0
+; CHECK-NEXT: [[FRAMEPTR:%.*]] = bitcast ptr addrspace(21) [[TMP4]] to ptr addrspace(21)
+; CHECK-NEXT: [[DOTSPILL_ADDR:%.*]] = getelementptr inbounds [[AWAIT_WITH_RET_VALUE_FRAME:%.*]], ptr addrspace(21) [[FRAMEPTR]], i32 0, i32 0
+; CHECK-NEXT: store i64 -1, ptr addrspace(21) [[DOTSPILL_ADDR]], align 4
+; CHECK-NEXT: [[TMP5:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
+; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], 8
+; CHECK-NEXT: store i32 [[TMP7]], ptr [[TMP5]], align 4
+; CHECK-NEXT: [[TMP8:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+; CHECK-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP9]], i64 ptrtoint (ptr @await_with_ret_value.resume.0 to i64)), !continuation.registercount [[META2]], !continuation.returnedRegistercount !2
; CHECK-NEXT: unreachable
;
%FramePtr = bitcast i8* %0 to %await_with_ret_value.Frame*
@@ -185,31 +152,22 @@ define { i8*, %continuation.token* } @await_with_ret_value(i8* %0) !continuation
define internal { i8*, %continuation.token* } @await_with_ret_value.resume.0(i8* noalias nonnull align 16 dereferenceable(8) %0, i1 %1) !continuation !1 {
; CHECK-LABEL: define dso_local void @await_with_ret_value.resume.0(
-; CHECK-SAME: i32 [[TMP0:%.*]], i32 [[RES1:%.*]]) !continuation !6 !continuation.registercount !2 {
-; CHECK-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
+; CHECK-SAME: i32 [[TMP0:%.*]], i32 [[RES1:%.*]]) !continuation [[META6]] !continuation.registercount [[META2]] {
; CHECK-NEXT: [[TMP2:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i32 [[TMP3]] to ptr addrspace(21)
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP4]], i64 -8
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP5]], i32 0, i32 0
-; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(21) [[TMP6]], align 4
-; CHECK-NEXT: store i32 [[TMP8]], ptr [[TMP7]], align 4
-; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP5]], i32 0, i32 1
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(21) [[TMP9]], align 4
-; CHECK-NEXT: store i32 [[TMP11]], ptr [[TMP10]], align 4
-; CHECK-NEXT: [[TMP12:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4
-; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], -8
-; CHECK-NEXT: store i32 [[TMP14]], ptr [[TMP12]], align 4
-; CHECK-NEXT: [[FRAMEPTR:%.*]] = bitcast ptr [[CONT_STATE]] to ptr
-; CHECK-NEXT: [[VFRAME:%.*]] = bitcast ptr [[FRAMEPTR]] to ptr
-; CHECK-NEXT: [[DOTRELOAD_ADDR:%.*]] = getelementptr inbounds [[AWAIT_WITH_RET_VALUE_FRAME:%.*]], ptr [[FRAMEPTR]], i32 0, i32 0
-; CHECK-NEXT: [[DOTRELOAD:%.*]] = load i64, ptr [[DOTRELOAD_ADDR]], align 4
-; CHECK-NEXT: [[TMP15:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4
-; CHECK-NEXT: call void (i64, ...) @continuation.continue(i64 [[DOTRELOAD]], i32 [[TMP16]], i32 [[RES1]]), !continuation.registercount !2
+; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], -8
+; CHECK-NEXT: store i32 [[TMP4]], ptr [[TMP2]], align 4
+; CHECK-NEXT: [[TMP5:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
+; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i32 [[TMP6]] to ptr addrspace(21)
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP7]], i64 0
+; CHECK-NEXT: [[FRAMEPTR:%.*]] = bitcast ptr addrspace(21) [[TMP8]] to ptr addrspace(21)
+; CHECK-NEXT: [[VFRAME:%.*]] = bitcast ptr addrspace(21) [[FRAMEPTR]] to ptr addrspace(21)
+; CHECK-NEXT: [[DOTRELOAD_ADDR:%.*]] = getelementptr inbounds [[AWAIT_WITH_RET_VALUE_FRAME:%.*]], ptr addrspace(21) [[FRAMEPTR]], i32 0, i32 0
+; CHECK-NEXT: [[DOTRELOAD:%.*]] = load i64, ptr addrspace(21) [[DOTRELOAD_ADDR]], align 4
+; CHECK-NEXT: [[TMP9:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
+; CHECK-NEXT: call void (i64, ...) @continuation.continue(i64 [[DOTRELOAD]], i32 [[TMP10]], i32 [[RES1]]), !continuation.registercount [[META2]]
; CHECK-NEXT: unreachable
;
%FramePtr = bitcast i8* %0 to %await_with_ret_value.Frame*
@@ -237,10 +195,10 @@ attributes #0 = { nounwind }
; CHECK: attributes #[[ATTR2:[0-9]+]] = { nofree norecurse nosync nounwind speculatable willreturn memory(none) }
;.
; CHECK: [[META0:![0-9]+]] = !{i32 21}
-; CHECK: [[META1:![0-9]+]] = !{ptr @simple_await}
-; CHECK: [[META2:![0-9]+]] = !{i32 0}
-; CHECK: [[META3:![0-9]+]] = !{i32 8}
-; CHECK: [[META4:![0-9]+]] = !{ptr @simple_await_entry}
-; CHECK: [[META5:![0-9]+]] = !{}
-; CHECK: [[META6:![0-9]+]] = !{ptr @await_with_ret_value}
+; CHECK: [[META1]] = !{ptr @simple_await}
+; CHECK: [[META2]] = !{i32 0}
+; CHECK: [[META3]] = !{i32 8}
+; CHECK: [[META4]] = !{ptr @simple_await_entry}
+; CHECK: [[META5]] = !{}
+; CHECK: [[META6]] = !{ptr @await_with_ret_value}
;.
diff --git a/shared/continuations/test/dx/closest-hit-procedural.ll b/shared/continuations/test/dx/closest-hit-procedural.ll
index ec2e984a67..5a625d8ff5 100644
--- a/shared/continuations/test/dx/closest-hit-procedural.ll
+++ b/shared/continuations/test/dx/closest-hit-procedural.ll
@@ -124,99 +124,94 @@ define void @ClosestHit(%struct.RayPayload* noalias nocapture %payload, %struct.
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[HITATTRS:%.*]] = alloca [[STRUCT_HITATTRIBUTES:%.*]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = call [[STRUCT_SYSTEMDATA]] @continuations.getSystemData.s_struct.SystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP4]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = load i32, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP9]], ptr [[TMP8]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP6]], i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP10]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP12]], ptr [[TMP11]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP10]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[TMP10]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP16]], ptr [[TMP15]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP5]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = load i32, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP8]], ptr [[TMP7]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[TMP5]], i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP9]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP11]], ptr [[TMP10]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP9]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP13]], ptr [[TMP12]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP9]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP17]], ptr [[TMP2]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP20]], ptr [[TMP18]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP23]], ptr [[TMP21]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S]], ptr @PAYLOAD, i32 0, i32 0, i32 1), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP25]], ptr [[TMP24]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 2), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP27]], ptr [[TMP26]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP16]], ptr [[TMP2]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP19]], ptr [[TMP17]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP22]], ptr [[TMP20]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S]], ptr @PAYLOAD, i32 0, i32 0, i32 1), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP24]], ptr [[TMP23]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 2), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP26]], ptr [[TMP25]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr [[TMP28]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = getelementptr i32, ptr [[TMP29]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP30]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP31]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = getelementptr i32, ptr [[TMP28]], i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = getelementptr i32, ptr [[TMP32]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP33]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP34]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = getelementptr i32, ptr [[TMP32]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP35]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP36]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = getelementptr i32, ptr [[TMP32]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP37]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP38]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP40:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP39]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP40]], !continuation.registercount [[META21]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = getelementptr i32, ptr [[TMP27]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr [[TMP28]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP30]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = getelementptr i32, ptr [[TMP27]], i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = getelementptr i32, ptr [[TMP31]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = load i32, ptr [[TMP32]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP33]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = getelementptr i32, ptr [[TMP31]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = load i32, ptr [[TMP34]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP35]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = getelementptr i32, ptr [[TMP31]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP36]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP37]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP39:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP38]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP39]], !continuation.registercount [[META21]]
;
; DXILCONTPOSTPROCESS-LABEL: define void @ClosestHit(
; DXILCONTPOSTPROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] !lgc.rt.shaderstage [[META17:![0-9]+]] !continuation [[META18:![0-9]+]] !continuation.registercount [[META19:![0-9]+]] !continuation.state [[META14:![0-9]+]] {
; DXILCONTPOSTPROCESS-NEXT: AllocaSpillBB:
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
; DXILCONTPOSTPROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = load [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP1]], 0, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP0]], 0, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: store <3 x i32> [[DOTFCA_0_0_EXTRACT]], ptr [[DOTFCA_0_0_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP7]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP6]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_02_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = bitcast float [[DOTSROA_02_0_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = bitcast float [[DOTSROA_02_0_VEC_EXTRACT]] to i32
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_02_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT]], i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = bitcast float [[DOTSROA_02_4_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 1) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 2) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP3]], ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP4]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP5]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP6]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP12]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = bitcast float [[DOTSROA_02_4_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 1) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_2_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 2) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP2]], ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP3]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP4]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP5]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP11]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_LOAD:%.*]] = load <3 x i32>, ptr [[DOTFCA_0_GEP]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, <3 x i32> [[DOTFCA_0_LOAD]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP13]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META19]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP12]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META19]]
; DXILCONTPOSTPROCESS-NEXT: unreachable
;
ret void
diff --git a/shared/continuations/test/dx/closest-hit-traceray.ll b/shared/continuations/test/dx/closest-hit-traceray.ll
index d86cd10de8..95e8a64043 100644
--- a/shared/continuations/test/dx/closest-hit-traceray.ll
+++ b/shared/continuations/test/dx/closest-hit-traceray.ll
@@ -117,127 +117,122 @@ declare !types !35 i32 @_cont_HitKind(%struct.SystemData* nocapture readnone, %s
; Function Attrs: nounwind
define void @ClosestHit(%struct.RayPayload* noalias nocapture %payload, %struct.BuiltInTriangleIntersectionAttributes* nocapture readonly %attr) #3 !types !36 {
; LOWERRAYTRACINGPIPELINE-LABEL: define %struct.DispatchSystemData @ClosestHit(
-; LOWERRAYTRACINGPIPELINE-SAME: [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] !continuation [[META18:![0-9]+]] !lgc.rt.shaderstage [[META19:![0-9]+]] !continuation.registercount [[META20:![0-9]+]] {
+; LOWERRAYTRACINGPIPELINE-SAME: [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] !continuation [[META18:![0-9]+]] !lgc.rt.shaderstage [[META19:![0-9]+]] !continuation.registercount [[META20:![0-9]+]] {
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP2:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[HITATTRS:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = call [[STRUCT_SYSTEMDATA]] @continuations.getSystemData.s_struct.SystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP4]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = load i32, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP9]], ptr [[TMP8]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP6]], i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP10]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP12]], ptr [[TMP11]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP10]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[TMP10]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP16]], ptr [[TMP15]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP5]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = load i32, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP8]], ptr [[TMP7]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[TMP5]], i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP9]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP11]], ptr [[TMP10]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP9]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP13]], ptr [[TMP12]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP9]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP17]], ptr [[TMP2]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP20]], ptr [[TMP18]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP23]], ptr [[TMP21]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = alloca [[STRUCT_RAYPAYLOAD]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = bitcast ptr [[TMP26]] to ptr
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr [[TMP27]]) #[[ATTR10:[0-9]+]]
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP26]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: store <4 x float> zeroinitializer, ptr [[TMP28]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP24]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP29]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[TMP30]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[DIS_DATA_I:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP32]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP16]], ptr [[TMP2]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP19]], ptr [[TMP17]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP22]], ptr [[TMP20]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = alloca [[STRUCT_RAYPAYLOAD]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = bitcast ptr [[TMP25]] to ptr
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr [[TMP26]]) #[[ATTR10:[0-9]+]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP25]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: store <4 x float> zeroinitializer, ptr [[TMP27]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP23]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP28]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[TMP29]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[DIS_DATA_I:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP31]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYS_DATA_I:%.*]] = insertvalue [[STRUCT_SYSTEMDATA]] undef, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I]], 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TRAV_DATA_I:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA:%.*]] undef, [[STRUCT_SYSTEMDATA]] [[SYS_DATA_I]], 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @amd.dx.Traversal([[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP33]], ptr [[TMP32]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[NEWDATA_I:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @amd.dx.Traversal([[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[NEWDATA_I]], ptr [[TMP31]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = getelementptr i32, ptr [[TMP34]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = getelementptr i32, ptr [[TMP35]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP36]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP37]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = getelementptr i32, ptr [[TMP34]], i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP39:%.*]] = getelementptr i32, ptr [[TMP38]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = getelementptr i32, ptr [[TMP32]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = getelementptr i32, ptr [[TMP33]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = load i32, ptr [[TMP34]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP35]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = getelementptr i32, ptr [[TMP32]], i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = getelementptr i32, ptr [[TMP36]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP37]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP38]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP39:%.*]] = getelementptr i32, ptr [[TMP36]], i64 1
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP39]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP40]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP41:%.*]] = getelementptr i32, ptr [[TMP38]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP40]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP41:%.*]] = getelementptr i32, ptr [[TMP36]], i64 2
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP42:%.*]] = load i32, ptr [[TMP41]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP42]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP43:%.*]] = getelementptr i32, ptr [[TMP38]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP44]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP46:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[TMP45]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP46]], !continuation.registercount [[META20]]
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP42]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP44:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[TMP43]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP44]], !continuation.registercount [[META20]]
;
; DXILCONTPOSTPROCESS-LABEL: define void @ClosestHit(
-; DXILCONTPOSTPROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] !continuation [[META17:![0-9]+]] !lgc.rt.shaderstage [[META18:![0-9]+]] !continuation.registercount [[META19:![0-9]+]] !continuation.state [[META14:![0-9]+]] {
+; DXILCONTPOSTPROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] !continuation [[META17:![0-9]+]] !lgc.rt.shaderstage [[META18:![0-9]+]] !continuation.registercount [[META19:![0-9]+]] !continuation.state [[META14:![0-9]+]] {
; DXILCONTPOSTPROCESS-NEXT: AllocaSpillBB:
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
; DXILCONTPOSTPROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = load [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP1]], 0, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP0]], 0, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: store <3 x i32> [[DOTFCA_0_0_EXTRACT]], ptr [[DOTFCA_0_0_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP6]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_03_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT]], i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = bitcast float [[DOTSROA_03_0_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_03_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT]], i32 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = bitcast float [[DOTSROA_03_4_VEC_EXTRACT]] to i32
; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT3:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP7]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_05_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT3]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = bitcast float [[DOTSROA_05_0_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_05_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT3]], i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = bitcast float [[DOTSROA_05_4_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP10]])
-; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP12]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
-; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[TMP13]])
-; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[DIS_DATA_I_FCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP15]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP9]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP11]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
+; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[TMP12]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[DIS_DATA_I_FCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP14]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: [[DIS_DATA_I_FCA_0_LOAD:%.*]] = load <3 x i32>, ptr [[DIS_DATA_I_FCA_0_GEP]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[DIS_DATA_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, <3 x i32> [[DIS_DATA_I_FCA_0_LOAD]], 0
; DXILCONTPOSTPROCESS-NEXT: [[SYS_DATA_I:%.*]] = insertvalue [[STRUCT_SYSTEMDATA]] undef, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I_FCA_0_INSERT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[TRAV_DATA_I:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA:%.*]] undef, [[STRUCT_SYSTEMDATA]] [[SYS_DATA_I]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @amd.dx.Traversal([[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP16]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP2:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[TMP15]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: store <3 x i32> [[DOTFCA_0_EXTRACT]], ptr [[DOTFCA_0_GEP2]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP3]], ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP4]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP5]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP6]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[TMP17]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[NEWDATA_I:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @amd.dx.Traversal([[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]])
+; DXILCONTPOSTPROCESS-NEXT: [[NEWDATA_I_FCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[NEWDATA_I]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[NEWDATA_I_FCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[TMP14]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: store <3 x i32> [[NEWDATA_I_FCA_0_EXTRACT]], ptr [[NEWDATA_I_FCA_0_GEP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP2]], ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP3]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP4]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP5]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[TMP15]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_LOAD:%.*]] = load <3 x i32>, ptr [[DOTFCA_0_GEP]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, <3 x i32> [[DOTFCA_0_LOAD]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP18]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META19]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP16]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META19]]
; DXILCONTPOSTPROCESS-NEXT: unreachable
;
%1 = load %dx.types.Handle, %dx.types.Handle* @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
diff --git a/shared/continuations/test/dx/closest-hit.ll b/shared/continuations/test/dx/closest-hit.ll
index af8d138fc9..b3fd8ca1ff 100644
--- a/shared/continuations/test/dx/closest-hit.ll
+++ b/shared/continuations/test/dx/closest-hit.ll
@@ -109,47 +109,46 @@ define void @ClosestHit(%struct.RayPayload* noalias nocapture %payload, %struct.
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[HITATTRS:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = call [[STRUCT_SYSTEMDATA]] @continuations.getSystemData.s_struct.SystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP4]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = load i32, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP9]], ptr [[TMP8]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP6]], i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP10]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP12]], ptr [[TMP11]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP5]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = load i32, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP8]], ptr [[TMP7]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[TMP5]], i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP9]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP11]], ptr [[TMP10]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP13]], ptr [[TMP2]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP16]], ptr [[TMP14]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP19]], ptr [[TMP17]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP12]], ptr [[TMP2]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP15]], ptr [[TMP13]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP18]], ptr [[TMP16]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; LOWERRAYTRACINGPIPELINE-NEXT: [[PTR:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[BARYPTR:%.*]] = getelementptr inbounds [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[HITATTRS]], i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[BARY:%.*]] = load <2 x float>, ptr [[BARYPTR]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store <2 x float> [[BARY]], ptr [[PTR]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[TMP20]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr [[TMP21]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP23]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr [[TMP20]], i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[TMP24]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP26]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP27]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP28]], !continuation.registercount [[META15]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[TMP19]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[TMP20]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP22]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = getelementptr i32, ptr [[TMP19]], i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr [[TMP23]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP25]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP26]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP27]], !continuation.registercount [[META15]]
;
%ptr = getelementptr inbounds %struct.RayPayload, %struct.RayPayload* %payload, i32 0, i32 0
%baryPtr = getelementptr inbounds %struct.BuiltInTriangleIntersectionAttributes, %struct.BuiltInTriangleIntersectionAttributes* %attr, i32 0, i32 0
diff --git a/shared/continuations/test/dx/continuation-stacksize.ll b/shared/continuations/test/dx/continuation-stacksize.ll
index 7b88f84b92..d718ea7fae 100644
--- a/shared/continuations/test/dx/continuation-stacksize.ll
+++ b/shared/continuations/test/dx/continuation-stacksize.ll
@@ -76,17 +76,17 @@ define void @_cont_CallShader(%struct.DispatchSystemData* %data, i32 %0) #0 !typ
ret void
}
-; LOWERRAYTRACINGPIPELINE-STACKSIZE-DAG: define void @main(){{.*}} !continuation.stacksize ![[main_stacksize:[0-9]+]]
+; LOWERRAYTRACINGPIPELINE-STACKSIZE-DAG: define void @main(%struct.DispatchSystemData %0){{.*}} !continuation.stacksize ![[main_stacksize:[0-9]+]]
; LOWERRAYTRACINGPIPELINE-STACKSIZE-DAG: ![[main_stacksize]] = !{i32 140}
-; CLEANUP-STACKSIZE-DAG: define void @main(){{.*}} !continuation.stacksize ![[main_stacksize:[0-9]+]]
+; CLEANUP-STACKSIZE-DAG: define void @main(%struct.DispatchSystemData %0){{.*}} !continuation.stacksize ![[main_stacksize:[0-9]+]]
; CLEANUP-STACKSIZE-DAG: ![[main_stacksize]] = !{i32 140}
-; CLEANUP-STATESIZE-DAG: define void @main(){{.*}} !continuation.state ![[main_state:[0-9]+]]
+; CLEANUP-STATESIZE-DAG: define void @main(%struct.DispatchSystemData %0){{.*}} !continuation.state ![[main_state:[0-9]+]]
; CLEANUP-STATESIZE-DAG: ![[main_state]] = !{i32 0}
-; SAVESTATE-STACKSIZE-DAG: define void @main(){{.*}} !continuation.stacksize ![[main_stacksize:[0-9]+]]
+; SAVESTATE-STACKSIZE-DAG: define void @main(%struct.DispatchSystemData %0){{.*}} !continuation.stacksize ![[main_stacksize:[0-9]+]]
; SAVESTATE-STACKSIZE-DAG: ![[main_stacksize]] = !{i32 140}
-; SAVESTATE-STATESIZE-DAG: define void @main(){{.*}} !continuation.state ![[main_state:[0-9]+]]
+; SAVESTATE-STATESIZE-DAG: define void @main(%struct.DispatchSystemData %0){{.*}} !continuation.state ![[main_state:[0-9]+]]
; SAVESTATE-STATESIZE-DAG: ![[main_state]] = !{i32 0}
define void @main() {
@@ -95,16 +95,16 @@ define void @main() {
ret void
}
-; LOWERRAYTRACINGPIPELINE-STACKSIZE-DAG: define void @mainTrace(){{.*}} !continuation.stacksize ![[maintrace_stacksize:[0-9]+]]
+; LOWERRAYTRACINGPIPELINE-STACKSIZE-DAG: define void @mainTrace(%struct.DispatchSystemData %0){{.*}} !continuation.stacksize ![[maintrace_stacksize:[0-9]+]]
; LOWERRAYTRACINGPIPELINE-STACKSIZE-DAG: ![[maintrace_stacksize]] = !{i32 180}
-; CLEANUP-STACKSIZE-DAG: define void @mainTrace(){{.*}} !continuation.stacksize ![[maintrace_stacksize:[0-9]+]]
+; CLEANUP-STACKSIZE-DAG: define void @mainTrace(%struct.DispatchSystemData %0){{.*}} !continuation.stacksize ![[maintrace_stacksize:[0-9]+]]
; CLEANUP-STACKSIZE-DAG: ![[maintrace_stacksize]] = !{i32 180}
-; CLEANUP-STATESIZE-DAG: define void @mainTrace(){{.*}} !continuation.state ![[main_state]]
+; CLEANUP-STATESIZE-DAG: define void @mainTrace(%struct.DispatchSystemData %0){{.*}} !continuation.state ![[main_state]]
-; SAVESTATE-STACKSIZE-DAG: define void @mainTrace(){{.*}} !continuation.stacksize ![[maintrace_stacksize:[0-9]+]]
+; SAVESTATE-STACKSIZE-DAG: define void @mainTrace(%struct.DispatchSystemData %0){{.*}} !continuation.stacksize ![[maintrace_stacksize:[0-9]+]]
; SAVESTATE-STACKSIZE-DAG: ![[maintrace_stacksize]] = !{i32 180}
-; SAVESTATE-STATESIZE-DAG: define void @mainTrace(){{.*}} !continuation.state ![[main_state]]
+; SAVESTATE-STATESIZE-DAG: define void @mainTrace(%struct.DispatchSystemData %0){{.*}} !continuation.state ![[main_state]]
define void @mainTrace() {
%1 = load %dx.types.Handle, %dx.types.Handle* @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
diff --git a/shared/continuations/test/dx/continuation-state.ll b/shared/continuations/test/dx/continuation-state.ll
index 616bfddb69..a64776f5e3 100644
--- a/shared/continuations/test/dx/continuation-state.ll
+++ b/shared/continuations/test/dx/continuation-state.ll
@@ -36,358 +36,168 @@ define void @simple_await_entry(<4 x i32> %arg, <4 x i32> addrspace(1)* %mem) !c
!2 = !{i32 30}
!3 = !{i32 21}
; CLEANUP-LABEL: define void @simple_await(
-; CLEANUP-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], <4 x i32> [[ARG:%.*]]) !continuation.registercount !2 !continuation !3 !continuation.state !4 !continuation.stacksize !4 {
+; CLEANUP-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], <4 x i32> [[ARG:%.*]]) !continuation.registercount [[META2:![0-9]+]] !continuation [[META3:![0-9]+]] !continuation.state [[META4:![0-9]+]] !continuation.stacksize [[META4]] {
; CLEANUP-NEXT: AllocaSpillBB:
-; CLEANUP-NEXT: [[CONT_STATE:%.*]] = alloca [6 x i32], align 4
-; CLEANUP-NEXT: [[ARG_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANUP-NEXT: store <4 x i32> [[ARG]], ptr [[ARG_SPILL_ADDR]], align 4
-; CLEANUP-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME]], ptr [[CONT_STATE]], i32 0, i32 1
-; CLEANUP-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
; CLEANUP-NEXT: [[TMP0:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CLEANUP-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-; CLEANUP-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 24
-; CLEANUP-NEXT: store i32 [[TMP2]], ptr [[TMP0]], align 4
-; CLEANUP-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
-; CLEANUP-NEXT: [[TMP4:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANUP-NEXT: [[TMP5:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 0
-; CLEANUP-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP4]], align 4
-; CLEANUP-NEXT: store i32 [[TMP6]], ptr addrspace(21) [[TMP5]], align 4
-; CLEANUP-NEXT: [[TMP7:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CLEANUP-NEXT: [[TMP8:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 1
-; CLEANUP-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4
-; CLEANUP-NEXT: store i32 [[TMP9]], ptr addrspace(21) [[TMP8]], align 4
-; CLEANUP-NEXT: [[TMP10:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; CLEANUP-NEXT: [[TMP11:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 2
-; CLEANUP-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP10]], align 4
-; CLEANUP-NEXT: store i32 [[TMP12]], ptr addrspace(21) [[TMP11]], align 4
-; CLEANUP-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 3
-; CLEANUP-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 3
-; CLEANUP-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP13]], align 4
-; CLEANUP-NEXT: store i32 [[TMP15]], ptr addrspace(21) [[TMP14]], align 4
-; CLEANUP-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 4
-; CLEANUP-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 4
-; CLEANUP-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4
-; CLEANUP-NEXT: store i32 [[TMP18]], ptr addrspace(21) [[TMP17]], align 4
-; CLEANUP-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 5
-; CLEANUP-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 5
-; CLEANUP-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP19]], align 4
-; CLEANUP-NEXT: store i32 [[TMP21]], ptr addrspace(21) [[TMP20]], align 4
-; CLEANUP-NEXT: [[TMP22:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANUP-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
-; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP23]], i64 ptrtoint (ptr @simple_await.resume.0 to i64)), !continuation.registercount !2, !continuation.returnedRegistercount !2
+; CLEANUP-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
+; CLEANUP-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP2]], i64 0
+; CLEANUP-NEXT: [[ARG_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME:%.*]], ptr addrspace(21) [[TMP3]], i32 0, i32 0
+; CLEANUP-NEXT: store <4 x i32> [[ARG]], ptr addrspace(21) [[ARG_SPILL_ADDR]], align 4
+; CLEANUP-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME]], ptr addrspace(21) [[TMP3]], i32 0, i32 1
+; CLEANUP-NEXT: store i64 [[RETURNADDR]], ptr addrspace(21) [[RETURNADDR_SPILL_ADDR]], align 4
+; CLEANUP-NEXT: [[TMP4:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+; CLEANUP-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 24
+; CLEANUP-NEXT: store i32 [[TMP6]], ptr [[TMP4]], align 4
+; CLEANUP-NEXT: [[TMP7:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP8]], i64 ptrtoint (ptr @simple_await.resume.0 to i64)), !continuation.registercount [[META2]], !continuation.returnedRegistercount !2
; CLEANUP-NEXT: unreachable
;
;
; CLEANUP-LABEL: define dso_local void @simple_await.resume.0(
-; CLEANUP-SAME: i32 [[TMP0:%.*]]) !continuation.registercount !2 !continuation !3 {
+; CLEANUP-SAME: i32 [[TMP0:%.*]]) !continuation.registercount [[META2]] !continuation [[META3]] {
; CLEANUP-NEXT: entryresume.0:
-; CLEANUP-NEXT: [[CONT_STATE:%.*]] = alloca [6 x i32], align 4
; CLEANUP-NEXT: [[TMP1:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CLEANUP-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-; CLEANUP-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(21)
-; CLEANUP-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP3]], i64 -24
-; CLEANUP-NEXT: [[TMP5:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 0
-; CLEANUP-NEXT: [[TMP6:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANUP-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(21) [[TMP5]], align 4
-; CLEANUP-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
-; CLEANUP-NEXT: [[TMP8:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 1
-; CLEANUP-NEXT: [[TMP9:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CLEANUP-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(21) [[TMP8]], align 4
-; CLEANUP-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4
-; CLEANUP-NEXT: [[TMP11:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 2
-; CLEANUP-NEXT: [[TMP12:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; CLEANUP-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(21) [[TMP11]], align 4
-; CLEANUP-NEXT: store i32 [[TMP13]], ptr [[TMP12]], align 4
-; CLEANUP-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 3
-; CLEANUP-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 3
-; CLEANUP-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(21) [[TMP14]], align 4
-; CLEANUP-NEXT: store i32 [[TMP16]], ptr [[TMP15]], align 4
-; CLEANUP-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 4
-; CLEANUP-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 4
-; CLEANUP-NEXT: [[TMP19:%.*]] = load i32, ptr addrspace(21) [[TMP17]], align 4
-; CLEANUP-NEXT: store i32 [[TMP19]], ptr [[TMP18]], align 4
-; CLEANUP-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 5
-; CLEANUP-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 5
-; CLEANUP-NEXT: [[TMP22:%.*]] = load i32, ptr addrspace(21) [[TMP20]], align 4
-; CLEANUP-NEXT: store i32 [[TMP22]], ptr [[TMP21]], align 4
-; CLEANUP-NEXT: [[TMP23:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANUP-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4
-; CLEANUP-NEXT: [[TMP25:%.*]] = add i32 [[TMP24]], -24
-; CLEANUP-NEXT: store i32 [[TMP25]], ptr [[TMP23]], align 4
-; CLEANUP-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANUP-NEXT: [[ARG_RELOAD:%.*]] = load <4 x i32>, ptr [[ARG_RELOAD_ADDR]], align 4
-; CLEANUP-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME]], ptr [[CONT_STATE]], i32 0, i32 1
-; CLEANUP-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr [[RETURNADDR_RELOAD_ADDR]], align 4
-; CLEANUP-NEXT: [[TMP26:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANUP-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4
-; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP27]], <4 x i32> [[ARG_RELOAD]]), !continuation.registercount !2
+; CLEANUP-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], -24
+; CLEANUP-NEXT: store i32 [[TMP3]], ptr [[TMP1]], align 4
+; CLEANUP-NEXT: [[TMP4:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+; CLEANUP-NEXT: [[TMP6:%.*]] = inttoptr i32 [[TMP5]] to ptr addrspace(21)
+; CLEANUP-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP6]], i64 0
+; CLEANUP-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME:%.*]], ptr addrspace(21) [[TMP7]], i32 0, i32 0
+; CLEANUP-NEXT: [[ARG_RELOAD:%.*]] = load <4 x i32>, ptr addrspace(21) [[ARG_RELOAD_ADDR]], align 4
+; CLEANUP-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME]], ptr addrspace(21) [[TMP7]], i32 0, i32 1
+; CLEANUP-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr addrspace(21) [[RETURNADDR_RELOAD_ADDR]], align 4
+; CLEANUP-NEXT: [[TMP8:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP9]], <4 x i32> [[ARG_RELOAD]]), !continuation.registercount [[META2]]
; CLEANUP-NEXT: unreachable
;
;
; CLEANUP-LABEL: define void @simple_await_entry(
-; CLEANUP-SAME: <4 x i32> [[ARG:%.*]], ptr addrspace(1) [[MEM:%.*]]) !continuation.registercount !2 !continuation.entry !5 !continuation !6 !continuation.state !4 !continuation.stacksize !4 {
+; CLEANUP-SAME: <4 x i32> [[ARG:%.*]], ptr addrspace(1) [[MEM:%.*]]) !continuation.registercount [[META2]] !continuation.entry [[META5:![0-9]+]] !continuation [[META6:![0-9]+]] !continuation.state [[META4]] !continuation.stacksize [[META4]] {
; CLEANUP-NEXT: AllocaSpillBB:
-; CLEANUP-NEXT: [[CONT_STATE:%.*]] = alloca [6 x i32], align 4
-; CLEANUP-NEXT: [[MEM_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 1
-; CLEANUP-NEXT: store ptr addrspace(1) [[MEM]], ptr [[MEM_SPILL_ADDR]], align 4
-; CLEANUP-NEXT: [[ARG_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME]], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANUP-NEXT: store <4 x i32> [[ARG]], ptr [[ARG_SPILL_ADDR]], align 4
; CLEANUP-NEXT: [[TMP0:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CLEANUP-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-; CLEANUP-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 24
-; CLEANUP-NEXT: store i32 [[TMP2]], ptr [[TMP0]], align 4
-; CLEANUP-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
-; CLEANUP-NEXT: [[TMP4:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANUP-NEXT: [[TMP5:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 0
-; CLEANUP-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP4]], align 4
-; CLEANUP-NEXT: store i32 [[TMP6]], ptr addrspace(21) [[TMP5]], align 4
-; CLEANUP-NEXT: [[TMP7:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CLEANUP-NEXT: [[TMP8:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 1
-; CLEANUP-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4
-; CLEANUP-NEXT: store i32 [[TMP9]], ptr addrspace(21) [[TMP8]], align 4
-; CLEANUP-NEXT: [[TMP10:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; CLEANUP-NEXT: [[TMP11:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 2
-; CLEANUP-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP10]], align 4
-; CLEANUP-NEXT: store i32 [[TMP12]], ptr addrspace(21) [[TMP11]], align 4
-; CLEANUP-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 3
-; CLEANUP-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 3
-; CLEANUP-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP13]], align 4
-; CLEANUP-NEXT: store i32 [[TMP15]], ptr addrspace(21) [[TMP14]], align 4
-; CLEANUP-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 4
-; CLEANUP-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 4
-; CLEANUP-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4
-; CLEANUP-NEXT: store i32 [[TMP18]], ptr addrspace(21) [[TMP17]], align 4
-; CLEANUP-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 5
-; CLEANUP-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 5
-; CLEANUP-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP19]], align 4
-; CLEANUP-NEXT: store i32 [[TMP21]], ptr addrspace(21) [[TMP20]], align 4
-; CLEANUP-NEXT: [[TMP22:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANUP-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
-; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP23]], i64 ptrtoint (ptr @simple_await_entry.resume.0 to i64)), !continuation.registercount !2, !continuation.returnedRegistercount !2
+; CLEANUP-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
+; CLEANUP-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP2]], i64 0
+; CLEANUP-NEXT: [[MEM_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME:%.*]], ptr addrspace(21) [[TMP3]], i32 0, i32 1
+; CLEANUP-NEXT: store ptr addrspace(1) [[MEM]], ptr addrspace(21) [[MEM_SPILL_ADDR]], align 4
+; CLEANUP-NEXT: [[ARG_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME]], ptr addrspace(21) [[TMP3]], i32 0, i32 0
+; CLEANUP-NEXT: store <4 x i32> [[ARG]], ptr addrspace(21) [[ARG_SPILL_ADDR]], align 4
+; CLEANUP-NEXT: [[TMP4:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+; CLEANUP-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 24
+; CLEANUP-NEXT: store i32 [[TMP6]], ptr [[TMP4]], align 4
+; CLEANUP-NEXT: [[TMP7:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP8]], i64 ptrtoint (ptr @simple_await_entry.resume.0 to i64)), !continuation.registercount [[META2]], !continuation.returnedRegistercount !2
; CLEANUP-NEXT: unreachable
;
;
; CLEANUP-LABEL: define dso_local void @simple_await_entry.resume.0(
-; CLEANUP-SAME: i32 [[TMP0:%.*]]) !continuation.registercount !2 !continuation !6 {
+; CLEANUP-SAME: i32 [[TMP0:%.*]]) !continuation.registercount [[META2]] !continuation [[META6]] {
; CLEANUP-NEXT: entryresume.0:
-; CLEANUP-NEXT: [[CONT_STATE:%.*]] = alloca [6 x i32], align 4
; CLEANUP-NEXT: [[TMP1:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CLEANUP-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-; CLEANUP-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(21)
-; CLEANUP-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP3]], i64 -24
-; CLEANUP-NEXT: [[TMP5:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 0
-; CLEANUP-NEXT: [[TMP6:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANUP-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(21) [[TMP5]], align 4
-; CLEANUP-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
-; CLEANUP-NEXT: [[TMP8:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 1
-; CLEANUP-NEXT: [[TMP9:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CLEANUP-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(21) [[TMP8]], align 4
-; CLEANUP-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4
-; CLEANUP-NEXT: [[TMP11:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 2
-; CLEANUP-NEXT: [[TMP12:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; CLEANUP-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(21) [[TMP11]], align 4
-; CLEANUP-NEXT: store i32 [[TMP13]], ptr [[TMP12]], align 4
-; CLEANUP-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 3
-; CLEANUP-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 3
-; CLEANUP-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(21) [[TMP14]], align 4
-; CLEANUP-NEXT: store i32 [[TMP16]], ptr [[TMP15]], align 4
-; CLEANUP-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 4
-; CLEANUP-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 4
-; CLEANUP-NEXT: [[TMP19:%.*]] = load i32, ptr addrspace(21) [[TMP17]], align 4
-; CLEANUP-NEXT: store i32 [[TMP19]], ptr [[TMP18]], align 4
-; CLEANUP-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 5
-; CLEANUP-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 5
-; CLEANUP-NEXT: [[TMP22:%.*]] = load i32, ptr addrspace(21) [[TMP20]], align 4
-; CLEANUP-NEXT: store i32 [[TMP22]], ptr [[TMP21]], align 4
-; CLEANUP-NEXT: [[TMP23:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANUP-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4
-; CLEANUP-NEXT: [[TMP25:%.*]] = add i32 [[TMP24]], -24
-; CLEANUP-NEXT: store i32 [[TMP25]], ptr [[TMP23]], align 4
-; CLEANUP-NEXT: [[MEM_RELOAD_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 1
-; CLEANUP-NEXT: [[MEM_RELOAD:%.*]] = load ptr addrspace(1), ptr [[MEM_RELOAD_ADDR]], align 4
-; CLEANUP-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME]], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANUP-NEXT: [[ARG_RELOAD:%.*]] = load <4 x i32>, ptr [[ARG_RELOAD_ADDR]], align 4
+; CLEANUP-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], -24
+; CLEANUP-NEXT: store i32 [[TMP3]], ptr [[TMP1]], align 4
+; CLEANUP-NEXT: [[TMP4:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+; CLEANUP-NEXT: [[TMP6:%.*]] = inttoptr i32 [[TMP5]] to ptr addrspace(21)
+; CLEANUP-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP6]], i64 0
+; CLEANUP-NEXT: [[MEM_RELOAD_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME:%.*]], ptr addrspace(21) [[TMP7]], i32 0, i32 1
+; CLEANUP-NEXT: [[MEM_RELOAD:%.*]] = load ptr addrspace(1), ptr addrspace(21) [[MEM_RELOAD_ADDR]], align 4
+; CLEANUP-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME]], ptr addrspace(21) [[TMP7]], i32 0, i32 0
+; CLEANUP-NEXT: [[ARG_RELOAD:%.*]] = load <4 x i32>, ptr addrspace(21) [[ARG_RELOAD_ADDR]], align 4
; CLEANUP-NEXT: store <4 x i32> [[ARG_RELOAD]], ptr addrspace(1) [[MEM_RELOAD]], align 4
; CLEANUP-NEXT: call void @continuation.complete()
; CLEANUP-NEXT: unreachable
;
;
; POST-PROCESS-LABEL: define void @simple_await(
-; POST-PROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], <4 x i32> [[ARG:%.*]]) !continuation.registercount !2 !continuation !3 !continuation.state !4 !continuation.stacksize !4 {
+; POST-PROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], <4 x i32> [[ARG:%.*]]) !continuation.registercount [[META2:![0-9]+]] !continuation [[META3:![0-9]+]] !continuation.state [[META4:![0-9]+]] !continuation.stacksize [[META4]] {
; POST-PROCESS-NEXT: AllocaSpillBB:
-; POST-PROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [6 x i32], align 4
; POST-PROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
; POST-PROCESS-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[ARG_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; POST-PROCESS-NEXT: store <4 x i32> [[ARG]], ptr [[ARG_SPILL_ADDR]], align 4
-; POST-PROCESS-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME]], ptr [[CONT_STATE]], i32 0, i32 1
-; POST-PROCESS-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
; POST-PROCESS-NEXT: [[TMP0:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 24
-; POST-PROCESS-NEXT: store i32 [[TMP1]], ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP0]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP3:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP2]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP3]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP5]], ptr addrspace(21) [[TMP4]], align 4
-; POST-PROCESS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; POST-PROCESS-NEXT: [[TMP7:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP2]], i32 0, i32 1
-; POST-PROCESS-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP6]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP8]], ptr addrspace(21) [[TMP7]], align 4
-; POST-PROCESS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; POST-PROCESS-NEXT: [[TMP10:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP2]], i32 0, i32 2
-; POST-PROCESS-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP9]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP11]], ptr addrspace(21) [[TMP10]], align 4
-; POST-PROCESS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 3
-; POST-PROCESS-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP2]], i32 0, i32 3
-; POST-PROCESS-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP12]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP14]], ptr addrspace(21) [[TMP13]], align 4
-; POST-PROCESS-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 4
-; POST-PROCESS-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP2]], i32 0, i32 4
-; POST-PROCESS-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP15]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP17]], ptr addrspace(21) [[TMP16]], align 4
-; POST-PROCESS-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 5
-; POST-PROCESS-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP2]], i32 0, i32 5
-; POST-PROCESS-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP18]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP20]], ptr addrspace(21) [[TMP19]], align 4
-; POST-PROCESS-NEXT: [[TMP21:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP22:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @async_fun to i64))
-; POST-PROCESS-NEXT: [[TMP23:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @simple_await.resume.0 to i64))
-; POST-PROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[TMP22]], i32 [[TMP21]], i64 [[TMP23]]), !continuation.registercount !2, !continuation.returnedRegistercount !2
+; POST-PROCESS-NEXT: [[TMP1:%.*]] = inttoptr i32 [[TMP0]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP1]], i64 0
+; POST-PROCESS-NEXT: [[ARG_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME:%.*]], ptr addrspace(21) [[TMP2]], i32 0, i32 0
+; POST-PROCESS-NEXT: store <4 x i32> [[ARG]], ptr addrspace(21) [[ARG_SPILL_ADDR]], align 4
+; POST-PROCESS-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME]], ptr addrspace(21) [[TMP2]], i32 0, i32 1
+; POST-PROCESS-NEXT: store i64 [[RETURNADDR]], ptr addrspace(21) [[RETURNADDR_SPILL_ADDR]], align 4
+; POST-PROCESS-NEXT: [[TMP3:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], 24
+; POST-PROCESS-NEXT: store i32 [[TMP4]], ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP5:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP6:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @async_fun to i64))
+; POST-PROCESS-NEXT: [[TMP7:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @simple_await.resume.0 to i64))
+; POST-PROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[TMP6]], i32 [[TMP5]], i64 [[TMP7]]), !continuation.registercount [[META2]], !continuation.returnedRegistercount !2
; POST-PROCESS-NEXT: unreachable
;
;
; POST-PROCESS-LABEL: define dso_local void @simple_await.resume.0(
-; POST-PROCESS-SAME: i32 [[TMP0:%.*]]) !continuation.registercount !2 !continuation !3 {
+; POST-PROCESS-SAME: i32 [[TMP0:%.*]]) !continuation.registercount [[META2]] !continuation [[META3]] {
; POST-PROCESS-NEXT: entryresume.0:
-; POST-PROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [6 x i32], align 4
; POST-PROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
; POST-PROCESS-NEXT: store i32 [[TMP0]], ptr [[CSP]], align 4
; POST-PROCESS-NEXT: [[TMP1:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP2]], i64 -24
-; POST-PROCESS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(21) [[TMP4]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP6]], ptr [[TMP5]], align 4
-; POST-PROCESS-NEXT: [[TMP7:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 1
-; POST-PROCESS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; POST-PROCESS-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(21) [[TMP7]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP9]], ptr [[TMP8]], align 4
-; POST-PROCESS-NEXT: [[TMP10:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 2
-; POST-PROCESS-NEXT: [[TMP11:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; POST-PROCESS-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(21) [[TMP10]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP12]], ptr [[TMP11]], align 4
-; POST-PROCESS-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 3
-; POST-PROCESS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 3
-; POST-PROCESS-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(21) [[TMP13]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 4
-; POST-PROCESS-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 4
-; POST-PROCESS-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 4
-; POST-PROCESS-NEXT: [[TMP18:%.*]] = load i32, ptr addrspace(21) [[TMP16]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP18]], ptr [[TMP17]], align 4
-; POST-PROCESS-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 5
-; POST-PROCESS-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 5
-; POST-PROCESS-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(21) [[TMP19]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP21]], ptr [[TMP20]], align 4
-; POST-PROCESS-NEXT: [[TMP22:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP23:%.*]] = add i32 [[TMP22]], -24
-; POST-PROCESS-NEXT: store i32 [[TMP23]], ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[ARG_RELOAD:%.*]] = load <4 x i32>, ptr [[ARG_RELOAD_ADDR]], align 4
-; POST-PROCESS-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME]], ptr [[CONT_STATE]], i32 0, i32 1
-; POST-PROCESS-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr [[RETURNADDR_RELOAD_ADDR]], align 4
-; POST-PROCESS-NEXT: [[TMP24:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP24]], <4 x i32> [[ARG_RELOAD]]), !continuation.registercount !2
+; POST-PROCESS-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], -24
+; POST-PROCESS-NEXT: store i32 [[TMP2]], ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP3:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP4:%.*]] = inttoptr i32 [[TMP3]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP4]], i64 0
+; POST-PROCESS-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME:%.*]], ptr addrspace(21) [[TMP5]], i32 0, i32 0
+; POST-PROCESS-NEXT: [[ARG_RELOAD:%.*]] = load <4 x i32>, ptr addrspace(21) [[ARG_RELOAD_ADDR]], align 4
+; POST-PROCESS-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME]], ptr addrspace(21) [[TMP5]], i32 0, i32 1
+; POST-PROCESS-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr addrspace(21) [[RETURNADDR_RELOAD_ADDR]], align 4
+; POST-PROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP6]], <4 x i32> [[ARG_RELOAD]]), !continuation.registercount [[META2]]
; POST-PROCESS-NEXT: unreachable
;
;
; POST-PROCESS-LABEL: define void @simple_await_entry(
-; POST-PROCESS-SAME: <4 x i32> [[ARG:%.*]], ptr addrspace(1) [[MEM:%.*]]) !continuation.registercount !2 !continuation.entry !5 !continuation !6 !continuation.state !4 !continuation.stacksize !4 {
+; POST-PROCESS-SAME: <4 x i32> [[ARG:%.*]], ptr addrspace(1) [[MEM:%.*]]) !continuation.registercount [[META2]] !continuation.entry [[META5:![0-9]+]] !continuation [[META6:![0-9]+]] !continuation.state [[META4]] !continuation.stacksize [[META4]] {
; POST-PROCESS-NEXT: AllocaSpillBB:
-; POST-PROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [6 x i32], align 4
; POST-PROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
; POST-PROCESS-NEXT: [[TMP0:%.*]] = call i32 @_cont_GetContinuationStackAddr()
; POST-PROCESS-NEXT: store i32 [[TMP0]], ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[MEM_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 1
-; POST-PROCESS-NEXT: store ptr addrspace(1) [[MEM]], ptr [[MEM_SPILL_ADDR]], align 4
-; POST-PROCESS-NEXT: [[ARG_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME]], ptr [[CONT_STATE]], i32 0, i32 0
-; POST-PROCESS-NEXT: store <4 x i32> [[ARG]], ptr [[ARG_SPILL_ADDR]], align 4
; POST-PROCESS-NEXT: [[TMP1:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 24
-; POST-PROCESS-NEXT: store i32 [[TMP2]], ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP4]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP6]], ptr addrspace(21) [[TMP5]], align 4
-; POST-PROCESS-NEXT: [[TMP7:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; POST-PROCESS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 1
-; POST-PROCESS-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP9]], ptr addrspace(21) [[TMP8]], align 4
-; POST-PROCESS-NEXT: [[TMP10:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; POST-PROCESS-NEXT: [[TMP11:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 2
-; POST-PROCESS-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP10]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP12]], ptr addrspace(21) [[TMP11]], align 4
-; POST-PROCESS-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 3
-; POST-PROCESS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 3
-; POST-PROCESS-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP13]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP15]], ptr addrspace(21) [[TMP14]], align 4
-; POST-PROCESS-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 4
-; POST-PROCESS-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 4
-; POST-PROCESS-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP18]], ptr addrspace(21) [[TMP17]], align 4
-; POST-PROCESS-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 5
-; POST-PROCESS-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 5
-; POST-PROCESS-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP19]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP21]], ptr addrspace(21) [[TMP20]], align 4
-; POST-PROCESS-NEXT: [[TMP22:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP23:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @async_fun to i64))
-; POST-PROCESS-NEXT: [[TMP24:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @simple_await_entry.resume.0 to i64))
-; POST-PROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[TMP23]], i32 [[TMP22]], i64 [[TMP24]]), !continuation.registercount !2, !continuation.returnedRegistercount !2
+; POST-PROCESS-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP2]], i64 0
+; POST-PROCESS-NEXT: [[MEM_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME:%.*]], ptr addrspace(21) [[TMP3]], i32 0, i32 1
+; POST-PROCESS-NEXT: store ptr addrspace(1) [[MEM]], ptr addrspace(21) [[MEM_SPILL_ADDR]], align 4
+; POST-PROCESS-NEXT: [[ARG_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME]], ptr addrspace(21) [[TMP3]], i32 0, i32 0
+; POST-PROCESS-NEXT: store <4 x i32> [[ARG]], ptr addrspace(21) [[ARG_SPILL_ADDR]], align 4
+; POST-PROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], 24
+; POST-PROCESS-NEXT: store i32 [[TMP5]], ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP7:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @async_fun to i64))
+; POST-PROCESS-NEXT: [[TMP8:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @simple_await_entry.resume.0 to i64))
+; POST-PROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[TMP7]], i32 [[TMP6]], i64 [[TMP8]]), !continuation.registercount [[META2]], !continuation.returnedRegistercount !2
; POST-PROCESS-NEXT: unreachable
;
;
; POST-PROCESS-LABEL: define dso_local void @simple_await_entry.resume.0(
-; POST-PROCESS-SAME: i32 [[TMP0:%.*]]) !continuation.registercount !2 !continuation !6 {
+; POST-PROCESS-SAME: i32 [[TMP0:%.*]]) !continuation.registercount [[META2]] !continuation [[META6]] {
; POST-PROCESS-NEXT: entryresume.0:
-; POST-PROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [6 x i32], align 4
; POST-PROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
; POST-PROCESS-NEXT: store i32 [[TMP0]], ptr [[CSP]], align 4
; POST-PROCESS-NEXT: [[TMP1:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP2]], i64 -24
-; POST-PROCESS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(21) [[TMP4]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP6]], ptr [[TMP5]], align 4
-; POST-PROCESS-NEXT: [[TMP7:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 1
-; POST-PROCESS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; POST-PROCESS-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(21) [[TMP7]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP9]], ptr [[TMP8]], align 4
-; POST-PROCESS-NEXT: [[TMP10:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 2
-; POST-PROCESS-NEXT: [[TMP11:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; POST-PROCESS-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(21) [[TMP10]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP12]], ptr [[TMP11]], align 4
-; POST-PROCESS-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 3
-; POST-PROCESS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 3
-; POST-PROCESS-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(21) [[TMP13]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 4
-; POST-PROCESS-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 4
-; POST-PROCESS-NEXT: [[TMP17:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 4
-; POST-PROCESS-NEXT: [[TMP18:%.*]] = load i32, ptr addrspace(21) [[TMP16]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP18]], ptr [[TMP17]], align 4
-; POST-PROCESS-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 5
-; POST-PROCESS-NEXT: [[TMP20:%.*]] = getelementptr inbounds [6 x i32], ptr [[CONT_STATE]], i32 0, i32 5
-; POST-PROCESS-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(21) [[TMP19]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP21]], ptr [[TMP20]], align 4
-; POST-PROCESS-NEXT: [[TMP22:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP23:%.*]] = add i32 [[TMP22]], -24
-; POST-PROCESS-NEXT: store i32 [[TMP23]], ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[MEM_RELOAD_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 1
-; POST-PROCESS-NEXT: [[MEM_RELOAD:%.*]] = load ptr addrspace(1), ptr [[MEM_RELOAD_ADDR]], align 4
-; POST-PROCESS-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME]], ptr [[CONT_STATE]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[ARG_RELOAD:%.*]] = load <4 x i32>, ptr [[ARG_RELOAD_ADDR]], align 4
+; POST-PROCESS-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], -24
+; POST-PROCESS-NEXT: store i32 [[TMP2]], ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP3:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP4:%.*]] = inttoptr i32 [[TMP3]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP4]], i64 0
+; POST-PROCESS-NEXT: [[MEM_RELOAD_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME:%.*]], ptr addrspace(21) [[TMP5]], i32 0, i32 1
+; POST-PROCESS-NEXT: [[MEM_RELOAD:%.*]] = load ptr addrspace(1), ptr addrspace(21) [[MEM_RELOAD_ADDR]], align 4
+; POST-PROCESS-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_ENTRY_FRAME]], ptr addrspace(21) [[TMP5]], i32 0, i32 0
+; POST-PROCESS-NEXT: [[ARG_RELOAD:%.*]] = load <4 x i32>, ptr addrspace(21) [[ARG_RELOAD_ADDR]], align 4
; POST-PROCESS-NEXT: store <4 x i32> [[ARG_RELOAD]], ptr addrspace(1) [[MEM_RELOAD]], align 4
; POST-PROCESS-NEXT: call void @continuation.complete()
; POST-PROCESS-NEXT: unreachable
diff --git a/shared/continuations/test/dx/continuation-without-await.ll b/shared/continuations/test/dx/continuation-without-await.ll
index 3d6ad894f7..b42fd10b3d 100644
--- a/shared/continuations/test/dx/continuation-without-await.ll
+++ b/shared/continuations/test/dx/continuation-without-await.ll
@@ -127,12 +127,11 @@ attributes #2 = { nounwind }
;
;
; LOWERRAYTRACINGPIPELINE-LABEL: define void @main(
-; LOWERRAYTRACINGPIPELINE-SAME: ) !lgc.rt.shaderstage [[META9:![0-9]+]] !continuation.entry [[META19:![0-9]+]] !continuation.registercount [[META9]] !continuation [[META20:![0-9]+]] {
+; LOWERRAYTRACINGPIPELINE-SAME: [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage [[META9:![0-9]+]] !continuation.entry [[META19:![0-9]+]] !continuation.registercount [[META9]] !continuation [[META20:![0-9]+]] {
; LOWERRAYTRACINGPIPELINE-NEXT: [[PARAMS:%.*]] = alloca [[STRUCT_THEIRPARAMS:%.*]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP1:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_THEIRPARAMS]] zeroinitializer, ptr [[PARAMS]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[DIS_DATA_I:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_THEIRPARAMS]], ptr [[PARAMS]], i32 0, i32 0
@@ -145,16 +144,15 @@ attributes #2 = { nounwind }
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = load [1 x i32], ptr @PAYLOAD, align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [1 x i32] [[TMP7]], ptr [[TMP6]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP5]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; LOWERRAYTRACINGPIPELINE-NEXT: ret void, !continuation.registercount [[META17:![0-9]+]]
;
;
; LOWERRAYTRACINGPIPELINE-LABEL: define void @main_no_call(
-; LOWERRAYTRACINGPIPELINE-SAME: ) !lgc.rt.shaderstage [[META9]] !continuation.entry [[META19]] !continuation.registercount [[META9]] !continuation [[META22:![0-9]+]] {
-; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP1:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; LOWERRAYTRACINGPIPELINE-SAME: [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage [[META9]] !continuation.entry [[META19]] !continuation.registercount [[META9]] !continuation [[META22:![0-9]+]] {
+; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; LOWERRAYTRACINGPIPELINE-NEXT: ret void, !continuation.registercount [[META17]]
;
;
@@ -162,35 +160,34 @@ attributes #2 = { nounwind }
; LOWERRAYTRACINGPIPELINE-SAME: [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage [[META23:![0-9]+]] !continuation.registercount [[META24:![0-9]+]] !continuation [[META25:![0-9]+]] {
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP2:%.*]] = alloca [[STRUCT_MYPARAMS:%.*]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP3]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_MYPARAMS]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[TMP4]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP5]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = load i32, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP5]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 1), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP9]], ptr [[TMP8]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP5]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 2), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP11]], ptr [[TMP10]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_MYPARAMS]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[TMP3]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[TMP4]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = load i32, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP6]], ptr [[TMP5]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP4]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 1), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP8]], ptr [[TMP7]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[TMP4]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 2), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_MYPARAMS]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP12]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP13]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP15]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP13]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP17]], ptr getelementptr (i32, ptr @PAYLOAD, i64 1), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = getelementptr i32, ptr [[TMP13]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP19]], ptr getelementptr (i32, ptr @PAYLOAD, i64 2), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP20]], !continuation.registercount [[META24]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_MYPARAMS]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP11]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP12]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP14]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[TMP12]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP16]], ptr getelementptr (i32, ptr @PAYLOAD, i64 1), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[TMP12]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP18]], ptr getelementptr (i32, ptr @PAYLOAD, i64 2), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP19]], !continuation.registercount [[META24]]
;
;
; CLEANUP-LABEL: define i32 @_cont_GetLocalRootIndex(
@@ -199,12 +196,10 @@ attributes #2 = { nounwind }
;
;
; CLEANUP-LABEL: define void @main(
-; CLEANUP-SAME: ) !lgc.rt.shaderstage [[META9:![0-9]+]] !continuation.entry [[META19:![0-9]+]] !continuation.registercount [[META9]] !continuation [[META20:![0-9]+]] !continuation.state [[META9]] {
+; CLEANUP-SAME: [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage [[META9:![0-9]+]] !continuation.entry [[META19:![0-9]+]] !continuation.registercount [[META9]] !continuation [[META20:![0-9]+]] !continuation.state [[META9]] {
; CLEANUP-NEXT: AllocaSpillBB:
-; CLEANUP-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
-; CLEANUP-NEXT: [[TMP0:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA:%.*]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
; CLEANUP-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], 0
-; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; CLEANUP-NEXT: [[DIS_DATA_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, i32 [[DOTFCA_0_EXTRACT]], 0
; CLEANUP-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [1 x i32] poison, i32 0, 0
; CLEANUP-NEXT: store [1 x i32] [[DOTFCA_0_INSERT]], ptr @PAYLOAD, align 4
@@ -217,22 +212,19 @@ attributes #2 = { nounwind }
; CLEANUP-LABEL: define dso_local void @main.resume.0(
; CLEANUP-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.shaderstage [[META9]] !continuation.registercount [[META21]] !continuation [[META20]] {
; CLEANUP-NEXT: entryresume.0:
-; CLEANUP-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
; CLEANUP-NEXT: [[TMP2:%.*]] = load [1 x i32], ptr @PAYLOAD, align 4
; CLEANUP-NEXT: [[DOTFCA_0_EXTRACT4:%.*]] = extractvalue [1 x i32] [[TMP2]], 0
; CLEANUP-NEXT: [[DOTFCA_0_EXTRACT1:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
-; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; CLEANUP-NEXT: call void @continuation.complete()
; CLEANUP-NEXT: unreachable
;
;
; CLEANUP-LABEL: define void @main_no_call(
-; CLEANUP-SAME: ) !lgc.rt.shaderstage [[META9]] !continuation.entry [[META19]] !continuation.registercount [[META9]] !continuation [[META22:![0-9]+]] !continuation.state [[META9]] {
+; CLEANUP-SAME: [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage [[META9]] !continuation.entry [[META19]] !continuation.registercount [[META9]] !continuation [[META22:![0-9]+]] !continuation.state [[META9]] {
; CLEANUP-NEXT: AllocaSpillBB:
-; CLEANUP-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
-; CLEANUP-NEXT: [[TMP0:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA:%.*]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
; CLEANUP-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], 0
-; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; CLEANUP-NEXT: call void @continuation.complete()
; CLEANUP-NEXT: unreachable
;
@@ -240,22 +232,20 @@ attributes #2 = { nounwind }
; CLEANUP-LABEL: define void @called(
; CLEANUP-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage [[META23:![0-9]+]] !continuation.registercount [[META24:![0-9]+]] !continuation [[META25:![0-9]+]] !continuation.state [[META9]] {
; CLEANUP-NEXT: AllocaSpillBB:
-; CLEANUP-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
-; CLEANUP-NEXT: [[TMP1:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; CLEANUP-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
-; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; CLEANUP-NEXT: [[TMP2:%.*]] = load i32, ptr @PAYLOAD, align 4
-; CLEANUP-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 1), align 4
-; CLEANUP-NEXT: [[TMP4:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 2), align 4
+; CLEANUP-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], 0
+; CLEANUP-NEXT: [[TMP1:%.*]] = load i32, ptr @PAYLOAD, align 4
+; CLEANUP-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 1), align 4
+; CLEANUP-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 2), align 4
; CLEANUP-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
+; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; CLEANUP-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; CLEANUP-NEXT: store i32 [[TMP2]], ptr @PAYLOAD, align 4
-; CLEANUP-NEXT: store i32 [[TMP3]], ptr getelementptr (i32, ptr @PAYLOAD, i64 1), align 4
-; CLEANUP-NEXT: store i32 [[TMP4]], ptr getelementptr (i32, ptr @PAYLOAD, i64 2), align 4
+; CLEANUP-NEXT: store i32 [[TMP1]], ptr @PAYLOAD, align 4
+; CLEANUP-NEXT: store i32 [[TMP2]], ptr getelementptr (i32, ptr @PAYLOAD, i64 1), align 4
+; CLEANUP-NEXT: store i32 [[TMP3]], ptr getelementptr (i32, ptr @PAYLOAD, i64 2), align 4
; CLEANUP-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, i32 [[DOTFCA_0_EXTRACT]], 0
-; CLEANUP-NEXT: [[TMP5:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANUP-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP6]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META24]]
+; CLEANUP-NEXT: [[TMP4:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP5]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META24]]
; CLEANUP-NEXT: unreachable
;
;
@@ -265,15 +255,13 @@ attributes #2 = { nounwind }
;
;
; SAVESTATE-LABEL: define void @main(
-; SAVESTATE-SAME: ) !lgc.rt.shaderstage [[META8:![0-9]+]] !continuation.entry [[META18:![0-9]+]] !continuation.registercount [[META8]] !continuation [[META19:![0-9]+]] !continuation.state [[META8]] {
+; SAVESTATE-SAME: [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage [[META8:![0-9]+]] !continuation.entry [[META18:![0-9]+]] !continuation.registercount [[META8]] !continuation [[META19:![0-9]+]] !continuation.state [[META8]] {
; SAVESTATE-NEXT: AllocaSpillBB:
-; SAVESTATE-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
; SAVESTATE-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; SAVESTATE-NEXT: [[TMP0:%.*]] = call i32 @continuation.initialContinuationStackPtr()
-; SAVESTATE-NEXT: store i32 [[TMP0]], ptr [[CSP]], align 4
-; SAVESTATE-NEXT: [[TMP1:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA:%.*]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; SAVESTATE-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
-; SAVESTATE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; SAVESTATE-NEXT: [[TMP1:%.*]] = call i32 @continuation.initialContinuationStackPtr()
+; SAVESTATE-NEXT: store i32 [[TMP1]], ptr [[CSP]], align 4
+; SAVESTATE-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], 0
+; SAVESTATE-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; SAVESTATE-NEXT: [[DIS_DATA_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, i32 [[DOTFCA_0_EXTRACT]], 0
; SAVESTATE-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [1 x i32] poison, i32 0, 0
; SAVESTATE-NEXT: [[DOTFCA_0_INSERT_FCA_0_EXTRACT:%.*]] = extractvalue [1 x i32] [[DOTFCA_0_INSERT]], 0
@@ -286,23 +274,20 @@ attributes #2 = { nounwind }
; SAVESTATE-LABEL: define dso_local void @main.resume.0(
; SAVESTATE-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.shaderstage [[META8]] !continuation.registercount [[META20]] !continuation [[META19]] {
; SAVESTATE-NEXT: entryresume.0:
-; SAVESTATE-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
; SAVESTATE-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(20) @PAYLOAD, align 4
; SAVESTATE-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [1 x i32] poison, i32 [[TMP2]], 0
; SAVESTATE-NEXT: [[DOTFCA_0_EXTRACT4:%.*]] = extractvalue [1 x i32] [[DOTFCA_0_INSERT]], 0
; SAVESTATE-NEXT: [[DOTFCA_0_EXTRACT1:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
-; SAVESTATE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; SAVESTATE-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; SAVESTATE-NEXT: call void @continuation.complete()
; SAVESTATE-NEXT: unreachable
;
;
; SAVESTATE-LABEL: define void @main_no_call(
-; SAVESTATE-SAME: ) !lgc.rt.shaderstage [[META8]] !continuation.entry [[META18]] !continuation.registercount [[META8]] !continuation [[META21:![0-9]+]] !continuation.state [[META8]] {
+; SAVESTATE-SAME: [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage [[META8]] !continuation.entry [[META18]] !continuation.registercount [[META8]] !continuation [[META21:![0-9]+]] !continuation.state [[META8]] {
; SAVESTATE-NEXT: AllocaSpillBB:
-; SAVESTATE-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
-; SAVESTATE-NEXT: [[TMP0:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA:%.*]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
; SAVESTATE-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], 0
-; SAVESTATE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; SAVESTATE-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; SAVESTATE-NEXT: call void @continuation.complete()
; SAVESTATE-NEXT: unreachable
;
@@ -310,22 +295,20 @@ attributes #2 = { nounwind }
; SAVESTATE-LABEL: define void @called(
; SAVESTATE-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage [[META22:![0-9]+]] !continuation.registercount [[META23:![0-9]+]] !continuation [[META24:![0-9]+]] !continuation.state [[META8]] {
; SAVESTATE-NEXT: AllocaSpillBB:
-; SAVESTATE-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
; SAVESTATE-NEXT: [[CSP:%.*]] = alloca i32, align 4
; SAVESTATE-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
-; SAVESTATE-NEXT: [[TMP1:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; SAVESTATE-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
-; SAVESTATE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; SAVESTATE-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(20) @PAYLOAD, align 4
-; SAVESTATE-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr (i32, ptr addrspacecast (ptr addrspace(20) @PAYLOAD to ptr), i64 1) to ptr addrspace(20)), align 4
-; SAVESTATE-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr (i32, ptr addrspacecast (ptr addrspace(20) @PAYLOAD to ptr), i64 2) to ptr addrspace(20)), align 4
+; SAVESTATE-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], 0
+; SAVESTATE-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(20) @PAYLOAD, align 4
+; SAVESTATE-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr (i32, ptr addrspacecast (ptr addrspace(20) @PAYLOAD to ptr), i64 1) to ptr addrspace(20)), align 4
+; SAVESTATE-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr (i32, ptr addrspacecast (ptr addrspace(20) @PAYLOAD to ptr), i64 2) to ptr addrspace(20)), align 4
; SAVESTATE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr addrspacecast (ptr addrspace(20) @PAYLOAD to ptr))
+; SAVESTATE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; SAVESTATE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr addrspacecast (ptr addrspace(20) @PAYLOAD to ptr))
-; SAVESTATE-NEXT: store i32 [[TMP2]], ptr addrspace(20) @PAYLOAD, align 4
-; SAVESTATE-NEXT: store i32 [[TMP3]], ptr addrspace(20) addrspacecast (ptr getelementptr (i32, ptr addrspacecast (ptr addrspace(20) @PAYLOAD to ptr), i64 1) to ptr addrspace(20)), align 4
-; SAVESTATE-NEXT: store i32 [[TMP4]], ptr addrspace(20) addrspacecast (ptr getelementptr (i32, ptr addrspacecast (ptr addrspace(20) @PAYLOAD to ptr), i64 2) to ptr addrspace(20)), align 4
+; SAVESTATE-NEXT: store i32 [[TMP1]], ptr addrspace(20) @PAYLOAD, align 4
+; SAVESTATE-NEXT: store i32 [[TMP2]], ptr addrspace(20) addrspacecast (ptr getelementptr (i32, ptr addrspacecast (ptr addrspace(20) @PAYLOAD to ptr), i64 1) to ptr addrspace(20)), align 4
+; SAVESTATE-NEXT: store i32 [[TMP3]], ptr addrspace(20) addrspacecast (ptr getelementptr (i32, ptr addrspacecast (ptr addrspace(20) @PAYLOAD to ptr), i64 2) to ptr addrspace(20)), align 4
; SAVESTATE-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, i32 [[DOTFCA_0_EXTRACT]], 0
-; SAVESTATE-NEXT: [[TMP5:%.*]] = load i32, ptr [[CSP]], align 4
-; SAVESTATE-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP5]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META23]]
+; SAVESTATE-NEXT: [[TMP4:%.*]] = load i32, ptr [[CSP]], align 4
+; SAVESTATE-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP4]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META23]]
; SAVESTATE-NEXT: unreachable
;
diff --git a/shared/continuations/test/dx/dxil-cont-convert-lgc-rt-op-trace-payload-type.ll b/shared/continuations/test/dx/dxil-cont-convert-lgc-rt-op-trace-payload-type.ll
index 5f4b4d1267..baffcd6dbf 100644
--- a/shared/continuations/test/dx/dxil-cont-convert-lgc-rt-op-trace-payload-type.ll
+++ b/shared/continuations/test/dx/dxil-cont-convert-lgc-rt-op-trace-payload-type.ll
@@ -45,16 +45,16 @@ declare !types !42 i1 @dx.op.reportHit.struct.BuiltInTriangleIntersectionAttribu
define void @main() {
; PAYLOADTYPE-LABEL: define void @main
-; PAYLOADTYPE: call void (...) @lgc.rt.call.callable.shader(i32 1, %struct.TheirParams* %{{.*}}, i32 256), !dxil.payload.type ![[call_callable_shader_payload_type:[0-9]+]]
-; PAYLOADTYPE-NEXT: call void (...) @lgc.rt.call.callable.shader(i32 1, %struct.TheirParams* %{{.*}}, i32 256), !dxil.payload.type ![[call_callable_shader_payload_type]]
-; PAYLOADTYPE-NEXT: call void (...) @lgc.rt.call.callable.shader(i32 2, %struct.TheirParams2* %{{.*}}, i32 260), !dxil.payload.type ![[call_callable_shader_payload_type2:[0-9]+]]
+; PAYLOADTYPE: call void (...) @lgc.rt.call.callable.shader(i32 1, %struct.TheirParams* %{{.*}}, i32 256), !cont.payload.type ![[call_callable_shader_payload_type:[0-9]+]]
+; PAYLOADTYPE-NEXT: call void (...) @lgc.rt.call.callable.shader(i32 1, %struct.TheirParams* %{{.*}}, i32 256), !cont.payload.type ![[call_callable_shader_payload_type]]
+; PAYLOADTYPE-NEXT: call void (...) @lgc.rt.call.callable.shader(i32 2, %struct.TheirParams2* %{{.*}}, i32 260), !cont.payload.type ![[call_callable_shader_payload_type2:[0-9]+]]
; PAYLOADTYPE: ![[call_callable_shader_payload_type]] = !{%struct.TheirParams poison}
; PAYLOADTYPE: ![[call_callable_shader_payload_type2]] = !{%struct.TheirParams2 poison}
; PAYLOADTYPE-OPAQUE-LABEL: define void @main
-; PAYLOADTYPE-OPAQUE: call void (...) @lgc.rt.call.callable.shader(i32 1, ptr %{{.*}}, i32 256), !dxil.payload.type ![[call_callable_shader_payload_type:[0-9]+]]
-; PAYLOADTYPE-OPAQUE-NEXT: call void (...) @lgc.rt.call.callable.shader(i32 1, ptr %{{.*}}, i32 256), !dxil.payload.type ![[call_callable_shader_payload_type]]
-; PAYLOADTYPE-OPAQUE-NEXT: call void (...) @lgc.rt.call.callable.shader(i32 2, ptr %{{.*}}, i32 260), !dxil.payload.type ![[call_callable_shader_payload_type2:[0-9]+]]
+; PAYLOADTYPE-OPAQUE: call void (...) @lgc.rt.call.callable.shader(i32 1, ptr %{{.*}}, i32 256), !cont.payload.type ![[call_callable_shader_payload_type:[0-9]+]]
+; PAYLOADTYPE-OPAQUE-NEXT: call void (...) @lgc.rt.call.callable.shader(i32 1, ptr %{{.*}}, i32 256), !cont.payload.type ![[call_callable_shader_payload_type]]
+; PAYLOADTYPE-OPAQUE-NEXT: call void (...) @lgc.rt.call.callable.shader(i32 2, ptr %{{.*}}, i32 260), !cont.payload.type ![[call_callable_shader_payload_type2:[0-9]+]]
; PAYLOADTYPE-OPAQUE: ![[call_callable_shader_payload_type]] = !{%struct.TheirParams poison}
; PAYLOADTYPE-OPAQUE: ![[call_callable_shader_payload_type2]] = !{%struct.TheirParams2 poison}
;
@@ -68,14 +68,14 @@ define void @main() {
define void @mainTrace() {
; PAYLOADTYPE2-LABEL: define void @mainTrace
-; PAYLOADTYPE2: call void (...) @lgc.rt.trace.ray(i64 %{{.*}}, i32 16, i32 -1, i32 0, i32 1, i32 0, <3 x float> zeroinitializer, float 0x3F50624DE0000000, <3 x float> <float 1.000000e+00, float 0.000000e+00, float 0.000000e+00>, float 1.000000e+04, %struct.RayPayload* %{{.*}}, [1 x i32] [i32 272]), !dxil.payload.type ![[traceray_payload_type:[0-9]+]]
-; PAYLOADTYPE2: call void (...) @lgc.rt.trace.ray(i64 %{{.*}}, i32 16, i32 -1, i32 0, i32 1, i32 0, <3 x float> zeroinitializer, float 0x3F50624DE0000000, <3 x float> <float 1.000000e+00, float 0.000000e+00, float 0.000000e+00>, float 1.000000e+04, %struct.RayPayload2* %{{.*}}, [1 x i32] [i32 256]), !dxil.payload.type ![[traceray_payload_type2:[0-9]+]]
+; PAYLOADTYPE2: call void (...) @lgc.rt.trace.ray(i64 %{{.*}}, i32 16, i32 -1, i32 0, i32 1, i32 0, <3 x float> zeroinitializer, float 0x3F50624DE0000000, <3 x float> <float 1.000000e+00, float 0.000000e+00, float 0.000000e+00>, float 1.000000e+04, %struct.RayPayload* %{{.*}}, [1 x i32] [i32 272]), !cont.payload.type ![[traceray_payload_type:[0-9]+]]
+; PAYLOADTYPE2: call void (...) @lgc.rt.trace.ray(i64 %{{.*}}, i32 16, i32 -1, i32 0, i32 1, i32 0, <3 x float> zeroinitializer, float 0x3F50624DE0000000, <3 x float> <float 1.000000e+00, float 0.000000e+00, float 0.000000e+00>, float 1.000000e+04, %struct.RayPayload2* %{{.*}}, [1 x i32] [i32 256]), !cont.payload.type ![[traceray_payload_type2:[0-9]+]]
; PAYLOADTYPE2: ![[traceray_payload_type]] = !{%struct.RayPayload poison}
; PAYLOADTYPE2: ![[traceray_payload_type2]] = !{%struct.RayPayload2 poison}
; PAYLOADTYPE2-OPAQUE-LABEL: define void @mainTrace
-; PAYLOADTYPE2-OPAQUE: call void (...) @lgc.rt.trace.ray(i64 %{{.*}}, i32 16, i32 -1, i32 0, i32 1, i32 0, <3 x float> zeroinitializer, float 0x3F50624DE0000000, <3 x float> <float 1.000000e+00, float 0.000000e+00, float 0.000000e+00>, float 1.000000e+04, ptr %{{.*}}, [1 x i32] [i32 272]), !dxil.payload.type ![[traceray_payload_type:[0-9]+]]
-; PAYLOADTYPE2-OPAQUE: call void (...) @lgc.rt.trace.ray(i64 %{{.*}}, i32 16, i32 -1, i32 0, i32 1, i32 0, <3 x float> zeroinitializer, float 0x3F50624DE0000000, <3 x float> <float 1.000000e+00, float 0.000000e+00, float 0.000000e+00>, float 1.000000e+04, ptr %{{.*}}, [1 x i32] [i32 256]), !dxil.payload.type ![[traceray_payload_type2:[0-9]+]]
+; PAYLOADTYPE2-OPAQUE: call void (...) @lgc.rt.trace.ray(i64 %{{.*}}, i32 16, i32 -1, i32 0, i32 1, i32 0, <3 x float> zeroinitializer, float 0x3F50624DE0000000, <3 x float> <float 1.000000e+00, float 0.000000e+00, float 0.000000e+00>, float 1.000000e+04, ptr %{{.*}}, [1 x i32] [i32 272]), !cont.payload.type ![[traceray_payload_type:[0-9]+]]
+; PAYLOADTYPE2-OPAQUE: call void (...) @lgc.rt.trace.ray(i64 %{{.*}}, i32 16, i32 -1, i32 0, i32 1, i32 0, <3 x float> zeroinitializer, float 0x3F50624DE0000000, <3 x float> <float 1.000000e+00, float 0.000000e+00, float 0.000000e+00>, float 1.000000e+04, ptr %{{.*}}, [1 x i32] [i32 256]), !cont.payload.type ![[traceray_payload_type2:[0-9]+]]
; PAYLOADTYPE2-OPAQUE: ![[traceray_payload_type]] = !{%struct.RayPayload poison}
; PAYLOADTYPE2-OPAQUE: ![[traceray_payload_type2]] = !{%struct.RayPayload2 poison}
;
@@ -94,10 +94,10 @@ define void @mainTrace() {
define void @called(%struct.MyParams* %arg) !types !38 {
; PAYLOADTYPE3-LABEL: define void @called
-; PAYLOADTYPE3: call void (...) @lgc.rt.call.callable.shader(i32 2, %struct.TheirParams2* %{{.*}}, i32 260), !dxil.payload.type ![[call_callable_shader_payload_type:[0-9]+]]
+; PAYLOADTYPE3: call void (...) @lgc.rt.call.callable.shader(i32 2, %struct.TheirParams2* %{{.*}}, i32 260), !cont.payload.type ![[call_callable_shader_payload_type:[0-9]+]]
; PAYLOADTYPE3: ![[call_callable_shader_payload_type]] = !{%struct.TheirParams2 poison}
; PAYLOADTYPE3-OPAQUE-LABEL: define void @called
-; PAYLOADTYPE3-OPAQUE: call void (...) @lgc.rt.call.callable.shader(i32 2, ptr %{{.*}}, i32 260), !dxil.payload.type ![[call_callable_shader_payload_type:[0-9]+]]
+; PAYLOADTYPE3-OPAQUE: call void (...) @lgc.rt.call.callable.shader(i32 2, ptr %{{.*}}, i32 260), !cont.payload.type ![[call_callable_shader_payload_type:[0-9]+]]
; PAYLOADTYPE3-OPAQUE: ![[call_callable_shader_payload_type]] = !{%struct.TheirParams2 poison}
;
%params = alloca %struct.TheirParams2, align 4
diff --git a/shared/continuations/test/dx/dxil-cont-convert-lgc-rt-op-trace.ll b/shared/continuations/test/dx/dxil-cont-convert-lgc-rt-op-trace.ll
index c94258e1ca..2c743083e4 100644
--- a/shared/continuations/test/dx/dxil-cont-convert-lgc-rt-op-trace.ll
+++ b/shared/continuations/test/dx/dxil-cont-convert-lgc-rt-op-trace.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
; RUN: opt --verify-each -passes='dxil-cont-lgc-rt-op-converter,lint' -S %s 2> %t0.stderr | FileCheck %s
; RUN: count 0 < %t0.stderr
@@ -40,14 +40,14 @@ declare !types !42 i1 @dx.op.reportHit.struct.BuiltInTriangleIntersectionAttribu
; Function Attrs: nounwind
define void @Intersection() #0 {
-; CHECK-LABEL: define void @Intersection
-; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
+; CHECK-LABEL: define void @Intersection(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[TMP1:%.*]] = call float @lgc.rt.ray.tmin()
; CHECK-NEXT: [[TMP2:%.*]] = call float @lgc.rt.ray.tcurrent()
; CHECK-NEXT: [[TMP3:%.*]] = call i32 @lgc.rt.instance.id()
; CHECK-NEXT: [[TMP4:%.*]] = call i32 @lgc.rt.hit.kind()
; CHECK-NEXT: [[TMP5:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]], align 4
-; CHECK-NEXT: [[TMP6:%.*]] = call i1 (...) @lgc.rt.report.hit(float 4.000000e+00, i32 0, ptr [[TMP5]], i32 8), !dxil.payload.type !25
+; CHECK-NEXT: [[TMP6:%.*]] = call i1 (...) @lgc.rt.report.hit(float 4.000000e+00, i32 0, ptr [[TMP5]], i32 8), !cont.payload.type [[META25:![0-9]+]]
; CHECK-NEXT: ret void
;
%1 = call float @dx.op.rayTMin.f32(i32 153) ; RayTMin()
@@ -60,9 +60,12 @@ define void @Intersection() #0 {
}
define void @main() {
-; CHECK-LABEL: define void @main() !lgc.rt.shaderstage !8 {
+; CHECK-LABEL: define void @main(
+; CHECK-SAME: ) !lgc.rt.shaderstage [[META8:![0-9]+]] {
; CHECK-NEXT: [[PARAMS:%.*]] = alloca [[STRUCT_THEIRPARAMS:%.*]], align 4
-; CHECK-NEXT: call void (...) @lgc.rt.call.callable.shader(i32 1, ptr [[PARAMS]], i32 256), !dxil.payload.type !26
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @lgc.rt.shader.index()
+; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[TMP1]])
+; CHECK-NEXT: call void (...) @lgc.rt.call.callable.shader(i32 1, ptr [[PARAMS]], i32 256), !cont.payload.type [[META26:![0-9]+]]
; CHECK-NEXT: ret void
;
%params = alloca %struct.TheirParams, align 4
@@ -71,15 +74,18 @@ define void @main() {
}
define void @mainTrace() {
-; CHECK-LABEL: define void @mainTrace() !lgc.rt.shaderstage !8 {
-; CHECK-NEXT: [[TMP1:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
-; CHECK-NEXT: [[TMP2:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
-; CHECK-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 4
-; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP1]])
-; CHECK-NEXT: [[TMP6:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP5]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
-; CHECK-NEXT: [[TMP7:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[TMP6]])
-; CHECK-NEXT: call void (...) @lgc.rt.trace.ray(i64 [[TMP7]], i32 16, i32 -1, i32 0, i32 1, i32 0, <3 x float> zeroinitializer, float 0x3F50624DE0000000, <3 x float> <float 1.000000e+00, float 0.000000e+00, float 0.000000e+00>, float 1.000000e+04, ptr [[TMP3]], [1 x i32] [i32 272]), !dxil.payload.type !27
+; CHECK-LABEL: define void @mainTrace(
+; CHECK-SAME: ) !lgc.rt.shaderstage [[META8]] {
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @lgc.rt.shader.index()
+; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[TMP1]])
+; CHECK-NEXT: [[TMP2:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
+; CHECK-NEXT: [[TMP4:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 4
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP4]], i32 0, i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP2]])
+; CHECK-NEXT: [[TMP7:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP6]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[TMP7]])
+; CHECK-NEXT: call void (...) @lgc.rt.trace.ray(i64 [[TMP8]], i32 16, i32 -1, i32 0, i32 1, i32 0, <3 x float> zeroinitializer, float 0x3F50624DE0000000, <3 x float> <float 1.000000e+00, float 0.000000e+00, float 0.000000e+00>, float 1.000000e+04, ptr [[TMP4]], [1 x i32] [i32 272]), !cont.payload.type [[META27:![0-9]+]]
; CHECK-NEXT: ret void
;
%1 = load %dx.types.Handle, %dx.types.Handle* @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
@@ -93,10 +99,12 @@ define void @mainTrace() {
}
define void @called(%struct.MyParams* %arg) !types !38 {
-; CHECK-LABEL: define void @called
-; CHECK-SAME: (ptr [[ARG:%.*]]) !types !28 !lgc.rt.shaderstage !30 !dxil.payload.type !31 {
+; CHECK-LABEL: define void @called(
+; CHECK-SAME: ptr [[ARG:%.*]]) !types [[META28:![0-9]+]] !lgc.rt.shaderstage [[META30:![0-9]+]] !cont.payload.type [[META31:![0-9]+]] {
; CHECK-NEXT: [[PARAMS:%.*]] = alloca [[STRUCT_THEIRPARAMS2:%.*]], align 4
-; CHECK-NEXT: call void (...) @lgc.rt.call.callable.shader(i32 2, ptr [[PARAMS]], i32 260), !dxil.payload.type !32
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @lgc.rt.shader.index()
+; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[TMP1]])
+; CHECK-NEXT: call void (...) @lgc.rt.call.callable.shader(i32 2, ptr [[PARAMS]], i32 260), !cont.payload.type [[META32:![0-9]+]]
; CHECK-NEXT: ret void
;
%params = alloca %struct.TheirParams2, align 4
diff --git a/shared/continuations/test/dx/dxil-cont-convert-lgc-rt-op.ll b/shared/continuations/test/dx/dxil-cont-convert-lgc-rt-op.ll
index cf7eba0c28..dd0be64828 100644
--- a/shared/continuations/test/dx/dxil-cont-convert-lgc-rt-op.ll
+++ b/shared/continuations/test/dx/dxil-cont-convert-lgc-rt-op.ll
@@ -19,46 +19,48 @@ target datalayout = "e-m:e-p:64:32-p20:32:32-p21:32:32-i1:32-i8:8-i16:32-i32:32-
; Function Attrs: nounwind
define void @ClosestHit(%struct.RayPayload*, %struct.BuiltInTriangleIntersectionAttributes*) #0 !types !31 {
; CHECK-LABEL: define void @ClosestHit(
-; CHECK-SAME: ptr [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] !lgc.rt.shaderstage !19 !dxil.payload.type !20 {
+; CHECK-SAME: ptr [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] !cont.payload.type [[META19:![0-9]+]] !lgc.rt.shaderstage [[META20:![0-9]+]] {
; CHECK-NEXT: [[TMP3:%.*]] = alloca [4 x <3 x float>], align 4
; CHECK-NEXT: [[TMP4:%.*]] = alloca [4 x <3 x float>], align 4
; CHECK-NEXT: [[TMP5:%.*]] = alloca [4 x <3 x float>], align 4
; CHECK-NEXT: [[TMP6:%.*]] = alloca [4 x <3 x float>], align 4
-; CHECK-NEXT: [[TMP7:%.*]] = call <3 x i32> @lgc.rt.dispatch.rays.index()
-; CHECK-NEXT: [[A:%.*]] = extractelement <3 x i32> [[TMP7]], i8 0
-; CHECK-NEXT: [[TMP8:%.*]] = call <3 x i32> @lgc.rt.dispatch.rays.dimensions()
-; CHECK-NEXT: [[B:%.*]] = extractelement <3 x i32> [[TMP8]], i8 0
-; CHECK-NEXT: [[TMP9:%.*]] = call <3 x float> @lgc.rt.world.ray.origin()
-; CHECK-NEXT: [[C:%.*]] = extractelement <3 x float> [[TMP9]], i8 0
-; CHECK-NEXT: [[TMP10:%.*]] = call <3 x float> @lgc.rt.world.ray.direction()
-; CHECK-NEXT: [[D:%.*]] = extractelement <3 x float> [[TMP10]], i8 0
+; CHECK-NEXT: [[TMP7:%.*]] = call i32 @lgc.rt.shader.index()
+; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[TMP7]])
+; CHECK-NEXT: [[TMP8:%.*]] = call <3 x i32> @lgc.rt.dispatch.rays.index()
+; CHECK-NEXT: [[A:%.*]] = extractelement <3 x i32> [[TMP8]], i8 0
+; CHECK-NEXT: [[TMP9:%.*]] = call <3 x i32> @lgc.rt.dispatch.rays.dimensions()
+; CHECK-NEXT: [[B:%.*]] = extractelement <3 x i32> [[TMP9]], i8 0
+; CHECK-NEXT: [[TMP10:%.*]] = call <3 x float> @lgc.rt.world.ray.origin()
+; CHECK-NEXT: [[C:%.*]] = extractelement <3 x float> [[TMP10]], i8 0
+; CHECK-NEXT: [[TMP11:%.*]] = call <3 x float> @lgc.rt.world.ray.direction()
+; CHECK-NEXT: [[D:%.*]] = extractelement <3 x float> [[TMP11]], i8 0
; CHECK-NEXT: [[E:%.*]] = call float @lgc.rt.ray.tmin()
; CHECK-NEXT: [[F:%.*]] = call float @lgc.rt.ray.tcurrent()
; CHECK-NEXT: [[G:%.*]] = call i32 @lgc.rt.ray.flags()
; CHECK-NEXT: [[H:%.*]] = call i32 @lgc.rt.instance.index()
; CHECK-NEXT: [[I:%.*]] = call i32 @lgc.rt.instance.id()
; CHECK-NEXT: [[J:%.*]] = call i32 @lgc.rt.primitive.index()
-; CHECK-NEXT: [[TMP11:%.*]] = call <3 x float> @lgc.rt.object.ray.origin()
-; CHECK-NEXT: [[K:%.*]] = extractelement <3 x float> [[TMP11]], i8 0
-; CHECK-NEXT: [[TMP12:%.*]] = call <3 x float> @lgc.rt.object.ray.direction()
-; CHECK-NEXT: [[L:%.*]] = extractelement <3 x float> [[TMP12]], i8 0
-; CHECK-NEXT: [[TMP13:%.*]] = call [4 x <3 x float>] @lgc.rt.object.to.world()
-; CHECK-NEXT: store [4 x <3 x float>] [[TMP13]], ptr [[TMP4]], align 4
+; CHECK-NEXT: [[TMP12:%.*]] = call <3 x float> @lgc.rt.object.ray.origin()
+; CHECK-NEXT: [[K:%.*]] = extractelement <3 x float> [[TMP12]], i8 0
+; CHECK-NEXT: [[TMP13:%.*]] = call <3 x float> @lgc.rt.object.ray.direction()
+; CHECK-NEXT: [[L:%.*]] = extractelement <3 x float> [[TMP13]], i8 0
+; CHECK-NEXT: [[TMP14:%.*]] = call [4 x <3 x float>] @lgc.rt.object.to.world()
+; CHECK-NEXT: store [4 x <3 x float>] [[TMP14]], ptr [[TMP4]], align 4
; CHECK-NEXT: [[COL_GEP1:%.*]] = getelementptr [4 x <3 x float>], ptr [[TMP4]], i32 0, i8 0
; CHECK-NEXT: [[COL_GEP_LOAD2:%.*]] = load <3 x float>, ptr [[COL_GEP1]], align 4
; CHECK-NEXT: [[M:%.*]] = extractelement <3 x float> [[COL_GEP_LOAD2]], i32 0
-; CHECK-NEXT: [[TMP14:%.*]] = call [4 x <3 x float>] @lgc.rt.world.to.object()
-; CHECK-NEXT: store [4 x <3 x float>] [[TMP14]], ptr [[TMP3]], align 4
+; CHECK-NEXT: [[TMP15:%.*]] = call [4 x <3 x float>] @lgc.rt.world.to.object()
+; CHECK-NEXT: store [4 x <3 x float>] [[TMP15]], ptr [[TMP3]], align 4
; CHECK-NEXT: [[COL_GEP:%.*]] = getelementptr [4 x <3 x float>], ptr [[TMP3]], i32 0, i8 0
; CHECK-NEXT: [[COL_GEP_LOAD:%.*]] = load <3 x float>, ptr [[COL_GEP]], align 4
; CHECK-NEXT: [[N:%.*]] = extractelement <3 x float> [[COL_GEP_LOAD]], i32 0
-; CHECK-NEXT: [[TMP15:%.*]] = call [4 x <3 x float>] @lgc.rt.object.to.world()
-; CHECK-NEXT: store [4 x <3 x float>] [[TMP15]], ptr [[TMP5]], align 4
+; CHECK-NEXT: [[TMP16:%.*]] = call [4 x <3 x float>] @lgc.rt.object.to.world()
+; CHECK-NEXT: store [4 x <3 x float>] [[TMP16]], ptr [[TMP5]], align 4
; CHECK-NEXT: [[COL_GEP3:%.*]] = getelementptr [4 x <3 x float>], ptr [[TMP5]], i32 0, i8 3
; CHECK-NEXT: [[COL_GEP_LOAD4:%.*]] = load <3 x float>, ptr [[COL_GEP3]], align 4
; CHECK-NEXT: [[O:%.*]] = extractelement <3 x float> [[COL_GEP_LOAD4]], i32 0
-; CHECK-NEXT: [[TMP16:%.*]] = call [4 x <3 x float>] @lgc.rt.object.to.world()
-; CHECK-NEXT: store [4 x <3 x float>] [[TMP16]], ptr [[TMP6]], align 4
+; CHECK-NEXT: [[TMP17:%.*]] = call [4 x <3 x float>] @lgc.rt.object.to.world()
+; CHECK-NEXT: store [4 x <3 x float>] [[TMP17]], ptr [[TMP6]], align 4
; CHECK-NEXT: [[COL_GEP5:%.*]] = getelementptr [4 x <3 x float>], ptr [[TMP6]], i32 0, i8 3
; CHECK-NEXT: [[COL_GEP_LOAD6:%.*]] = load <3 x float>, ptr [[COL_GEP5]], align 4
; CHECK-NEXT: [[P:%.*]] = extractelement <3 x float> [[COL_GEP_LOAD6]], i32 2
diff --git a/shared/continuations/test/dx/dxil-cont-intrinsic-prepare.ll b/shared/continuations/test/dx/dxil-cont-intrinsic-prepare.ll
index 74ec0f5fc5..4da900240e 100644
--- a/shared/continuations/test/dx/dxil-cont-intrinsic-prepare.ll
+++ b/shared/continuations/test/dx/dxil-cont-intrinsic-prepare.ll
@@ -84,7 +84,7 @@ attributes #4 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
;
;
; CHECK-LABEL: define %struct.DispatchSystemData @_cont_SetupRayGen(
-; CHECK-SAME: ) #[[ATTR1:[0-9]+]] !types !0 {
+; CHECK-SAME: ) #[[ATTR1:[0-9]+]] !types [[META0:![0-9]+]] {
; CHECK-NEXT: [[TMP1:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[TMP1]], i32 0, i32 0
; CHECK-NEXT: store i32 2, ptr [[TMP2]], align 4
@@ -100,7 +100,7 @@ attributes #4 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
;
;
; CHECK-LABEL: define %struct.DispatchSystemData @_cont_TraceRay(
-; CHECK-SAME: ptr nocapture readonly [[DATA:%.*]], i64 [[ACCELSTRUCT:%.*]], i32 [[RAYFLAGS:%.*]], i32 [[INSTANCEINCLUSIOMASK:%.*]], i32 [[RAYCONTRIBUTIONTOHITGROUPINDEX:%.*]], i32 [[MULTIPLIERFORGEOMETRYCONTRIBUTIONTOSHADERINDEX:%.*]], i32 [[MISSSHADERINDEX:%.*]], float [[ORIGINX:%.*]], float [[ORIGINY:%.*]], float [[ORIGINZ:%.*]], float [[TMIN:%.*]], float [[DIRX:%.*]], float [[DIRY:%.*]], float [[DIRZ:%.*]], float [[TMAX:%.*]]) #[[ATTR1]] !types !2 {
+; CHECK-SAME: ptr nocapture readonly [[DATA:%.*]], i64 [[ACCELSTRUCT:%.*]], i32 [[RAYFLAGS:%.*]], i32 [[INSTANCEINCLUSIOMASK:%.*]], i32 [[RAYCONTRIBUTIONTOHITGROUPINDEX:%.*]], i32 [[MULTIPLIERFORGEOMETRYCONTRIBUTIONTOSHADERINDEX:%.*]], i32 [[MISSSHADERINDEX:%.*]], float [[ORIGINX:%.*]], float [[ORIGINY:%.*]], float [[ORIGINZ:%.*]], float [[TMIN:%.*]], float [[DIRX:%.*]], float [[DIRY:%.*]], float [[DIRZ:%.*]], float [[TMAX:%.*]]) #[[ATTR1]] !types [[META2:![0-9]+]] {
; CHECK-NEXT: [[TMP1:%.*]] = alloca [[STRUCT_TRAVERSALDATA:%.*]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
diff --git a/shared/continuations/test/dx/dxil-cont-post-process-report-sizes.ll b/shared/continuations/test/dx/dxil-cont-post-process-report-sizes.ll
index ccb415c7e8..8939df5a18 100644
--- a/shared/continuations/test/dx/dxil-cont-post-process-report-sizes.ll
+++ b/shared/continuations/test/dx/dxil-cont-post-process-report-sizes.ll
@@ -15,7 +15,7 @@ declare void @continuation.continue(i64, ...)
; REPORT-CONT-SIZES: Continuation state size of "RayGen" (raygeneration): 108 bytes
; REPORT-PAYLOAD-SIZES: Incoming and max outgoing payload VGPR size of "RayGen" (raygeneration): 28 and 24 bytes
-define void @RayGen() !continuation.entry !0 !continuation !3 !continuation.state !5 !continuation.registercount !7 !lgc.rt.shaderstage !12 {
+define void @RayGen(%struct.DispatchSystemData %0) !continuation.entry !0 !continuation !3 !continuation.state !5 !continuation.registercount !7 !lgc.rt.shaderstage !12 {
%csp = alloca i32, align 4
%cspInit = call i32 @continuation.initialContinuationStackPtr()
store i32 %cspInit, i32* %csp
diff --git a/shared/continuations/test/dx/dxil-cont-post-process.ll b/shared/continuations/test/dx/dxil-cont-post-process.ll
index 82fe3c7fa1..f1e2846dc0 100644
--- a/shared/continuations/test/dx/dxil-cont-post-process.ll
+++ b/shared/continuations/test/dx/dxil-cont-post-process.ll
@@ -11,14 +11,13 @@ declare i32 @_cont_GetContinuationStackAddr()
declare i32 @_cont_GetLocalRootIndex(%struct.DispatchSystemData*)
declare %struct.DispatchSystemData @_cont_SetupRayGen()
-define void @RayGen() !lgc.rt.shaderstage !5 !continuation.entry !0 !continuation !3 {
-; CHECK-LABEL: define void @RayGen() !lgc.rt.shaderstage !3 !continuation.entry !4 !continuation !5 {
-; CHECK-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
+define void @RayGen(%struct.DispatchSystemData %0) !lgc.rt.shaderstage !5 !continuation.entry !0 !continuation !3 {
+; CHECK-LABEL: define void @RayGen(
+; CHECK-SAME: ) !lgc.rt.shaderstage [[META3:![0-9]+]] !continuation.entry [[META4:![0-9]+]] !continuation [[META5:![0-9]+]] {
; CHECK-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; CHECK-NEXT: [[TMP1:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @_cont_SetupRayGen()
-; CHECK-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = call i32 @_cont_GetContinuationStackAddr()
-; CHECK-NEXT: store i32 [[TMP2]], ptr [[CSP]], align 4
+; CHECK-NEXT: [[SYSTEM_DATA:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA:%.*]] @_cont_SetupRayGen()
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @_cont_GetContinuationStackAddr()
+; CHECK-NEXT: store i32 [[TMP1]], ptr [[CSP]], align 4
; CHECK-NEXT: ret void
;
%csp = alloca i32, align 4
@@ -29,9 +28,7 @@ define void @RayGen() !lgc.rt.shaderstage !5 !continuation.entry !0 !continuatio
define void @RayGen.resume.0(i32 %0, %struct.DispatchSystemData %1) !lgc.rt.shaderstage !5 !continuation !3 {
; CHECK-LABEL: define void @RayGen.resume.0(
-; CHECK-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.shaderstage !3 !continuation !5 {
-; CHECK-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
-; CHECK-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA]], align 4
+; CHECK-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.shaderstage [[META3]] !continuation [[META5]] {
; CHECK-NEXT: ret void
;
ret void
diff --git a/shared/continuations/test/dx/global-mem-stack.ll b/shared/continuations/test/dx/global-mem-stack.ll
index 8eb7e1d3e7..dfa5cd9dff 100644
--- a/shared/continuations/test/dx/global-mem-stack.ll
+++ b/shared/continuations/test/dx/global-mem-stack.ll
@@ -142,109 +142,105 @@ define void @MyClosestHitShader(%struct.RayPayload* noalias nocapture %payload,
;
;
; CHECK-LABEL: define void @MyClosestHitShader(
-; CHECK-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage !9 !continuation.registercount !8 !continuation !10 !continuation.state !6 {
+; CHECK-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage [[META9:![0-9]+]] !continuation.registercount [[META8:![0-9]+]] !continuation [[META10:![0-9]+]] !continuation.state [[META6:![0-9]+]] {
; CHECK-NEXT: AllocaSpillBB:
-; CHECK-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
-; CHECK-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
; CHECK-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; CHECK-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
; CHECK-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = load [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA]], align 4
-; CHECK-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP1]], 0, 0
-; CHECK-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP1]], 1, 0
-; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; CHECK-NEXT: [[TMP3:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
-; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr addrspace(22)
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP4]], i32 [[TMP2]]
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP5]], i32 -2
-; CHECK-NEXT: [[TMP7:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspace(22) [[TMP6]], i32 0, i32 0, i32 7
-; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(22) [[TMP7]], align 4
-; CHECK-NEXT: [[TMP9:%.*]] = bitcast i32 [[TMP8]] to float
-; CHECK-NEXT: [[DOTSROA_0_0_VEC_INSERT:%.*]] = insertelement <4 x float> undef, float [[TMP9]], i32 0
-; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; CHECK-NEXT: [[TMP11:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
-; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr addrspace(22)
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP12]], i32 [[TMP10]]
-; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP13]], i32 -2
-; CHECK-NEXT: [[TMP15:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP14]], i32 0, i32 0, i64 8
-; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(22) [[TMP15]], align 4
-; CHECK-NEXT: [[TMP17:%.*]] = bitcast i32 [[TMP16]] to float
-; CHECK-NEXT: [[DOTSROA_0_4_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_0_VEC_INSERT]], float [[TMP17]], i32 1
-; CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; CHECK-NEXT: [[TMP19:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
-; CHECK-NEXT: [[TMP20:%.*]] = inttoptr i64 [[TMP19]] to ptr addrspace(22)
-; CHECK-NEXT: [[TMP21:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP20]], i32 [[TMP18]]
-; CHECK-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP21]], i32 -2
-; CHECK-NEXT: [[TMP23:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP22]], i32 0, i32 0, i64 9
-; CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr addrspace(22) [[TMP23]], align 4
-; CHECK-NEXT: [[TMP25:%.*]] = bitcast i32 [[TMP24]] to float
-; CHECK-NEXT: [[DOTSROA_0_8_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_4_VEC_INSERT]], float [[TMP25]], i32 2
-; CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; CHECK-NEXT: [[TMP27:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
-; CHECK-NEXT: [[TMP28:%.*]] = inttoptr i64 [[TMP27]] to ptr addrspace(22)
-; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP28]], i32 [[TMP26]]
-; CHECK-NEXT: [[TMP30:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP29]], i32 -2
-; CHECK-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP30]], i32 0, i32 0, i64 10
-; CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr addrspace(22) [[TMP31]], align 4
-; CHECK-NEXT: [[TMP33:%.*]] = bitcast i32 [[TMP32]] to float
-; CHECK-NEXT: [[DOTSROA_0_12_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_8_VEC_INSERT]], float [[TMP33]], i32 3
+; CHECK-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP0]], 0, 0
+; CHECK-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP0]], 1, 0
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; CHECK-NEXT: [[TMP2:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr addrspace(22)
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP3]], i32 [[TMP1]]
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP4]], i32 -2
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspace(22) [[TMP5]], i32 0, i32 0, i32 7
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(22) [[TMP6]], align 4
+; CHECK-NEXT: [[TMP8:%.*]] = bitcast i32 [[TMP7]] to float
+; CHECK-NEXT: [[DOTSROA_0_0_VEC_INSERT:%.*]] = insertelement <4 x float> undef, float [[TMP8]], i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; CHECK-NEXT: [[TMP10:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr addrspace(22)
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP11]], i32 [[TMP9]]
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP12]], i32 -2
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP13]], i32 0, i32 0, i64 8
+; CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(22) [[TMP14]], align 4
+; CHECK-NEXT: [[TMP16:%.*]] = bitcast i32 [[TMP15]] to float
+; CHECK-NEXT: [[DOTSROA_0_4_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_0_VEC_INSERT]], float [[TMP16]], i32 1
+; CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; CHECK-NEXT: [[TMP18:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to ptr addrspace(22)
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP19]], i32 [[TMP17]]
+; CHECK-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP20]], i32 -2
+; CHECK-NEXT: [[TMP22:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP21]], i32 0, i32 0, i64 9
+; CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr addrspace(22) [[TMP22]], align 4
+; CHECK-NEXT: [[TMP24:%.*]] = bitcast i32 [[TMP23]] to float
+; CHECK-NEXT: [[DOTSROA_0_8_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_4_VEC_INSERT]], float [[TMP24]], i32 2
+; CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; CHECK-NEXT: [[TMP26:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; CHECK-NEXT: [[TMP27:%.*]] = inttoptr i64 [[TMP26]] to ptr addrspace(22)
+; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP27]], i32 [[TMP25]]
+; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP28]], i32 -2
+; CHECK-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP29]], i32 0, i32 0, i64 10
+; CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(22) [[TMP30]], align 4
+; CHECK-NEXT: [[TMP32:%.*]] = bitcast i32 [[TMP31]] to float
+; CHECK-NEXT: [[DOTSROA_0_12_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_8_VEC_INSERT]], float [[TMP32]], i32 3
; CHECK-NEXT: [[VAL_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] poison, <2 x float> [[DOTFCA_1_0_EXTRACT]], 0
; CHECK-NEXT: [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[VAL_I_FCA_0_INSERT]], 0
; CHECK-NEXT: [[DOTSROA_06_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT]], i32 0
-; CHECK-NEXT: [[TMP34:%.*]] = bitcast float [[DOTSROA_06_0_VEC_EXTRACT]] to i32
-; CHECK-NEXT: [[TMP35:%.*]] = bitcast i32 [[TMP34]] to float
-; CHECK-NEXT: [[HITATTRS_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x float> undef, float [[TMP35]], i32 0
+; CHECK-NEXT: [[TMP33:%.*]] = bitcast float [[DOTSROA_06_0_VEC_EXTRACT]] to i32
+; CHECK-NEXT: [[TMP34:%.*]] = bitcast i32 [[TMP33]] to float
+; CHECK-NEXT: [[HITATTRS_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x float> undef, float [[TMP34]], i32 0
; CHECK-NEXT: [[DOTSROA_06_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT]], i32 1
-; CHECK-NEXT: [[TMP36:%.*]] = bitcast float [[DOTSROA_06_4_VEC_EXTRACT]] to i32
-; CHECK-NEXT: [[TMP37:%.*]] = bitcast i32 [[TMP36]] to float
-; CHECK-NEXT: [[HITATTRS_SROA_0_4_VEC_INSERT:%.*]] = insertelement <2 x float> [[HITATTRS_SROA_0_0_VEC_INSERT]], float [[TMP37]], i32 1
-; CHECK-NEXT: [[TMP38:%.*]] = extractelement <2 x float> [[HITATTRS_SROA_0_4_VEC_INSERT]], i32 0
-; CHECK-NEXT: [[TMP39:%.*]] = fsub fast float 1.000000e+00, [[TMP38]]
-; CHECK-NEXT: [[TMP40:%.*]] = extractelement <2 x float> [[HITATTRS_SROA_0_4_VEC_INSERT]], i32 1
-; CHECK-NEXT: [[TMP41:%.*]] = fsub fast float [[TMP39]], [[TMP40]]
-; CHECK-NEXT: [[TMP42:%.*]] = insertelement <4 x float> undef, float [[TMP41]], i64 0
-; CHECK-NEXT: [[TMP43:%.*]] = insertelement <4 x float> [[TMP42]], float [[TMP38]], i64 1
-; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x float> [[TMP43]], float [[TMP40]], i64 2
-; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x float> [[TMP44]], float 1.000000e+00, i64 3
-; CHECK-NEXT: [[DOTSROA_0_0_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[TMP45]], i32 0
-; CHECK-NEXT: [[TMP46:%.*]] = bitcast float [[DOTSROA_0_0_VEC_EXTRACT]] to i32
-; CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; CHECK-NEXT: [[TMP48:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
-; CHECK-NEXT: [[TMP49:%.*]] = inttoptr i64 [[TMP48]] to ptr addrspace(22)
-; CHECK-NEXT: [[TMP50:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP49]], i32 [[TMP47]]
-; CHECK-NEXT: [[TMP51:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP50]], i32 -2
-; CHECK-NEXT: [[TMP52:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspace(22) [[TMP51]], i32 0, i32 0, i32 7
-; CHECK-NEXT: store i32 [[TMP46]], ptr addrspace(22) [[TMP52]], align 4
-; CHECK-NEXT: [[DOTSROA_0_4_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[TMP45]], i32 1
-; CHECK-NEXT: [[TMP53:%.*]] = bitcast float [[DOTSROA_0_4_VEC_EXTRACT]] to i32
-; CHECK-NEXT: [[TMP54:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; CHECK-NEXT: [[TMP55:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
-; CHECK-NEXT: [[TMP56:%.*]] = inttoptr i64 [[TMP55]] to ptr addrspace(22)
-; CHECK-NEXT: [[TMP57:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP56]], i32 [[TMP54]]
-; CHECK-NEXT: [[TMP58:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP57]], i32 -2
-; CHECK-NEXT: [[TMP59:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP58]], i32 0, i32 0, i64 8
-; CHECK-NEXT: store i32 [[TMP53]], ptr addrspace(22) [[TMP59]], align 4
-; CHECK-NEXT: [[DOTSROA_0_8_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[TMP45]], i32 2
-; CHECK-NEXT: [[TMP60:%.*]] = bitcast float [[DOTSROA_0_8_VEC_EXTRACT]] to i32
-; CHECK-NEXT: [[TMP61:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; CHECK-NEXT: [[TMP62:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
-; CHECK-NEXT: [[TMP63:%.*]] = inttoptr i64 [[TMP62]] to ptr addrspace(22)
-; CHECK-NEXT: [[TMP64:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP63]], i32 [[TMP61]]
-; CHECK-NEXT: [[TMP65:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP64]], i32 -2
-; CHECK-NEXT: [[TMP66:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP65]], i32 0, i32 0, i64 9
-; CHECK-NEXT: store i32 [[TMP60]], ptr addrspace(22) [[TMP66]], align 4
-; CHECK-NEXT: [[DOTSROA_0_12_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[TMP45]], i32 3
-; CHECK-NEXT: [[TMP67:%.*]] = bitcast float [[DOTSROA_0_12_VEC_EXTRACT]] to i32
-; CHECK-NEXT: [[TMP68:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; CHECK-NEXT: [[TMP69:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
-; CHECK-NEXT: [[TMP70:%.*]] = inttoptr i64 [[TMP69]] to ptr addrspace(22)
-; CHECK-NEXT: [[TMP71:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP70]], i32 [[TMP68]]
-; CHECK-NEXT: [[TMP72:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP71]], i32 -2
-; CHECK-NEXT: [[TMP73:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP72]], i32 0, i32 0, i64 10
-; CHECK-NEXT: store i32 [[TMP67]], ptr addrspace(22) [[TMP73]], align 4
+; CHECK-NEXT: [[TMP35:%.*]] = bitcast float [[DOTSROA_06_4_VEC_EXTRACT]] to i32
+; CHECK-NEXT: [[TMP36:%.*]] = bitcast i32 [[TMP35]] to float
+; CHECK-NEXT: [[HITATTRS_SROA_0_4_VEC_INSERT:%.*]] = insertelement <2 x float> [[HITATTRS_SROA_0_0_VEC_INSERT]], float [[TMP36]], i32 1
+; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; CHECK-NEXT: [[TMP37:%.*]] = extractelement <2 x float> [[HITATTRS_SROA_0_4_VEC_INSERT]], i32 0
+; CHECK-NEXT: [[TMP38:%.*]] = fsub fast float 1.000000e+00, [[TMP37]]
+; CHECK-NEXT: [[TMP39:%.*]] = extractelement <2 x float> [[HITATTRS_SROA_0_4_VEC_INSERT]], i32 1
+; CHECK-NEXT: [[TMP40:%.*]] = fsub fast float [[TMP38]], [[TMP39]]
+; CHECK-NEXT: [[TMP41:%.*]] = insertelement <4 x float> undef, float [[TMP40]], i64 0
+; CHECK-NEXT: [[TMP42:%.*]] = insertelement <4 x float> [[TMP41]], float [[TMP37]], i64 1
+; CHECK-NEXT: [[TMP43:%.*]] = insertelement <4 x float> [[TMP42]], float [[TMP39]], i64 2
+; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x float> [[TMP43]], float 1.000000e+00, i64 3
+; CHECK-NEXT: [[DOTSROA_0_0_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[TMP44]], i32 0
+; CHECK-NEXT: [[TMP45:%.*]] = bitcast float [[DOTSROA_0_0_VEC_EXTRACT]] to i32
+; CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; CHECK-NEXT: [[TMP47:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; CHECK-NEXT: [[TMP48:%.*]] = inttoptr i64 [[TMP47]] to ptr addrspace(22)
+; CHECK-NEXT: [[TMP49:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP48]], i32 [[TMP46]]
+; CHECK-NEXT: [[TMP50:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP49]], i32 -2
+; CHECK-NEXT: [[TMP51:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspace(22) [[TMP50]], i32 0, i32 0, i32 7
+; CHECK-NEXT: store i32 [[TMP45]], ptr addrspace(22) [[TMP51]], align 4
+; CHECK-NEXT: [[DOTSROA_0_4_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[TMP44]], i32 1
+; CHECK-NEXT: [[TMP52:%.*]] = bitcast float [[DOTSROA_0_4_VEC_EXTRACT]] to i32
+; CHECK-NEXT: [[TMP53:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; CHECK-NEXT: [[TMP54:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; CHECK-NEXT: [[TMP55:%.*]] = inttoptr i64 [[TMP54]] to ptr addrspace(22)
+; CHECK-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP55]], i32 [[TMP53]]
+; CHECK-NEXT: [[TMP57:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP56]], i32 -2
+; CHECK-NEXT: [[TMP58:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP57]], i32 0, i32 0, i64 8
+; CHECK-NEXT: store i32 [[TMP52]], ptr addrspace(22) [[TMP58]], align 4
+; CHECK-NEXT: [[DOTSROA_0_8_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[TMP44]], i32 2
+; CHECK-NEXT: [[TMP59:%.*]] = bitcast float [[DOTSROA_0_8_VEC_EXTRACT]] to i32
+; CHECK-NEXT: [[TMP60:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; CHECK-NEXT: [[TMP61:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; CHECK-NEXT: [[TMP62:%.*]] = inttoptr i64 [[TMP61]] to ptr addrspace(22)
+; CHECK-NEXT: [[TMP63:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP62]], i32 [[TMP60]]
+; CHECK-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP63]], i32 -2
+; CHECK-NEXT: [[TMP65:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP64]], i32 0, i32 0, i64 9
+; CHECK-NEXT: store i32 [[TMP59]], ptr addrspace(22) [[TMP65]], align 4
+; CHECK-NEXT: [[DOTSROA_0_12_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[TMP44]], i32 3
+; CHECK-NEXT: [[TMP66:%.*]] = bitcast float [[DOTSROA_0_12_VEC_EXTRACT]] to i32
+; CHECK-NEXT: [[TMP67:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; CHECK-NEXT: [[TMP68:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; CHECK-NEXT: [[TMP69:%.*]] = inttoptr i64 [[TMP68]] to ptr addrspace(22)
+; CHECK-NEXT: [[TMP70:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP69]], i32 [[TMP67]]
+; CHECK-NEXT: [[TMP71:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP70]], i32 -2
+; CHECK-NEXT: [[TMP72:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP71]], i32 0, i32 0, i64 10
+; CHECK-NEXT: store i32 [[TMP66]], ptr addrspace(22) [[TMP72]], align 4
; CHECK-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA:%.*]] poison, <3 x i32> [[DOTFCA_0_0_EXTRACT]], 0
-; CHECK-NEXT: [[TMP74:%.*]] = load i32, ptr [[CSP]], align 4
-; CHECK-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP74]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount !8
+; CHECK-NEXT: [[TMP73:%.*]] = load i32, ptr [[CSP]], align 4
+; CHECK-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP73]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META8]]
; CHECK-NEXT: unreachable
;
diff --git a/shared/continuations/test/dx/intrinsics/cont-payload-registers-get-i32.ll b/shared/continuations/test/dx/intrinsics/cont-payload-registers-get-i32.ll
index 1ab6008549..9170a0749c 100644
--- a/shared/continuations/test/dx/intrinsics/cont-payload-registers-get-i32.ll
+++ b/shared/continuations/test/dx/intrinsics/cont-payload-registers-get-i32.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function main --version 2
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function main --version 3
; RUN: opt --verify-each -passes='dxil-cont-intrinsic-prepare,lint,dxil-cont-lgc-rt-op-converter,lint,inline,lint,lower-raytracing-pipeline,lint,sroa,lint,lower-await,lint,coro-early,dxil-coro-split,coro-cleanup,lint,legacy-cleanup-continuations,lint,register-buffer,lint,save-continuation-state,lint,dxil-cont-post-process,lint,remove-types-metadata' -S %s 2> %t.stderr | FileCheck %s
; RUN: count 0 < %t.stderr
@@ -20,21 +20,14 @@ declare !types !11 %struct.BuiltInTriangleIntersectionAttributes @_cont_GetTrian
declare !types !12 i32 @_cont_HitKind(%struct.DispatchSystemData*, %struct.HitData*)
define void @main() {
-; CHECK-LABEL: define void @main() !continuation !11 !lgc.rt.shaderstage !5 !continuation.entry !12 !continuation.registercount !5 !continuation.state !5 {
+; CHECK-LABEL: define void @main(
+; CHECK-SAME: ) !continuation [[META11:![0-9]+]] !lgc.rt.shaderstage [[META5:![0-9]+]] !continuation.entry [[META12:![0-9]+]] !continuation.registercount [[META5]] !continuation.state [[META5]] {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
-; CHECK-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
-; CHECK-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
-; CHECK-NEXT: [[TMP0:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @_cont_SetupRayGen()
-; CHECK-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA]], align 4
-; CHECK-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
-; CHECK-NEXT: [[DOTFCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; CHECK-NEXT: store i32 [[DOTFCA_0_EXTRACT]], ptr [[DOTFCA_0_GEP]], align 4
-; CHECK-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
-; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(20) getelementptr inbounds ([30 x i32], ptr addrspace(20) @REGISTERS, i32 0, i32 5), align 4
-; CHECK-NEXT: store i32 [[TMP2]], ptr @debug_global, align 4
+; CHECK-NEXT: [[SYSTEM_DATA:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA:%.*]] @_cont_SetupRayGen()
+; CHECK-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[SYSTEM_DATA]], 0
+; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(20) getelementptr inbounds ([30 x i32], ptr addrspace(20) @REGISTERS, i32 0, i32 5), align 4
+; CHECK-NEXT: store i32 [[TMP0]], ptr @debug_global, align 4
; CHECK-NEXT: call void @continuation.complete()
; CHECK-NEXT: unreachable
;
diff --git a/shared/continuations/test/dx/intrinsics/cont-payload-registers-i32-count.ll b/shared/continuations/test/dx/intrinsics/cont-payload-registers-i32-count.ll
index d08b814171..4ac94794d8 100644
--- a/shared/continuations/test/dx/intrinsics/cont-payload-registers-i32-count.ll
+++ b/shared/continuations/test/dx/intrinsics/cont-payload-registers-i32-count.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
; RUN: grep -v continuation.minPayloadRegisterCount %s | opt --verify-each -passes='dxil-cont-intrinsic-prepare,lint,dxil-cont-lgc-rt-op-converter,lint,inline,lint,lower-raytracing-pipeline,lint,sroa,lint,lower-await,lint,coro-early,dxil-coro-split,coro-cleanup,lint,legacy-cleanup-continuations,lint,register-buffer,lint,save-continuation-state,lint,dxil-cont-post-process,lint,remove-types-metadata' -S 2> %t0.stderr | FileCheck -check-prefix=NOMINCOUNT %s
; RUN: count 0 < %t0.stderr
; RUN: cat %s | opt --verify-each -passes='dxil-cont-intrinsic-prepare,lint,dxil-cont-lgc-rt-op-converter,lint,inline,lint,lower-raytracing-pipeline,lint,sroa,lint,lower-await,lint,coro-early,dxil-coro-split,coro-cleanup,lint,legacy-cleanup-continuations,lint,register-buffer,lint,save-continuation-state,lint,dxil-cont-post-process,lint,remove-types-metadata' -S 2> %t1.stderr | FileCheck -check-prefix=MINCOUNT %s
@@ -15,36 +15,22 @@ declare %struct.DispatchSystemData @_cont_SetupRayGen()
declare !types !9 i32 @_cont_GetLocalRootIndex(%struct.DispatchSystemData*)
define void @main() {
-; NOMINCOUNT-LABEL: define void @main() !continuation !9 !lgc.rt.shaderstage !5 !continuation.entry !10 !continuation.registercount !5 !continuation.state !5 {
+; NOMINCOUNT-LABEL: define void @main(
+; NOMINCOUNT-SAME: ) !continuation [[META9:![0-9]+]] !lgc.rt.shaderstage [[META5:![0-9]+]] !continuation.entry [[META10:![0-9]+]] !continuation.registercount [[META5]] !continuation.state [[META5]] {
; NOMINCOUNT-NEXT: entry:
-; NOMINCOUNT-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
-; NOMINCOUNT-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
-; NOMINCOUNT-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
-; NOMINCOUNT-NEXT: [[TMP0:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @_cont_SetupRayGen()
-; NOMINCOUNT-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
-; NOMINCOUNT-NEXT: [[TMP1:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA]], align 4
-; NOMINCOUNT-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
-; NOMINCOUNT-NEXT: [[DOTFCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; NOMINCOUNT-NEXT: store i32 [[DOTFCA_0_EXTRACT]], ptr [[DOTFCA_0_GEP]], align 4
-; NOMINCOUNT-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
-; NOMINCOUNT-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
+; NOMINCOUNT-NEXT: [[SYSTEM_DATA:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA:%.*]] @_cont_SetupRayGen()
+; NOMINCOUNT-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[SYSTEM_DATA]], 0
+; NOMINCOUNT-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; NOMINCOUNT-NEXT: store i32 15, ptr @debug_global, align 4
; NOMINCOUNT-NEXT: call void @continuation.complete()
; NOMINCOUNT-NEXT: unreachable
;
-; MINCOUNT-LABEL: define void @main() !continuation !10 !lgc.rt.shaderstage !5 !continuation.entry !11 !continuation.registercount !5 !continuation.state !5 {
+; MINCOUNT-LABEL: define void @main(
+; MINCOUNT-SAME: ) !continuation [[META10:![0-9]+]] !lgc.rt.shaderstage [[META5:![0-9]+]] !continuation.entry [[META11:![0-9]+]] !continuation.registercount [[META5]] !continuation.state [[META5]] {
; MINCOUNT-NEXT: entry:
-; MINCOUNT-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
-; MINCOUNT-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
-; MINCOUNT-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
-; MINCOUNT-NEXT: [[TMP0:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @_cont_SetupRayGen()
-; MINCOUNT-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
-; MINCOUNT-NEXT: [[TMP1:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA]], align 4
-; MINCOUNT-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
-; MINCOUNT-NEXT: [[DOTFCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; MINCOUNT-NEXT: store i32 [[DOTFCA_0_EXTRACT]], ptr [[DOTFCA_0_GEP]], align 4
-; MINCOUNT-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
-; MINCOUNT-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
+; MINCOUNT-NEXT: [[SYSTEM_DATA:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA:%.*]] @_cont_SetupRayGen()
+; MINCOUNT-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[SYSTEM_DATA]], 0
+; MINCOUNT-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; MINCOUNT-NEXT: store i32 11, ptr @debug_global, align 4
; MINCOUNT-NEXT: call void @continuation.complete()
; MINCOUNT-NEXT: unreachable
diff --git a/shared/continuations/test/dx/intrinsics/cont-payload-registers-set-i32.ll b/shared/continuations/test/dx/intrinsics/cont-payload-registers-set-i32.ll
index adbe62c135..b4c5357a97 100644
--- a/shared/continuations/test/dx/intrinsics/cont-payload-registers-set-i32.ll
+++ b/shared/continuations/test/dx/intrinsics/cont-payload-registers-set-i32.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function main --version 2
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function main --version 3
; RUN: opt --verify-each -passes='dxil-cont-intrinsic-prepare,lint,dxil-cont-lgc-rt-op-converter,lint,inline,lint,lower-raytracing-pipeline,lint,sroa,lint,lower-await,lint,coro-early,dxil-coro-split,coro-cleanup,lint,legacy-cleanup-continuations,lint,register-buffer,lint,save-continuation-state,lint,dxil-cont-post-process,lint,remove-types-metadata' -S %s 2> %t.stderr | FileCheck %s
; RUN: count 0 < %t.stderr
@@ -18,19 +18,12 @@ declare !types !11 %struct.BuiltInTriangleIntersectionAttributes @_cont_GetTrian
declare !types !12 i32 @_cont_HitKind(%struct.DispatchSystemData*, %struct.HitData*)
define void @main() {
-; CHECK-LABEL: define void @main() !continuation !11 !lgc.rt.shaderstage !5 !continuation.entry !12 !continuation.registercount !5 !continuation.state !5 {
+; CHECK-LABEL: define void @main(
+; CHECK-SAME: ) !continuation [[META11:![0-9]+]] !lgc.rt.shaderstage [[META5:![0-9]+]] !continuation.entry [[META12:![0-9]+]] !continuation.registercount [[META5]] !continuation.state [[META5]] {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
-; CHECK-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
-; CHECK-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
-; CHECK-NEXT: [[TMP0:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @_cont_SetupRayGen()
-; CHECK-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA]], align 4
-; CHECK-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
-; CHECK-NEXT: [[DOTFCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; CHECK-NEXT: store i32 [[DOTFCA_0_EXTRACT]], ptr [[DOTFCA_0_GEP]], align 4
-; CHECK-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
-; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
+; CHECK-NEXT: [[SYSTEM_DATA:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA:%.*]] @_cont_SetupRayGen()
+; CHECK-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[SYSTEM_DATA]], 0
+; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; CHECK-NEXT: store i32 42, ptr addrspace(20) getelementptr inbounds ([30 x i32], ptr addrspace(20) @REGISTERS, i32 0, i32 5), align 4
; CHECK-NEXT: call void @continuation.complete()
; CHECK-NEXT: unreachable
diff --git a/shared/continuations/test/dx/intrinsics/cont-stack-alloc.ll b/shared/continuations/test/dx/intrinsics/cont-stack-alloc.ll
index d8924d9f5b..0cee6f236f 100644
--- a/shared/continuations/test/dx/intrinsics/cont-stack-alloc.ll
+++ b/shared/continuations/test/dx/intrinsics/cont-stack-alloc.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function main --version 2
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function main --version 3
; RUN: opt --verify-each -passes='cgscc(inline),lint,lower-raytracing-pipeline,lint,sroa,lint,lower-await,lint,coro-early,dxil-coro-split,coro-cleanup,lint,legacy-cleanup-continuations,lint,register-buffer,lint,save-continuation-state,lint,dxil-cont-post-process,lint,remove-types-metadata' -S %s 2> %t.stderr | FileCheck %s
; RUN: count 0 < %t.stderr
@@ -18,24 +18,16 @@ declare !types !12 i32 @_cont_HitKind(%struct.DispatchSystemData*, %struct.HitDa
@debug_global = external global i32
define void @main() !lgc.rt.shaderstage !17 {
-; CHECK-LABEL: define void @main() !lgc.rt.shaderstage !5 !continuation.entry !11 !continuation.registercount !5 !continuation !12 !continuation.state !5 !continuation.stacksize !13 {
+; CHECK-LABEL: define void @main(
+; CHECK-SAME: ) !lgc.rt.shaderstage [[META5:![0-9]+]] !continuation.entry [[META11:![0-9]+]] !continuation.registercount [[META5]] !continuation [[META12:![0-9]+]] !continuation.state [[META5]] !continuation.stacksize [[META13:![0-9]+]] {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
-; CHECK-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
-; CHECK-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
-; CHECK-NEXT: [[TMP0:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @_cont_SetupRayGen()
-; CHECK-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA]], align 4
-; CHECK-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
-; CHECK-NEXT: [[DOTFCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; CHECK-NEXT: store i32 [[DOTFCA_0_EXTRACT]], ptr [[DOTFCA_0_GEP]], align 4
-; CHECK-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
-; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
+; CHECK-NEXT: [[SYSTEM_DATA:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA:%.*]] @_cont_SetupRayGen()
+; CHECK-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[SYSTEM_DATA]], 0
; CHECK-NEXT: [[PL_BYTES:%.*]] = mul i32 30, 4
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @debug_global, align 4
-; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], 120
-; CHECK-NEXT: store i32 [[TMP3]], ptr @debug_global, align 4
-; CHECK-NEXT: store i32 [[TMP2]], ptr @debug_global, align 4
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @debug_global, align 4
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 120
+; CHECK-NEXT: store i32 [[TMP1]], ptr @debug_global, align 4
+; CHECK-NEXT: store i32 [[TMP0]], ptr @debug_global, align 4
; CHECK-NEXT: call void @continuation.complete()
; CHECK-NEXT: unreachable
;
diff --git a/shared/continuations/test/dx/intrinsics/continuation-stack-is-global-false.ll b/shared/continuations/test/dx/intrinsics/continuation-stack-is-global-false.ll
index b7625111be..9c47ed0d7f 100644
--- a/shared/continuations/test/dx/intrinsics/continuation-stack-is-global-false.ll
+++ b/shared/continuations/test/dx/intrinsics/continuation-stack-is-global-false.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
; RUN: opt --verify-each -passes='dxil-cont-lgc-rt-op-converter,lint,dxil-cont-intrinsic-prepare,lint' -S %s 2> %t.stderr | FileCheck %s
; RUN: count 0 < %t.stderr
@@ -13,8 +13,11 @@ declare %struct.DispatchSystemData @_cont_SetupRayGen()
declare !types !8 i32 @_cont_GetLocalRootIndex(%struct.DispatchSystemData*)
define void @main() {
-; CHECK-LABEL: define void @main() !lgc.rt.shaderstage !5 {
+; CHECK-LABEL: define void @main(
+; CHECK-SAME: ) !lgc.rt.shaderstage [[META5:![0-9]+]] {
; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = call i32 @lgc.rt.shader.index()
+; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[TMP0]])
; CHECK-NEXT: store i1 false, ptr @debug_global, align 1
; CHECK-NEXT: ret void
;
diff --git a/shared/continuations/test/dx/intrinsics/continuation-stack-is-global-true.ll b/shared/continuations/test/dx/intrinsics/continuation-stack-is-global-true.ll
index 1bd1dae523..cb440e7b9a 100644
--- a/shared/continuations/test/dx/intrinsics/continuation-stack-is-global-true.ll
+++ b/shared/continuations/test/dx/intrinsics/continuation-stack-is-global-true.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
; RUN: opt --verify-each -passes='dxil-cont-lgc-rt-op-converter,lint,dxil-cont-intrinsic-prepare,lint' -S %s 2> %t.stderr | FileCheck %s
; RUN: count 0 < %t.stderr
@@ -13,8 +13,11 @@ declare %struct.DispatchSystemData @_cont_SetupRayGen()
declare !types !8 i32 @_cont_GetLocalRootIndex(%struct.DispatchSystemData*)
define void @main() {
-; CHECK-LABEL: define void @main() !lgc.rt.shaderstage !5 {
+; CHECK-LABEL: define void @main(
+; CHECK-SAME: ) !lgc.rt.shaderstage [[META5:![0-9]+]] {
; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = call i32 @lgc.rt.shader.index()
+; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[TMP0]])
; CHECK-NEXT: store i1 true, ptr @debug_global, align 1
; CHECK-NEXT: ret void
;
diff --git a/shared/continuations/test/dx/intrinsics/get-flags.ll b/shared/continuations/test/dx/intrinsics/get-flags.ll
index 22f40f57ae..e442c896be 100644
--- a/shared/continuations/test/dx/intrinsics/get-flags.ll
+++ b/shared/continuations/test/dx/intrinsics/get-flags.ll
@@ -7,7 +7,8 @@ declare i32 @_AmdContinuationsGetFlags()
@debug_global = external global i32
define void @main() !lgc.rt.shaderstage !1 {
-; CHECK-LABEL: define void @main() !lgc.rt.shaderstage !1 {
+; CHECK-LABEL: define void @main(
+; CHECK-SAME: ) !lgc.rt.shaderstage [[META1:![0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: store i32 3, ptr @debug_global, align 4
; CHECK-NEXT: ret void
diff --git a/shared/continuations/test/dx/intrinsics/get-rtip.ll b/shared/continuations/test/dx/intrinsics/get-rtip.ll
index b904103831..0ddfdcebe7 100644
--- a/shared/continuations/test/dx/intrinsics/get-rtip.ll
+++ b/shared/continuations/test/dx/intrinsics/get-rtip.ll
@@ -11,7 +11,8 @@ declare !types !8 i32 @_cont_GetLocalRootIndex(%struct.DispatchSystemData*)
@debug_global = external global i32
define void @main() !lgc.rt.shaderstage !1 {
-; CHECK-LABEL: define void @main() !lgc.rt.shaderstage !3 {
+; CHECK-LABEL: define void @main(
+; CHECK-SAME: ) !lgc.rt.shaderstage [[META3:![0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: store i32 2, ptr @debug_global, align 4
; CHECK-NEXT: ret void
diff --git a/shared/continuations/test/dx/intrinsics/get-shader-kind.ll b/shared/continuations/test/dx/intrinsics/get-shader-kind.ll
index 95f52539fa..c8d2d803b0 100644
--- a/shared/continuations/test/dx/intrinsics/get-shader-kind.ll
+++ b/shared/continuations/test/dx/intrinsics/get-shader-kind.ll
@@ -32,14 +32,13 @@ define void @MyMiss(%struct.Payload* %payload) !types !1 !lgc.rt.shaderstage !16
; CHECK-SAME: ([[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !types [[META12:![0-9]+]] !lgc.rt.shaderstage [[META14:![0-9]+]] !continuation.registercount [[META15:![0-9]+]] !continuation [[META16:![0-9]+]] {
; CHECK-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = alloca [[STRUCT_PAYLOAD:%.*]], align 8
-; CHECK-NEXT: [[TMP3:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; CHECK-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP3]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; CHECK-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
-; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
+; CHECK-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_PAYLOAD]], ptr [[TMP2]], i32 0, i32 0
; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr @PAYLOAD, align 4
; CHECK-NEXT: store i32 [[TMP5]], ptr [[TMP4]], align 4
; CHECK-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
+; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[TMP3]])
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_PAYLOAD]], ptr [[TMP2]], i32 0, i32 0
; CHECK-NEXT: store i32 11, ptr [[TMP6]], align 4
; CHECK-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
diff --git a/shared/continuations/test/dx/intrinsics/shader-index.ll b/shared/continuations/test/dx/intrinsics/shader-index.ll
index 3819766269..526dc160ac 100644
--- a/shared/continuations/test/dx/intrinsics/shader-index.ll
+++ b/shared/continuations/test/dx/intrinsics/shader-index.ll
@@ -19,13 +19,11 @@ define i1 @_cont_ReportHit(%struct.DispatchSystemData* %data, float %t, i32 %hit
define void @main() !lgc.rt.shaderstage !24 {
; CHECK-LABEL: define void @main(
-; CHECK-SAME: {} [[CONT_STATE:%.*]], i32 [[RETURN_ADDR:%.*]], i32 [[SHADER_INDEX:%.*]]) !lgc.rt.shaderstage [[META13:![0-9]+]] !lgc.cps [[META13]] !continuation [[META14:![0-9]+]] {
+; CHECK-SAME: {} [[CONT_STATE:%.*]], i32 [[RETURN_ADDR:%.*]], i32 [[SHADER_INDEX:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage [[META13:![0-9]+]] !lgc.cps [[META13]] !continuation [[META14:![0-9]+]] {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
-; CHECK-NEXT: [[TMP0:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
+; CHECK-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
; CHECK-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; CHECK-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
-; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
+; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; CHECK-NEXT: store i32 0, ptr @debug_global, align 4
; CHECK-NEXT: ret void
;
@@ -41,17 +39,15 @@ define void @callable(%struct.Payload* %payload) !types !22 !lgc.rt.shaderstage
; CHECK-NEXT: entry:
; CHECK-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
; CHECK-NEXT: [[TMP1:%.*]] = alloca [[STRUCT_PAYLOAD:%.*]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; CHECK-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP2]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; CHECK-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
-; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
+; CHECK-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[SHADER_INDEX]])
; CHECK-NEXT: store i32 [[SHADER_INDEX]], ptr @debug_global, align 4
; CHECK-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_PAYLOAD]], ptr [[TMP1]], i32 0, i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-; CHECK-NEXT: store i32 [[TMP4]], ptr @PAYLOAD, align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 2, {} poison, [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP5]])
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_PAYLOAD]], ptr [[TMP1]], i32 0, i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+; CHECK-NEXT: store i32 [[TMP3]], ptr @PAYLOAD, align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 2, {} poison, i32 poison, i32 poison, [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP4]])
; CHECK-NEXT: unreachable
;
entry:
diff --git a/shared/continuations/test/dx/intrinsics/value-i32.ll b/shared/continuations/test/dx/intrinsics/value-i32.ll
index 9b82e871da..c5686d6fe0 100644
--- a/shared/continuations/test/dx/intrinsics/value-i32.ll
+++ b/shared/continuations/test/dx/intrinsics/value-i32.ll
@@ -12,7 +12,7 @@ declare !types !3 void @_AmdValueSetI32(%struct.Payload*, i32, i32)
define i32 @count(%struct.Payload* %pl) !types !0 {
; CHECK-LABEL: define i32 @count
-; CHECK-SAME: (ptr [[PL:%.*]]) !types !0 {
+; CHECK-SAME: (ptr [[PL:%.*]]) !types [[META0:![0-9]+]] {
; CHECK-NEXT: ret i32 5
;
%val = call i32 @_AmdValueI32Count(%struct.Payload* %pl)
@@ -21,7 +21,7 @@ define i32 @count(%struct.Payload* %pl) !types !0 {
define i32 @get(%struct.Payload* %pl) !types !0 {
; CHECK-LABEL: define i32 @get
-; CHECK-SAME: (ptr [[PL:%.*]]) !types !0 {
+; CHECK-SAME: (ptr [[PL:%.*]]) !types [[META0]] {
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[PL]], i32 2
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
; CHECK-NEXT: ret i32 [[TMP2]]
@@ -32,7 +32,7 @@ define i32 @get(%struct.Payload* %pl) !types !0 {
define void @set(%struct.Payload* %pl, i32 %val) !types !4 {
; CHECK-LABEL: define void @set
-; CHECK-SAME: (ptr [[PL:%.*]], i32 [[VAL:%.*]]) !types !2 {
+; CHECK-SAME: (ptr [[PL:%.*]], i32 [[VAL:%.*]]) !types [[META2:![0-9]+]] {
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[PL]], i32 2
; CHECK-NEXT: store i32 [[VAL]], ptr [[TMP1]], align 4
; CHECK-NEXT: ret void
diff --git a/shared/continuations/test/dx/lower-await.ll b/shared/continuations/test/dx/lower-await.ll
index 23f44b23d4..1ac4fe9abd 100644
--- a/shared/continuations/test/dx/lower-await.ll
+++ b/shared/continuations/test/dx/lower-await.ll
@@ -18,46 +18,40 @@ declare %continuation.token* @async_fun_with_arg(i32)
define void @simple_await() !continuation.registercount !1 {
; AWAIT-LABEL: define { ptr, ptr } @simple_await(
-; AWAIT-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], ptr [[TMP0:%.*]]) !continuation.registercount !1 !continuation !2 {
+; AWAIT-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], ptr [[TMP0:%.*]]) !continuation.registercount [[META1:![0-9]+]] !continuation [[META2:![0-9]+]] {
; AWAIT-NEXT: [[TMP2:%.*]] = call token @llvm.coro.id.retcon(i32 8, i32 4, ptr [[TMP0]], ptr @continuation.prototype.simple_await, ptr @continuation.malloc, ptr @continuation.free)
; AWAIT-NEXT: [[TMP3:%.*]] = call ptr @llvm.coro.begin(token [[TMP2]], ptr null)
-; AWAIT-NEXT: [[TOK:%.*]] = call ptr @async_fun(), !continuation.registercount !1, !continuation.returnedRegistercount !1
+; AWAIT-NEXT: [[TOK:%.*]] = call ptr @async_fun(), !continuation.registercount [[META1]], !continuation.returnedRegistercount !1
; AWAIT-NEXT: [[TMP4:%.*]] = call i1 (...) @llvm.coro.suspend.retcon.i1(ptr [[TOK]])
-; AWAIT-NEXT: call void (...) @continuation.return(i64 [[RETURNADDR]]), !continuation.registercount !1
+; AWAIT-NEXT: call void (...) @continuation.return(i64 [[RETURNADDR]]), !continuation.registercount [[META1]]
; AWAIT-NEXT: unreachable
;
; CORO-LABEL: define { ptr, ptr } @simple_await(
-; CORO-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], ptr [[TMP0:%.*]]) !continuation.registercount !1 !continuation !2 {
+; CORO-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], ptr [[TMP0:%.*]]) !continuation.registercount [[META1:![0-9]+]] !continuation [[META2:![0-9]+]] {
; CORO-NEXT: AllocaSpillBB:
; CORO-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME:%.*]], ptr [[TMP0]], i32 0, i32 0
; CORO-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
-; CORO-NEXT: [[TOK:%.*]] = call ptr @async_fun(), !continuation.registercount !1, !continuation.returnedRegistercount !1
+; CORO-NEXT: [[TOK:%.*]] = call ptr @async_fun(), !continuation.registercount [[META1]], !continuation.returnedRegistercount !1
; CORO-NEXT: [[TMP1:%.*]] = insertvalue { ptr, ptr } [[UNDEF_OR_POISON:undef|poison]], ptr @simple_await.resume.0, 0
; CORO-NEXT: [[TMP2:%.*]] = insertvalue { ptr, ptr } [[TMP1]], ptr [[TOK]], 1
; CORO-NEXT: ret { ptr, ptr } [[TMP2]]
;
; CLEANED-LABEL: define void @simple_await(
-; CLEANED-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]]) !continuation.registercount !1 !continuation !2 !continuation.state !3 !continuation.stacksize !3 {
+; CLEANED-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]]) !continuation.registercount [[META1:![0-9]+]] !continuation [[META2:![0-9]+]] !continuation.state [[META3:![0-9]+]] !continuation.stacksize [[META3]] {
; CLEANED-NEXT: AllocaSpillBB:
-; CLEANED-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
-; CLEANED-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANED-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
; CLEANED-NEXT: [[TMP0:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CLEANED-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-; CLEANED-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 8
-; CLEANED-NEXT: store i32 [[TMP2]], ptr [[TMP0]], align 4
-; CLEANED-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
-; CLEANED-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANED-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 0
-; CLEANED-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP4]], align 4
-; CLEANED-NEXT: store i32 [[TMP6]], ptr addrspace(21) [[TMP5]], align 4
-; CLEANED-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CLEANED-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 1
-; CLEANED-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4
-; CLEANED-NEXT: store i32 [[TMP9]], ptr addrspace(21) [[TMP8]], align 4
-; CLEANED-NEXT: [[TMP10:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANED-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-; CLEANED-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP11]], i64 ptrtoint (ptr @simple_await.resume.0 to i64)), !continuation.registercount !1, !continuation.returnedRegistercount !1
+; CLEANED-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
+; CLEANED-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP2]], i64 0
+; CLEANED-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[SIMPLE_AWAIT_FRAME:%.*]], ptr addrspace(21) [[TMP3]], i32 0, i32 0
+; CLEANED-NEXT: store i64 [[RETURNADDR]], ptr addrspace(21) [[RETURNADDR_SPILL_ADDR]], align 4
+; CLEANED-NEXT: [[TMP4:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANED-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+; CLEANED-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 8
+; CLEANED-NEXT: store i32 [[TMP6]], ptr [[TMP4]], align 4
+; CLEANED-NEXT: [[TMP7:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANED-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+; CLEANED-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP8]], i64 ptrtoint (ptr @simple_await.resume.0 to i64)), !continuation.registercount [[META1]], !continuation.returnedRegistercount !1
; CLEANED-NEXT: unreachable
;
%tok = call %continuation.token* @async_fun(), !continuation.registercount !1, !continuation.returnedRegistercount !1
@@ -67,28 +61,28 @@ define void @simple_await() !continuation.registercount !1 {
define void @simple_await_entry() !continuation.entry !0 !continuation.registercount !1 {
; AWAIT-LABEL: define { ptr, ptr } @simple_await_entry(
-; AWAIT-SAME: ptr [[TMP0:%.*]]) !continuation.registercount !1 !continuation.entry !3 !continuation !4 {
+; AWAIT-SAME: ptr [[TMP0:%.*]]) !continuation.registercount [[META1]] !continuation.entry [[META3:![0-9]+]] !continuation [[META4:![0-9]+]] {
; AWAIT-NEXT: [[TMP2:%.*]] = call token @llvm.coro.id.retcon(i32 8, i32 4, ptr [[TMP0]], ptr @continuation.prototype.simple_await_entry, ptr @continuation.malloc, ptr @continuation.free)
; AWAIT-NEXT: [[TMP3:%.*]] = call ptr @llvm.coro.begin(token [[TMP2]], ptr null)
-; AWAIT-NEXT: [[TOK:%.*]] = call ptr @async_fun(), !continuation.registercount !1, !continuation.returnedRegistercount !1
+; AWAIT-NEXT: [[TOK:%.*]] = call ptr @async_fun(), !continuation.registercount [[META1]], !continuation.returnedRegistercount !1
; AWAIT-NEXT: [[TMP4:%.*]] = call i1 (...) @llvm.coro.suspend.retcon.i1(ptr [[TOK]])
; AWAIT-NEXT: call void (...) @continuation.return(i64 [[UNDEF_OR_POISON:undef|poison]])
; AWAIT-NEXT: unreachable
;
; CORO-LABEL: define { ptr, ptr } @simple_await_entry(
-; CORO-SAME: ptr [[TMP0:%.*]]) !continuation.registercount !1 !continuation.entry !3 !continuation !4 {
+; CORO-SAME: ptr [[TMP0:%.*]]) !continuation.registercount [[META1]] !continuation.entry [[META3:![0-9]+]] !continuation [[META4:![0-9]+]] {
; CORO-NEXT: AllocaSpillBB:
-; CORO-NEXT: [[TOK:%.*]] = call ptr @async_fun(), !continuation.registercount !1, !continuation.returnedRegistercount !1
+; CORO-NEXT: [[TOK:%.*]] = call ptr @async_fun(), !continuation.registercount [[META1]], !continuation.returnedRegistercount !1
; CORO-NEXT: [[TMP1:%.*]] = insertvalue { ptr, ptr } [[UNDEF_OR_POISON]], ptr @simple_await_entry.resume.0, 0
; CORO-NEXT: [[TMP2:%.*]] = insertvalue { ptr, ptr } [[TMP1]], ptr [[TOK]], 1
; CORO-NEXT: ret { ptr, ptr } [[TMP2]]
;
-; CLEANED-LABEL: define void @simple_await_entry() !continuation.registercount !1 !continuation.entry !4 !continuation !5 !continuation.state !1 {
+; CLEANED-LABEL: define void @simple_await_entry(
+; CLEANED-SAME: ) !continuation.registercount [[META1]] !continuation.entry [[META4:![0-9]+]] !continuation [[META5:![0-9]+]] !continuation.state [[META1]] {
; CLEANED-NEXT: AllocaSpillBB:
-; CLEANED-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
; CLEANED-NEXT: [[TMP0:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CLEANED-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-; CLEANED-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP1]], i64 ptrtoint (ptr @simple_await_entry.resume.0 to i64)), !continuation.registercount !1, !continuation.returnedRegistercount !1
+; CLEANED-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP1]], i64 ptrtoint (ptr @simple_await_entry.resume.0 to i64)), !continuation.registercount [[META1]], !continuation.returnedRegistercount !1
; CLEANED-NEXT: unreachable
;
%tok = call %continuation.token* @async_fun(), !continuation.registercount !1, !continuation.returnedRegistercount !1
@@ -99,46 +93,40 @@ define void @simple_await_entry() !continuation.entry !0 !continuation.registerc
define void @await_with_arg(i32 %i) !continuation.registercount !1 {
; AWAIT-LABEL: define { ptr, ptr } @await_with_arg(
-; AWAIT-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], i32 [[I:%.*]], ptr [[TMP0:%.*]]) !continuation.registercount !1 !continuation !5 {
+; AWAIT-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], i32 [[I:%.*]], ptr [[TMP0:%.*]]) !continuation.registercount [[META1]] !continuation [[META5:![0-9]+]] {
; AWAIT-NEXT: [[TMP2:%.*]] = call token @llvm.coro.id.retcon(i32 8, i32 4, ptr [[TMP0]], ptr @continuation.prototype.await_with_arg, ptr @continuation.malloc, ptr @continuation.free)
; AWAIT-NEXT: [[TMP3:%.*]] = call ptr @llvm.coro.begin(token [[TMP2]], ptr null)
-; AWAIT-NEXT: [[TOK:%.*]] = call ptr @async_fun_with_arg(i32 [[I]]), !continuation.registercount !1, !continuation.returnedRegistercount !1
+; AWAIT-NEXT: [[TOK:%.*]] = call ptr @async_fun_with_arg(i32 [[I]]), !continuation.registercount [[META1]], !continuation.returnedRegistercount !1
; AWAIT-NEXT: [[TMP4:%.*]] = call i1 (...) @llvm.coro.suspend.retcon.i1(ptr [[TOK]])
-; AWAIT-NEXT: call void (...) @continuation.return(i64 [[RETURNADDR]]), !continuation.registercount !1
+; AWAIT-NEXT: call void (...) @continuation.return(i64 [[RETURNADDR]]), !continuation.registercount [[META1]]
; AWAIT-NEXT: unreachable
;
; CORO-LABEL: define { ptr, ptr } @await_with_arg(
-; CORO-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], i32 [[I:%.*]], ptr [[TMP0:%.*]]) !continuation.registercount !1 !continuation !5 {
+; CORO-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], i32 [[I:%.*]], ptr [[TMP0:%.*]]) !continuation.registercount [[META1]] !continuation [[META5:![0-9]+]] {
; CORO-NEXT: AllocaSpillBB:
-; CORO-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[AWAIT_WITH_ARG_FRAME:%.*]], ptr [[TMP0:%.*]], i32 0, i32 0
-; CORO-NEXT: store i64 [[RETURNADDR:%.*]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
-; CORO-NEXT: [[TOK:%.*]] = call ptr @async_fun_with_arg(i32 [[I:%.*]]), !continuation.registercount !1, !continuation.returnedRegistercount !1
+; CORO-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[AWAIT_WITH_ARG_FRAME:%.*]], ptr [[TMP0]], i32 0, i32 0
+; CORO-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
+; CORO-NEXT: [[TOK:%.*]] = call ptr @async_fun_with_arg(i32 [[I]]), !continuation.registercount [[META1]], !continuation.returnedRegistercount !1
; CORO-NEXT: [[TMP1:%.*]] = insertvalue { ptr, ptr } [[UNDEF_OR_POISON]], ptr @await_with_arg.resume.0, 0
; CORO-NEXT: [[TMP2:%.*]] = insertvalue { ptr, ptr } [[TMP1]], ptr [[TOK]], 1
; CORO-NEXT: ret { ptr, ptr } [[TMP2]]
;
; CLEANED-LABEL: define void @await_with_arg(
-; CLEANED-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], i32 [[I:%.*]]) !continuation.registercount !1 !continuation !6 !continuation.state !3 !continuation.stacksize !3 {
+; CLEANED-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], i32 [[I:%.*]]) !continuation.registercount [[META1]] !continuation [[META6:![0-9]+]] !continuation.state [[META3]] !continuation.stacksize [[META3]] {
; CLEANED-NEXT: AllocaSpillBB:
-; CLEANED-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
-; CLEANED-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[AWAIT_WITH_ARG_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANED-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
; CLEANED-NEXT: [[TMP0:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CLEANED-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-; CLEANED-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 8
-; CLEANED-NEXT: store i32 [[TMP2]], ptr [[TMP0]], align 4
-; CLEANED-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
-; CLEANED-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANED-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 0
-; CLEANED-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP4]], align 4
-; CLEANED-NEXT: store i32 [[TMP6]], ptr addrspace(21) [[TMP5]], align 4
-; CLEANED-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CLEANED-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 1
-; CLEANED-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4
-; CLEANED-NEXT: store i32 [[TMP9]], ptr addrspace(21) [[TMP8]], align 4
-; CLEANED-NEXT: [[TMP10:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANED-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-; CLEANED-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun_with_arg to i64), i32 [[TMP11]], i64 ptrtoint (ptr @await_with_arg.resume.0 to i64), i32 [[I]]), !continuation.registercount !1, !continuation.returnedRegistercount !1
+; CLEANED-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
+; CLEANED-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP2]], i64 0
+; CLEANED-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[AWAIT_WITH_ARG_FRAME:%.*]], ptr addrspace(21) [[TMP3]], i32 0, i32 0
+; CLEANED-NEXT: store i64 [[RETURNADDR]], ptr addrspace(21) [[RETURNADDR_SPILL_ADDR]], align 4
+; CLEANED-NEXT: [[TMP4:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANED-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+; CLEANED-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 8
+; CLEANED-NEXT: store i32 [[TMP6]], ptr [[TMP4]], align 4
+; CLEANED-NEXT: [[TMP7:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANED-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+; CLEANED-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun_with_arg to i64), i32 [[TMP8]], i64 ptrtoint (ptr @await_with_arg.resume.0 to i64), i32 [[I]]), !continuation.registercount [[META1]], !continuation.returnedRegistercount !1
; CLEANED-NEXT: unreachable
;
%tok = call %continuation.token* @async_fun_with_arg(i32 %i), !continuation.registercount !1, !continuation.returnedRegistercount !1
@@ -148,47 +136,41 @@ define void @await_with_arg(i32 %i) !continuation.registercount !1 {
define i32 @await_with_ret_value() !continuation.registercount !1 {
; AWAIT-LABEL: define { ptr, ptr } @await_with_ret_value(
-; AWAIT-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], ptr [[TMP0:%.*]]) !continuation.registercount !1 !continuation !6 {
+; AWAIT-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], ptr [[TMP0:%.*]]) !continuation.registercount [[META1]] !continuation [[META6:![0-9]+]] {
; AWAIT-NEXT: [[TMP2:%.*]] = call token @llvm.coro.id.retcon(i32 8, i32 4, ptr [[TMP0]], ptr @continuation.prototype.await_with_ret_value, ptr @continuation.malloc, ptr @continuation.free)
; AWAIT-NEXT: [[TMP3:%.*]] = call ptr @llvm.coro.begin(token [[TMP2]], ptr null)
-; AWAIT-NEXT: [[TOK:%.*]] = call ptr @async_fun(), !continuation.registercount !1, !continuation.returnedRegistercount !1
+; AWAIT-NEXT: [[TOK:%.*]] = call ptr @async_fun(), !continuation.registercount [[META1]], !continuation.returnedRegistercount !1
; AWAIT-NEXT: [[TMP4:%.*]] = call i1 (...) @llvm.coro.suspend.retcon.i1(ptr [[TOK]])
; AWAIT-NEXT: [[TMP5:%.*]] = call i32 @continuations.getReturnValue.i32()
-; AWAIT-NEXT: call void (...) @continuation.return(i64 [[RETURNADDR]], i32 [[TMP5]]), !continuation.registercount !1
+; AWAIT-NEXT: call void (...) @continuation.return(i64 [[RETURNADDR]], i32 [[TMP5]]), !continuation.registercount [[META1]]
; AWAIT-NEXT: unreachable
;
; CORO-LABEL: define { ptr, ptr } @await_with_ret_value(
-; CORO-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], ptr [[TMP0:%.*]]) !continuation.registercount !1 !continuation !6 {
+; CORO-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], ptr [[TMP0:%.*]]) !continuation.registercount [[META1]] !continuation [[META6:![0-9]+]] {
; CORO-NEXT: AllocaSpillBB:
; CORO-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[AWAIT_WITH_RET_VALUE_FRAME:%.*]], ptr [[TMP0]], i32 0, i32 0
; CORO-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
-; CORO-NEXT: [[TOK:%.*]] = call ptr @async_fun(), !continuation.registercount !1, !continuation.returnedRegistercount !1
+; CORO-NEXT: [[TOK:%.*]] = call ptr @async_fun(), !continuation.registercount [[META1]], !continuation.returnedRegistercount !1
; CORO-NEXT: [[TMP1:%.*]] = insertvalue { ptr, ptr } [[UNDEF_OR_POISON]], ptr @await_with_ret_value.resume.0, 0
; CORO-NEXT: [[TMP2:%.*]] = insertvalue { ptr, ptr } [[TMP1]], ptr [[TOK]], 1
; CORO-NEXT: ret { ptr, ptr } [[TMP2]]
;
; CLEANED-LABEL: define void @await_with_ret_value(
-; CLEANED-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]]) !continuation.registercount !1 !continuation !7 !continuation.state !3 !continuation.stacksize !3 {
+; CLEANED-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]]) !continuation.registercount [[META1]] !continuation [[META7:![0-9]+]] !continuation.state [[META3]] !continuation.stacksize [[META3]] {
; CLEANED-NEXT: AllocaSpillBB:
-; CLEANED-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
-; CLEANED-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[AWAIT_WITH_RET_VALUE_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANED-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
; CLEANED-NEXT: [[TMP0:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CLEANED-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-; CLEANED-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 8
-; CLEANED-NEXT: store i32 [[TMP2]], ptr [[TMP0]], align 4
-; CLEANED-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
-; CLEANED-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANED-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 0
-; CLEANED-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP4]], align 4
-; CLEANED-NEXT: store i32 [[TMP6]], ptr addrspace(21) [[TMP5]], align 4
-; CLEANED-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CLEANED-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 1
-; CLEANED-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4
-; CLEANED-NEXT: store i32 [[TMP9]], ptr addrspace(21) [[TMP8]], align 4
-; CLEANED-NEXT: [[TMP10:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANED-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-; CLEANED-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP11]], i64 ptrtoint (ptr @await_with_ret_value.resume.0 to i64)), !continuation.registercount !1, !continuation.returnedRegistercount !1
+; CLEANED-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
+; CLEANED-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP2]], i64 0
+; CLEANED-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[AWAIT_WITH_RET_VALUE_FRAME:%.*]], ptr addrspace(21) [[TMP3]], i32 0, i32 0
+; CLEANED-NEXT: store i64 [[RETURNADDR]], ptr addrspace(21) [[RETURNADDR_SPILL_ADDR]], align 4
+; CLEANED-NEXT: [[TMP4:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANED-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+; CLEANED-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 8
+; CLEANED-NEXT: store i32 [[TMP6]], ptr [[TMP4]], align 4
+; CLEANED-NEXT: [[TMP7:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANED-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+; CLEANED-NEXT: call void (i64, ...) @continuation.continue(i64 ptrtoint (ptr @async_fun to i64), i32 [[TMP8]], i64 ptrtoint (ptr @await_with_ret_value.resume.0 to i64)), !continuation.registercount [[META1]], !continuation.returnedRegistercount !1
; CLEANED-NEXT: unreachable
;
%tok = call %continuation.token* @async_fun(), !continuation.registercount !1, !continuation.returnedRegistercount !1
@@ -198,46 +180,40 @@ define i32 @await_with_ret_value() !continuation.registercount !1 {
define void @wait_await() !continuation.registercount !1 {
; AWAIT-LABEL: define { ptr, ptr } @wait_await(
-; AWAIT-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], ptr [[TMP0:%.*]]) !continuation.registercount !1 !continuation !7 {
+; AWAIT-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], ptr [[TMP0:%.*]]) !continuation.registercount [[META1]] !continuation [[META7:![0-9]+]] {
; AWAIT-NEXT: [[TMP2:%.*]] = call token @llvm.coro.id.retcon(i32 8, i32 4, ptr [[TMP0]], ptr @continuation.prototype.wait_await, ptr @continuation.malloc, ptr @continuation.free)
; AWAIT-NEXT: [[TMP3:%.*]] = call ptr @llvm.coro.begin(token [[TMP2]], ptr null)
-; AWAIT-NEXT: [[TOK:%.*]] = call ptr @async_fun_with_waitmask(i64 -1), !continuation.registercount !1, !continuation.returnedRegistercount !1, !continuation.wait.await !3
+; AWAIT-NEXT: [[TOK:%.*]] = call ptr @async_fun_with_waitmask(i64 -1), !continuation.registercount [[META1]], !continuation.returnedRegistercount !1, !continuation.wait.await [[META3]]
; AWAIT-NEXT: [[TMP4:%.*]] = call i1 (...) @llvm.coro.suspend.retcon.i1(ptr [[TOK]])
-; AWAIT-NEXT: call void (...) @continuation.return(i64 [[RETURNADDR]]), !continuation.registercount !1
+; AWAIT-NEXT: call void (...) @continuation.return(i64 [[RETURNADDR]]), !continuation.registercount [[META1]]
; AWAIT-NEXT: unreachable
;
; CORO-LABEL: define { ptr, ptr } @wait_await(
-; CORO-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], ptr [[TMP0:%.*]]) !continuation.registercount !1 !continuation !7 {
+; CORO-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], ptr [[TMP0:%.*]]) !continuation.registercount [[META1]] !continuation [[META7:![0-9]+]] {
; CORO-NEXT: AllocaSpillBB:
; CORO-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[WAIT_AWAIT_FRAME:%.*]], ptr [[TMP0]], i32 0, i32 0
; CORO-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
-; CORO-NEXT: [[TOK:%.*]] = call ptr @async_fun_with_waitmask(i64 -1), !continuation.registercount !1, !continuation.returnedRegistercount !1, !continuation.wait.await !3
+; CORO-NEXT: [[TOK:%.*]] = call ptr @async_fun_with_waitmask(i64 -1), !continuation.registercount [[META1]], !continuation.returnedRegistercount !1, !continuation.wait.await [[META3]]
; CORO-NEXT: [[TMP1:%.*]] = insertvalue { ptr, ptr } [[UNDEF_OR_POISON:undef|poison]], ptr @wait_await.resume.0, 0
; CORO-NEXT: [[TMP2:%.*]] = insertvalue { ptr, ptr } [[TMP1]], ptr [[TOK]], 1
; CORO-NEXT: ret { ptr, ptr } [[TMP2]]
;
; CLEANED-LABEL: define void @wait_await(
-; CLEANED-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]]) !continuation.registercount !1 !continuation !8 !continuation.state !3 !continuation.stacksize !3 {
+; CLEANED-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]]) !continuation.registercount [[META1]] !continuation [[META8:![0-9]+]] !continuation.state [[META3]] !continuation.stacksize [[META3]] {
; CLEANED-NEXT: AllocaSpillBB:
-; CLEANED-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
-; CLEANED-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[WAIT_AWAIT_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANED-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
; CLEANED-NEXT: [[TMP0:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CLEANED-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-; CLEANED-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 8
-; CLEANED-NEXT: store i32 [[TMP2]], ptr [[TMP0]], align 4
-; CLEANED-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
-; CLEANED-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANED-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 0
-; CLEANED-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP4]], align 4
-; CLEANED-NEXT: store i32 [[TMP6]], ptr addrspace(21) [[TMP5]], align 4
-; CLEANED-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CLEANED-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP3]], i32 0, i32 1
-; CLEANED-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4
-; CLEANED-NEXT: store i32 [[TMP9]], ptr addrspace(21) [[TMP8]], align 4
-; CLEANED-NEXT: [[TMP10:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANED-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-; CLEANED-NEXT: call void (i64, i64, ...) @continuation.waitContinue(i64 ptrtoint (ptr @async_fun_with_waitmask to i64), i64 -1, i32 [[TMP11]], i64 ptrtoint (ptr @wait_await.resume.0 to i64)), !continuation.registercount !1, !continuation.returnedRegistercount !1
+; CLEANED-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
+; CLEANED-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP2]], i64 0
+; CLEANED-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[WAIT_AWAIT_FRAME:%.*]], ptr addrspace(21) [[TMP3]], i32 0, i32 0
+; CLEANED-NEXT: store i64 [[RETURNADDR]], ptr addrspace(21) [[RETURNADDR_SPILL_ADDR]], align 4
+; CLEANED-NEXT: [[TMP4:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANED-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+; CLEANED-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 8
+; CLEANED-NEXT: store i32 [[TMP6]], ptr [[TMP4]], align 4
+; CLEANED-NEXT: [[TMP7:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANED-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+; CLEANED-NEXT: call void (i64, i64, ...) @continuation.waitContinue(i64 ptrtoint (ptr @async_fun_with_waitmask to i64), i64 -1, i32 [[TMP8]], i64 ptrtoint (ptr @wait_await.resume.0 to i64)), !continuation.registercount [[META1]], !continuation.returnedRegistercount !1
; CLEANED-NEXT: unreachable
;
%tok = call %continuation.token* @async_fun_with_waitmask(i64 -1), !continuation.wait.await !0, !continuation.registercount !1, !continuation.returnedRegistercount !1
diff --git a/shared/continuations/test/dx/lower-rt-pipeline-call-shader.ll b/shared/continuations/test/dx/lower-rt-pipeline-call-shader.ll
index e15c47304c..d319d92100 100644
--- a/shared/continuations/test/dx/lower-rt-pipeline-call-shader.ll
+++ b/shared/continuations/test/dx/lower-rt-pipeline-call-shader.ll
@@ -75,13 +75,11 @@ attributes #0 = { nounwind }
!19 = !{!"function", !"void", i32 poison, i32 poison, !20}
!20 = !{i32 0, %struct.TheirParams poison}
; LOWERRAYTRACINGPIPELINE-LABEL: define void @main(
-; LOWERRAYTRACINGPIPELINE-SAME: ) !lgc.rt.shaderstage [[META9:![0-9]+]] !continuation.entry [[META16:![0-9]+]] !continuation.registercount [[META9]] !continuation [[META17:![0-9]+]] {
+; LOWERRAYTRACINGPIPELINE-SAME: [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage [[META9:![0-9]+]] !continuation.entry [[META16:![0-9]+]] !continuation.registercount [[META9]] !continuation [[META17:![0-9]+]] {
; LOWERRAYTRACINGPIPELINE-NEXT: [[PARAMS:%.*]] = alloca [[STRUCT_THEIRPARAMS:%.*]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP1:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; LOWERRAYTRACINGPIPELINE-NEXT: [[DIS_DATA_I:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_THEIRPARAMS]], ptr [[PARAMS]], i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
@@ -93,30 +91,27 @@ attributes #0 = { nounwind }
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = load i32, ptr @PAYLOAD, align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP5]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[LOCAL_ROOT_INDEX1:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX1]])
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; LOWERRAYTRACINGPIPELINE-NEXT: ret void, !continuation.registercount [[META14:![0-9]+]]
;
;
; LOWERRAYTRACINGPIPELINE-CPS-LABEL: define void @main(
-; LOWERRAYTRACINGPIPELINE-CPS-SAME: {} [[CONT_STATE:%.*]], i32 [[RETURN_ADDR:%.*]], i32 [[SHADER_INDEX:%.*]]) !lgc.rt.shaderstage [[META9:![0-9]+]] !lgc.cps [[META9]] !continuation [[META16:![0-9]+]] {
+; LOWERRAYTRACINGPIPELINE-CPS-SAME: {} [[CONT_STATE:%.*]], i32 [[RETURN_ADDR:%.*]], i32 [[SHADER_INDEX:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage [[META9:![0-9]+]] !lgc.cps [[META9]] !continuation [[META16:![0-9]+]] {
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[PARAMS:%.*]] = alloca [[STRUCT_THEIRPARAMS:%.*]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP1:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[DIS_DATA_I:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_THEIRPARAMS]], ptr [[PARAMS]], i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP3]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP4:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] (...) @lgc.cps.await.s_struct.DispatchSystemDatas(i32 2, i32 2, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP4:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP5:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] (...) @lgc.cps.await.s_struct.DispatchSystemDatas(i32 2, i32 2, i32 [[TMP4]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_THEIRPARAMS]] poison, ptr [[PARAMS]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_THEIRPARAMS]], ptr [[PARAMS]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP6:%.*]] = load i32, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP6]], ptr [[TMP5]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP4]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[LOCAL_ROOT_INDEX1:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX1]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_THEIRPARAMS]], ptr [[PARAMS]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP7:%.*]] = load i32, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP5]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: ret void
;
diff --git a/shared/continuations/test/dx/lower-rt-pipeline-intrinsics-hit.ll b/shared/continuations/test/dx/lower-rt-pipeline-intrinsics-hit.ll
index 9bf49097ee..408476846d 100644
--- a/shared/continuations/test/dx/lower-rt-pipeline-intrinsics-hit.ll
+++ b/shared/continuations/test/dx/lower-rt-pipeline-intrinsics-hit.ll
@@ -181,23 +181,18 @@ declare !types !46 [4 x <3 x float>] @_cont_WorldToObject4x3(%struct.DispatchSys
; Function Attrs: nounwind
define void @RayGen() #3 {
; LOWERRAYTRACINGPIPELINE-LABEL: define void @RayGen(
-; LOWERRAYTRACINGPIPELINE-SAME: ) #[[ATTR5:[0-9]+]] !lgc.rt.shaderstage [[META19:![0-9]+]] !continuation [[META29:![0-9]+]] !continuation.entry [[META14:![0-9]+]] !continuation.registercount [[META19]] {
-; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP1:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; LOWERRAYTRACINGPIPELINE-SAME: [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] !lgc.rt.shaderstage [[META19:![0-9]+]] !continuation [[META29:![0-9]+]] !continuation.entry [[META14:![0-9]+]] !continuation.registercount [[META19]] {
+; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; LOWERRAYTRACINGPIPELINE-NEXT: ret void, !continuation.registercount [[META26:![0-9]+]]
;
; DXILCONTPOSTPROCESS-LABEL: define void @RayGen(
; DXILCONTPOSTPROCESS-SAME: ) #[[ATTR5:[0-9]+]] !lgc.rt.shaderstage [[META18:![0-9]+]] !continuation [[META27:![0-9]+]] !continuation.entry [[META13:![0-9]+]] !continuation.registercount [[META18]] !continuation.state [[META18]] {
; DXILCONTPOSTPROCESS-NEXT: AllocaSpillBB:
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP0:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @_cont_SetupRayGen()
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
-; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA:%.*]] @_cont_SetupRayGen()
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[SYSTEM_DATA]], 0
+; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; DXILCONTPOSTPROCESS-NEXT: call void @continuation.complete()
; DXILCONTPOSTPROCESS-NEXT: unreachable
;
@@ -211,75 +206,75 @@ define void @Intersection() #3 {
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP2:%.*]] = alloca [[STRUCT_HITDATA:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_HITDATA]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_ANYHITTRAVERSALDATA]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = call [[STRUCT_ANYHITTRAVERSALDATA]] @continuations.getSystemData.s_struct.AnyHitTraversalDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP4]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = call float @lgc.rt.ray.tmin()
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA:%.*]], ptr [[TMP8]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = call float @lgc.rt.ray.tmin()
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA:%.*]], ptr [[TMP7]], i32 0, i32 1
; LOWERRAYTRACINGPIPELINE-NEXT: [[RES_I:%.*]] = load [[STRUCT_HITDATA]], ptr [[RESPTR_I]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[RES_I]], ptr [[TMP3]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[RES_I1:%.*]] = load float, ptr [[TMP3]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = call i32 @lgc.rt.instance.id()
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I2:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA]], ptr [[TMP11]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = call i32 @lgc.rt.instance.id()
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I2:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA]], ptr [[TMP10]], i32 0, i32 1
; LOWERRAYTRACINGPIPELINE-NEXT: [[RES_I3:%.*]] = load [[STRUCT_HITDATA]], ptr [[RESPTR_I2]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[RES_I3]], ptr [[TMP2]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I4:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[TMP10]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I4:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[TMP9]], i32 0, i32 1
; LOWERRAYTRACINGPIPELINE-NEXT: [[RES_I5:%.*]] = load i32, ptr [[RESPTR_I4]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[TRAV_DATA_I:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP12]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = call ptr inttoptr (i64 3 to ptr)([[STRUCT_ANYHITTRAVERSALDATA]] [[TRAV_DATA_I]], float 4.000000e+00, i32 0, [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP13]]), !continuation.registercount [[META26]], !continuation.returnedRegistercount !26
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = call [[STRUCT_ANYHITTRAVERSALDATA]] @await.struct.AnyHitTraversalData(ptr [[TMP14]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP15]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP11]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = call ptr inttoptr (i64 3 to ptr)([[STRUCT_ANYHITTRAVERSALDATA]] [[TRAV_DATA_I]], float 4.000000e+00, i32 0, [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP12]]), !continuation.registercount [[META26]], !continuation.returnedRegistercount !26
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = call [[STRUCT_ANYHITTRAVERSALDATA]] @await.struct.AnyHitTraversalData(ptr [[TMP13]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP14]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[ISEND_I:%.*]] = call i1 @opaqueIsEnd()
-; LOWERRAYTRACINGPIPELINE-NEXT: br i1 [[ISEND_I]], label [[TMP17:%.*]], label [[TMP19:%.*]]
-; LOWERRAYTRACINGPIPELINE: 17:
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP18]], !continuation.registercount [[META26]]
-; LOWERRAYTRACINGPIPELINE: 19:
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP20]], !continuation.registercount [[META26]]
+; LOWERRAYTRACINGPIPELINE-NEXT: br i1 [[ISEND_I]], label [[TMP16:%.*]], label [[TMP18:%.*]]
+; LOWERRAYTRACINGPIPELINE: 16:
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP17]], !continuation.registercount [[META26]]
+; LOWERRAYTRACINGPIPELINE: 18:
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP19]], !continuation.registercount [[META26]]
;
; DXILCONTPOSTPROCESS-LABEL: define void @Intersection(
; DXILCONTPOSTPROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_ANYHITTRAVERSALDATA:%.*]] [[TMP0:%.*]]) #[[ATTR5]] !lgc.rt.shaderstage [[META28:![0-9]+]] !continuation [[META29:![0-9]+]] !continuation.registercount [[META25:![0-9]+]] !continuation.state [[META30:![0-9]+]] !continuation.stacksize [[META30]] {
; DXILCONTPOSTPROCESS-NEXT: AllocaSpillBB:
; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = alloca [[STRUCT_HITDATA:%.*]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_ANYHITTRAVERSALDATA]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
; DXILCONTPOSTPROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_ANYHITTRAVERSALDATA]], align 8
+; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[INTERSECTION_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP2]], 0, 0, 0, 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP2]], 0, 0, 1
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP2]], 0, 1, 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP2]], 0, 1, 1
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_2_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP2]], 0, 2
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_3_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP2]], 0, 3
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_4_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP2]], 0, 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP2]], 1, 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP2]], 1, 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP3]], i64 0
+; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[INTERSECTION_FRAME:%.*]], ptr addrspace(21) [[TMP4]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: store i64 [[RETURNADDR]], ptr addrspace(21) [[RETURNADDR_SPILL_ADDR]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 0, 0, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 0, 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 1, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 1, 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_2_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 2
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_3_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 3
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_4_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 4
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 1, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 1, 1
; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA]], i32 0, i32 0, i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = call float @_cont_RayTMin(ptr [[TMP3]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = call float @_cont_RayTMin(ptr [[TMP5]])
; DXILCONTPOSTPROCESS-NEXT: [[RES_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_HITDATA]] poison, float [[DOTFCA_0_1_0_EXTRACT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[RES_I_FCA_1_INSERT:%.*]] = insertvalue [[STRUCT_HITDATA]] [[RES_I_FCA_0_INSERT]], i32 [[DOTFCA_0_1_1_EXTRACT]], 1
; DXILCONTPOSTPROCESS-NEXT: [[RES_I_FCA_1_INSERT_FCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_HITDATA]] [[RES_I_FCA_1_INSERT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[RES_I_FCA_1_INSERT_FCA_1_EXTRACT:%.*]] = extractvalue [[STRUCT_HITDATA]] [[RES_I_FCA_1_INSERT]], 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA]], i32 0, i32 0, i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[RESPTR_I:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA:%.*]], ptr [[TMP6]], i32 0, i32 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[RESPTR_I:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA:%.*]], ptr [[TMP8]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: [[RES_I:%.*]] = load [[STRUCT_HITDATA]], ptr [[RESPTR_I]], align 4
; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_HITDATA]] [[RES_I]], ptr [[TMP1]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = call i32 @_cont_InstanceID(ptr [[TMP5]], ptr [[TMP1]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = call i32 @_cont_InstanceID(ptr [[TMP7]], ptr [[TMP1]])
; DXILCONTPOSTPROCESS-NEXT: [[RES_I3_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_HITDATA]] poison, float [[DOTFCA_0_1_0_EXTRACT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[RES_I3_FCA_1_INSERT:%.*]] = insertvalue [[STRUCT_HITDATA]] [[RES_I3_FCA_0_INSERT]], i32 [[DOTFCA_0_1_1_EXTRACT]], 1
; DXILCONTPOSTPROCESS-NEXT: [[RES_I3_FCA_1_INSERT_FCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_HITDATA]] [[RES_I3_FCA_1_INSERT]], 0
@@ -294,21 +289,12 @@ define void @Intersection() #3 {
; DXILCONTPOSTPROCESS-NEXT: [[TRAV_DATA_I_FCA_1_0_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TRAV_DATA_I_FCA_0_4_INSERT]], float [[DOTFCA_1_0_EXTRACT]], 1, 0
; DXILCONTPOSTPROCESS-NEXT: [[TRAV_DATA_I_FCA_1_1_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TRAV_DATA_I_FCA_1_0_INSERT]], i32 [[DOTFCA_1_1_EXTRACT]], 1, 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] poison, <2 x float> undef, 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = add i32 [[TMP8]], 8
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP9]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = inttoptr i32 [[TMP8]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP10]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP11]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP13]], ptr addrspace(21) [[TMP12]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP10]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP14]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP16]], ptr addrspace(21) [[TMP15]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP17:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @Intersection.resume.0 to i64))
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 3, i32 [[TMP17]], i64 [[TMP18]], [[STRUCT_ANYHITTRAVERSALDATA]] [[TRAV_DATA_I_FCA_1_1_INSERT]], float 4.000000e+00, i32 0, [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META25]], !continuation.returnedRegistercount !25
+; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], 8
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP11]], ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @Intersection.resume.0 to i64))
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 3, i32 [[TMP12]], i64 [[TMP13]], [[STRUCT_ANYHITTRAVERSALDATA]] [[TRAV_DATA_I_FCA_1_1_INSERT]], float 4.000000e+00, i32 0, [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META25]], !continuation.returnedRegistercount !25
; DXILCONTPOSTPROCESS-NEXT: unreachable
;
%1 = call float @dx.op.rayTMin.f32(i32 153)
@@ -333,146 +319,141 @@ define void @AnyHit(%struct.RayPayload* noalias nocapture %payload, %struct.Buil
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[ORIGHITATTRS:%.*]] = alloca [8 x i32], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[HITATTRSALLOCA:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = call [[STRUCT_ANYHITTRAVERSALDATA]] @continuations.getSystemData.s_struct.AnyHitTraversalDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP9]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP8]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = load float, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP12]], ptr [[TMP11]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP8]], i32 0, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = load float, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP14]], ptr [[TMP13]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP8]], i32 0, i32 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i32 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP16]], ptr [[TMP15]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP8]], i32 0, i32 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i32 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP18]], ptr [[TMP17]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP8]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = load float, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP11]], ptr [[TMP10]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP8]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = load float, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP13]], ptr [[TMP12]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP8]], i32 0, i32 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i32 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP8]], i32 0, i32 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i32 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP17]], ptr [[TMP16]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[TMP19]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP20]], ptr [[TMP7]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP23]], ptr [[TMP21]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP26]], ptr [[TMP24]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[TMP18]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP19]], ptr [[TMP7]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP22]], ptr [[TMP20]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP25]], ptr [[TMP23]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP1]], ptr [[HITATTRSALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = call float @_cont_RayTMin(ptr [[TMP27]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA:%.*]], ptr [[TMP30]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = call float @_cont_RayTMin(ptr [[TMP26]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA:%.*]], ptr [[TMP29]], i32 0, i32 1
; LOWERRAYTRACINGPIPELINE-NEXT: [[RES_I:%.*]] = load [[STRUCT_HITDATA]], ptr [[RESPTR_I]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[RES_I]], ptr [[TMP5]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[RES_I1:%.*]] = load float, ptr [[TMP5]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I6:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA]], ptr [[TMP32]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I6:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA]], ptr [[TMP31]], i32 0, i32 1
; LOWERRAYTRACINGPIPELINE-NEXT: [[RES_I7:%.*]] = load [[STRUCT_HITDATA]], ptr [[RESPTR_I6]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[RES_I7]], ptr [[TMP3]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = call i32 @_cont_InstanceID(ptr [[TMP31]], ptr [[TMP3]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I2:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA]], ptr [[TMP35]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = call i32 @_cont_InstanceID(ptr [[TMP30]], ptr [[TMP3]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I2:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA]], ptr [[TMP34]], i32 0, i32 1
; LOWERRAYTRACINGPIPELINE-NEXT: [[RES_I3:%.*]] = load [[STRUCT_HITDATA]], ptr [[RESPTR_I2]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[RES_I3]], ptr [[TMP4]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I4:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[TMP34]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I4:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[TMP33]], i32 0, i32 1
; LOWERRAYTRACINGPIPELINE-NEXT: [[RES_I5:%.*]] = load i32, ptr [[RESPTR_I4]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = insertvalue [[STRUCT_RAYPAYLOAD]] undef, float [[TMP28]], 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = insertvalue [[STRUCT_RAYPAYLOAD]] [[TMP36]], float [[RES_I1]], 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = insertvalue [[STRUCT_RAYPAYLOAD]] [[TMP37]], i32 [[TMP33]], 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP39:%.*]] = insertvalue [[STRUCT_RAYPAYLOAD]] [[TMP38]], i32 [[RES_I5]], 3
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_RAYPAYLOAD]] [[TMP39]], ptr [[TMP8]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = insertvalue [[STRUCT_RAYPAYLOAD]] undef, float [[TMP27]], 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = insertvalue [[STRUCT_RAYPAYLOAD]] [[TMP35]], float [[RES_I1]], 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = insertvalue [[STRUCT_RAYPAYLOAD]] [[TMP36]], i32 [[TMP32]], 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = insertvalue [[STRUCT_RAYPAYLOAD]] [[TMP37]], i32 [[RES_I5]], 3
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_RAYPAYLOAD]] [[TMP38]], ptr [[TMP8]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void @_cont_AcceptHit(ptr [[SYSTEM_DATA_ALLOCA]])
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP8]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP41:%.*]] = load float, ptr [[TMP40]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP41]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP8]], i32 0, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP43:%.*]] = load float, ptr [[TMP42]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP43]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP8]], i32 0, i32 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP45:%.*]] = load i32, ptr [[TMP44]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP45]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i32 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP8]], i32 0, i32 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP47:%.*]] = load i32, ptr [[TMP46]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP47]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i32 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP48:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP49:%.*]] = getelementptr inbounds i32, ptr [[TMP6]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP50:%.*]] = load i32, ptr [[TMP48]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP50]], ptr [[TMP49]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP51:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP52:%.*]] = getelementptr inbounds i32, ptr [[TMP6]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP53:%.*]] = load i32, ptr [[TMP51]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP53]], ptr [[TMP52]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP54:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP6]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @_cont_SetTriangleHitAttributes(ptr [[TMP55]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP54]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP56:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP56]], !continuation.registercount [[META34]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP8]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP40:%.*]] = load float, ptr [[TMP39]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP40]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP8]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP42:%.*]] = load float, ptr [[TMP41]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP42]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP8]], i32 0, i32 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP44]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i32 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP8]], i32 0, i32 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP46:%.*]] = load i32, ptr [[TMP45]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP46]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i32 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP47:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP48:%.*]] = getelementptr inbounds i32, ptr [[TMP6]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP49:%.*]] = load i32, ptr [[TMP47]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP49]], ptr [[TMP48]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP50:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP51:%.*]] = getelementptr inbounds i32, ptr [[TMP6]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP52:%.*]] = load i32, ptr [[TMP50]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP52]], ptr [[TMP51]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP53:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP6]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @_cont_SetTriangleHitAttributes(ptr [[TMP54]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP53]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP55:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP55]], !continuation.registercount [[META34]]
;
; DXILCONTPOSTPROCESS-LABEL: define void @AnyHit(
; DXILCONTPOSTPROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_ANYHITTRAVERSALDATA:%.*]] [[TMP0:%.*]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] [[TMP1:%.*]]) #[[ATTR5]] !lgc.rt.shaderstage [[META31:![0-9]+]] !continuation [[META32:![0-9]+]] !continuation.registercount [[META33:![0-9]+]] !continuation.state [[META18]] {
; DXILCONTPOSTPROCESS-NEXT: AllocaSpillBB:
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_ANYHITTRAVERSALDATA]], align 8
; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = alloca [[STRUCT_HITDATA:%.*]], align 8
; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_ANYHITTRAVERSALDATA]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
; DXILCONTPOSTPROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP3]], 0, 0, 0, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 0, 0, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: store <3 x i32> [[DOTFCA_0_0_0_0_EXTRACT]], ptr [[DOTFCA_0_0_0_0_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP3]], 0, 0, 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 0, 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_1_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_0_0_1_EXTRACT]], ptr [[DOTFCA_0_0_1_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP3]], 0, 1, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 1, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 1, i32 0
; DXILCONTPOSTPROCESS-NEXT: store float [[DOTFCA_0_1_0_EXTRACT]], ptr [[DOTFCA_0_1_0_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP3]], 0, 1, 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 1, 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_1_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 1, i32 1
; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_0_1_1_EXTRACT]], ptr [[DOTFCA_0_1_1_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_2_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP3]], 0, 2
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_2_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 2
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_2_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 2
; DXILCONTPOSTPROCESS-NEXT: store <3 x float> [[DOTFCA_0_2_EXTRACT]], ptr [[DOTFCA_0_2_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_3_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP3]], 0, 3
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_3_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 3
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_3_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 3
; DXILCONTPOSTPROCESS-NEXT: store <3 x float> [[DOTFCA_0_3_EXTRACT]], ptr [[DOTFCA_0_3_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_4_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP3]], 0, 4
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_4_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_4_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 4
; DXILCONTPOSTPROCESS-NEXT: store float [[DOTFCA_0_4_EXTRACT]], ptr [[DOTFCA_0_4_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP3]], 1, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 1, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 0
; DXILCONTPOSTPROCESS-NEXT: store float [[DOTFCA_1_0_EXTRACT]], ptr [[DOTFCA_1_0_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP3]], 1, 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 1, 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_1_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 1
; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_1_1_EXTRACT]], ptr [[DOTFCA_1_1_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = load float, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = load float, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 8) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 9) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[TMP9]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT18:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP10]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load float, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = load float, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 8) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 9) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[TMP8]])
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT18:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP9]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_019_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT18]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = bitcast float [[DOTSROA_019_0_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = bitcast float [[DOTSROA_019_0_VEC_EXTRACT]] to i32
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_019_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT18]], i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = bitcast float [[DOTSROA_019_4_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = bitcast float [[DOTSROA_019_4_VEC_EXTRACT]] to i32
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP1]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = call float @_cont_RayTMin(ptr [[TMP13]])
-; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[RESPTR_I:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA:%.*]], ptr [[TMP16]], i32 0, i32 1
+; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = call float @_cont_RayTMin(ptr [[TMP12]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[RESPTR_I:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA:%.*]], ptr [[TMP15]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: [[RES_I_FCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[RESPTR_I]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: [[RES_I_FCA_0_LOAD:%.*]] = load float, ptr [[RES_I_FCA_0_GEP]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[RES_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_HITDATA]] poison, float [[RES_I_FCA_0_LOAD]], 0
@@ -481,9 +462,9 @@ define void @AnyHit(%struct.RayPayload* noalias nocapture %payload, %struct.Buil
; DXILCONTPOSTPROCESS-NEXT: [[RES_I_FCA_1_INSERT:%.*]] = insertvalue [[STRUCT_HITDATA]] [[RES_I_FCA_0_INSERT]], i32 [[RES_I_FCA_1_LOAD]], 1
; DXILCONTPOSTPROCESS-NEXT: [[RES_I_FCA_1_INSERT_FCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_HITDATA]] [[RES_I_FCA_1_INSERT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[RES_I_FCA_1_INSERT_FCA_1_EXTRACT:%.*]] = extractvalue [[STRUCT_HITDATA]] [[RES_I_FCA_1_INSERT]], 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[RESPTR_I6:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA]], ptr [[TMP18]], i32 0, i32 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[RESPTR_I6:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA]], ptr [[TMP17]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: [[RES_I7_FCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[RESPTR_I6]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: [[RES_I7_FCA_0_LOAD:%.*]] = load float, ptr [[RES_I7_FCA_0_GEP]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[RES_I7_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_HITDATA]] poison, float [[RES_I7_FCA_0_LOAD]], 0
@@ -496,10 +477,10 @@ define void @AnyHit(%struct.RayPayload* noalias nocapture %payload, %struct.Buil
; DXILCONTPOSTPROCESS-NEXT: [[RES_I7_FCA_1_INSERT_FCA_1_EXTRACT:%.*]] = extractvalue [[STRUCT_HITDATA]] [[RES_I7_FCA_1_INSERT]], 1
; DXILCONTPOSTPROCESS-NEXT: [[RES_I7_FCA_1_INSERT_FCA_1_GEP:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP2]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: store i32 [[RES_I7_FCA_1_INSERT_FCA_1_EXTRACT]], ptr [[RES_I7_FCA_1_INSERT_FCA_1_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP19:%.*]] = call i32 @_cont_InstanceID(ptr [[TMP17]], ptr [[TMP2]])
-; DXILCONTPOSTPROCESS-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[RESPTR_I2:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA]], ptr [[TMP21]], i32 0, i32 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = call i32 @_cont_InstanceID(ptr [[TMP16]], ptr [[TMP2]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[RESPTR_I2:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA]], ptr [[TMP20]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: [[RES_I3_FCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[RESPTR_I2]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: [[RES_I3_FCA_0_LOAD:%.*]] = load float, ptr [[RES_I3_FCA_0_GEP]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[RES_I3_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_HITDATA]] poison, float [[RES_I3_FCA_0_LOAD]], 0
@@ -508,32 +489,32 @@ define void @AnyHit(%struct.RayPayload* noalias nocapture %payload, %struct.Buil
; DXILCONTPOSTPROCESS-NEXT: [[RES_I3_FCA_1_INSERT:%.*]] = insertvalue [[STRUCT_HITDATA]] [[RES_I3_FCA_0_INSERT]], i32 [[RES_I3_FCA_1_LOAD]], 1
; DXILCONTPOSTPROCESS-NEXT: [[RES_I3_FCA_1_INSERT_FCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_HITDATA]] [[RES_I3_FCA_1_INSERT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[RES_I3_FCA_1_INSERT_FCA_1_EXTRACT:%.*]] = extractvalue [[STRUCT_HITDATA]] [[RES_I3_FCA_1_INSERT]], 1
-; DXILCONTPOSTPROCESS-NEXT: [[RESPTR_I4:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[TMP20]], i32 0, i32 1
+; DXILCONTPOSTPROCESS-NEXT: [[RESPTR_I4:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[TMP19]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: [[RES_I5:%.*]] = load i32, ptr [[RESPTR_I4]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP22:%.*]] = insertvalue [[STRUCT_RAYPAYLOAD:%.*]] undef, float [[TMP14]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP23:%.*]] = insertvalue [[STRUCT_RAYPAYLOAD]] [[TMP22]], float [[RES_I_FCA_1_INSERT_FCA_0_EXTRACT]], 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP24:%.*]] = insertvalue [[STRUCT_RAYPAYLOAD]] [[TMP23]], i32 [[TMP19]], 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP25:%.*]] = insertvalue [[STRUCT_RAYPAYLOAD]] [[TMP24]], i32 [[RES_I5]], 3
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT8:%.*]] = extractvalue [[STRUCT_RAYPAYLOAD]] [[TMP25]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT:%.*]] = extractvalue [[STRUCT_RAYPAYLOAD]] [[TMP25]], 1
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_2_EXTRACT:%.*]] = extractvalue [[STRUCT_RAYPAYLOAD]] [[TMP25]], 2
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_EXTRACT:%.*]] = extractvalue [[STRUCT_RAYPAYLOAD]] [[TMP25]], 3
+; DXILCONTPOSTPROCESS-NEXT: [[TMP21:%.*]] = insertvalue [[STRUCT_RAYPAYLOAD:%.*]] undef, float [[TMP13]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP22:%.*]] = insertvalue [[STRUCT_RAYPAYLOAD]] [[TMP21]], float [[RES_I_FCA_1_INSERT_FCA_0_EXTRACT]], 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP23:%.*]] = insertvalue [[STRUCT_RAYPAYLOAD]] [[TMP22]], i32 [[TMP18]], 2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP24:%.*]] = insertvalue [[STRUCT_RAYPAYLOAD]] [[TMP23]], i32 [[RES_I5]], 3
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT8:%.*]] = extractvalue [[STRUCT_RAYPAYLOAD]] [[TMP24]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT:%.*]] = extractvalue [[STRUCT_RAYPAYLOAD]] [[TMP24]], 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_2_EXTRACT:%.*]] = extractvalue [[STRUCT_RAYPAYLOAD]] [[TMP24]], 2
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_EXTRACT:%.*]] = extractvalue [[STRUCT_RAYPAYLOAD]] [[TMP24]], 3
; DXILCONTPOSTPROCESS-NEXT: call void @_cont_AcceptHit(ptr [[SYSTEM_DATA_ALLOCA]])
; DXILCONTPOSTPROCESS-NEXT: store float [[DOTFCA_0_EXTRACT8]], ptr addrspace(20) @REGISTERS, align 4
; DXILCONTPOSTPROCESS-NEXT: store float [[DOTFCA_1_EXTRACT]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_2_EXTRACT]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 8) to ptr addrspace(20)), align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_3_EXTRACT]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 9) to ptr addrspace(20)), align 4
; DXILCONTPOSTPROCESS-NEXT: [[HITATTRSALLOCA_SROA_0_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP26:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_0_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: [[TMP27:%.*]] = bitcast i32 [[TMP26]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_020_0_VEC_INSERT:%.*]] = insertelement <2 x float> undef, float [[TMP27]], i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP25:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_0_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP26:%.*]] = bitcast i32 [[TMP25]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_020_0_VEC_INSERT:%.*]] = insertelement <2 x float> undef, float [[TMP26]], i32 0
; DXILCONTPOSTPROCESS-NEXT: [[HITATTRSALLOCA_SROA_0_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT]], i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP28:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_4_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: [[TMP29:%.*]] = bitcast i32 [[TMP28]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_020_4_VEC_INSERT:%.*]] = insertelement <2 x float> [[DOTSROA_020_0_VEC_INSERT]], float [[TMP29]], i32 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP27:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_4_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP28:%.*]] = bitcast i32 [[TMP27]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_020_4_VEC_INSERT:%.*]] = insertelement <2 x float> [[DOTSROA_020_0_VEC_INSERT]], float [[TMP28]], i32 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] poison, <2 x float> [[DOTSROA_020_4_VEC_INSERT]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: call void @_cont_SetTriangleHitAttributes(ptr [[TMP30]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_INSERT]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: call void @_cont_SetTriangleHitAttributes(ptr [[TMP29]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_INSERT]])
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_0_GEP9:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_0_LOAD:%.*]] = load <3 x i32>, ptr [[DOTFCA_0_0_0_0_GEP9]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_0_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] poison, <3 x i32> [[DOTFCA_0_0_0_0_LOAD]], 0, 0, 0, 0
@@ -561,8 +542,8 @@ define void @AnyHit(%struct.RayPayload* noalias nocapture %payload, %struct.Buil
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_1_GEP17:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_1_LOAD:%.*]] = load i32, ptr [[DOTFCA_1_1_GEP17]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_1_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_1_0_INSERT]], i32 [[DOTFCA_1_1_LOAD]], 1, 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP31:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP31]], [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_1_1_INSERT]]), !continuation.registercount [[META33]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP30:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP30]], [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_1_1_INSERT]]), !continuation.registercount [[META33]]
; DXILCONTPOSTPROCESS-NEXT: unreachable
;
%1 = call float @dx.op.rayTMin.f32(i32 153)
@@ -588,123 +569,118 @@ define void @ClosestHit(%struct.RayPayload* noalias nocapture %payload, %struct.
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[HITATTRS:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = call [[STRUCT_SYSTEMDATA]] @continuations.getSystemData.s_struct.SystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP7]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP6]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = load float, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP10]], ptr [[TMP9]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP6]], i32 0, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = load float, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP12]], ptr [[TMP11]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP6]], i32 0, i32 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i32 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP6]], i32 0, i32 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i32 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP16]], ptr [[TMP15]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP6]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = load float, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP9]], ptr [[TMP8]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP6]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = load float, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP11]], ptr [[TMP10]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP6]], i32 0, i32 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i32 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP13]], ptr [[TMP12]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP6]], i32 0, i32 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i32 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP17]], ptr [[TMP5]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP20]], ptr [[TMP18]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP23]], ptr [[TMP21]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = call float @_cont_RayTMin(ptr [[TMP24]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP27]], ptr [[TMP4]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP16]], ptr [[TMP5]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP19]], ptr [[TMP17]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP22]], ptr [[TMP20]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = call float @_cont_RayTMin(ptr [[TMP23]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP26]], ptr [[TMP4]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[RES_I:%.*]] = load float, ptr [[TMP4]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP29]], ptr [[TMP2]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = call i32 @_cont_InstanceID(ptr [[TMP28]], ptr [[TMP2]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP31]], ptr [[TMP3]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP28]], ptr [[TMP2]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = call i32 @_cont_InstanceID(ptr [[TMP27]], ptr [[TMP2]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP30]], ptr [[TMP3]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I:%.*]] = getelementptr [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1
; LOWERRAYTRACINGPIPELINE-NEXT: [[RES_I1:%.*]] = load i32, ptr [[RESPTR_I]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP6]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = load float, ptr [[TMP32]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP33]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP6]], i32 0, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = load float, ptr [[TMP34]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP35]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP6]], i32 0, i32 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP36]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP37]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i32 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP6]], i32 0, i32 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP39:%.*]] = load i32, ptr [[TMP38]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP39]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i32 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP41:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP40]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP41]], !continuation.registercount [[META34]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP6]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = load float, ptr [[TMP31]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP32]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP6]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = load float, ptr [[TMP33]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP34]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP6]], i32 0, i32 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP35]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP36]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i32 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP6]], i32 0, i32 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP37]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP38]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i32 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP40:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP39]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP40]], !continuation.registercount [[META34]]
;
; DXILCONTPOSTPROCESS-LABEL: define void @ClosestHit(
; DXILCONTPOSTPROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR5]] !lgc.rt.shaderstage [[META34:![0-9]+]] !continuation [[META35:![0-9]+]] !continuation.registercount [[META33]] !continuation.state [[META18]] {
; DXILCONTPOSTPROCESS-NEXT: AllocaSpillBB:
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = alloca [[STRUCT_HITDATA:%.*]], align 8
; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
; DXILCONTPOSTPROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = load [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP2]], 0, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP0]], 0, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: store <3 x i32> [[DOTFCA_0_0_EXTRACT]], ptr [[DOTFCA_0_0_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP2]], 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP0]], 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_GEP:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_1_EXTRACT]], ptr [[DOTFCA_1_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load float, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = load float, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 8) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 9) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP8]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = load float, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load float, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 8) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 9) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP7]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_03_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = bitcast float [[DOTSROA_03_0_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = bitcast float [[DOTSROA_03_0_VEC_EXTRACT]] to i32
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_03_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT]], i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = bitcast float [[DOTSROA_03_4_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = call float @_cont_RayTMin(ptr [[TMP11]])
-; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT4:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP14]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT6:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP14]], 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT15:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP16]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = bitcast float [[DOTSROA_03_4_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = call float @_cont_RayTMin(ptr [[TMP10]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT4:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP13]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT6:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP13]], 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT15:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP15]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP16:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP1]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: store float [[DOTFCA_0_EXTRACT15]], ptr [[DOTFCA_0_GEP16]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT17:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP16]], 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT17:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP15]], 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_GEP18:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP1]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_1_EXTRACT17]], ptr [[DOTFCA_1_GEP18]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP17:%.*]] = call i32 @_cont_InstanceID(ptr [[TMP15]], ptr [[TMP1]])
-; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT10:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP18]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT12:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP18]], 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = call i32 @_cont_InstanceID(ptr [[TMP14]], ptr [[TMP1]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP17:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT10:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP17]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT12:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP17]], 1
; DXILCONTPOSTPROCESS-NEXT: [[RESPTR_I:%.*]] = getelementptr [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: [[RES_I1:%.*]] = load i32, ptr [[RESPTR_I]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store float [[TMP4]], ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: store float [[TMP5]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP6]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 8) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP7]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 9) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP19]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: store float [[TMP3]], ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: store float [[TMP4]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP5]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 8) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP6]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 9) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP18]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_LOAD:%.*]] = load <3 x i32>, ptr [[DOTFCA_0_GEP]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, <3 x i32> [[DOTFCA_0_LOAD]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP20:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP20]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META33]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP19:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP19]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META33]]
; DXILCONTPOSTPROCESS-NEXT: unreachable
;
%1 = call float @dx.op.rayTMin.f32(i32 153)
diff --git a/shared/continuations/test/dx/lower-rt-pipeline-intrinsics.ll b/shared/continuations/test/dx/lower-rt-pipeline-intrinsics.ll
index 24fe7e686c..cebbea4656 100644
--- a/shared/continuations/test/dx/lower-rt-pipeline-intrinsics.ll
+++ b/shared/continuations/test/dx/lower-rt-pipeline-intrinsics.ll
@@ -113,113 +113,111 @@ define void @ClosestHit(%struct.RayPayload* %0, %struct.BuiltInTriangleIntersect
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[HITATTRS:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = call [[STRUCT_SYSTEMDATA]] @continuations.getSystemData.s_struct.SystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP15]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP14]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = load float, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP18]], ptr [[TMP17]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP14]], i32 0, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = load float, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP20]], ptr [[TMP19]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP14]], i32 0, i32 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i32 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP22]], ptr [[TMP21]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP14]], i32 0, i32 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i32 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP24]], ptr [[TMP23]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP14]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = load float, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP17]], ptr [[TMP16]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP14]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = load float, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP19]], ptr [[TMP18]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP14]], i32 0, i32 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i32 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP21]], ptr [[TMP20]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP14]], i32 0, i32 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i32 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP23]], ptr [[TMP22]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP25]], ptr [[TMP11]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = getelementptr inbounds i32, ptr [[TMP11]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP28]], ptr [[TMP26]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = getelementptr inbounds i32, ptr [[TMP11]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP30]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP31]], ptr [[TMP29]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = call <3 x i32> @lgc.rt.dispatch.rays.index()
-; LOWERRAYTRACINGPIPELINE-NEXT: [[A:%.*]] = extractelement <3 x i32> [[TMP32]], i8 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = call <3 x i32> @lgc.rt.dispatch.rays.dimensions()
-; LOWERRAYTRACINGPIPELINE-NEXT: [[B:%.*]] = extractelement <3 x i32> [[TMP33]], i8 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = call <3 x float> @_cont_WorldRayOrigin3(ptr [[TMP34]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[C:%.*]] = extractelement <3 x float> [[TMP35]], i8 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = call <3 x float> @_cont_WorldRayDirection3(ptr [[TMP36]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[D:%.*]] = extractelement <3 x float> [[TMP37]], i8 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP39:%.*]] = call float @_cont_RayTMin(ptr [[TMP38]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP41:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP41]], ptr [[TMP8]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP42:%.*]] = call float @_cont_RayTCurrent(ptr [[TMP40]], ptr [[TMP8]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP44:%.*]] = call i32 @_cont_RayFlags(ptr [[TMP43]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP46:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP46]], ptr [[TMP4]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP47:%.*]] = call i32 @_cont_InstanceIndex(ptr [[TMP45]], ptr [[TMP4]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP49:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP49]], ptr [[TMP5]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP50:%.*]] = call i32 @_cont_InstanceID(ptr [[TMP48]], ptr [[TMP5]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP52:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP52]], ptr [[TMP6]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP53:%.*]] = call i32 @_cont_PrimitiveIndex(ptr [[TMP51]], ptr [[TMP6]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP55:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP55]], ptr [[TMP9]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP56:%.*]] = call <3 x float> @_cont_ObjectRayOrigin3(ptr [[TMP54]], ptr [[TMP9]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[K:%.*]] = extractelement <3 x float> [[TMP56]], i8 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP58:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP58]], ptr [[TMP10]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP59:%.*]] = call <3 x float> @_cont_ObjectRayDirection3(ptr [[TMP57]], ptr [[TMP10]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[L:%.*]] = extractelement <3 x float> [[TMP59]], i8 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP61:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP61]], ptr [[TMP2]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP62:%.*]] = call [4 x <3 x float>] @_cont_ObjectToWorld4x3(ptr [[TMP60]], ptr [[TMP2]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [4 x <3 x float>] [[TMP62]], ptr [[TMP13]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP24]], ptr [[TMP11]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = getelementptr inbounds i32, ptr [[TMP11]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP27]], ptr [[TMP25]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = getelementptr inbounds i32, ptr [[TMP11]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP30]], ptr [[TMP28]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = call <3 x i32> @lgc.rt.dispatch.rays.index()
+; LOWERRAYTRACINGPIPELINE-NEXT: [[A:%.*]] = extractelement <3 x i32> [[TMP31]], i8 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = call <3 x i32> @lgc.rt.dispatch.rays.dimensions()
+; LOWERRAYTRACINGPIPELINE-NEXT: [[B:%.*]] = extractelement <3 x i32> [[TMP32]], i8 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = call <3 x float> @_cont_WorldRayOrigin3(ptr [[TMP33]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[C:%.*]] = extractelement <3 x float> [[TMP34]], i8 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = call <3 x float> @_cont_WorldRayDirection3(ptr [[TMP35]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[D:%.*]] = extractelement <3 x float> [[TMP36]], i8 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = call float @_cont_RayTMin(ptr [[TMP37]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP40:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP40]], ptr [[TMP8]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP41:%.*]] = call float @_cont_RayTCurrent(ptr [[TMP39]], ptr [[TMP8]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP43:%.*]] = call i32 @_cont_RayFlags(ptr [[TMP42]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP45:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP45]], ptr [[TMP4]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP46:%.*]] = call i32 @_cont_InstanceIndex(ptr [[TMP44]], ptr [[TMP4]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP48:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP48]], ptr [[TMP5]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP49:%.*]] = call i32 @_cont_InstanceID(ptr [[TMP47]], ptr [[TMP5]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP51:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP51]], ptr [[TMP6]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP52:%.*]] = call i32 @_cont_PrimitiveIndex(ptr [[TMP50]], ptr [[TMP6]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP54:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP54]], ptr [[TMP9]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP55:%.*]] = call <3 x float> @_cont_ObjectRayOrigin3(ptr [[TMP53]], ptr [[TMP9]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[K:%.*]] = extractelement <3 x float> [[TMP55]], i8 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP57:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP57]], ptr [[TMP10]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP58:%.*]] = call <3 x float> @_cont_ObjectRayDirection3(ptr [[TMP56]], ptr [[TMP10]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[L:%.*]] = extractelement <3 x float> [[TMP58]], i8 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP60:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP60]], ptr [[TMP2]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP61:%.*]] = call [4 x <3 x float>] @_cont_ObjectToWorld4x3(ptr [[TMP59]], ptr [[TMP2]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [4 x <3 x float>] [[TMP61]], ptr [[TMP13]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[COL_GEP1:%.*]] = getelementptr [4 x <3 x float>], ptr [[TMP13]], i32 0, i8 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[COL_GEP_LOAD2:%.*]] = load <3 x float>, ptr [[COL_GEP1]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[M:%.*]] = extractelement <3 x float> [[COL_GEP_LOAD2]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP63:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP64:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP64]], ptr [[TMP3]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP65:%.*]] = call [4 x <3 x float>] @_cont_WorldToObject4x3(ptr [[TMP63]], ptr [[TMP3]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [4 x <3 x float>] [[TMP65]], ptr [[TMP12]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP63:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP63]], ptr [[TMP3]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP64:%.*]] = call [4 x <3 x float>] @_cont_WorldToObject4x3(ptr [[TMP62]], ptr [[TMP3]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [4 x <3 x float>] [[TMP64]], ptr [[TMP12]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[COL_GEP:%.*]] = getelementptr [4 x <3 x float>], ptr [[TMP12]], i32 0, i8 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[COL_GEP_LOAD:%.*]] = load <3 x float>, ptr [[COL_GEP]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[N:%.*]] = extractelement <3 x float> [[COL_GEP_LOAD]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP66:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP66]], ptr [[TMP7]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP67:%.*]] = call i32 @_cont_HitKind(ptr [[SYSTEM_DATA_ALLOCA]], ptr [[TMP7]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP65:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP65]], ptr [[TMP7]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP66:%.*]] = call i32 @_cont_HitKind(ptr [[SYSTEM_DATA_ALLOCA]], ptr [[TMP7]])
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP68:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP14]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP69:%.*]] = load float, ptr [[TMP68]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP69]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP14]], i32 0, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP71:%.*]] = load float, ptr [[TMP70]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP71]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP14]], i32 0, i32 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP73:%.*]] = load i32, ptr [[TMP72]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP73]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i32 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP14]], i32 0, i32 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP75:%.*]] = load i32, ptr [[TMP74]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP75]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i32 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP77:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP76]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP77]], !continuation.registercount [[META25]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP67:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP14]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP68:%.*]] = load float, ptr [[TMP67]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP68]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP69:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP14]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP70:%.*]] = load float, ptr [[TMP69]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP70]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP14]], i32 0, i32 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP72:%.*]] = load i32, ptr [[TMP71]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP72]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i32 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP14]], i32 0, i32 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP74:%.*]] = load i32, ptr [[TMP73]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP74]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i32 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP76:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP75]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP76]], !continuation.registercount [[META25]]
;
; DXILCONTPOSTPROCESS-LABEL: define void @ClosestHit(
; DXILCONTPOSTPROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] !lgc.rt.shaderstage [[META21:![0-9]+]] !continuation [[META22:![0-9]+]] !continuation.registercount [[META23:![0-9]+]] !continuation.state [[META18:![0-9]+]] {
; DXILCONTPOSTPROCESS-NEXT: AllocaSpillBB:
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = alloca [[STRUCT_HITDATA:%.*]], align 8
; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = alloca [[STRUCT_HITDATA]], align 8
; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_HITDATA]], align 8
@@ -230,144 +228,143 @@ define void @ClosestHit(%struct.RayPayload* %0, %struct.BuiltInTriangleIntersect
; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = alloca [[STRUCT_HITDATA]], align 8
; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = alloca [[STRUCT_HITDATA]], align 8
; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
; DXILCONTPOSTPROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA_ALLOCA1:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
+; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA1]], align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = load [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP10]], 0, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP0]], 0, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: store <3 x i32> [[DOTFCA_0_0_EXTRACT]], ptr [[DOTFCA_0_0_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = load float, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = load float, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 8) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 9) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT14:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP16]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = load float, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = load float, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 8) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 9) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT14:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP15]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_016_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT14]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP17:%.*]] = bitcast float [[DOTSROA_016_0_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = bitcast float [[DOTSROA_016_0_VEC_EXTRACT]] to i32
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_016_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT14]], i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = bitcast float [[DOTSROA_016_4_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP20:%.*]] = call <3 x i32> @_cont_DispatchRaysIndex3(ptr [[TMP19]])
-; DXILCONTPOSTPROCESS-NEXT: [[A:%.*]] = extractelement <3 x i32> [[TMP20]], i8 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP22:%.*]] = call <3 x i32> @_cont_DispatchRaysDimensions3(ptr [[TMP21]])
-; DXILCONTPOSTPROCESS-NEXT: [[B:%.*]] = extractelement <3 x i32> [[TMP22]], i8 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP24:%.*]] = call <3 x float> @_cont_WorldRayOrigin3(ptr [[TMP23]])
-; DXILCONTPOSTPROCESS-NEXT: [[C:%.*]] = extractelement <3 x float> [[TMP24]], i8 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP26:%.*]] = call <3 x float> @_cont_WorldRayDirection3(ptr [[TMP25]])
-; DXILCONTPOSTPROCESS-NEXT: [[D:%.*]] = extractelement <3 x float> [[TMP26]], i8 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP28:%.*]] = call float @_cont_RayTMin(ptr [[TMP27]])
-; DXILCONTPOSTPROCESS-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP30:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT24:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP30]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP17:%.*]] = bitcast float [[DOTSROA_016_4_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA1]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP19:%.*]] = call <3 x i32> @_cont_DispatchRaysIndex3(ptr [[TMP18]])
+; DXILCONTPOSTPROCESS-NEXT: [[A:%.*]] = extractelement <3 x i32> [[TMP19]], i8 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA1]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP21:%.*]] = call <3 x i32> @_cont_DispatchRaysDimensions3(ptr [[TMP20]])
+; DXILCONTPOSTPROCESS-NEXT: [[B:%.*]] = extractelement <3 x i32> [[TMP21]], i8 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP23:%.*]] = call <3 x float> @_cont_WorldRayOrigin3(ptr [[TMP22]])
+; DXILCONTPOSTPROCESS-NEXT: [[C:%.*]] = extractelement <3 x float> [[TMP23]], i8 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP25:%.*]] = call <3 x float> @_cont_WorldRayDirection3(ptr [[TMP24]])
+; DXILCONTPOSTPROCESS-NEXT: [[D:%.*]] = extractelement <3 x float> [[TMP25]], i8 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP27:%.*]] = call float @_cont_RayTMin(ptr [[TMP26]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP29:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT24:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP29]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP25:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP7]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: store float [[DOTFCA_0_EXTRACT24]], ptr [[DOTFCA_0_GEP25]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT26:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP30]], 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT26:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP29]], 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_GEP27:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP7]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_1_EXTRACT26]], ptr [[DOTFCA_1_GEP27]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP31:%.*]] = call float @_cont_RayTCurrent(ptr [[TMP29]], ptr [[TMP7]])
-; DXILCONTPOSTPROCESS-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP33:%.*]] = call i32 @_cont_RayFlags(ptr [[TMP32]])
-; DXILCONTPOSTPROCESS-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP35:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT40:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP35]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP30:%.*]] = call float @_cont_RayTCurrent(ptr [[TMP28]], ptr [[TMP7]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP32:%.*]] = call i32 @_cont_RayFlags(ptr [[TMP31]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP34:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT40:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP34]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP41:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP3]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: store float [[DOTFCA_0_EXTRACT40]], ptr [[DOTFCA_0_GEP41]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT42:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP35]], 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT42:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP34]], 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_GEP43:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP3]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_1_EXTRACT42]], ptr [[DOTFCA_1_GEP43]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP36:%.*]] = call i32 @_cont_InstanceIndex(ptr [[TMP34]], ptr [[TMP3]])
-; DXILCONTPOSTPROCESS-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP38:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT36:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP38]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP35:%.*]] = call i32 @_cont_InstanceIndex(ptr [[TMP33]], ptr [[TMP3]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP37:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT36:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP37]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP37:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP4]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: store float [[DOTFCA_0_EXTRACT36]], ptr [[DOTFCA_0_GEP37]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT38:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP38]], 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT38:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP37]], 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_GEP39:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP4]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_1_EXTRACT38]], ptr [[DOTFCA_1_GEP39]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP39:%.*]] = call i32 @_cont_InstanceID(ptr [[TMP37]], ptr [[TMP4]])
-; DXILCONTPOSTPROCESS-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP41:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT32:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP41]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP38:%.*]] = call i32 @_cont_InstanceID(ptr [[TMP36]], ptr [[TMP4]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP40:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT32:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP40]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP33:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP5]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: store float [[DOTFCA_0_EXTRACT32]], ptr [[DOTFCA_0_GEP33]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT34:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP41]], 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT34:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP40]], 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_GEP35:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP5]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_1_EXTRACT34]], ptr [[DOTFCA_1_GEP35]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP42:%.*]] = call i32 @_cont_PrimitiveIndex(ptr [[TMP40]], ptr [[TMP5]])
-; DXILCONTPOSTPROCESS-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP44:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT20:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP44]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP41:%.*]] = call i32 @_cont_PrimitiveIndex(ptr [[TMP39]], ptr [[TMP5]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP43:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT20:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP43]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP21:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP8]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: store float [[DOTFCA_0_EXTRACT20]], ptr [[DOTFCA_0_GEP21]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT22:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP44]], 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT22:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP43]], 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_GEP23:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP8]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_1_EXTRACT22]], ptr [[DOTFCA_1_GEP23]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP45:%.*]] = call <3 x float> @_cont_ObjectRayOrigin3(ptr [[TMP43]], ptr [[TMP8]])
-; DXILCONTPOSTPROCESS-NEXT: [[K:%.*]] = extractelement <3 x float> [[TMP45]], i8 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP47:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT17:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP47]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP44:%.*]] = call <3 x float> @_cont_ObjectRayOrigin3(ptr [[TMP42]], ptr [[TMP8]])
+; DXILCONTPOSTPROCESS-NEXT: [[K:%.*]] = extractelement <3 x float> [[TMP44]], i8 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP46:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT17:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP46]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP18:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP9]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: store float [[DOTFCA_0_EXTRACT17]], ptr [[DOTFCA_0_GEP18]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT19:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP47]], 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT19:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP46]], 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_GEP:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP9]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_1_EXTRACT19]], ptr [[DOTFCA_1_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP48:%.*]] = call <3 x float> @_cont_ObjectRayDirection3(ptr [[TMP46]], ptr [[TMP9]])
-; DXILCONTPOSTPROCESS-NEXT: [[L:%.*]] = extractelement <3 x float> [[TMP48]], i8 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP50:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT48:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP50]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP47:%.*]] = call <3 x float> @_cont_ObjectRayDirection3(ptr [[TMP45]], ptr [[TMP9]])
+; DXILCONTPOSTPROCESS-NEXT: [[L:%.*]] = extractelement <3 x float> [[TMP47]], i8 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP49:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT48:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP49]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP49:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP1]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: store float [[DOTFCA_0_EXTRACT48]], ptr [[DOTFCA_0_GEP49]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT50:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP50]], 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT50:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP49]], 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_GEP51:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP1]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_1_EXTRACT50]], ptr [[DOTFCA_1_GEP51]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP51:%.*]] = call [4 x <3 x float>] @_cont_ObjectToWorld4x3(ptr [[TMP49]], ptr [[TMP1]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [4 x <3 x float>] [[TMP51]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT:%.*]] = extractvalue [4 x <3 x float>] [[TMP51]], 1
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_2_EXTRACT:%.*]] = extractvalue [4 x <3 x float>] [[TMP51]], 2
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_EXTRACT:%.*]] = extractvalue [4 x <3 x float>] [[TMP51]], 3
+; DXILCONTPOSTPROCESS-NEXT: [[TMP50:%.*]] = call [4 x <3 x float>] @_cont_ObjectToWorld4x3(ptr [[TMP48]], ptr [[TMP1]])
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [4 x <3 x float>] [[TMP50]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT:%.*]] = extractvalue [4 x <3 x float>] [[TMP50]], 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_2_EXTRACT:%.*]] = extractvalue [4 x <3 x float>] [[TMP50]], 2
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_EXTRACT:%.*]] = extractvalue [4 x <3 x float>] [[TMP50]], 3
; DXILCONTPOSTPROCESS-NEXT: [[M:%.*]] = extractelement <3 x float> [[DOTFCA_0_EXTRACT]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP53:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT44:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP53]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP52:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT44:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP52]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP45:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP2]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: store float [[DOTFCA_0_EXTRACT44]], ptr [[DOTFCA_0_GEP45]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT46:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP53]], 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT46:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP52]], 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_GEP47:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP2]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_1_EXTRACT46]], ptr [[DOTFCA_1_GEP47]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP54:%.*]] = call [4 x <3 x float>] @_cont_WorldToObject4x3(ptr [[TMP52]], ptr [[TMP2]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT5:%.*]] = extractvalue [4 x <3 x float>] [[TMP54]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT7:%.*]] = extractvalue [4 x <3 x float>] [[TMP54]], 1
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_2_EXTRACT8:%.*]] = extractvalue [4 x <3 x float>] [[TMP54]], 2
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_EXTRACT9:%.*]] = extractvalue [4 x <3 x float>] [[TMP54]], 3
+; DXILCONTPOSTPROCESS-NEXT: [[TMP53:%.*]] = call [4 x <3 x float>] @_cont_WorldToObject4x3(ptr [[TMP51]], ptr [[TMP2]])
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT5:%.*]] = extractvalue [4 x <3 x float>] [[TMP53]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT7:%.*]] = extractvalue [4 x <3 x float>] [[TMP53]], 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_2_EXTRACT8:%.*]] = extractvalue [4 x <3 x float>] [[TMP53]], 2
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_EXTRACT9:%.*]] = extractvalue [4 x <3 x float>] [[TMP53]], 3
; DXILCONTPOSTPROCESS-NEXT: [[N:%.*]] = extractelement <3 x float> [[DOTFCA_0_EXTRACT5]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP55:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT28:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP55]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP54:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCommittedState(ptr [[SYSTEM_DATA_ALLOCA]])
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT28:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP54]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP29:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP6]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: store float [[DOTFCA_0_EXTRACT28]], ptr [[DOTFCA_0_GEP29]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT30:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP55]], 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_EXTRACT30:%.*]] = extractvalue [[STRUCT_HITDATA]] [[TMP54]], 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_GEP31:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP6]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_1_EXTRACT30]], ptr [[DOTFCA_1_GEP31]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP56:%.*]] = call i32 @_cont_HitKind(ptr [[SYSTEM_DATA_ALLOCA]], ptr [[TMP6]])
-; DXILCONTPOSTPROCESS-NEXT: store float [[TMP12]], ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: store float [[TMP13]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP14]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 8) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP15]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 9) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP57]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP55:%.*]] = call i32 @_cont_HitKind(ptr [[SYSTEM_DATA_ALLOCA]], ptr [[TMP6]])
+; DXILCONTPOSTPROCESS-NEXT: store float [[TMP11]], ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: store float [[TMP12]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP13]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 8) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP14]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 9) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP56]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_LOAD:%.*]] = load <3 x i32>, ptr [[DOTFCA_0_GEP]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, <3 x i32> [[DOTFCA_0_LOAD]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP58:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP58]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META23]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP57:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP57]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META23]]
; DXILCONTPOSTPROCESS-NEXT: unreachable
;
%a = call i32 @dx.op.dispatchRaysIndex.i32(i32 145, i8 0)
diff --git a/shared/continuations/test/dx/lower-rt-pipeline-large-payload.ll b/shared/continuations/test/dx/lower-rt-pipeline-large-payload.ll
index 387ef66b41..148b7ef948 100644
--- a/shared/continuations/test/dx/lower-rt-pipeline-large-payload.ll
+++ b/shared/continuations/test/dx/lower-rt-pipeline-large-payload.ll
@@ -43,7 +43,7 @@ define void @_cont_TraceRay(%struct.DispatchSystemData* %data, i64 %0, i32 %1, i
ret void
}
-define void @Miss(%struct.SmallPayload* noalias nocapture %outerpayload) !types !204 !continuation.maxHitAttributeBytes !32 {
+define void @Miss(%struct.SmallPayload* noalias nocapture %outerpayload) !types !204 !lgc.rt.attribute.size !32 {
%p1 = alloca %struct.SmallPayload
%p2 = alloca %struct.MediumPayload
%p3 = alloca %struct.LargePayload
@@ -152,152 +152,151 @@ attributes #3 = { nounwind memory(none) }
!203 = !{!"function", !"void", !103, i64 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison}
!204 = !{!"function", !"void", !100}
; LOWERRAYTRACINGPIPELINE-LABEL: define %struct.DispatchSystemData @Miss(
-; LOWERRAYTRACINGPIPELINE-SAME: [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) !continuation.maxHitAttributeBytes !16 !lgc.rt.shaderstage [[META17:![0-9]+]] !continuation.registercount [[META18:![0-9]+]] !continuation [[META19:![0-9]+]] !continuation.stacksize [[META20:![0-9]+]] {
+; LOWERRAYTRACINGPIPELINE-SAME: [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.attribute.size !16 !lgc.rt.shaderstage [[META17:![0-9]+]] !continuation.registercount [[META18:![0-9]+]] !continuation [[META19:![0-9]+]] !continuation.stacksize [[META20:![0-9]+]] {
; LOWERRAYTRACINGPIPELINE-NEXT: [[P1:%.*]] = alloca [[STRUCT_SMALLPAYLOAD:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[P2:%.*]] = alloca [[STRUCT_MEDIUMPAYLOAD:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[P3:%.*]] = alloca [[STRUCT_LARGEPAYLOAD:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP2:%.*]] = alloca [[STRUCT_SMALLPAYLOAD]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = call [[STRUCT_SYSTEMDATA]] @continuations.getSystemData.s_struct.SystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP3]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], 16
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP7]], ptr [[TMP5]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_SMALLPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = load [1 x i32], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store [1 x i32] [[TMP9]], ptr [[TMP8]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 16
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP6]], ptr [[TMP4]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_SMALLPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = load [1 x i32], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [1 x i32] [[TMP8]], ptr [[TMP7]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SMALLPAYLOAD]] zeroinitializer, ptr [[P1]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_MEDIUMPAYLOAD]] zeroinitializer, ptr [[P2]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_LARGEPAYLOAD]] zeroinitializer, ptr [[P3]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[T1:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[T2:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[T1]])
; LOWERRAYTRACINGPIPELINE-NEXT: [[T3:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[T2]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[T3]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[DIS_DATA_I:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP11]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[T3]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[DIS_DATA_I:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP10]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYS_DATA_I:%.*]] = insertvalue [[STRUCT_SYSTEMDATA]] undef, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I]], 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TRAV_DATA_I:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA:%.*]] undef, [[STRUCT_SYSTEMDATA]] [[SYS_DATA_I]], 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TRAV_DATA2_I:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]], i64 -1, 5
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_SMALLPAYLOAD]], ptr [[P1]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = load [1 x i32], ptr [[TMP12]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store [1 x i32] [[TMP13]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = call ptr inttoptr (i64 4 to ptr)([[STRUCT_TRAVERSALDATA]] [[TRAV_DATA2_I]]), !continuation.registercount [[META18]], !continuation.returnedRegistercount !18
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @await.struct.DispatchSystemData(ptr [[TMP14]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_SMALLPAYLOAD]], ptr [[P1]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = load [1 x i32], ptr [[TMP11]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [1 x i32] [[TMP12]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = call ptr inttoptr (i64 4 to ptr)([[STRUCT_TRAVERSALDATA]] [[TRAV_DATA2_I]]), !continuation.registercount [[META18]], !continuation.returnedRegistercount !18
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @await.struct.DispatchSystemData(ptr [[TMP13]])
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SMALLPAYLOAD]] poison, ptr [[P1]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_SMALLPAYLOAD]], ptr [[P1]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = load [1 x i32], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store [1 x i32] [[TMP17]], ptr [[TMP16]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP15]], ptr [[TMP11]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_SMALLPAYLOAD]], ptr [[P1]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = load [1 x i32], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [1 x i32] [[TMP16]], ptr [[TMP15]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP14]], ptr [[TMP10]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; LOWERRAYTRACINGPIPELINE-NEXT: br label [[DOTSPLIT10:%.*]]
; LOWERRAYTRACINGPIPELINE: .split10:
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[T3]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[DIS_DATA_I1:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[TMP19]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[T3]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[DIS_DATA_I1:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[TMP18]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYS_DATA_I2:%.*]] = insertvalue [[STRUCT_SYSTEMDATA]] undef, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I1]], 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TRAV_DATA_I3:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] undef, [[STRUCT_SYSTEMDATA]] [[SYS_DATA_I2]], 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TRAV_DATA2_I4:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I3]], i64 -1, 5
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], -16
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP22]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = add i32 [[TMP20]], -16
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP21]], ptr @PAYLOAD, align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_MEDIUMPAYLOAD]], ptr [[P2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr [[TMP23]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[TMP24]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP26]], ptr getelementptr inbounds ([[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 1), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = getelementptr i32, ptr [[TMP24]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP28]], ptr getelementptr ([[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 2), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr [[TMP24]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP30]], ptr getelementptr ([[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 3), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = call ptr inttoptr (i64 4 to ptr)([[STRUCT_TRAVERSALDATA]] [[TRAV_DATA2_I4]]), !continuation.registercount [[META14:![0-9]+]], !continuation.returnedRegistercount !14
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @await.struct.DispatchSystemData(ptr [[TMP31]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_MEDIUMPAYLOAD]], ptr [[P2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = getelementptr i32, ptr [[TMP22]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr [[TMP23]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP25]], ptr getelementptr inbounds ([[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 1), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[TMP23]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP27]], ptr getelementptr ([[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 2), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = getelementptr i32, ptr [[TMP23]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP29]], ptr getelementptr ([[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 3), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = call ptr inttoptr (i64 4 to ptr)([[STRUCT_TRAVERSALDATA]] [[TRAV_DATA2_I4]]), !continuation.registercount [[META14:![0-9]+]], !continuation.returnedRegistercount !14
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @await.struct.DispatchSystemData(ptr [[TMP30]])
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_MEDIUMPAYLOAD]] poison, ptr [[P2]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_MEDIUMPAYLOAD]], ptr [[P2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = getelementptr i32, ptr [[TMP33]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = getelementptr i32, ptr [[TMP34]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 1), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP36]], ptr [[TMP35]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = getelementptr i32, ptr [[TMP34]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = load i32, ptr getelementptr ([[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 2), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP38]], ptr [[TMP37]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP39:%.*]] = getelementptr i32, ptr [[TMP34]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP40:%.*]] = load i32, ptr getelementptr ([[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 3), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP40]], ptr [[TMP39]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP32]], ptr [[TMP19]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_MEDIUMPAYLOAD]], ptr [[P2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = getelementptr i32, ptr [[TMP32]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = getelementptr i32, ptr [[TMP33]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 1), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP35]], ptr [[TMP34]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = getelementptr i32, ptr [[TMP33]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = load i32, ptr getelementptr ([[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 2), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP37]], ptr [[TMP36]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = getelementptr i32, ptr [[TMP33]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP39:%.*]] = load i32, ptr getelementptr ([[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 3), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP39]], ptr [[TMP38]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP31]], ptr [[TMP18]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; LOWERRAYTRACINGPIPELINE-NEXT: br label [[DOTSPLIT9:%.*]]
; LOWERRAYTRACINGPIPELINE: .split9:
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP41:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[T3]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[DIS_DATA_I5:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[TMP42]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP40:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[T3]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[DIS_DATA_I5:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[TMP41]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYS_DATA_I6:%.*]] = insertvalue [[STRUCT_SYSTEMDATA]] undef, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I5]], 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TRAV_DATA_I7:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] undef, [[STRUCT_SYSTEMDATA]] [[SYS_DATA_I6]], 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TRAV_DATA2_I8:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I7]], i64 -1, 5
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP43:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP45:%.*]] = add i32 [[TMP44]], -16
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP45]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP42:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP43:%.*]] = load i32, ptr [[TMP42]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP44:%.*]] = add i32 [[TMP43]], -16
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP44]], ptr @PAYLOAD, align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT_LARGEPAYLOAD]], ptr [[P3]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP47:%.*]] = getelementptr i32, ptr [[TMP46]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP48:%.*]] = getelementptr i32, ptr [[TMP47]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP49:%.*]] = load i32, ptr [[TMP48]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP49]], ptr getelementptr inbounds ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 1), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP50:%.*]] = getelementptr i32, ptr [[TMP47]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP51:%.*]] = load i32, ptr [[TMP50]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP51]], ptr getelementptr ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 2), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP52:%.*]] = getelementptr i32, ptr [[TMP47]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP53:%.*]] = load i32, ptr [[TMP52]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP53]], ptr getelementptr ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 3), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP54:%.*]] = getelementptr i32, ptr [[TMP47]], i64 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP55:%.*]] = load i32, ptr [[TMP54]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP55]], ptr getelementptr ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 4), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP56:%.*]] = getelementptr i32, ptr [[TMP47]], i64 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP57:%.*]] = load i32, ptr [[TMP56]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP57]], ptr getelementptr ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 5), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP58:%.*]] = call ptr inttoptr (i64 4 to ptr)([[STRUCT_TRAVERSALDATA]] [[TRAV_DATA2_I8]]), !continuation.registercount [[META14]], !continuation.returnedRegistercount !14
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP59:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @await.struct.DispatchSystemData(ptr [[TMP58]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_LARGEPAYLOAD]], ptr [[P3]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP46:%.*]] = getelementptr i32, ptr [[TMP45]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP47:%.*]] = getelementptr i32, ptr [[TMP46]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP48:%.*]] = load i32, ptr [[TMP47]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP48]], ptr getelementptr inbounds ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 1), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP49:%.*]] = getelementptr i32, ptr [[TMP46]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP50:%.*]] = load i32, ptr [[TMP49]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP50]], ptr getelementptr ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 2), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP51:%.*]] = getelementptr i32, ptr [[TMP46]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP52:%.*]] = load i32, ptr [[TMP51]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP52]], ptr getelementptr ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 3), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP53:%.*]] = getelementptr i32, ptr [[TMP46]], i64 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP54:%.*]] = load i32, ptr [[TMP53]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP54]], ptr getelementptr ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 4), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP55:%.*]] = getelementptr i32, ptr [[TMP46]], i64 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP56:%.*]] = load i32, ptr [[TMP55]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP56]], ptr getelementptr ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 5), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP57:%.*]] = call ptr inttoptr (i64 4 to ptr)([[STRUCT_TRAVERSALDATA]] [[TRAV_DATA2_I8]]), !continuation.registercount [[META14]], !continuation.returnedRegistercount !14
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP58:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @await.struct.DispatchSystemData(ptr [[TMP57]])
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_LARGEPAYLOAD]] poison, ptr [[P3]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT_LARGEPAYLOAD]], ptr [[P3]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP61:%.*]] = getelementptr i32, ptr [[TMP60]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP62:%.*]] = getelementptr i32, ptr [[TMP61]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP63:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 1), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP63]], ptr [[TMP62]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr [[TMP61]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP65:%.*]] = load i32, ptr getelementptr ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 2), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP65]], ptr [[TMP64]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP66:%.*]] = getelementptr i32, ptr [[TMP61]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP67:%.*]] = load i32, ptr getelementptr ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 3), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP67]], ptr [[TMP66]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP68:%.*]] = getelementptr i32, ptr [[TMP61]], i64 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP69:%.*]] = load i32, ptr getelementptr ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 4), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP69]], ptr [[TMP68]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP70:%.*]] = getelementptr i32, ptr [[TMP61]], i64 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP71:%.*]] = load i32, ptr getelementptr ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 5), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP71]], ptr [[TMP70]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP59]], ptr [[TMP42]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT_LARGEPAYLOAD]], ptr [[P3]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP60:%.*]] = getelementptr i32, ptr [[TMP59]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP61:%.*]] = getelementptr i32, ptr [[TMP60]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP62:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 1), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP62]], ptr [[TMP61]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP63:%.*]] = getelementptr i32, ptr [[TMP60]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP64:%.*]] = load i32, ptr getelementptr ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 2), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP64]], ptr [[TMP63]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP65:%.*]] = getelementptr i32, ptr [[TMP60]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP66:%.*]] = load i32, ptr getelementptr ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 3), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP66]], ptr [[TMP65]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP67:%.*]] = getelementptr i32, ptr [[TMP60]], i64 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP68:%.*]] = load i32, ptr getelementptr ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 4), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP68]], ptr [[TMP67]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP69:%.*]] = getelementptr i32, ptr [[TMP60]], i64 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP70:%.*]] = load i32, ptr getelementptr ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 5), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP70]], ptr [[TMP69]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP58]], ptr [[TMP41]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; LOWERRAYTRACINGPIPELINE-NEXT: br label [[DOTSPLIT:%.*]]
; LOWERRAYTRACINGPIPELINE: .split:
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT_SMALLPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP73:%.*]] = load [1 x i32], ptr [[TMP72]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store [1 x i32] [[TMP73]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP74:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP75:%.*]] = load i32, ptr [[TMP74]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP76:%.*]] = add i32 [[TMP75]], -16
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP76]], ptr [[TMP74]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP78:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[TMP77]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP78]], !continuation.registercount [[META18]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT_SMALLPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP72:%.*]] = load [1 x i32], ptr [[TMP71]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [1 x i32] [[TMP72]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP73:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP74:%.*]] = load i32, ptr [[TMP73]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP75:%.*]] = add i32 [[TMP74]], -16
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP75]], ptr [[TMP73]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP77:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[TMP76]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP77]], !continuation.registercount [[META18]]
;
;
; LOWERRAYTRACINGPIPELINE-LABEL: define i32 @_cont_GetLocalRootIndex(
@@ -306,30 +305,29 @@ attributes #3 = { nounwind memory(none) }
;
;
; DXILCONTPOSTPROCESS-LABEL: define void @Miss(
-; DXILCONTPOSTPROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) !continuation.maxHitAttributeBytes !15 !lgc.rt.shaderstage [[META16:![0-9]+]] !continuation.registercount [[META17:![0-9]+]] !continuation [[META18:![0-9]+]] !continuation.stacksize [[META19:![0-9]+]] !continuation.state [[META20:![0-9]+]] {
+; DXILCONTPOSTPROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.attribute.size !15 !lgc.rt.shaderstage [[META16:![0-9]+]] !continuation.registercount [[META17:![0-9]+]] !continuation [[META18:![0-9]+]] !continuation.stacksize [[META19:![0-9]+]] !continuation.state [[META20:![0-9]+]] {
; DXILCONTPOSTPROCESS-NEXT: AllocaSpillBB:
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [3 x i32], align 4
; DXILCONTPOSTPROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[MISS_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = load [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP1]], 0, 0
-; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], 16
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP3]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [1 x i32] poison, i32 [[TMP4]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP2]], i64 16
+; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[MISS_FRAME:%.*]], ptr addrspace(21) [[TMP3]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: store i64 [[RETURNADDR]], ptr addrspace(21) [[RETURNADDR_SPILL_ADDR]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP0]], 0, 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], 16
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP5]], ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [1 x i32] poison, i32 [[TMP6]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [1 x i32] [[DOTFCA_0_INSERT]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT_SPILL_ADDR:%.*]] = getelementptr inbounds [[MISS_FRAME]], ptr [[CONT_STATE]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_0_EXTRACT]], ptr [[DOTFCA_0_EXTRACT_SPILL_ADDR]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT_SPILL_ADDR:%.*]] = getelementptr inbounds [[MISS_FRAME]], ptr addrspace(21) [[TMP3]], i32 0, i32 1
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_0_EXTRACT]], ptr addrspace(21) [[DOTFCA_0_EXTRACT_SPILL_ADDR]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; DXILCONTPOSTPROCESS-NEXT: [[T1:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
; DXILCONTPOSTPROCESS-NEXT: [[T2:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[T1]])
; DXILCONTPOSTPROCESS-NEXT: [[T3:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[T2]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
-; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[T3]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[T3]])
; DXILCONTPOSTPROCESS-NEXT: [[DIS_DATA_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA:%.*]] poison, <3 x i32> [[DOTFCA_0_0_EXTRACT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[SYS_DATA_I:%.*]] = insertvalue [[STRUCT_SYSTEMDATA]] undef, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I_FCA_0_INSERT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[TRAV_DATA_I:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA:%.*]] undef, [[STRUCT_SYSTEMDATA]] [[SYS_DATA_I]], 0
@@ -337,258 +335,174 @@ attributes #3 = { nounwind memory(none) }
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT30:%.*]] = insertvalue [1 x i32] poison, i32 0, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT30_FCA_0_EXTRACT:%.*]] = extractvalue [1 x i32] [[DOTFCA_0_INSERT30]], 0
; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_0_INSERT30_FCA_0_EXTRACT]], ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], 12
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP7]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = inttoptr i32 [[TMP6]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i32], ptr addrspace(21) [[TMP8]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP9]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP11]], ptr addrspace(21) [[TMP10]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i32], ptr addrspace(21) [[TMP8]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP12]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP14]], ptr addrspace(21) [[TMP13]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i32], ptr addrspace(21) [[TMP8]], i32 0, i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP15]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP17]], ptr addrspace(21) [[TMP16]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP19:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @Miss.resume.0 to i64))
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 4, i32 [[TMP18]], i64 [[TMP19]], [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA2_I]]), !continuation.registercount [[META17]], !continuation.returnedRegistercount !17
+; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = add i32 [[TMP8]], 12
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP9]], ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @Miss.resume.0 to i64))
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 4, i32 [[TMP10]], i64 [[TMP11]], [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA2_I]]), !continuation.registercount [[META17]], !continuation.returnedRegistercount !17
; DXILCONTPOSTPROCESS-NEXT: unreachable
;
;
; DXILCONTPOSTPROCESS-LABEL: define dso_local void @Miss.resume.0(
-; DXILCONTPOSTPROCESS-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !continuation.maxHitAttributeBytes !15 !lgc.rt.shaderstage [[META16]] !continuation.registercount [[META17]] !continuation [[META18]] {
+; DXILCONTPOSTPROCESS-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.attribute.size !15 !lgc.rt.shaderstage [[META16]] !continuation.registercount [[META17]] !continuation [[META18]] {
; DXILCONTPOSTPROCESS-NEXT: entryresume.0:
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [3 x i32], align 4
; DXILCONTPOSTPROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA]], align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP0]], ptr [[CSP]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP3]], i64 -12
-; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(21) [[TMP5]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(21) [[TMP8]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(21) [[TMP11]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP13]], ptr [[TMP12]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = add i32 [[TMP14]], -12
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP15]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [1 x i32] poison, i32 [[TMP16]], 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], -12
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP3]], ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP4]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP5]], i64 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [1 x i32] poison, i32 [[TMP7]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT32:%.*]] = extractvalue [1 x i32] [[DOTFCA_0_INSERT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT13:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; DXILCONTPOSTPROCESS-NEXT: [[T110:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
; DXILCONTPOSTPROCESS-NEXT: [[T29:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[T110]])
; DXILCONTPOSTPROCESS-NEXT: [[T38:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[T29]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
-; DXILCONTPOSTPROCESS-NEXT: [[TMP17:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[T38]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[T38]])
; DXILCONTPOSTPROCESS-NEXT: [[DIS_DATA_I1_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, <3 x i32> [[DOTFCA_0_EXTRACT13]], 0
; DXILCONTPOSTPROCESS-NEXT: [[SYS_DATA_I2:%.*]] = insertvalue [[STRUCT_SYSTEMDATA:%.*]] undef, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I1_FCA_0_INSERT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[TRAV_DATA_I3:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA:%.*]] undef, [[STRUCT_SYSTEMDATA]] [[SYS_DATA_I2]], 0
; DXILCONTPOSTPROCESS-NEXT: [[TRAV_DATA2_I4:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I3]], i64 -1, 5
-; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP19:%.*]] = add i32 [[TMP18]], -16
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP19]], ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = add i32 [[TMP9]], -16
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP10]], ptr addrspace(20) @REGISTERS, align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 0, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 1) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP21:%.*]] = inttoptr i32 [[TMP20]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP21]], i32 -2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP23:%.*]] = getelementptr [[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP22]], i32 0, i32 0, i64 2
-; DXILCONTPOSTPROCESS-NEXT: store i32 0, ptr addrspace(21) [[TMP23]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP24:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP25:%.*]] = inttoptr i32 [[TMP24]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP25]], i32 -2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP26]], i32 0, i32 0, i64 3
-; DXILCONTPOSTPROCESS-NEXT: store i32 0, ptr addrspace(21) [[TMP27]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP28:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP29:%.*]] = add i32 [[TMP28]], 12
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP29]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP30:%.*]] = inttoptr i32 [[TMP28]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x i32], ptr addrspace(21) [[TMP30]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP33:%.*]] = load i32, ptr [[TMP31]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP33]], ptr addrspace(21) [[TMP32]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i32], ptr addrspace(21) [[TMP30]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP34]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP36]], ptr addrspace(21) [[TMP35]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i32], ptr addrspace(21) [[TMP30]], i32 0, i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP39:%.*]] = load i32, ptr [[TMP37]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP39]], ptr addrspace(21) [[TMP38]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP40:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP41:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @Miss.resume.1 to i64))
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 4, i32 [[TMP40]], i64 [[TMP41]], [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA2_I4]]), !continuation.registercount [[META13:![0-9]+]], !continuation.returnedRegistercount !13
+; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = inttoptr i32 [[TMP11]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP12]], i32 -2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = getelementptr [[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP13]], i32 0, i32 0, i64 2
+; DXILCONTPOSTPROCESS-NEXT: store i32 0, ptr addrspace(21) [[TMP14]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = inttoptr i32 [[TMP15]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP16]], i32 -2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = getelementptr [[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP17]], i32 0, i32 0, i64 3
+; DXILCONTPOSTPROCESS-NEXT: store i32 0, ptr addrspace(21) [[TMP18]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP19:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP20:%.*]] = add i32 [[TMP19]], 12
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP20]], ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP21:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP22:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @Miss.resume.1 to i64))
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 4, i32 [[TMP21]], i64 [[TMP22]], [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA2_I4]]), !continuation.registercount [[META13:![0-9]+]], !continuation.returnedRegistercount !13
; DXILCONTPOSTPROCESS-NEXT: unreachable
;
;
; DXILCONTPOSTPROCESS-LABEL: define dso_local void @Miss.resume.1(
-; DXILCONTPOSTPROCESS-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !continuation.maxHitAttributeBytes !15 !lgc.rt.shaderstage [[META16]] !continuation.registercount [[META13]] !continuation [[META18]] {
+; DXILCONTPOSTPROCESS-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.attribute.size !15 !lgc.rt.shaderstage [[META16]] !continuation.registercount [[META13]] !continuation [[META18]] {
; DXILCONTPOSTPROCESS-NEXT: entryresume.1:
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [3 x i32], align 4
; DXILCONTPOSTPROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA]], align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP0]], ptr [[CSP]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP3]], i64 -12
-; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(21) [[TMP5]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(21) [[TMP8]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(21) [[TMP11]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP13]], ptr [[TMP12]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = add i32 [[TMP14]], -12
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP15]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 1) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = inttoptr i32 [[TMP17]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP19:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP18]], i32 -2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP20:%.*]] = getelementptr [[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP19]], i32 0, i32 0, i64 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(21) [[TMP20]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP22:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP22]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP23]], i32 -2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP25:%.*]] = getelementptr [[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP24]], i32 0, i32 0, i64 3
-; DXILCONTPOSTPROCESS-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(21) [[TMP25]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], -12
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP3]], ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP4]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP5]], i64 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 1) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP8]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP9]], i32 -2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = getelementptr [[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP10]], i32 0, i32 0, i64 2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(21) [[TMP11]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = inttoptr i32 [[TMP13]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP14]], i32 -2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = getelementptr [[STRUCT_MEDIUMPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP15]], i32 0, i32 0, i64 3
+; DXILCONTPOSTPROCESS-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(21) [[TMP16]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT15:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; DXILCONTPOSTPROCESS-NEXT: [[T17:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
; DXILCONTPOSTPROCESS-NEXT: [[T26:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[T17]])
; DXILCONTPOSTPROCESS-NEXT: [[T35:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[T26]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
-; DXILCONTPOSTPROCESS-NEXT: [[TMP27:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[T35]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[T35]])
; DXILCONTPOSTPROCESS-NEXT: [[DIS_DATA_I5_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, <3 x i32> [[DOTFCA_0_EXTRACT15]], 0
; DXILCONTPOSTPROCESS-NEXT: [[SYS_DATA_I6:%.*]] = insertvalue [[STRUCT_SYSTEMDATA:%.*]] undef, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I5_FCA_0_INSERT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[TRAV_DATA_I7:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA:%.*]] undef, [[STRUCT_SYSTEMDATA]] [[SYS_DATA_I6]], 0
; DXILCONTPOSTPROCESS-NEXT: [[TRAV_DATA2_I8:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I7]], i64 -1, 5
-; DXILCONTPOSTPROCESS-NEXT: [[TMP28:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP29:%.*]] = add i32 [[TMP28]], -16
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP29]], ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP19:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP20:%.*]] = add i32 [[TMP19]], -16
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP20]], ptr addrspace(20) @REGISTERS, align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 0, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 1) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP30:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP31:%.*]] = inttoptr i32 [[TMP30]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP32:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP31]], i32 -2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP33:%.*]] = getelementptr [[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP32]], i32 0, i32 0, i64 2
-; DXILCONTPOSTPROCESS-NEXT: store i32 0, ptr addrspace(21) [[TMP33]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP34:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP35:%.*]] = inttoptr i32 [[TMP34]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP36:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP35]], i32 -2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP37:%.*]] = getelementptr [[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP36]], i32 0, i32 0, i64 3
-; DXILCONTPOSTPROCESS-NEXT: store i32 0, ptr addrspace(21) [[TMP37]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP38:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP39:%.*]] = inttoptr i32 [[TMP38]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP40:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP39]], i32 -2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP41:%.*]] = getelementptr [[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP40]], i32 0, i32 0, i64 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 0, ptr addrspace(21) [[TMP41]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP42:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP43:%.*]] = inttoptr i32 [[TMP42]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP44:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP43]], i32 -2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP45:%.*]] = getelementptr [[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP44]], i32 0, i32 0, i64 5
-; DXILCONTPOSTPROCESS-NEXT: store i32 0, ptr addrspace(21) [[TMP45]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP46:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP47:%.*]] = add i32 [[TMP46]], 12
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP47]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP48:%.*]] = inttoptr i32 [[TMP46]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP50:%.*]] = getelementptr inbounds [3 x i32], ptr addrspace(21) [[TMP48]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP51:%.*]] = load i32, ptr [[TMP49]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP51]], ptr addrspace(21) [[TMP50]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP53:%.*]] = getelementptr inbounds [3 x i32], ptr addrspace(21) [[TMP48]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP54:%.*]] = load i32, ptr [[TMP52]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP54]], ptr addrspace(21) [[TMP53]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP55:%.*]] = getelementptr inbounds [3 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i32], ptr addrspace(21) [[TMP48]], i32 0, i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP57:%.*]] = load i32, ptr [[TMP55]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP57]], ptr addrspace(21) [[TMP56]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP58:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP59:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @Miss.resume.2 to i64))
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 4, i32 [[TMP58]], i64 [[TMP59]], [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA2_I8]]), !continuation.registercount [[META13]], !continuation.returnedRegistercount !13
+; DXILCONTPOSTPROCESS-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP22:%.*]] = inttoptr i32 [[TMP21]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP23:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP22]], i32 -2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP24:%.*]] = getelementptr [[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP23]], i32 0, i32 0, i64 2
+; DXILCONTPOSTPROCESS-NEXT: store i32 0, ptr addrspace(21) [[TMP24]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP25:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP26:%.*]] = inttoptr i32 [[TMP25]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP27:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP26]], i32 -2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP28:%.*]] = getelementptr [[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP27]], i32 0, i32 0, i64 3
+; DXILCONTPOSTPROCESS-NEXT: store i32 0, ptr addrspace(21) [[TMP28]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP29:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP30:%.*]] = inttoptr i32 [[TMP29]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP31:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP30]], i32 -2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP32:%.*]] = getelementptr [[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP31]], i32 0, i32 0, i64 4
+; DXILCONTPOSTPROCESS-NEXT: store i32 0, ptr addrspace(21) [[TMP32]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP33:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP34:%.*]] = inttoptr i32 [[TMP33]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP35:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP34]], i32 -2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP36:%.*]] = getelementptr [[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP35]], i32 0, i32 0, i64 5
+; DXILCONTPOSTPROCESS-NEXT: store i32 0, ptr addrspace(21) [[TMP36]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP37:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP38:%.*]] = add i32 [[TMP37]], 12
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP38]], ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP39:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP40:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @Miss.resume.2 to i64))
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 4, i32 [[TMP39]], i64 [[TMP40]], [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA2_I8]]), !continuation.registercount [[META13]], !continuation.returnedRegistercount !13
; DXILCONTPOSTPROCESS-NEXT: unreachable
;
;
; DXILCONTPOSTPROCESS-LABEL: define dso_local void @Miss.resume.2(
-; DXILCONTPOSTPROCESS-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !continuation.maxHitAttributeBytes !15 !lgc.rt.shaderstage [[META16]] !continuation.registercount [[META13]] !continuation [[META18]] {
+; DXILCONTPOSTPROCESS-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.attribute.size !15 !lgc.rt.shaderstage [[META16]] !continuation.registercount [[META13]] !continuation [[META18]] {
; DXILCONTPOSTPROCESS-NEXT: entryresume.2:
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [3 x i32], align 4
; DXILCONTPOSTPROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA]], align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP0]], ptr [[CSP]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP3]], i64 -12
-; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(21) [[TMP5]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(21) [[TMP8]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(21) [[TMP11]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP13]], ptr [[TMP12]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = add i32 [[TMP14]], -12
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP15]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 1) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = inttoptr i32 [[TMP17]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP19:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP18]], i32 -2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP20:%.*]] = getelementptr [[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP19]], i32 0, i32 0, i64 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(21) [[TMP20]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP22:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP22]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP23]], i32 -2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP25:%.*]] = getelementptr [[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP24]], i32 0, i32 0, i64 3
-; DXILCONTPOSTPROCESS-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(21) [[TMP25]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP27:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP28:%.*]] = inttoptr i32 [[TMP27]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP28]], i32 -2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP29]], i32 0, i32 0, i64 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(21) [[TMP30]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP32:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP33:%.*]] = inttoptr i32 [[TMP32]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP34:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP33]], i32 -2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP35:%.*]] = getelementptr [[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP34]], i32 0, i32 0, i64 5
-; DXILCONTPOSTPROCESS-NEXT: [[TMP36:%.*]] = load i32, ptr addrspace(21) [[TMP35]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], -12
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP3]], ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP4]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP5]], i64 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 1) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP8]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP9]], i32 -2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = getelementptr [[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP10]], i32 0, i32 0, i64 2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(21) [[TMP11]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = inttoptr i32 [[TMP13]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP14]], i32 -2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = getelementptr [[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP15]], i32 0, i32 0, i64 3
+; DXILCONTPOSTPROCESS-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(21) [[TMP16]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP19:%.*]] = inttoptr i32 [[TMP18]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP19]], i32 -2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP21:%.*]] = getelementptr [[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP20]], i32 0, i32 0, i64 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP22:%.*]] = load i32, ptr addrspace(21) [[TMP21]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP23:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP24:%.*]] = inttoptr i32 [[TMP23]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP24]], i32 -2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP26:%.*]] = getelementptr [[STRUCT_LARGEPAYLOAD_ATTR_MAX_2_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP25]], i32 0, i32 0, i64 5
+; DXILCONTPOSTPROCESS-NEXT: [[TMP27:%.*]] = load i32, ptr addrspace(21) [[TMP26]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT17:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT_RELOAD_ADDR:%.*]] = getelementptr inbounds [[MISS_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT_RELOAD:%.*]] = load i32, ptr [[DOTFCA_0_EXTRACT_RELOAD_ADDR]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[MISS_FRAME]], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr [[RETURNADDR_RELOAD_ADDR]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT_RELOAD_ADDR:%.*]] = getelementptr inbounds [[MISS_FRAME:%.*]], ptr addrspace(21) [[TMP6]], i32 0, i32 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT_RELOAD:%.*]] = load i32, ptr addrspace(21) [[DOTFCA_0_EXTRACT_RELOAD_ADDR]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[MISS_FRAME]], ptr addrspace(21) [[TMP6]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr addrspace(21) [[RETURNADDR_RELOAD_ADDR]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [1 x i32] poison, i32 [[DOTFCA_0_EXTRACT_RELOAD]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT_FCA_0_EXTRACT:%.*]] = extractvalue [1 x i32] [[DOTFCA_0_INSERT]], 0
; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_0_INSERT_FCA_0_EXTRACT]], ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP37:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP38:%.*]] = add i32 [[TMP37]], -16
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP38]], ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP28:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP29:%.*]] = add i32 [[TMP28]], -16
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP29]], ptr [[CSP]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT12:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, <3 x i32> [[DOTFCA_0_EXTRACT17]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP39:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP39]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT12]]), !continuation.registercount [[META17]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP30:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP30]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT12]]), !continuation.registercount [[META17]]
; DXILCONTPOSTPROCESS-NEXT: unreachable
;
;
diff --git a/shared/continuations/test/dx/lower-rt-pipeline-simple-call-shader.ll b/shared/continuations/test/dx/lower-rt-pipeline-simple-call-shader.ll
index 6b1f8dfd0b..16f794a3e2 100644
--- a/shared/continuations/test/dx/lower-rt-pipeline-simple-call-shader.ll
+++ b/shared/continuations/test/dx/lower-rt-pipeline-simple-call-shader.ll
@@ -41,6 +41,12 @@ define i32 @_cont_GetLocalRootIndex(%struct.DispatchSystemData* %data) !types !1
ret i32 5
}
+; Function Attrs: nounwind memory(none)
+declare !types !22 <3 x i32> @_cont_DispatchRaysIndex3(%struct.DispatchSystemData* nocapture readnone %data) #1
+
+; Function Attrs: nounwind memory(none)
+declare !types !22 <3 x i32> @_cont_DispatchRaysDimensions3(%struct.DispatchSystemData* nocapture readnone %data) #1
+
define void @_cont_CallShader(%struct.DispatchSystemData* %data, i32 %0) #1 !types !18 {
%dis_data = load %struct.DispatchSystemData, %struct.DispatchSystemData* %data, align 4
%newdata = call %struct.DispatchSystemData @_AmdAwaitShader(i64 2, %struct.DispatchSystemData %dis_data)
@@ -51,12 +57,19 @@ define void @_cont_CallShader(%struct.DispatchSystemData* %data, i32 %0) #1 !typ
define void @called(%struct.MyParams* %params) !types !19 {
call void @dx.op.callShader.struct.MyParams(i32 159, i32 2, %struct.MyParams* nonnull %params)
+ %a = call i32 @dx.op.dispatchRaysIndex.i32(i32 145, i8 0)
+ %b = call i32 @dx.op.dispatchRaysDimensions.i32(i32 146, i8 0)
ret void
}
; Function Attrs: nounwind
declare !types !21 void @dx.op.callShader.struct.MyParams(i32, i32, %struct.MyParams*) #0
+; Function Attrs: nounwind memory(none)
+declare i32 @dx.op.dispatchRaysDimensions.i32(i32, i8) #1
+
+; Function Attrs: nounwind memory(none)
+declare i32 @dx.op.dispatchRaysIndex.i32(i32, i8) #1
attributes #0 = { nounwind }
attributes #1 = { alwaysinline }
@@ -89,6 +102,8 @@ attributes #1 = { alwaysinline }
!19 = !{!"function", !"void", !20}
!20 = !{i32 0, %struct.MyParams poison}
!21 = !{!"function", !"void", i32 poison, i32 poison, !20}
+!22 = !{!"function", <3 x i32> poison, !16}
+
; LOWERRAYTRACINGPIPELINE-LABEL: define i32 @_cont_GetLocalRootIndex(
; LOWERRAYTRACINGPIPELINE-SAME: ptr [[DATA:%.*]]) {
; LOWERRAYTRACINGPIPELINE-NEXT: ret i32 5
@@ -98,33 +113,36 @@ attributes #1 = { alwaysinline }
; LOWERRAYTRACINGPIPELINE-SAME: [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage [[META16:![0-9]+]] !continuation.registercount [[META17:![0-9]+]] !continuation [[META18:![0-9]+]] {
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP2:%.*]] = alloca [[STRUCT_MYPARAMS:%.*]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP3]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_MYPARAMS]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = load i32, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP5]], ptr [[TMP4]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_MYPARAMS]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = load i32, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP4]], ptr [[TMP3]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; LOWERRAYTRACINGPIPELINE-NEXT: [[DIS_DATA_I:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_MYPARAMS]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP7]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = call ptr inttoptr (i64 2 to ptr)([[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I]]), !continuation.registercount [[META17]], !continuation.returnedRegistercount !17
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @await.struct.DispatchSystemData(ptr [[TMP8]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_MYPARAMS]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP6]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = call ptr inttoptr (i64 2 to ptr)([[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I]]), !continuation.registercount [[META17]], !continuation.returnedRegistercount !17
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @await.struct.DispatchSystemData(ptr [[TMP7]])
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_MYPARAMS]] poison, ptr [[TMP2]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_MYPARAMS]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = load i32, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP11]], ptr [[TMP10]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP9]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_MYPARAMS]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = load i32, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP8]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; LOWERRAYTRACINGPIPELINE-NEXT: br label [[DOTSPLIT:%.*]]
; LOWERRAYTRACINGPIPELINE: .split:
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = call <3 x i32> @lgc.rt.dispatch.rays.index()
+; LOWERRAYTRACINGPIPELINE-NEXT: [[A:%.*]] = extractelement <3 x i32> [[TMP11]], i8 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = call <3 x i32> @lgc.rt.dispatch.rays.dimensions()
+; LOWERRAYTRACINGPIPELINE-NEXT: [[B:%.*]] = extractelement <3 x i32> [[TMP12]], i8 0
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_MYPARAMS]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP13]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP14]], !continuation.registercount [[META17]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_MYPARAMS]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP14]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP15]], !continuation.registercount [[META17]]
;
;
; CLEANUP-LABEL: define i32 @_cont_GetLocalRootIndex(
@@ -135,66 +153,54 @@ attributes #1 = { alwaysinline }
; CLEANUP-LABEL: define void @called(
; CLEANUP-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage [[META16:![0-9]+]] !continuation.registercount [[META17:![0-9]+]] !continuation [[META18:![0-9]+]] !continuation.state [[META19:![0-9]+]] !continuation.stacksize [[META19]] {
; CLEANUP-NEXT: AllocaSpillBB:
-; CLEANUP-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
-; CLEANUP-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[CALLED_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANUP-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
-; CLEANUP-NEXT: [[TMP1:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; CLEANUP-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
-; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; CLEANUP-NEXT: [[TMP2:%.*]] = load i32, ptr @PAYLOAD, align 4
+; CLEANUP-NEXT: [[TMP1:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
+; CLEANUP-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(21)
+; CLEANUP-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP3]], i64 0
+; CLEANUP-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[CALLED_FRAME:%.*]], ptr addrspace(21) [[TMP4]], i32 0, i32 0
+; CLEANUP-NEXT: store i64 [[RETURNADDR]], ptr addrspace(21) [[RETURNADDR_SPILL_ADDR]], align 4
+; CLEANUP-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], 0
+; CLEANUP-NEXT: [[TMP5:%.*]] = load i32, ptr @PAYLOAD, align 4
; CLEANUP-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
+; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; CLEANUP-NEXT: [[DIS_DATA_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, i32 [[DOTFCA_0_EXTRACT]], 0
-; CLEANUP-NEXT: store i32 [[TMP2]], ptr @PAYLOAD, align 4
-; CLEANUP-NEXT: [[TMP3:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANUP-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-; CLEANUP-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], 8
-; CLEANUP-NEXT: store i32 [[TMP5]], ptr [[TMP3]], align 4
-; CLEANUP-NEXT: [[TMP6:%.*]] = inttoptr i32 [[TMP4]] to ptr addrspace(21)
-; CLEANUP-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANUP-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP6]], i32 0, i32 0
-; CLEANUP-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4
-; CLEANUP-NEXT: store i32 [[TMP9]], ptr addrspace(21) [[TMP8]], align 4
-; CLEANUP-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CLEANUP-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP6]], i32 0, i32 1
-; CLEANUP-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP10]], align 4
-; CLEANUP-NEXT: store i32 [[TMP12]], ptr addrspace(21) [[TMP11]], align 4
-; CLEANUP-NEXT: [[TMP13:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANUP-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
-; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 2, i32 [[TMP14]], i64 ptrtoint (ptr @called.resume.0 to i64), [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I_FCA_0_INSERT]]), !continuation.registercount [[META17]], !continuation.returnedRegistercount !17
+; CLEANUP-NEXT: store i32 [[TMP5]], ptr @PAYLOAD, align 4
+; CLEANUP-NEXT: [[TMP6:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+; CLEANUP-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], 8
+; CLEANUP-NEXT: store i32 [[TMP8]], ptr [[TMP6]], align 4
+; CLEANUP-NEXT: [[TMP9:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
+; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 2, i32 [[TMP10]], i64 ptrtoint (ptr @called.resume.0 to i64), [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I_FCA_0_INSERT]]), !continuation.registercount [[META17]], !continuation.returnedRegistercount !17
; CLEANUP-NEXT: unreachable
;
;
; CLEANUP-LABEL: define dso_local void @called.resume.0(
; CLEANUP-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.shaderstage [[META16]] !continuation.registercount [[META17]] !continuation [[META18]] {
; CLEANUP-NEXT: entryresume.0:
-; CLEANUP-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
; CLEANUP-NEXT: [[TMP2:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CLEANUP-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-; CLEANUP-NEXT: [[TMP4:%.*]] = inttoptr i32 [[TMP3]] to ptr addrspace(21)
-; CLEANUP-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP4]], i64 -8
-; CLEANUP-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP5]], i32 0, i32 0
-; CLEANUP-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANUP-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(21) [[TMP6]], align 4
-; CLEANUP-NEXT: store i32 [[TMP8]], ptr [[TMP7]], align 4
-; CLEANUP-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP5]], i32 0, i32 1
-; CLEANUP-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CLEANUP-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(21) [[TMP9]], align 4
-; CLEANUP-NEXT: store i32 [[TMP11]], ptr [[TMP10]], align 4
-; CLEANUP-NEXT: [[TMP12:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANUP-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4
-; CLEANUP-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], -8
-; CLEANUP-NEXT: store i32 [[TMP14]], ptr [[TMP12]], align 4
-; CLEANUP-NEXT: [[TMP15:%.*]] = load i32, ptr @PAYLOAD, align 4
+; CLEANUP-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], -8
+; CLEANUP-NEXT: store i32 [[TMP4]], ptr [[TMP2]], align 4
+; CLEANUP-NEXT: [[TMP5:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
+; CLEANUP-NEXT: [[TMP7:%.*]] = inttoptr i32 [[TMP6]] to ptr addrspace(21)
+; CLEANUP-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP7]], i64 0
+; CLEANUP-NEXT: [[TMP9:%.*]] = load i32, ptr @PAYLOAD, align 4
; CLEANUP-NEXT: [[DOTFCA_0_EXTRACT3:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; CLEANUP-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[CALLED_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANUP-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr [[RETURNADDR_RELOAD_ADDR]], align 4
+; CLEANUP-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[CALLED_FRAME:%.*]], ptr addrspace(21) [[TMP8]], i32 0, i32 0
+; CLEANUP-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr addrspace(21) [[RETURNADDR_RELOAD_ADDR]], align 4
+; CLEANUP-NEXT: [[TMP10:%.*]] = call <3 x i32> @lgc.rt.dispatch.rays.index()
+; CLEANUP-NEXT: [[A:%.*]] = extractelement <3 x i32> [[TMP10]], i8 0
+; CLEANUP-NEXT: [[TMP11:%.*]] = call <3 x i32> @lgc.rt.dispatch.rays.dimensions()
+; CLEANUP-NEXT: [[B:%.*]] = extractelement <3 x i32> [[TMP11]], i8 0
; CLEANUP-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; CLEANUP-NEXT: store i32 [[TMP15]], ptr @PAYLOAD, align 4
+; CLEANUP-NEXT: store i32 [[TMP9]], ptr @PAYLOAD, align 4
; CLEANUP-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, i32 [[DOTFCA_0_EXTRACT3]], 0
-; CLEANUP-NEXT: [[TMP16:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANUP-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
-; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP17]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META17]]
+; CLEANUP-NEXT: [[TMP12:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4
+; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP13]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META17]]
; CLEANUP-NEXT: unreachable
;
;
@@ -206,65 +212,52 @@ attributes #1 = { alwaysinline }
; SAVESTATE-LABEL: define void @called(
; SAVESTATE-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage [[META15:![0-9]+]] !continuation.registercount [[META16:![0-9]+]] !continuation [[META17:![0-9]+]] !continuation.state [[META18:![0-9]+]] !continuation.stacksize [[META18]] {
; SAVESTATE-NEXT: AllocaSpillBB:
-; SAVESTATE-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
; SAVESTATE-NEXT: [[CSP:%.*]] = alloca i32, align 4
; SAVESTATE-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
-; SAVESTATE-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[CALLED_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; SAVESTATE-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
-; SAVESTATE-NEXT: [[TMP1:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; SAVESTATE-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
-; SAVESTATE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; SAVESTATE-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(20) @PAYLOAD, align 4
+; SAVESTATE-NEXT: [[TMP1:%.*]] = load i32, ptr [[CSP]], align 4
+; SAVESTATE-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
+; SAVESTATE-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP2]], i64 0
+; SAVESTATE-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[CALLED_FRAME:%.*]], ptr addrspace(21) [[TMP3]], i32 0, i32 0
+; SAVESTATE-NEXT: store i64 [[RETURNADDR]], ptr addrspace(21) [[RETURNADDR_SPILL_ADDR]], align 4
+; SAVESTATE-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], 0
+; SAVESTATE-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(20) @PAYLOAD, align 4
; SAVESTATE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr addrspacecast (ptr addrspace(20) @PAYLOAD to ptr))
+; SAVESTATE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; SAVESTATE-NEXT: [[DIS_DATA_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, i32 [[DOTFCA_0_EXTRACT]], 0
-; SAVESTATE-NEXT: store i32 [[TMP2]], ptr addrspace(20) @PAYLOAD, align 4
-; SAVESTATE-NEXT: [[TMP3:%.*]] = load i32, ptr [[CSP]], align 4
-; SAVESTATE-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], 8
-; SAVESTATE-NEXT: store i32 [[TMP4]], ptr [[CSP]], align 4
-; SAVESTATE-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP3]] to ptr addrspace(21)
-; SAVESTATE-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; SAVESTATE-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP5]], i32 0, i32 0
-; SAVESTATE-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP6]], align 4
-; SAVESTATE-NEXT: store i32 [[TMP8]], ptr addrspace(21) [[TMP7]], align 4
-; SAVESTATE-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; SAVESTATE-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP5]], i32 0, i32 1
-; SAVESTATE-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP9]], align 4
-; SAVESTATE-NEXT: store i32 [[TMP11]], ptr addrspace(21) [[TMP10]], align 4
-; SAVESTATE-NEXT: [[TMP12:%.*]] = load i32, ptr [[CSP]], align 4
-; SAVESTATE-NEXT: call void (i64, ...) @continuation.continue(i64 2, i32 [[TMP12]], i64 ptrtoint (ptr @called.resume.0 to i64), [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I_FCA_0_INSERT]]), !continuation.registercount [[META16]], !continuation.returnedRegistercount !16
+; SAVESTATE-NEXT: store i32 [[TMP4]], ptr addrspace(20) @PAYLOAD, align 4
+; SAVESTATE-NEXT: [[TMP5:%.*]] = load i32, ptr [[CSP]], align 4
+; SAVESTATE-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 8
+; SAVESTATE-NEXT: store i32 [[TMP6]], ptr [[CSP]], align 4
+; SAVESTATE-NEXT: [[TMP7:%.*]] = load i32, ptr [[CSP]], align 4
+; SAVESTATE-NEXT: call void (i64, ...) @continuation.continue(i64 2, i32 [[TMP7]], i64 ptrtoint (ptr @called.resume.0 to i64), [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I_FCA_0_INSERT]]), !continuation.registercount [[META16]], !continuation.returnedRegistercount !16
; SAVESTATE-NEXT: unreachable
;
;
; SAVESTATE-LABEL: define dso_local void @called.resume.0(
; SAVESTATE-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.shaderstage [[META15]] !continuation.registercount [[META16]] !continuation [[META17]] {
; SAVESTATE-NEXT: entryresume.0:
-; SAVESTATE-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
; SAVESTATE-NEXT: [[CSP:%.*]] = alloca i32, align 4
; SAVESTATE-NEXT: store i32 [[TMP0]], ptr [[CSP]], align 4
; SAVESTATE-NEXT: [[TMP2:%.*]] = load i32, ptr [[CSP]], align 4
-; SAVESTATE-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(21)
-; SAVESTATE-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP3]], i64 -8
-; SAVESTATE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 0
-; SAVESTATE-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; SAVESTATE-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(21) [[TMP5]], align 4
-; SAVESTATE-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
-; SAVESTATE-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 1
-; SAVESTATE-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; SAVESTATE-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(21) [[TMP8]], align 4
-; SAVESTATE-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4
-; SAVESTATE-NEXT: [[TMP11:%.*]] = load i32, ptr [[CSP]], align 4
-; SAVESTATE-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], -8
-; SAVESTATE-NEXT: store i32 [[TMP12]], ptr [[CSP]], align 4
-; SAVESTATE-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(20) @PAYLOAD, align 4
+; SAVESTATE-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], -8
+; SAVESTATE-NEXT: store i32 [[TMP3]], ptr [[CSP]], align 4
+; SAVESTATE-NEXT: [[TMP4:%.*]] = load i32, ptr [[CSP]], align 4
+; SAVESTATE-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP4]] to ptr addrspace(21)
+; SAVESTATE-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP5]], i64 0
+; SAVESTATE-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(20) @PAYLOAD, align 4
; SAVESTATE-NEXT: [[DOTFCA_0_EXTRACT3:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
; SAVESTATE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; SAVESTATE-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[CALLED_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; SAVESTATE-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr [[RETURNADDR_RELOAD_ADDR]], align 4
+; SAVESTATE-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[CALLED_FRAME:%.*]], ptr addrspace(21) [[TMP6]], i32 0, i32 0
+; SAVESTATE-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr addrspace(21) [[RETURNADDR_RELOAD_ADDR]], align 4
+; SAVESTATE-NEXT: [[TMP8:%.*]] = call <3 x i32> @lgc.rt.dispatch.rays.index()
+; SAVESTATE-NEXT: [[A:%.*]] = extractelement <3 x i32> [[TMP8]], i8 0
+; SAVESTATE-NEXT: [[TMP9:%.*]] = call <3 x i32> @lgc.rt.dispatch.rays.dimensions()
+; SAVESTATE-NEXT: [[B:%.*]] = extractelement <3 x i32> [[TMP9]], i8 0
; SAVESTATE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr addrspacecast (ptr addrspace(20) @PAYLOAD to ptr))
-; SAVESTATE-NEXT: store i32 [[TMP13]], ptr addrspace(20) @PAYLOAD, align 4
+; SAVESTATE-NEXT: store i32 [[TMP7]], ptr addrspace(20) @PAYLOAD, align 4
; SAVESTATE-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, i32 [[DOTFCA_0_EXTRACT3]], 0
-; SAVESTATE-NEXT: [[TMP14:%.*]] = load i32, ptr [[CSP]], align 4
-; SAVESTATE-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP14]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META16]]
+; SAVESTATE-NEXT: [[TMP10:%.*]] = load i32, ptr [[CSP]], align 4
+; SAVESTATE-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP10]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META16]]
; SAVESTATE-NEXT: unreachable
;
;
@@ -277,28 +270,31 @@ attributes #1 = { alwaysinline }
; LOWERRAYTRACINGPIPELINE-CPS-SAME: {} [[CONT_STATE:%.*]], i32 [[RETURN_ADDR:%.*]], i32 [[SHADER_INDEX:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage [[META16:![0-9]+]] !lgc.cps [[META17:![0-9]+]] !continuation [[META18:![0-9]+]] {
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP2:%.*]] = alloca [[STRUCT_MYPARAMS:%.*]], align 8
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP3:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP3]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[SHADER_INDEX]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[DIS_DATA_I:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_MYPARAMS]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP5]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP6:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] (...) @lgc.cps.await.s_struct.DispatchSystemDatas(i32 2, i32 2, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_MYPARAMS]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP4]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP5:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] (...) @lgc.cps.await.s_struct.DispatchSystemDatas(i32 2, i32 2, i32 5)
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_MYPARAMS]] poison, ptr [[TMP2]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_MYPARAMS]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP8:%.*]] = load i32, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP8]], ptr [[TMP7]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP6]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_MYPARAMS]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP7:%.*]] = load i32, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP5]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: br label [[DOTSPLIT:%.*]]
; LOWERRAYTRACINGPIPELINE-CPS: .split:
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP8:%.*]] = call <3 x i32> @lgc.rt.dispatch.rays.index()
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[A:%.*]] = extractelement <3 x i32> [[TMP8]], i8 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP9:%.*]] = call <3 x i32> @lgc.rt.dispatch.rays.dimensions()
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[B:%.*]] = extractelement <3 x i32> [[TMP9]], i8 0
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_MYPARAMS]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP10]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP11:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 2, {} poison, [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP11]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_MYPARAMS]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP11]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP12:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 2, {} poison, i32 poison, i32 poison, [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP12]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: unreachable
;
;
@@ -313,29 +309,34 @@ attributes #1 = { alwaysinline }
; CLEANUP-CPS-NEXT: [[TMP1:%.*]] = call ptr addrspace(32) @lgc.cps.alloc(i32 8)
; CLEANUP-CPS-NEXT: [[RETURN_ADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[CALLED_FRAME:%.*]], ptr addrspace(32) [[TMP1]], i32 0, i32 0
; CLEANUP-CPS-NEXT: store i32 [[RETURN_ADDR]], ptr addrspace(32) [[RETURN_ADDR_SPILL_ADDR]], align 4
-; CLEANUP-CPS-NEXT: [[TMP2:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; CLEANUP-CPS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP2]], 0
-; CLEANUP-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; CLEANUP-CPS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], 0
+; CLEANUP-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[SHADER_INDEX]])
; CLEANUP-CPS-NEXT: [[DIS_DATA_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, i32 [[DOTFCA_0_EXTRACT]], 0
; CLEANUP-CPS-NEXT: store i32 undef, ptr @PAYLOAD, align 4
-; CLEANUP-CPS-NEXT: [[TMP3:%.*]] = call i32 (...) @lgc.cps.as.continuation.reference(ptr @called.resume.0)
-; CLEANUP-CPS-NEXT: call void (...) @lgc.cps.jump(i32 2, i32 2, {} poison, i32 [[TMP3]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I_FCA_0_INSERT]])
+; CLEANUP-CPS-NEXT: [[TMP2:%.*]] = call i32 (...) @lgc.cps.as.continuation.reference(ptr @called.resume.0)
+; CLEANUP-CPS-NEXT: call void (...) @lgc.cps.jump(i32 2, i32 2, {} poison, i32 [[TMP2]], i32 5)
; CLEANUP-CPS-NEXT: unreachable
;
;
; CLEANUP-CPS-LABEL: define dso_local void @called.resume.0(
-; CLEANUP-CPS-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP2:%.*]]) !lgc.rt.shaderstage [[META16]] !lgc.cps [[META17]] !continuation [[META18]] {
+; CLEANUP-CPS-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP3:%.*]]) !lgc.rt.shaderstage [[META16]] !lgc.cps [[META17]] !continuation [[META18]] {
; CLEANUP-CPS-NEXT: entryresume.0:
-; CLEANUP-CPS-NEXT: [[TMP3:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 8)
-; CLEANUP-CPS-NEXT: [[TMP4:%.*]] = load i32, ptr @PAYLOAD, align 4
-; CLEANUP-CPS-NEXT: [[DOTFCA_0_EXTRACT3:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP2]], 0
+; CLEANUP-CPS-NEXT: [[TMP4:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
+; CLEANUP-CPS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP3]], ptr [[TMP4]], align 4
+; CLEANUP-CPS-NEXT: [[TMP5:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 8)
+; CLEANUP-CPS-NEXT: [[TMP6:%.*]] = load i32, ptr @PAYLOAD, align 4
+; CLEANUP-CPS-NEXT: [[DOTFCA_0_EXTRACT3:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP3]], 0
; CLEANUP-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; CLEANUP-CPS-NEXT: [[RETURN_ADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[CALLED_FRAME:%.*]], ptr addrspace(32) [[TMP3]], i32 0, i32 0
+; CLEANUP-CPS-NEXT: [[RETURN_ADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[CALLED_FRAME:%.*]], ptr addrspace(32) [[TMP5]], i32 0, i32 0
; CLEANUP-CPS-NEXT: [[RETURN_ADDR_RELOAD:%.*]] = load i32, ptr addrspace(32) [[RETURN_ADDR_RELOAD_ADDR]], align 4
+; CLEANUP-CPS-NEXT: [[TMP7:%.*]] = call <3 x i32> @_cont_DispatchRaysIndex3(ptr [[TMP4]])
+; CLEANUP-CPS-NEXT: [[A:%.*]] = extractelement <3 x i32> [[TMP7]], i8 0
+; CLEANUP-CPS-NEXT: [[TMP8:%.*]] = call <3 x i32> @_cont_DispatchRaysDimensions3(ptr [[TMP4]])
+; CLEANUP-CPS-NEXT: [[B:%.*]] = extractelement <3 x i32> [[TMP8]], i8 0
; CLEANUP-CPS-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; CLEANUP-CPS-NEXT: store i32 [[TMP4]], ptr @PAYLOAD, align 4
+; CLEANUP-CPS-NEXT: store i32 [[TMP6]], ptr @PAYLOAD, align 4
; CLEANUP-CPS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, i32 [[DOTFCA_0_EXTRACT3]], 0
; CLEANUP-CPS-NEXT: call void @lgc.cps.free(i32 8)
-; CLEANUP-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR_RELOAD]], i32 2, {} poison, [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]])
+; CLEANUP-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR_RELOAD]], i32 2, {} poison, i32 poison, i32 poison, [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]])
; CLEANUP-CPS-NEXT: unreachable
;
diff --git a/shared/continuations/test/dx/lower-rt-pipeline-small-payload-field.ll b/shared/continuations/test/dx/lower-rt-pipeline-small-payload-field.ll
index b8d80912d3..2f0edc058a 100644
--- a/shared/continuations/test/dx/lower-rt-pipeline-small-payload-field.ll
+++ b/shared/continuations/test/dx/lower-rt-pipeline-small-payload-field.ll
@@ -104,49 +104,48 @@ attributes #3 = { nounwind memory(none) }
!29 = !{i32 0, %struct.AnyHitTraversalData poison}
!30 = !{!"function", i32 poison, !27}
; LOWERRAYTRACINGPIPELINE-LABEL: define %struct.DispatchSystemData @Miss(
-; LOWERRAYTRACINGPIPELINE-SAME: [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] !lgc.rt.shaderstage !20 !continuation.registercount !21 !continuation !22 {
+; LOWERRAYTRACINGPIPELINE-SAME: [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] !lgc.rt.shaderstage [[META20:![0-9]+]] !continuation.registercount [[META21:![0-9]+]] !continuation [[META22:![0-9]+]] {
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP2:%.*]] = alloca [[STRUCT_PAYLOAD:%.*]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = call [[STRUCT_SYSTEMDATA]] @continuations.getSystemData.s_struct.SystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP3]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_PAYLOAD]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[TMP4]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP5]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = load i32, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP4]], i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[TMP8]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_PAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP8]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = load i32, ptr getelementptr ([[STRUCT_PAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP12]], ptr [[TMP11]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP8]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = load i32, ptr getelementptr ([[STRUCT_PAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[TMP8]], i64 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = load i32, ptr getelementptr ([[STRUCT_PAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 10), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP16]], ptr [[TMP15]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_PAYLOAD]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP5]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = load i32, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP8]], ptr [[TMP7]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[TMP5]], i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP9]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_PAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP11]], ptr [[TMP10]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP9]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr ([[STRUCT_PAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP13]], ptr [[TMP12]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP9]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr ([[STRUCT_PAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP9]], i64 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = load i32, ptr getelementptr ([[STRUCT_PAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 10), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP17]], ptr [[TMP16]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_PAYLOAD]], ptr [[TMP2]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: store i16 17, ptr [[TMP17]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_PAYLOAD]], ptr [[TMP2]], i32 0, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: store i16 17, ptr [[TMP18]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_PAYLOAD]], ptr [[TMP2]], i32 0, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = load i16, ptr [[TMP19]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i16 [[TMP20]], ptr getelementptr inbounds ([[STRUCT_PAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 1), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_PAYLOAD]], ptr [[TMP2]], i32 0, i32 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr [[TMP21]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = getelementptr i32, ptr [[TMP22]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP24]], ptr getelementptr inbounds ([[STRUCT_PAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i32 2), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[TMP22]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = load [[TMP0]], ptr [[TMP25]], align 1
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[TMP0]] [[TMP26]], ptr getelementptr ([[STRUCT_PAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 3), align 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP27]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP28]], !continuation.registercount !21
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = load i16, ptr [[TMP18]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i16 [[TMP19]], ptr getelementptr inbounds ([[STRUCT_PAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 1), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_PAYLOAD]], ptr [[TMP2]], i32 0, i32 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[TMP20]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr [[TMP21]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP23]], ptr getelementptr inbounds ([[STRUCT_PAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i32 2), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr [[TMP21]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = load [[TMP0]], ptr [[TMP24]], align 1
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[TMP0]] [[TMP25]], ptr getelementptr ([[STRUCT_PAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 3), align 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP26]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP27]], !continuation.registercount [[META21]]
;
;
; LOWERRAYTRACINGPIPELINE-LABEL: define i32 @_cont_GetLocalRootIndex(
diff --git a/shared/continuations/test/dx/lower-rt-pipeline.ll b/shared/continuations/test/dx/lower-rt-pipeline.ll
index 7645dd3100..5bc2877d82 100644
--- a/shared/continuations/test/dx/lower-rt-pipeline.ll
+++ b/shared/continuations/test/dx/lower-rt-pipeline.ll
@@ -447,12 +447,10 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
;
;
; LOWERRAYTRACINGPIPELINE-LABEL: define void @MyRayGen(
-; LOWERRAYTRACINGPIPELINE-SAME: ) #[[ATTR2:[0-9]+]] !lgc.rt.shaderstage [[META23:![0-9]+]] !continuation.entry [[META14:![0-9]+]] !continuation.registercount [[META23]] !continuation [[META35:![0-9]+]] {
-; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP1:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
+; LOWERRAYTRACINGPIPELINE-SAME: [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] !lgc.rt.shaderstage [[META23:![0-9]+]] !continuation.entry [[META14:![0-9]+]] !continuation.registercount [[META23]] !continuation [[META35:![0-9]+]] {
+; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP2:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 4
@@ -502,8 +500,7 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP33]], ptr [[TMP32]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP22]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[LOCAL_ROOT_INDEX1:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX1]])
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; LOWERRAYTRACINGPIPELINE-NEXT: br label [[DOTSPLIT:%.*]]
; LOWERRAYTRACINGPIPELINE: .split:
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = load <4 x float>, ptr [[TMP6]], align 4, !tbaa [[TBAA36]]
@@ -528,11 +525,9 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[HITATTRS:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = call [[STRUCT_SYSTEMDATA]] @continuations.getSystemData.s_struct.SystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP4]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP5]])
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP4]])
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i64 0
@@ -559,6 +554,7 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 1
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP23]], ptr [[TMP21]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[TMP5]])
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[HITATTRS]], i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = load <2 x float>, ptr [[TMP24]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = extractelement <2 x float> [[TMP25]], i32 0
@@ -607,11 +603,9 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[ORIGHITATTRS:%.*]] = alloca [8 x i32], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[HITATTRSALLOCA:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = call [[STRUCT_ANYHITTRAVERSALDATA]] @continuations.getSystemData.s_struct.AnyHitTraversalDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP13]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP14]])
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP13]])
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP12]], i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP15]], i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[TMP16]], i64 0
@@ -640,6 +634,7 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = load i32, ptr [[TMP32]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP33]], ptr [[TMP31]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP1]], ptr [[HITATTRSALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[TMP14]])
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP12]], i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = load <4 x float>, ptr [[TMP34]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
@@ -853,11 +848,10 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_ANYHITTRAVERSALDATA]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = call [[STRUCT_ANYHITTRAVERSALDATA]] @continuations.getSystemData.s_struct.AnyHitTraversalDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP5]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP6]])
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP5]])
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[TMP6]])
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCandidateState(ptr [[SYSTEM_DATA_ALLOCA]])
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP8]], ptr [[TMP2]], align 4
@@ -876,8 +870,8 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = call [[STRUCT_ANYHITTRAVERSALDATA]] @await.struct.AnyHitTraversalData(ptr [[TMP11]])
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP12]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[LOCAL_ROOT_INDEX1:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP13]])
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX1]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP13]])
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
; LOWERRAYTRACINGPIPELINE-NEXT: br label [[_CONT_REPORTHIT_EXIT:%.*]]
; LOWERRAYTRACINGPIPELINE: isEnd.i:
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 0
@@ -911,11 +905,10 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES2:%.*]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_ANYHITTRAVERSALDATA]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = call [[STRUCT_ANYHITTRAVERSALDATA]] @continuations.getSystemData.s_struct.AnyHitTraversalDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP5]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP6]])
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP5]])
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[TMP6]])
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCandidateState(ptr [[SYSTEM_DATA_ALLOCA]])
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[TMP8]], ptr [[TMP2]], align 4
@@ -934,8 +927,8 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = call [[STRUCT_ANYHITTRAVERSALDATA]] @await.struct.AnyHitTraversalData(ptr [[TMP11]])
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP12]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[LOCAL_ROOT_INDEX1:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP13]])
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX1]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP13]])
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
; LOWERRAYTRACINGPIPELINE-NEXT: br label [[_CONT_REPORTHIT_EXIT:%.*]]
; LOWERRAYTRACINGPIPELINE: isEnd.i:
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 0
@@ -967,11 +960,9 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-SAME: [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR2]] !lgc.rt.shaderstage [[META47:![0-9]+]] !continuation.registercount [[META39]] !continuation [[META48:![0-9]+]] {
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP2:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = call [[STRUCT_SYSTEMDATA]] @continuations.getSystemData.s_struct.SystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP3]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP4]])
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP3]])
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP5]], i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i64 0
@@ -988,6 +979,7 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[TMP4]])
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: store <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, ptr [[TMP16]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
@@ -1061,12 +1053,10 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
;
;
; LOWERRAYTRACINGPIPELINE-CPS-LABEL: define void @MyRayGen(
-; LOWERRAYTRACINGPIPELINE-CPS-SAME: {} [[CONT_STATE:%.*]], i32 [[RETURN_ADDR:%.*]], i32 [[SHADER_INDEX:%.*]]) #[[ATTR2:[0-9]+]] !lgc.rt.shaderstage [[META23:![0-9]+]] !lgc.cps [[META23]] !continuation [[META35:![0-9]+]] {
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP1:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
+; LOWERRAYTRACINGPIPELINE-CPS-SAME: {} [[CONT_STATE:%.*]], i32 [[RETURN_ADDR:%.*]], i32 [[SHADER_INDEX:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] !lgc.rt.shaderstage [[META23:![0-9]+]] !lgc.cps [[META23]] !continuation [[META35:![0-9]+]] {
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP2:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP3:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP4:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 4
@@ -1097,40 +1087,40 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP19:%.*]] = getelementptr i32, ptr [[TMP14]], i64 2
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP20]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP21:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] (...) @lgc.cps.await.s_struct.DispatchSystemDatas(i32 4, i32 4, [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA2_I]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP21:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP22:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] (...) @lgc.cps.await.s_struct.DispatchSystemDatas(i32 4, i32 4, i32 [[TMP21]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_RAYPAYLOAD]] poison, ptr [[TMP4]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP4]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP23:%.*]] = getelementptr i32, ptr [[TMP22]], i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr [[TMP23]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP25:%.*]] = load i32, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP25]], ptr [[TMP24]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[TMP22]], i32 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP27:%.*]] = getelementptr i32, ptr [[TMP26]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP28:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP28]], ptr [[TMP27]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr [[TMP26]], i64 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP30:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP30]], ptr [[TMP29]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP31:%.*]] = getelementptr i32, ptr [[TMP26]], i64 2
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP32:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP32]], ptr [[TMP31]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP21]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[LOCAL_ROOT_INDEX1:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX1]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP4]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr [[TMP23]], i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[TMP24]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP26:%.*]] = load i32, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP26]], ptr [[TMP25]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP27:%.*]] = getelementptr i32, ptr [[TMP23]], i32 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP28:%.*]] = getelementptr i32, ptr [[TMP27]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP29:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP29]], ptr [[TMP28]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP30:%.*]] = getelementptr i32, ptr [[TMP27]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP31:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP31]], ptr [[TMP30]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP32:%.*]] = getelementptr i32, ptr [[TMP27]], i64 2
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP33:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP33]], ptr [[TMP32]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP22]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: br label [[DOTSPLIT:%.*]]
; LOWERRAYTRACINGPIPELINE-CPS: .split:
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP33:%.*]] = load <4 x float>, ptr [[TMP6]], align 4, !tbaa [[TBAA36]]
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP34:%.*]] = call <3 x i32> @lgc.rt.dispatch.rays.index()
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[EXTRACT:%.*]] = extractelement <3 x i32> [[TMP34]], i8 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP34:%.*]] = load <4 x float>, ptr [[TMP6]], align 4, !tbaa [[TBAA36]]
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP35:%.*]] = call <3 x i32> @lgc.rt.dispatch.rays.index()
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[EXTRACT1:%.*]] = extractelement <3 x i32> [[TMP35]], i8 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP36:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP3]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP37:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP36]], [[DX_TYPES_RESOURCEPROPERTIES]] { i32 4098, i32 1033 })
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP38:%.*]] = extractelement <4 x float> [[TMP33]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP39:%.*]] = extractelement <4 x float> [[TMP33]], i64 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP40:%.*]] = extractelement <4 x float> [[TMP33]], i64 2
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP41:%.*]] = extractelement <4 x float> [[TMP33]], i64 3
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @dx.op.textureStore.f32(i32 67, [[DX_TYPES_HANDLE]] [[TMP37]], i32 [[EXTRACT]], i32 [[EXTRACT1]], i32 undef, float [[TMP38]], float [[TMP39]], float [[TMP40]], float [[TMP41]], i8 15)
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[EXTRACT:%.*]] = extractelement <3 x i32> [[TMP35]], i8 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP36:%.*]] = call <3 x i32> @lgc.rt.dispatch.rays.index()
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[EXTRACT1:%.*]] = extractelement <3 x i32> [[TMP36]], i8 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP37:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP3]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP38:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP37]], [[DX_TYPES_RESOURCEPROPERTIES]] { i32 4098, i32 1033 })
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP39:%.*]] = extractelement <4 x float> [[TMP34]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP40:%.*]] = extractelement <4 x float> [[TMP34]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP41:%.*]] = extractelement <4 x float> [[TMP34]], i64 2
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP42:%.*]] = extractelement <4 x float> [[TMP34]], i64 3
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @dx.op.textureStore.f32(i32 67, [[DX_TYPES_HANDLE]] [[TMP38]], i32 [[EXTRACT]], i32 [[EXTRACT1]], i32 undef, float [[TMP39]], float [[TMP40]], float [[TMP41]], float [[TMP42]], i8 15)
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[TMP5]]) #[[ATTR1]]
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: ret void
;
@@ -1141,52 +1131,49 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[HITATTRS:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], align 8
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP4:%.*]] = call [[STRUCT_SYSTEMDATA]] @continuations.getSystemData.s_struct.SystemDatas()
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP4]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP5]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP6:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP6]], ptr [[TMP2]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP9]], ptr [[TMP7]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP12]], ptr [[TMP10]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[HITATTRS]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP14:%.*]] = load <2 x float>, ptr [[TMP13]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP15:%.*]] = extractelement <2 x float> [[TMP14]], i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP16:%.*]] = fsub fast float 1.000000e+00, [[TMP15]]
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP17:%.*]] = extractelement <2 x float> [[TMP14]], i32 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP18:%.*]] = fsub fast float [[TMP16]], [[TMP17]]
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP19:%.*]] = insertelement <4 x float> undef, float [[TMP18]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP20:%.*]] = insertelement <4 x float> [[TMP19]], float [[TMP15]], i64 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP21:%.*]] = insertelement <4 x float> [[TMP20]], float [[TMP17]], i64 2
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP22:%.*]] = insertelement <4 x float> [[TMP21]], float 1.000000e+00, i64 3
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store <4 x float> [[TMP22]], ptr [[TMP23]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP4:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP4]], ptr [[TMP2]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP7]], ptr [[TMP5]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP10]], ptr [[TMP8]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[SHADER_INDEX]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[HITATTRS]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP12:%.*]] = load <2 x float>, ptr [[TMP11]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP13:%.*]] = extractelement <2 x float> [[TMP12]], i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP14:%.*]] = fsub fast float 1.000000e+00, [[TMP13]]
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP15:%.*]] = extractelement <2 x float> [[TMP12]], i32 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP16:%.*]] = fsub fast float [[TMP14]], [[TMP15]]
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP17:%.*]] = insertelement <4 x float> undef, float [[TMP16]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP18:%.*]] = insertelement <4 x float> [[TMP17]], float [[TMP13]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP19:%.*]] = insertelement <4 x float> [[TMP18]], float [[TMP15]], i64 2
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP20:%.*]] = insertelement <4 x float> [[TMP19]], float 1.000000e+00, i64 3
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store <4 x float> [[TMP20]], ptr [[TMP21]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[TMP24]], i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[TMP25]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP27]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP28:%.*]] = getelementptr i32, ptr [[TMP24]], i32 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr [[TMP28]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP23:%.*]] = getelementptr i32, ptr [[TMP22]], i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr [[TMP23]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP25]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[TMP22]], i32 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP27:%.*]] = getelementptr i32, ptr [[TMP26]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP28]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr [[TMP26]], i64 1
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP30]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP31:%.*]] = getelementptr i32, ptr [[TMP28]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP30]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP31:%.*]] = getelementptr i32, ptr [[TMP26]], i64 2
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP31]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP32]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP33:%.*]] = getelementptr i32, ptr [[TMP28]], i64 2
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP33]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP34]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP36:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP35]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 6, {} poison, [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP36]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP32]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP34:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP33]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 6, {} poison, i32 poison, i32 poison, [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP34]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: unreachable
;
;
@@ -1205,28 +1192,25 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP12:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[ORIGHITATTRS:%.*]] = alloca [8 x i32], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[HITATTRSALLOCA:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], align 8
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP13:%.*]] = call [[STRUCT_ANYHITTRAVERSALDATA]] @continuations.getSystemData.s_struct.AnyHitTraversalDatas()
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP13]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP14]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP16:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[TMP15]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP16]], ptr [[TMP11]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[TMP11]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP19]], ptr [[TMP17]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP20:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[TMP11]], i64 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP22]], ptr [[TMP20]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP14:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[TMP13]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP14]], ptr [[TMP11]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[TMP11]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP17]], ptr [[TMP15]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[TMP11]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP20]], ptr [[TMP18]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP1]], ptr [[HITATTRSALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP12]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP24:%.*]] = load <4 x float>, ptr [[TMP23]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP26:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCandidateState(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_HITDATA]] [[TMP26]], ptr [[TMP4]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[SHADER_INDEX]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP12]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP22:%.*]] = load <4 x float>, ptr [[TMP21]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP24:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCandidateState(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_HITDATA]] [[TMP24]], ptr [[TMP4]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[RES_1_I1:%.*]] = load float, ptr [[TMP4]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[RESPTR_2_I2:%.*]] = getelementptr [[STRUCT_HITDATA]], ptr [[TMP4]], i32 0, i32 0, i32 1
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[RES_2_I3:%.*]] = load float, ptr [[RESPTR_2_I2]], align 4
@@ -1236,9 +1220,9 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[VAL_1_I7:%.*]] = insertelement <3 x float> [[VAL_0_I6]], float [[RES_2_I3]], i32 1
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[VAL_2_I8:%.*]] = insertelement <3 x float> [[VAL_1_I7]], float [[RES_3_I5]], i32 2
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[EXTRACT1:%.*]] = extractelement <3 x float> [[VAL_2_I8]], i8 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP28:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCandidateState(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_HITDATA]] [[TMP28]], ptr [[TMP5]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP26:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCandidateState(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_HITDATA]] [[TMP26]], ptr [[TMP5]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[RESPTR_1_I:%.*]] = getelementptr [[STRUCT_HITDATA]], ptr [[TMP5]], i32 0, i32 1, i32 0
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[RES_1_I:%.*]] = load float, ptr [[RESPTR_1_I]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[RESPTR_2_I:%.*]] = getelementptr [[STRUCT_HITDATA]], ptr [[TMP5]], i32 0, i32 1, i32 1
@@ -1249,188 +1233,188 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[VAL_1_I:%.*]] = insertelement <3 x float> [[VAL_0_I]], float [[RES_2_I]], i32 1
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[VAL_2_I:%.*]] = insertelement <3 x float> [[VAL_1_I]], float [[RES_3_I]], i32 2
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[EXTRACT:%.*]] = extractelement <3 x float> [[VAL_2_I]], i8 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP30:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCandidateState(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_HITDATA]] [[TMP30]], ptr [[TMP3]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP28:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCandidateState(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_HITDATA]] [[TMP28]], ptr [[TMP3]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[RESPTR_I:%.*]] = getelementptr [[STRUCT_HITDATA]], ptr [[TMP3]], i32 0, i32 2
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[RES_I:%.*]] = load float, ptr [[RESPTR_I]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP31:%.*]] = fmul fast float [[RES_I]], [[EXTRACT]]
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP32:%.*]] = fadd fast float [[TMP31]], [[EXTRACT1]]
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP33:%.*]] = fcmp fast ogt float [[TMP32]], 0.000000e+00
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP34:%.*]] = fcmp fast ogt float [[TMP32]], 1.000000e+00
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP35:%.*]] = fcmp fast ogt float [[TMP32]], -1.000000e+00
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: br i1 [[TMP33]], label [[TMP36:%.*]], label [[TMP81:%.*]]
-; LOWERRAYTRACINGPIPELINE-CPS: 36:
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store <4 x float> [[TMP24]], ptr [[TMP23]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: br i1 [[TMP34]], label [[TMP37:%.*]], label [[TMP59:%.*]]
-; LOWERRAYTRACINGPIPELINE-CPS: 37:
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @_cont_AcceptHitAndEndSearch(ptr [[TMP38]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP29:%.*]] = fmul fast float [[RES_I]], [[EXTRACT]]
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP30:%.*]] = fadd fast float [[TMP29]], [[EXTRACT1]]
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP31:%.*]] = fcmp fast ogt float [[TMP30]], 0.000000e+00
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP32:%.*]] = fcmp fast ogt float [[TMP30]], 1.000000e+00
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP33:%.*]] = fcmp fast ogt float [[TMP30]], -1.000000e+00
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: br i1 [[TMP31]], label [[TMP34:%.*]], label [[TMP79:%.*]]
+; LOWERRAYTRACINGPIPELINE-CPS: 34:
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store <4 x float> [[TMP22]], ptr [[TMP21]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: br i1 [[TMP32]], label [[TMP35:%.*]], label [[TMP57:%.*]]
+; LOWERRAYTRACINGPIPELINE-CPS: 35:
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @_cont_AcceptHitAndEndSearch(ptr [[TMP36]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP12]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP40:%.*]] = getelementptr i32, ptr [[TMP39]], i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP41:%.*]] = getelementptr i32, ptr [[TMP40]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP42:%.*]] = load i32, ptr [[TMP41]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP42]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP43:%.*]] = getelementptr i32, ptr [[TMP39]], i32 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP44:%.*]] = getelementptr i32, ptr [[TMP43]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP12]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP38:%.*]] = getelementptr i32, ptr [[TMP37]], i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP39:%.*]] = getelementptr i32, ptr [[TMP38]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP39]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP40]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP41:%.*]] = getelementptr i32, ptr [[TMP37]], i32 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP42:%.*]] = getelementptr i32, ptr [[TMP41]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP43:%.*]] = load i32, ptr [[TMP42]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP43]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP44:%.*]] = getelementptr i32, ptr [[TMP41]], i64 1
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP45:%.*]] = load i32, ptr [[TMP44]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP45]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP46:%.*]] = getelementptr i32, ptr [[TMP43]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP45]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP46:%.*]] = getelementptr i32, ptr [[TMP41]], i64 2
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP47:%.*]] = load i32, ptr [[TMP46]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP47]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP48:%.*]] = getelementptr i32, ptr [[TMP43]], i64 2
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP49:%.*]] = load i32, ptr [[TMP48]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP49]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP50:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP51:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP52:%.*]] = load i32, ptr [[TMP50]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP52]], ptr [[TMP51]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP53:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP54:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i64 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP55:%.*]] = load i32, ptr [[TMP53]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP55]], ptr [[TMP54]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP56:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP10]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @_cont_SetTriangleHitAttributes(ptr [[TMP57]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP56]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP58:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 18, {} poison, [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP58]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP47]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP48:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP49:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP50:%.*]] = load i32, ptr [[TMP48]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP50]], ptr [[TMP49]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP51:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP52:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP53:%.*]] = load i32, ptr [[TMP51]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP53]], ptr [[TMP52]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP54:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP10]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @_cont_SetTriangleHitAttributes(ptr [[TMP55]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP54]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP56:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 18, {} poison, i32 poison, i32 poison, [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP56]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: unreachable
-; LOWERRAYTRACINGPIPELINE-CPS: 59:
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @_cont_AcceptHitAndEndSearch(ptr [[TMP60]])
+; LOWERRAYTRACINGPIPELINE-CPS: 57:
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @_cont_AcceptHitAndEndSearch(ptr [[TMP58]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP61:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP12]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP62:%.*]] = getelementptr i32, ptr [[TMP61]], i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP63:%.*]] = getelementptr i32, ptr [[TMP62]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP64:%.*]] = load i32, ptr [[TMP63]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP64]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP65:%.*]] = getelementptr i32, ptr [[TMP61]], i32 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP66:%.*]] = getelementptr i32, ptr [[TMP65]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP12]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP60:%.*]] = getelementptr i32, ptr [[TMP59]], i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP61:%.*]] = getelementptr i32, ptr [[TMP60]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP62:%.*]] = load i32, ptr [[TMP61]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP62]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP63:%.*]] = getelementptr i32, ptr [[TMP59]], i32 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr [[TMP63]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP65:%.*]] = load i32, ptr [[TMP64]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP65]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP66:%.*]] = getelementptr i32, ptr [[TMP63]], i64 1
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP67:%.*]] = load i32, ptr [[TMP66]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP67]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP68:%.*]] = getelementptr i32, ptr [[TMP65]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP67]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP68:%.*]] = getelementptr i32, ptr [[TMP63]], i64 2
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP69:%.*]] = load i32, ptr [[TMP68]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP69]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP70:%.*]] = getelementptr i32, ptr [[TMP65]], i64 2
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP71:%.*]] = load i32, ptr [[TMP70]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP71]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP72:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP73:%.*]] = getelementptr inbounds i32, ptr [[TMP9]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP74:%.*]] = load i32, ptr [[TMP72]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP74]], ptr [[TMP73]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP75:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP76:%.*]] = getelementptr inbounds i32, ptr [[TMP9]], i64 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP77:%.*]] = load i32, ptr [[TMP75]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP77]], ptr [[TMP76]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP78:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP9]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @_cont_SetTriangleHitAttributes(ptr [[TMP79]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP78]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP80:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 18, {} poison, [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP80]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP69]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP70:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP71:%.*]] = getelementptr inbounds i32, ptr [[TMP9]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP72:%.*]] = load i32, ptr [[TMP70]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP72]], ptr [[TMP71]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP73:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP74:%.*]] = getelementptr inbounds i32, ptr [[TMP9]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP75:%.*]] = load i32, ptr [[TMP73]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP75]], ptr [[TMP74]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP76:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP9]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @_cont_SetTriangleHitAttributes(ptr [[TMP77]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP76]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP78:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 18, {} poison, i32 poison, i32 poison, [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP78]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: unreachable
+; LOWERRAYTRACINGPIPELINE-CPS: 79:
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: br i1 [[TMP33]], label [[TMP80:%.*]], label [[TMP125:%.*]]
+; LOWERRAYTRACINGPIPELINE-CPS: 80:
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: br i1 [[TMP32]], label [[TMP81:%.*]], label [[TMP103:%.*]]
; LOWERRAYTRACINGPIPELINE-CPS: 81:
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: br i1 [[TMP35]], label [[TMP82:%.*]], label [[TMP127:%.*]]
-; LOWERRAYTRACINGPIPELINE-CPS: 82:
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: br i1 [[TMP34]], label [[TMP83:%.*]], label [[TMP105:%.*]]
-; LOWERRAYTRACINGPIPELINE-CPS: 83:
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP84:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @_cont_IgnoreHit(ptr [[TMP84]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @_cont_IgnoreHit(ptr [[TMP82]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP85:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP12]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP86:%.*]] = getelementptr i32, ptr [[TMP85]], i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP87:%.*]] = getelementptr i32, ptr [[TMP86]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP88:%.*]] = load i32, ptr [[TMP87]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP88]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP89:%.*]] = getelementptr i32, ptr [[TMP85]], i32 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP90:%.*]] = getelementptr i32, ptr [[TMP89]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP83:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP12]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP84:%.*]] = getelementptr i32, ptr [[TMP83]], i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP85:%.*]] = getelementptr i32, ptr [[TMP84]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP86:%.*]] = load i32, ptr [[TMP85]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP86]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP87:%.*]] = getelementptr i32, ptr [[TMP83]], i32 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP88:%.*]] = getelementptr i32, ptr [[TMP87]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP89:%.*]] = load i32, ptr [[TMP88]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP89]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP90:%.*]] = getelementptr i32, ptr [[TMP87]], i64 1
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP91:%.*]] = load i32, ptr [[TMP90]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP91]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP92:%.*]] = getelementptr i32, ptr [[TMP89]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP91]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP92:%.*]] = getelementptr i32, ptr [[TMP87]], i64 2
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP93:%.*]] = load i32, ptr [[TMP92]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP93]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP94:%.*]] = getelementptr i32, ptr [[TMP89]], i64 2
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP95:%.*]] = load i32, ptr [[TMP94]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP95]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP96:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP97:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP98:%.*]] = load i32, ptr [[TMP96]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP98]], ptr [[TMP97]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP99:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP100:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i64 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP101:%.*]] = load i32, ptr [[TMP99]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP101]], ptr [[TMP100]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP102:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP8]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @_cont_SetTriangleHitAttributes(ptr [[TMP103]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP102]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP104:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 18, {} poison, [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP104]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP93]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP94:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP95:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP96:%.*]] = load i32, ptr [[TMP94]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP96]], ptr [[TMP95]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP97:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP98:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP99:%.*]] = load i32, ptr [[TMP97]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP99]], ptr [[TMP98]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP100:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP8]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @_cont_SetTriangleHitAttributes(ptr [[TMP101]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP100]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP102:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 18, {} poison, i32 poison, i32 poison, [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP102]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: unreachable
-; LOWERRAYTRACINGPIPELINE-CPS: 105:
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @_cont_IgnoreHit(ptr [[TMP106]])
+; LOWERRAYTRACINGPIPELINE-CPS: 103:
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @_cont_IgnoreHit(ptr [[TMP104]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP12]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP108:%.*]] = getelementptr i32, ptr [[TMP107]], i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP109:%.*]] = getelementptr i32, ptr [[TMP108]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP110:%.*]] = load i32, ptr [[TMP109]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP110]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP111:%.*]] = getelementptr i32, ptr [[TMP107]], i32 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP112:%.*]] = getelementptr i32, ptr [[TMP111]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP12]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP106:%.*]] = getelementptr i32, ptr [[TMP105]], i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP107:%.*]] = getelementptr i32, ptr [[TMP106]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP108:%.*]] = load i32, ptr [[TMP107]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP108]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP109:%.*]] = getelementptr i32, ptr [[TMP105]], i32 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP110:%.*]] = getelementptr i32, ptr [[TMP109]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP111:%.*]] = load i32, ptr [[TMP110]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP111]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP112:%.*]] = getelementptr i32, ptr [[TMP109]], i64 1
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP113:%.*]] = load i32, ptr [[TMP112]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP113]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP114:%.*]] = getelementptr i32, ptr [[TMP111]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP113]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP114:%.*]] = getelementptr i32, ptr [[TMP109]], i64 2
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP115:%.*]] = load i32, ptr [[TMP114]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP115]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP116:%.*]] = getelementptr i32, ptr [[TMP111]], i64 2
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP117:%.*]] = load i32, ptr [[TMP116]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP117]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP118:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP119:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP120:%.*]] = load i32, ptr [[TMP118]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP120]], ptr [[TMP119]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP121:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP122:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i64 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP123:%.*]] = load i32, ptr [[TMP121]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP123]], ptr [[TMP122]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP124:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP7]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP125:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @_cont_SetTriangleHitAttributes(ptr [[TMP125]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP124]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP126:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 18, {} poison, [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP126]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP115]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP116:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP117:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP118:%.*]] = load i32, ptr [[TMP116]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP118]], ptr [[TMP117]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP119:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP120:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP121:%.*]] = load i32, ptr [[TMP119]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP121]], ptr [[TMP120]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP122:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP7]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP123:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @_cont_SetTriangleHitAttributes(ptr [[TMP123]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP122]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP124:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 18, {} poison, i32 poison, i32 poison, [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP124]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: unreachable
-; LOWERRAYTRACINGPIPELINE-CPS: 127:
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store <4 x float> [[TMP24]], ptr [[TMP23]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS: 125:
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store <4 x float> [[TMP22]], ptr [[TMP21]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @_cont_AcceptHit(ptr [[SYSTEM_DATA_ALLOCA]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP128:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP12]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP129:%.*]] = getelementptr i32, ptr [[TMP128]], i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP130:%.*]] = getelementptr i32, ptr [[TMP129]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP131:%.*]] = load i32, ptr [[TMP130]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP131]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP132:%.*]] = getelementptr i32, ptr [[TMP128]], i32 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP133:%.*]] = getelementptr i32, ptr [[TMP132]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP126:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP12]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP127:%.*]] = getelementptr i32, ptr [[TMP126]], i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP128:%.*]] = getelementptr i32, ptr [[TMP127]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP129:%.*]] = load i32, ptr [[TMP128]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP129]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP130:%.*]] = getelementptr i32, ptr [[TMP126]], i32 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP131:%.*]] = getelementptr i32, ptr [[TMP130]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP132:%.*]] = load i32, ptr [[TMP131]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP132]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP133:%.*]] = getelementptr i32, ptr [[TMP130]], i64 1
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP134:%.*]] = load i32, ptr [[TMP133]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP134]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP135:%.*]] = getelementptr i32, ptr [[TMP132]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP134]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP135:%.*]] = getelementptr i32, ptr [[TMP130]], i64 2
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP136:%.*]] = load i32, ptr [[TMP135]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP136]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP137:%.*]] = getelementptr i32, ptr [[TMP132]], i64 2
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP138:%.*]] = load i32, ptr [[TMP137]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP138]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP139:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP140:%.*]] = getelementptr inbounds i32, ptr [[TMP6]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP141:%.*]] = load i32, ptr [[TMP139]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP141]], ptr [[TMP140]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP142:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP143:%.*]] = getelementptr inbounds i32, ptr [[TMP6]], i64 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP144:%.*]] = load i32, ptr [[TMP142]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP144]], ptr [[TMP143]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP145:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP6]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP146:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @_cont_SetTriangleHitAttributes(ptr [[TMP146]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP145]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP147:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 18, {} poison, [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP147]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP136]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP137:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP138:%.*]] = getelementptr inbounds i32, ptr [[TMP6]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP139:%.*]] = load i32, ptr [[TMP137]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP139]], ptr [[TMP138]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP140:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP141:%.*]] = getelementptr inbounds i32, ptr [[TMP6]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP142:%.*]] = load i32, ptr [[TMP140]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP142]], ptr [[TMP141]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP143:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP6]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP144:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @_cont_SetTriangleHitAttributes(ptr [[TMP144]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP143]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP145:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 18, {} poison, i32 poison, i32 poison, [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP145]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: unreachable
;
;
@@ -1440,30 +1424,29 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP4:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_ANYHITTRAVERSALDATA]], align 8
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP5:%.*]] = call [[STRUCT_ANYHITTRAVERSALDATA]] @continuations.getSystemData.s_struct.AnyHitTraversalDatas()
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP5]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP6]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP8:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCandidateState(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_HITDATA]] [[TMP8]], ptr [[TMP2]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[SHADER_INDEX]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP6:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCandidateState(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_HITDATA]] [[TMP6]], ptr [[TMP2]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[RESPTR_I:%.*]] = getelementptr [[STRUCT_HITDATA]], ptr [[TMP2]], i32 0, i32 2
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[RES_I:%.*]] = load float, ptr [[RESPTR_I]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP9:%.*]] = bitcast ptr [[TMP4]] to ptr
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @llvm.lifetime.start.p0(i64 8, ptr [[TMP9]]) #[[ATTR1]]
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP7:%.*]] = bitcast ptr [[TMP4]] to ptr
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @llvm.lifetime.start.p0(i64 8, ptr [[TMP7]]) #[[ATTR1]]
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[ORIGTPTR_I:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[ORIGT_I:%.*]] = load float, ptr [[ORIGTPTR_I]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[ISNOHIT_I:%.*]] = fcmp fast uge float [[RES_I]], [[ORIGT_I]]
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: br i1 [[ISNOHIT_I]], label [[ISEND_I:%.*]], label [[CALLAHIT_I:%.*]]
; LOWERRAYTRACINGPIPELINE-CPS: callAHit.i:
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TRAV_DATA_I:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP9:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP8]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP10:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP4]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP11:%.*]] = call [[STRUCT_ANYHITTRAVERSALDATA]] (...) @lgc.cps.await.s_struct.AnyHitTraversalDatas(i32 3, i32 8, [[STRUCT_ANYHITTRAVERSALDATA]] [[TRAV_DATA_I]], float [[RES_I]], i32 0, [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP10]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP11:%.*]] = call [[STRUCT_ANYHITTRAVERSALDATA]] (...) @lgc.cps.await.s_struct.AnyHitTraversalDatas(i32 3, i32 8, i32 [[TMP9]], float [[RES_I]], i32 0, [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP10]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP11]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[LOCAL_ROOT_INDEX1:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP12]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX1]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP12]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: br label [[_CONT_REPORTHIT_EXIT:%.*]]
; LOWERRAYTRACINGPIPELINE-CPS: isEnd.i:
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 0
@@ -1484,12 +1467,12 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: br i1 [[TMP22]], label [[TMP23:%.*]], label [[TMP25:%.*]]
; LOWERRAYTRACINGPIPELINE-CPS: 23:
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP24:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 10, {} poison, [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP24]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 10, {} poison, i32 poison, i32 poison, [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP24]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: unreachable
; LOWERRAYTRACINGPIPELINE-CPS: 25:
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @llvm.lifetime.end.p0(i64 8, ptr [[TMP9]]) #[[ATTR1]]
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @llvm.lifetime.end.p0(i64 8, ptr [[TMP7]]) #[[ATTR1]]
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP26:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 10, {} poison, [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP26]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 10, {} poison, i32 poison, i32 poison, [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP26]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: unreachable
;
;
@@ -1499,30 +1482,29 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP4:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES2:%.*]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_ANYHITTRAVERSALDATA]], align 8
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP5:%.*]] = call [[STRUCT_ANYHITTRAVERSALDATA]] @continuations.getSystemData.s_struct.AnyHitTraversalDatas()
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP5]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP6]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP8:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCandidateState(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_HITDATA]] [[TMP8]], ptr [[TMP2]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[SHADER_INDEX]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP6:%.*]] = call [[STRUCT_HITDATA]] @_cont_GetCandidateState(ptr [[SYSTEM_DATA_ALLOCA]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_HITDATA]] [[TMP6]], ptr [[TMP2]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[RESPTR_I:%.*]] = getelementptr [[STRUCT_HITDATA]], ptr [[TMP2]], i32 0, i32 2
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[RES_I:%.*]] = load float, ptr [[RESPTR_I]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP9:%.*]] = bitcast ptr [[TMP4]] to ptr
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @llvm.lifetime.start.p0(i64 8, ptr [[TMP9]]) #[[ATTR1]]
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP7:%.*]] = bitcast ptr [[TMP4]] to ptr
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @llvm.lifetime.start.p0(i64 8, ptr [[TMP7]]) #[[ATTR1]]
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[ORIGTPTR_I:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[ORIGT_I:%.*]] = load float, ptr [[ORIGTPTR_I]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[ISNOHIT_I:%.*]] = fcmp fast uge float [[RES_I]], [[ORIGT_I]]
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: br i1 [[ISNOHIT_I]], label [[ISEND_I:%.*]], label [[CALLAHIT_I:%.*]]
; LOWERRAYTRACINGPIPELINE-CPS: callAHit.i:
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TRAV_DATA_I:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP9:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP8]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP10:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES2]], ptr [[TMP4]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP11:%.*]] = call [[STRUCT_ANYHITTRAVERSALDATA]] (...) @lgc.cps.await.s_struct.AnyHitTraversalDatas(i32 3, i32 8, [[STRUCT_ANYHITTRAVERSALDATA]] [[TRAV_DATA_I]], float [[RES_I]], i32 0, [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES2]] [[TMP10]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP11:%.*]] = call [[STRUCT_ANYHITTRAVERSALDATA]] (...) @lgc.cps.await.s_struct.AnyHitTraversalDatas(i32 3, i32 8, i32 [[TMP9]], float [[RES_I]], i32 0, [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES2]] [[TMP10]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP11]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[LOCAL_ROOT_INDEX1:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP12]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX1]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP12]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: br label [[_CONT_REPORTHIT_EXIT:%.*]]
; LOWERRAYTRACINGPIPELINE-CPS: isEnd.i:
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 0
@@ -1543,12 +1525,12 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: br i1 [[TMP22]], label [[TMP23:%.*]], label [[TMP25:%.*]]
; LOWERRAYTRACINGPIPELINE-CPS: 23:
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP24:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 10, {} poison, [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP24]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 10, {} poison, i32 poison, i32 poison, [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP24]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: unreachable
; LOWERRAYTRACINGPIPELINE-CPS: 25:
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @llvm.lifetime.end.p0(i64 8, ptr [[TMP9]]) #[[ATTR1]]
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @llvm.lifetime.end.p0(i64 8, ptr [[TMP7]]) #[[ATTR1]]
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP26:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 10, {} poison, [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP26]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 10, {} poison, i32 poison, i32 poison, [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP26]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: unreachable
;
;
@@ -1556,31 +1538,28 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-CPS-SAME: {} [[CONT_STATE:%.*]], i32 [[RETURN_ADDR:%.*]], i32 [[SHADER_INDEX:%.*]], [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR2]] !lgc.rt.shaderstage [[META44]] !lgc.cps [[META40]] !continuation [[META47:![0-9]+]] {
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP2:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 8
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP3:%.*]] = call [[STRUCT_SYSTEMDATA]] @continuations.getSystemData.s_struct.SystemDatas()
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP3]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP4]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, ptr [[TMP5]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[SHADER_INDEX]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, ptr [[TMP3]], align 4
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i64 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP9]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP6]], i32 1
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP10]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[TMP4]], i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP5]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP7]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP4]], i32 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[TMP8]], i64 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP10]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP8]], i64 1
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP12]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP10]], i64 1
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP12]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP8]], i64 2
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP14]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[TMP10]], i64 2
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP16]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP18:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP17]], align 4
-; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 6, {} poison, [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP18]])
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: store i32 [[TMP14]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: [[TMP16:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP15]], align 4
+; LOWERRAYTRACINGPIPELINE-CPS-NEXT: call void (...) @lgc.cps.jump(i32 [[RETURN_ADDR]], i32 6, {} poison, i32 poison, i32 poison, [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP16]])
; LOWERRAYTRACINGPIPELINE-CPS-NEXT: unreachable
;
diff --git a/shared/continuations/test/dx/paq-hit-attribute-size.ll b/shared/continuations/test/dx/paq-hit-attribute-size.ll
index 378dd610d6..20003fd520 100644
--- a/shared/continuations/test/dx/paq-hit-attribute-size.ll
+++ b/shared/continuations/test/dx/paq-hit-attribute-size.ll
@@ -40,19 +40,19 @@ target datalayout = "e-m:e-p:64:32-p20:32:32-p21:32:32-i1:32-i8:8-i16:32-i32:32-
; CHECK-LABEL: define {{.*}} @AnyHit1DWordsMax1DWords(
; CHECK: {{.*}}%struct.MyPayload.attr_max_1_i32s.layout_2_anyhit_out_accept
-define void @AnyHit1DWordsMax1DWords(%struct.MyPayload* %payload, %struct.Attributes1DWords* %attrs) !continuation.maxHitAttributeBytes !49 !types !60 {
+define void @AnyHit1DWordsMax1DWords(%struct.MyPayload* %payload, %struct.Attributes1DWords* %attrs) !lgc.rt.attribute.size !49 !types !60 {
ret void
}
; CHECK-LABEL: define {{.*}} @AnyHit1DWordsMax2DWords(
; CHECK: {{.*}}%struct.MyPayload.attr_max_2_i32s.layout_2_anyhit_out_accept
-define void @AnyHit1DWordsMax2DWords(%struct.MyPayload* %payload, %struct.Attributes1DWords* %attrs) !continuation.maxHitAttributeBytes !22 !types !60 {
+define void @AnyHit1DWordsMax2DWords(%struct.MyPayload* %payload, %struct.Attributes1DWords* %attrs) !lgc.rt.attribute.size !22 !types !60 {
ret void
}
; CHECK-LABEL: define {{.*}} @AnyHit1DWordsMax8DWords(
; CHECK: {{.*}}%struct.MyPayload.attr_max_8_i32s.layout_2_anyhit_out_accept.payload_attr_0_i32s
-define void @AnyHit1DWordsMax8DWords(%struct.MyPayload* %payload, %struct.Attributes1DWords* %attrs) !continuation.maxHitAttributeBytes !27 !types !60 {
+define void @AnyHit1DWordsMax8DWords(%struct.MyPayload* %payload, %struct.Attributes1DWords* %attrs) !lgc.rt.attribute.size !27 !types !60 {
ret void
}
@@ -60,7 +60,7 @@ define void @AnyHit1DWordsMax8DWords(%struct.MyPayload* %payload, %struct.Attrib
; is not specialized, thus no payload_attr_N_i32s suffix.
; CHECK-LABEL: define {{.*}} @AnyHit2DWordsMax2DWords(
; CHECK: {{.*}}%struct.MyPayload.attr_max_2_i32s.layout_2_anyhit_out_accept
-define void @AnyHit2DWordsMax2DWords(%struct.MyPayload* %payload, %struct.Attributes2DWords* %attrs) !continuation.maxHitAttributeBytes !22 !types !23 {
+define void @AnyHit2DWordsMax2DWords(%struct.MyPayload* %payload, %struct.Attributes2DWords* %attrs) !lgc.rt.attribute.size !22 !types !23 {
ret void
}
@@ -68,13 +68,13 @@ define void @AnyHit2DWordsMax2DWords(%struct.MyPayload* %payload, %struct.Attrib
; There are 2 unused DWords in the layout.
; CHECK-LABEL: define {{.*}} @AnyHit2DWordsMax4DWords(
; CHECK: {{.*}}%struct.MyPayload.attr_max_4_i32s.layout_2_anyhit_out_accept.payload_attr_0_i32s
-define void @AnyHit2DWordsMax4DWords(%struct.MyPayload* %payload, %struct.Attributes2DWords* %attrs) !continuation.maxHitAttributeBytes !26 !types !23 {
+define void @AnyHit2DWordsMax4DWords(%struct.MyPayload* %payload, %struct.Attributes2DWords* %attrs) !lgc.rt.attribute.size !26 !types !23 {
ret void
}
; CHECK-LABEL: define {{.*}} @AnyHit2DWordsMax8DWords(
; CHECK: {{.*}}%struct.MyPayload.attr_max_8_i32s.layout_2_anyhit_out_accept.payload_attr_0_i32s
-define void @AnyHit2DWordsMax8DWords(%struct.MyPayload* %payload, %struct.Attributes2DWords* %attrs) !continuation.maxHitAttributeBytes !27 !types !23 {
+define void @AnyHit2DWordsMax8DWords(%struct.MyPayload* %payload, %struct.Attributes2DWords* %attrs) !lgc.rt.attribute.size !27 !types !23 {
ret void
}
@@ -86,13 +86,13 @@ define void @AnyHit2DWordsNoLimit(%struct.MyPayload* %payload, %struct.Attribute
; CHECK-LABEL: define {{.*}} @AnyHit4DWordsMax4DWords(
; CHECK: {{.*}}%struct.MyPayload.attr_max_4_i32s.layout_2_anyhit_out_accept
-define void @AnyHit4DWordsMax4DWords(%struct.MyPayload* %payload, %struct.Attributes4DWords* %attrs) !continuation.maxHitAttributeBytes !26 !types !28 {
+define void @AnyHit4DWordsMax4DWords(%struct.MyPayload* %payload, %struct.Attributes4DWords* %attrs) !lgc.rt.attribute.size !26 !types !28 {
ret void
}
; CHECK-LABEL: define {{.*}} @AnyHit4DWordsMax8DWords(
; CHECK: {{.*}}%struct.MyPayload.attr_max_8_i32s.layout_2_anyhit_out_accept.payload_attr_2_i32s
-define void @AnyHit4DWordsMax8DWords(%struct.MyPayload* %payload, %struct.Attributes4DWords* %attrs) !continuation.maxHitAttributeBytes !27 !types !28 {
+define void @AnyHit4DWordsMax8DWords(%struct.MyPayload* %payload, %struct.Attributes4DWords* %attrs) !lgc.rt.attribute.size !27 !types !28 {
ret void
}
@@ -103,7 +103,7 @@ define void @AnyHit4DWordsNoLimit(%struct.MyPayload* %payload, %struct.Attribute
}
; The following one violates the limit and should crash:
-define void @AnyHit4DWordsMax2DWords(%struct.MyPayload* %payload, %struct.Attributes4DWords* %attrs) !continuation.maxHitAttributeBytes !22 !types !28 {
+define void @AnyHit4DWordsMax2DWords(%struct.MyPayload* %payload, %struct.Attributes4DWords* %attrs) !lgc.rt.attribute.size !22 !types !28 {
ret void
}
diff --git a/shared/continuations/test/dx/payload-caller-in-paq.ll b/shared/continuations/test/dx/payload-caller-in-paq.ll
index 626217e56b..cde834e0d2 100644
--- a/shared/continuations/test/dx/payload-caller-in-paq.ll
+++ b/shared/continuations/test/dx/payload-caller-in-paq.ll
@@ -31,11 +31,10 @@ target datalayout = "e-m:e-p:64:32-p20:32:32-p21:32:32-i1:32-i8:8-i16:32-i32:32-
; Function Attrs: nounwind
define void @RayGen() #0 {
; LOWERRAYTRACINGPIPELINE-LABEL: define void @RayGen(
-; LOWERRAYTRACINGPIPELINE-SAME: ) #[[ATTR0:[0-9]+]] !lgc.rt.shaderstage [[META24:![0-9]+]] !continuation.entry [[META14:![0-9]+]] !continuation.registercount [[META24]] !continuation [[META27:![0-9]+]] {
-; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP1:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; LOWERRAYTRACINGPIPELINE-SAME: [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] !lgc.rt.shaderstage [[META24:![0-9]+]] !continuation.entry [[META14:![0-9]+]] !continuation.registercount [[META24]] !continuation [[META27:![0-9]+]] {
+; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP2:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?myAccelerationStructure@@3URaytracingAccelerationStructure@@A", align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?gOutput@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = alloca [[STRUCT_MYPAYLOAD:%.*]], align 8
@@ -70,7 +69,7 @@ define void @RayGen() #0 {
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = load i32, ptr getelementptr ([[STRUCT_MYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 2), align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP23]], ptr [[TMP22]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP13]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; LOWERRAYTRACINGPIPELINE-NEXT: br label [[DOTSPLIT:%.*]]
; LOWERRAYTRACINGPIPELINE: .split:
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = load float, ptr [[TMP6]], align 8, !tbaa [[TBAA28]]
diff --git a/shared/continuations/test/dx/payload-save-registers.ll b/shared/continuations/test/dx/payload-save-registers.ll
index efe5b41f12..da2c40b5a0 100644
--- a/shared/continuations/test/dx/payload-save-registers.ll
+++ b/shared/continuations/test/dx/payload-save-registers.ll
@@ -33,158 +33,157 @@ define void @Miss(%struct.OuterPayload* noalias nocapture %outerPayload) #0 !typ
; LOWERRAYTRACINGPIPELINE-SAME: [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] !lgc.rt.shaderstage [[META26:![0-9]+]] !continuation.registercount [[META24:![0-9]+]] !continuation [[META27:![0-9]+]] {
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP2:%.*]] = alloca [[STRUCT_OUTERPAYLOAD:%.*]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = call [[STRUCT_SYSTEMDATA]] @continuations.getSystemData.s_struct.SystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP3]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP5]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP8]], ptr [[TMP7]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[TMP6]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP6]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP12]], ptr [[TMP11]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP6]], i64 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 10), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[TMP6]], i64 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 11), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP16]], ptr [[TMP15]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[TMP6]], i64 5
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 12), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP18]], ptr [[TMP17]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = getelementptr i32, ptr [[TMP6]], i64 6
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 13), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP20]], ptr [[TMP19]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[TMP6]], i64 7
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 14), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP22]], ptr [[TMP21]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = getelementptr i32, ptr [[TMP6]], i64 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 15), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP24]], ptr [[TMP23]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[TMP6]], i64 9
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP26]], ptr [[TMP25]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = getelementptr i32, ptr [[TMP6]], i64 10
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP28]], ptr [[TMP27]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr [[TMP6]], i64 11
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP30]], ptr [[TMP29]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = getelementptr i32, ptr [[TMP6]], i64 12
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP32]], ptr [[TMP31]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = getelementptr i32, ptr [[TMP6]], i64 13
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP34]], ptr [[TMP33]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = getelementptr i32, ptr [[TMP6]], i64 14
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP36]], ptr [[TMP35]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[TMP4]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP5]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP5]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP9]], ptr [[TMP8]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP5]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP11]], ptr [[TMP10]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP5]], i64 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 10), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP13]], ptr [[TMP12]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP5]], i64 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 11), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP5]], i64 5
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 12), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP17]], ptr [[TMP16]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = getelementptr i32, ptr [[TMP5]], i64 6
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 13), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP19]], ptr [[TMP18]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[TMP5]], i64 7
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 14), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP21]], ptr [[TMP20]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr [[TMP5]], i64 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 15), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP23]], ptr [[TMP22]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr [[TMP5]], i64 9
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP25]], ptr [[TMP24]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[TMP5]], i64 10
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP27]], ptr [[TMP26]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = getelementptr i32, ptr [[TMP5]], i64 11
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP29]], ptr [[TMP28]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = getelementptr i32, ptr [[TMP5]], i64 12
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP31]], ptr [[TMP30]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = getelementptr i32, ptr [[TMP5]], i64 13
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP33]], ptr [[TMP32]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = getelementptr i32, ptr [[TMP5]], i64 14
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP35]], ptr [[TMP34]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = load i32, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = load i32, ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 22), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP39:%.*]] = load i32, ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 23), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP40:%.*]] = load i32, ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 24), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP41:%.*]] = load i32, ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 25), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP42:%.*]] = load i32, ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 26), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP43:%.*]] = load i32, ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 27), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP44:%.*]] = load i32, ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 28), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP45:%.*]] = load i32, ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 29), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP46:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?myAccelerationStructure@@3URaytracingAccelerationStructure@@A", align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP47:%.*]] = alloca [[STRUCT_INNERPAYLOAD:%.*]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP48:%.*]] = bitcast ptr [[TMP47]] to ptr
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP48]]) #[[ATTR0]]
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 14
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP50:%.*]] = load float, ptr [[TMP49]], align 4, !tbaa [[TBAA28:![0-9]+]]
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT_INNERPAYLOAD]], ptr [[TMP47]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP50]], ptr [[TMP51]], align 4, !tbaa [[TBAA28]]
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP52:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP46]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP53:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP52]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP54:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[TMP53]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[DIS_DATA_I:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP55]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = load i32, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = load i32, ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 22), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = load i32, ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 23), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP39:%.*]] = load i32, ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 24), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP40:%.*]] = load i32, ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 25), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP41:%.*]] = load i32, ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 26), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP42:%.*]] = load i32, ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 27), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP43:%.*]] = load i32, ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 28), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP44:%.*]] = load i32, ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 29), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP45:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?myAccelerationStructure@@3URaytracingAccelerationStructure@@A", align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP46:%.*]] = alloca [[STRUCT_INNERPAYLOAD:%.*]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP47:%.*]] = bitcast ptr [[TMP46]] to ptr
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP47]]) #[[ATTR0]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 14
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP49:%.*]] = load float, ptr [[TMP48]], align 4, !tbaa [[TBAA28:![0-9]+]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT_INNERPAYLOAD]], ptr [[TMP46]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP49]], ptr [[TMP50]], align 4, !tbaa [[TBAA28]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP51:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP45]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP52:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP51]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP53:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[TMP52]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[DIS_DATA_I:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP54]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYS_DATA_I:%.*]] = insertvalue [[STRUCT_SYSTEMDATA]] undef, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I]], 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TRAV_DATA_I:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA:%.*]] undef, [[STRUCT_SYSTEMDATA]] [[SYS_DATA_I]], 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT_INNERPAYLOAD]], ptr [[TMP47]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP57:%.*]] = load float, ptr [[TMP56]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP57]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP58:%.*]] = call ptr inttoptr (i64 4 to ptr)([[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]]), !continuation.registercount [[META32:![0-9]+]], !continuation.returnedRegistercount !32
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP59:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @await.struct.DispatchSystemData(ptr [[TMP58]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_INNERPAYLOAD]] poison, ptr [[TMP47]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT_INNERPAYLOAD]], ptr [[TMP47]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP61:%.*]] = load float, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP61]], ptr [[TMP60]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP59]], ptr [[TMP55]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT_INNERPAYLOAD]], ptr [[TMP46]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP56:%.*]] = load float, ptr [[TMP55]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP56]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP57:%.*]] = call ptr inttoptr (i64 4 to ptr)([[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]]), !continuation.registercount [[META32:![0-9]+]], !continuation.returnedRegistercount !32
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP58:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @await.struct.DispatchSystemData(ptr [[TMP57]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_INNERPAYLOAD]] poison, ptr [[TMP46]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT_INNERPAYLOAD]], ptr [[TMP46]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP60:%.*]] = load float, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP60]], ptr [[TMP59]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP58]], ptr [[TMP54]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; LOWERRAYTRACINGPIPELINE-NEXT: br label [[DOTSPLIT:%.*]]
; LOWERRAYTRACINGPIPELINE: .split:
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP62:%.*]] = load float, ptr [[TMP51]], align 4, !tbaa [[TBAA28]]
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP62]], ptr [[TMP49]], align 4, !tbaa [[TBAA28]]
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP48]]) #[[ATTR0]]
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP37]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP38]], ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 22), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP39]], ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 23), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP40]], ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 24), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP41]], ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 25), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP42]], ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 26), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP43]], ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 27), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP44]], ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 28), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP45]], ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 29), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP61:%.*]] = load float, ptr [[TMP50]], align 4, !tbaa [[TBAA28]]
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP61]], ptr [[TMP48]], align 4, !tbaa [[TBAA28]]
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP47]]) #[[ATTR0]]
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP36]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP37]], ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 22), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP38]], ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 23), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP39]], ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 24), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP40]], ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 25), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP41]], ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 26), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP42]], ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 27), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP43]], ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 28), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP44]], ptr getelementptr inbounds ([37 x i32], ptr @PAYLOAD, i32 0, i32 29), align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP63:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr [[TMP63]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP65:%.*]] = getelementptr i32, ptr [[TMP64]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP66:%.*]] = load i32, ptr [[TMP65]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP66]], ptr getelementptr inbounds ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP67:%.*]] = getelementptr i32, ptr [[TMP64]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP68:%.*]] = load i32, ptr [[TMP67]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP68]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP69:%.*]] = getelementptr i32, ptr [[TMP64]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP70:%.*]] = load i32, ptr [[TMP69]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP70]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP71:%.*]] = getelementptr i32, ptr [[TMP64]], i64 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP72:%.*]] = load i32, ptr [[TMP71]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP72]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 10), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP73:%.*]] = getelementptr i32, ptr [[TMP64]], i64 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP74:%.*]] = load i32, ptr [[TMP73]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP74]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 11), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP75:%.*]] = getelementptr i32, ptr [[TMP64]], i64 5
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP76:%.*]] = load i32, ptr [[TMP75]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP76]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 12), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP77:%.*]] = getelementptr i32, ptr [[TMP64]], i64 6
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP78:%.*]] = load i32, ptr [[TMP77]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP78]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 13), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP79:%.*]] = getelementptr i32, ptr [[TMP64]], i64 7
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP80:%.*]] = load i32, ptr [[TMP79]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP80]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 14), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP81:%.*]] = getelementptr i32, ptr [[TMP64]], i64 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP82:%.*]] = load i32, ptr [[TMP81]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP82]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 15), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP83:%.*]] = getelementptr i32, ptr [[TMP64]], i64 9
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP84:%.*]] = load i32, ptr [[TMP83]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP84]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP85:%.*]] = getelementptr i32, ptr [[TMP64]], i64 10
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP86:%.*]] = load i32, ptr [[TMP85]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP86]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP87:%.*]] = getelementptr i32, ptr [[TMP64]], i64 11
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP88:%.*]] = load i32, ptr [[TMP87]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP88]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP89:%.*]] = getelementptr i32, ptr [[TMP64]], i64 12
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP90:%.*]] = load i32, ptr [[TMP89]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP90]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP91:%.*]] = getelementptr i32, ptr [[TMP64]], i64 13
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP92:%.*]] = load i32, ptr [[TMP91]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP92]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP93:%.*]] = getelementptr i32, ptr [[TMP64]], i64 14
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP94:%.*]] = load i32, ptr [[TMP93]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP94]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP95:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP96:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[TMP95]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP96]], !continuation.registercount [[META24]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP63:%.*]] = getelementptr i32, ptr [[TMP62]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr [[TMP63]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP65:%.*]] = load i32, ptr [[TMP64]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP65]], ptr getelementptr inbounds ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP66:%.*]] = getelementptr i32, ptr [[TMP63]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP67:%.*]] = load i32, ptr [[TMP66]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP67]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP68:%.*]] = getelementptr i32, ptr [[TMP63]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP69:%.*]] = load i32, ptr [[TMP68]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP69]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP70:%.*]] = getelementptr i32, ptr [[TMP63]], i64 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP71:%.*]] = load i32, ptr [[TMP70]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP71]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 10), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP72:%.*]] = getelementptr i32, ptr [[TMP63]], i64 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP73:%.*]] = load i32, ptr [[TMP72]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP73]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 11), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP74:%.*]] = getelementptr i32, ptr [[TMP63]], i64 5
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP75:%.*]] = load i32, ptr [[TMP74]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP75]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 12), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP76:%.*]] = getelementptr i32, ptr [[TMP63]], i64 6
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP77:%.*]] = load i32, ptr [[TMP76]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP77]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 13), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP78:%.*]] = getelementptr i32, ptr [[TMP63]], i64 7
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP79:%.*]] = load i32, ptr [[TMP78]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP79]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 14), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP80:%.*]] = getelementptr i32, ptr [[TMP63]], i64 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP81:%.*]] = load i32, ptr [[TMP80]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP81]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 15), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP82:%.*]] = getelementptr i32, ptr [[TMP63]], i64 9
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP83:%.*]] = load i32, ptr [[TMP82]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP83]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP84:%.*]] = getelementptr i32, ptr [[TMP63]], i64 10
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP85:%.*]] = load i32, ptr [[TMP84]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP85]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP86:%.*]] = getelementptr i32, ptr [[TMP63]], i64 11
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP87:%.*]] = load i32, ptr [[TMP86]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP87]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP88:%.*]] = getelementptr i32, ptr [[TMP63]], i64 12
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP89:%.*]] = load i32, ptr [[TMP88]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP89]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP90:%.*]] = getelementptr i32, ptr [[TMP63]], i64 13
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP91:%.*]] = load i32, ptr [[TMP90]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP91]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP92:%.*]] = getelementptr i32, ptr [[TMP63]], i64 14
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP93:%.*]] = load i32, ptr [[TMP92]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP93]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP94:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP95:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[TMP94]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP95]], !continuation.registercount [[META24]]
;
%1 = load %dx.types.Handle, %dx.types.Handle* @"\01?myAccelerationStructure@@3URaytracingAccelerationStructure@@A", align 4
%2 = alloca %struct.InnerPayload, align 4
@@ -210,577 +209,576 @@ define void @Callable(%struct.OuterPayload* noalias %outerPayload) #0 !types !23
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP2:%.*]] = alloca [[STRUCT_OUTERPAYLOAD:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_OUTERPAYLOAD]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP4]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP5]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = load i32, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP8]], ptr [[TMP7]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[TMP6]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 1), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP6]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 2), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP12]], ptr [[TMP11]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP6]], i64 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 3), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[TMP6]], i64 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 4), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP16]], ptr [[TMP15]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[TMP6]], i64 5
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 5), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP18]], ptr [[TMP17]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = getelementptr i32, ptr [[TMP6]], i64 6
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 6), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP20]], ptr [[TMP19]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[TMP6]], i64 7
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP22]], ptr [[TMP21]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = getelementptr i32, ptr [[TMP6]], i64 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP24]], ptr [[TMP23]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[TMP6]], i64 9
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP26]], ptr [[TMP25]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = getelementptr i32, ptr [[TMP6]], i64 10
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 10), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP28]], ptr [[TMP27]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr [[TMP6]], i64 11
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 11), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP30]], ptr [[TMP29]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = getelementptr i32, ptr [[TMP6]], i64 12
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 12), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP32]], ptr [[TMP31]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = getelementptr i32, ptr [[TMP6]], i64 13
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 13), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP34]], ptr [[TMP33]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = getelementptr i32, ptr [[TMP6]], i64 14
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 14), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP36]], ptr [[TMP35]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = getelementptr i32, ptr [[TMP37]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP39:%.*]] = getelementptr i32, ptr [[TMP38]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP40:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 15), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP40]], ptr [[TMP39]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP41:%.*]] = getelementptr i32, ptr [[TMP38]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP42:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP42]], ptr [[TMP41]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP43:%.*]] = getelementptr i32, ptr [[TMP38]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP44:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP44]], ptr [[TMP43]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP45:%.*]] = getelementptr i32, ptr [[TMP38]], i64 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP46:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP46]], ptr [[TMP45]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP47:%.*]] = getelementptr i32, ptr [[TMP38]], i64 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP48:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP48]], ptr [[TMP47]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP49:%.*]] = getelementptr i32, ptr [[TMP38]], i64 5
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP50:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP50]], ptr [[TMP49]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP51:%.*]] = getelementptr i32, ptr [[TMP38]], i64 6
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP52:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP52]], ptr [[TMP51]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP53:%.*]] = getelementptr i32, ptr [[TMP38]], i64 7
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP54:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP54]], ptr [[TMP53]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP55:%.*]] = getelementptr i32, ptr [[TMP38]], i64 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP56:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP56]], ptr [[TMP55]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP57:%.*]] = getelementptr i32, ptr [[TMP38]], i64 9
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP58:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP58]], ptr [[TMP57]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP59:%.*]] = getelementptr i32, ptr [[TMP38]], i64 10
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP60:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP60]], ptr [[TMP59]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP61:%.*]] = getelementptr i32, ptr [[TMP38]], i64 11
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP62:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP62]], ptr [[TMP61]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP63:%.*]] = getelementptr i32, ptr [[TMP38]], i64 12
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP64:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP64]], ptr [[TMP63]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP65:%.*]] = getelementptr i32, ptr [[TMP38]], i64 13
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP66:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP66]], ptr [[TMP65]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP67:%.*]] = getelementptr i32, ptr [[TMP38]], i64 14
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP68:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP68]], ptr [[TMP67]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[TMP4]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP5]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = load i32, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP5]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 1), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP9]], ptr [[TMP8]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP5]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 2), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP11]], ptr [[TMP10]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP5]], i64 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 3), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP13]], ptr [[TMP12]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP5]], i64 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 4), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP5]], i64 5
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 5), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP17]], ptr [[TMP16]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = getelementptr i32, ptr [[TMP5]], i64 6
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 6), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP19]], ptr [[TMP18]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[TMP5]], i64 7
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP21]], ptr [[TMP20]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr [[TMP5]], i64 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP23]], ptr [[TMP22]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr [[TMP5]], i64 9
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP25]], ptr [[TMP24]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[TMP5]], i64 10
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 10), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP27]], ptr [[TMP26]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = getelementptr i32, ptr [[TMP5]], i64 11
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 11), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP29]], ptr [[TMP28]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = getelementptr i32, ptr [[TMP5]], i64 12
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 12), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP31]], ptr [[TMP30]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = getelementptr i32, ptr [[TMP5]], i64 13
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 13), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP33]], ptr [[TMP32]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = getelementptr i32, ptr [[TMP5]], i64 14
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 14), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP35]], ptr [[TMP34]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = getelementptr i32, ptr [[TMP36]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = getelementptr i32, ptr [[TMP37]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP39:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 15), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP39]], ptr [[TMP38]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP40:%.*]] = getelementptr i32, ptr [[TMP37]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP41:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP41]], ptr [[TMP40]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP42:%.*]] = getelementptr i32, ptr [[TMP37]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP43:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP43]], ptr [[TMP42]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP44:%.*]] = getelementptr i32, ptr [[TMP37]], i64 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP45:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP45]], ptr [[TMP44]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP46:%.*]] = getelementptr i32, ptr [[TMP37]], i64 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP47:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP47]], ptr [[TMP46]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP48:%.*]] = getelementptr i32, ptr [[TMP37]], i64 5
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP49:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP49]], ptr [[TMP48]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP50:%.*]] = getelementptr i32, ptr [[TMP37]], i64 6
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP51:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP51]], ptr [[TMP50]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP52:%.*]] = getelementptr i32, ptr [[TMP37]], i64 7
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP53:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP53]], ptr [[TMP52]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP54:%.*]] = getelementptr i32, ptr [[TMP37]], i64 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP55:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP55]], ptr [[TMP54]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP56:%.*]] = getelementptr i32, ptr [[TMP37]], i64 9
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP57:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP57]], ptr [[TMP56]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP58:%.*]] = getelementptr i32, ptr [[TMP37]], i64 10
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP59:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP59]], ptr [[TMP58]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP60:%.*]] = getelementptr i32, ptr [[TMP37]], i64 11
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP61:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP61]], ptr [[TMP60]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP62:%.*]] = getelementptr i32, ptr [[TMP37]], i64 12
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP63:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP63]], ptr [[TMP62]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr [[TMP37]], i64 13
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP65:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP65]], ptr [[TMP64]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP66:%.*]] = getelementptr i32, ptr [[TMP37]], i64 14
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP67:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP67]], ptr [[TMP66]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP69:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP71:%.*]] = load float, ptr [[TMP70]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP71]], ptr [[TMP69]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP74:%.*]] = load float, ptr [[TMP73]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP74]], ptr [[TMP72]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP77:%.*]] = load float, ptr [[TMP76]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP77]], ptr [[TMP75]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP80:%.*]] = load float, ptr [[TMP79]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP80]], ptr [[TMP78]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP83:%.*]] = load float, ptr [[TMP82]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP83]], ptr [[TMP81]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP84:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 5
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP85:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 5
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP86:%.*]] = load float, ptr [[TMP85]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP86]], ptr [[TMP84]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP87:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 6
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP88:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 6
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP89:%.*]] = load float, ptr [[TMP88]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP89]], ptr [[TMP87]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP90:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 7
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP91:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 7
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP92:%.*]] = load float, ptr [[TMP91]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP92]], ptr [[TMP90]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP93:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP94:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP95:%.*]] = load float, ptr [[TMP94]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP95]], ptr [[TMP93]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP96:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 9
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP97:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 9
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP98:%.*]] = load float, ptr [[TMP97]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP98]], ptr [[TMP96]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP99:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 10
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP100:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 10
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP101:%.*]] = load float, ptr [[TMP100]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP101]], ptr [[TMP99]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 11
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 11
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP104:%.*]] = load float, ptr [[TMP103]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP104]], ptr [[TMP102]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 12
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 12
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP107:%.*]] = load float, ptr [[TMP106]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP107]], ptr [[TMP105]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 13
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 13
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP110:%.*]] = load float, ptr [[TMP109]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP110]], ptr [[TMP108]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 14
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 14
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP113:%.*]] = load float, ptr [[TMP112]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP113]], ptr [[TMP111]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP114:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP115:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP116:%.*]] = load float, ptr [[TMP115]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP116]], ptr [[TMP114]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP117:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP118:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP119:%.*]] = load float, ptr [[TMP118]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP119]], ptr [[TMP117]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP120:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP121:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP122:%.*]] = load float, ptr [[TMP121]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP122]], ptr [[TMP120]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP123:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP124:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP125:%.*]] = load float, ptr [[TMP124]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP125]], ptr [[TMP123]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP126:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP127:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP128:%.*]] = load float, ptr [[TMP127]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP128]], ptr [[TMP126]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 5
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 5
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP131:%.*]] = load float, ptr [[TMP130]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP131]], ptr [[TMP129]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 6
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 6
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP134:%.*]] = load float, ptr [[TMP133]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP134]], ptr [[TMP132]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 7
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 7
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP137:%.*]] = load float, ptr [[TMP136]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP137]], ptr [[TMP135]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP140:%.*]] = load float, ptr [[TMP139]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP140]], ptr [[TMP138]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 9
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP142:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 9
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP143:%.*]] = load float, ptr [[TMP142]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP143]], ptr [[TMP141]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP144:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 10
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP145:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 10
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP146:%.*]] = load float, ptr [[TMP145]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP146]], ptr [[TMP144]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 11
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP148:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 11
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP149:%.*]] = load float, ptr [[TMP148]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP149]], ptr [[TMP147]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP150:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 12
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP151:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 12
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP152:%.*]] = load float, ptr [[TMP151]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP152]], ptr [[TMP150]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP153:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 13
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP154:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 13
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP155:%.*]] = load float, ptr [[TMP154]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP155]], ptr [[TMP153]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP156:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 14
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP157:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 14
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP158:%.*]] = load float, ptr [[TMP157]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP158]], ptr [[TMP156]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP68:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP69:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP70:%.*]] = load float, ptr [[TMP69]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP70]], ptr [[TMP68]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP73:%.*]] = load float, ptr [[TMP72]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP73]], ptr [[TMP71]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP76:%.*]] = load float, ptr [[TMP75]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP76]], ptr [[TMP74]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP79:%.*]] = load float, ptr [[TMP78]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP79]], ptr [[TMP77]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP82:%.*]] = load float, ptr [[TMP81]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP82]], ptr [[TMP80]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP83:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 5
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP84:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 5
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP85:%.*]] = load float, ptr [[TMP84]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP85]], ptr [[TMP83]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP86:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 6
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP87:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 6
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP88:%.*]] = load float, ptr [[TMP87]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP88]], ptr [[TMP86]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP89:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 7
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP90:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 7
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP91:%.*]] = load float, ptr [[TMP90]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP91]], ptr [[TMP89]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP92:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP93:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP94:%.*]] = load float, ptr [[TMP93]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP94]], ptr [[TMP92]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP95:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 9
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP96:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 9
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP97:%.*]] = load float, ptr [[TMP96]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP97]], ptr [[TMP95]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP98:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 10
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP99:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 10
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP100:%.*]] = load float, ptr [[TMP99]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP100]], ptr [[TMP98]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 11
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 11
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP103:%.*]] = load float, ptr [[TMP102]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP103]], ptr [[TMP101]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 12
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 12
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP106:%.*]] = load float, ptr [[TMP105]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP106]], ptr [[TMP104]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 13
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 13
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP109:%.*]] = load float, ptr [[TMP108]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP109]], ptr [[TMP107]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0, i32 14
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0, i32 14
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP112:%.*]] = load float, ptr [[TMP111]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP112]], ptr [[TMP110]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP114:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP115:%.*]] = load float, ptr [[TMP114]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP115]], ptr [[TMP113]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP116:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP117:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP118:%.*]] = load float, ptr [[TMP117]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP118]], ptr [[TMP116]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP119:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP120:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP121:%.*]] = load float, ptr [[TMP120]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP121]], ptr [[TMP119]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP122:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP123:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP124:%.*]] = load float, ptr [[TMP123]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP124]], ptr [[TMP122]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP125:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP126:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP127:%.*]] = load float, ptr [[TMP126]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP127]], ptr [[TMP125]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP128:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 5
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 5
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP130:%.*]] = load float, ptr [[TMP129]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP130]], ptr [[TMP128]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 6
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 6
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP133:%.*]] = load float, ptr [[TMP132]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP133]], ptr [[TMP131]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 7
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 7
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP136:%.*]] = load float, ptr [[TMP135]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP136]], ptr [[TMP134]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP139:%.*]] = load float, ptr [[TMP138]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP139]], ptr [[TMP137]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 9
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 9
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP142:%.*]] = load float, ptr [[TMP141]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP142]], ptr [[TMP140]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP143:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 10
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP144:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 10
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP145:%.*]] = load float, ptr [[TMP144]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP145]], ptr [[TMP143]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP146:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 11
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 11
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP148:%.*]] = load float, ptr [[TMP147]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP148]], ptr [[TMP146]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP149:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 12
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP150:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 12
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP151:%.*]] = load float, ptr [[TMP150]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP151]], ptr [[TMP149]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP152:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 13
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP153:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 13
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP154:%.*]] = load float, ptr [[TMP153]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP154]], ptr [[TMP152]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP155:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1, i32 14
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP156:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1, i32 14
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP157:%.*]] = load float, ptr [[TMP156]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP157]], ptr [[TMP155]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[DIS_DATA_I:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP159:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP160:%.*]] = getelementptr i32, ptr [[TMP159]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP161:%.*]] = getelementptr i32, ptr [[TMP160]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP162:%.*]] = load i32, ptr [[TMP161]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP162]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP163:%.*]] = getelementptr i32, ptr [[TMP160]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP164:%.*]] = load i32, ptr [[TMP163]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP164]], ptr getelementptr (i32, ptr @PAYLOAD, i64 1), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP165:%.*]] = getelementptr i32, ptr [[TMP160]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP166:%.*]] = load i32, ptr [[TMP165]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP166]], ptr getelementptr (i32, ptr @PAYLOAD, i64 2), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP167:%.*]] = getelementptr i32, ptr [[TMP160]], i64 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP168:%.*]] = load i32, ptr [[TMP167]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP168]], ptr getelementptr (i32, ptr @PAYLOAD, i64 3), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP169:%.*]] = getelementptr i32, ptr [[TMP160]], i64 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP170:%.*]] = load i32, ptr [[TMP169]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP170]], ptr getelementptr (i32, ptr @PAYLOAD, i64 4), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP171:%.*]] = getelementptr i32, ptr [[TMP160]], i64 5
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP172:%.*]] = load i32, ptr [[TMP171]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP172]], ptr getelementptr (i32, ptr @PAYLOAD, i64 5), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP173:%.*]] = getelementptr i32, ptr [[TMP160]], i64 6
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP174:%.*]] = load i32, ptr [[TMP173]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP174]], ptr getelementptr (i32, ptr @PAYLOAD, i64 6), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP175:%.*]] = getelementptr i32, ptr [[TMP160]], i64 7
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP176:%.*]] = load i32, ptr [[TMP175]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP176]], ptr getelementptr (i32, ptr @PAYLOAD, i64 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP177:%.*]] = getelementptr i32, ptr [[TMP160]], i64 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP178:%.*]] = load i32, ptr [[TMP177]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP178]], ptr getelementptr (i32, ptr @PAYLOAD, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP179:%.*]] = getelementptr i32, ptr [[TMP160]], i64 9
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP180:%.*]] = load i32, ptr [[TMP179]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP180]], ptr getelementptr (i32, ptr @PAYLOAD, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP181:%.*]] = getelementptr i32, ptr [[TMP160]], i64 10
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP182:%.*]] = load i32, ptr [[TMP181]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP182]], ptr getelementptr (i32, ptr @PAYLOAD, i64 10), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP183:%.*]] = getelementptr i32, ptr [[TMP160]], i64 11
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP184:%.*]] = load i32, ptr [[TMP183]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP184]], ptr getelementptr (i32, ptr @PAYLOAD, i64 11), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP185:%.*]] = getelementptr i32, ptr [[TMP160]], i64 12
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP186:%.*]] = load i32, ptr [[TMP185]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP186]], ptr getelementptr (i32, ptr @PAYLOAD, i64 12), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP187:%.*]] = getelementptr i32, ptr [[TMP160]], i64 13
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP188:%.*]] = load i32, ptr [[TMP187]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP188]], ptr getelementptr (i32, ptr @PAYLOAD, i64 13), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP189:%.*]] = getelementptr i32, ptr [[TMP160]], i64 14
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP190:%.*]] = load i32, ptr [[TMP189]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP190]], ptr getelementptr (i32, ptr @PAYLOAD, i64 14), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP191:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP192:%.*]] = getelementptr i32, ptr [[TMP191]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP193:%.*]] = getelementptr i32, ptr [[TMP192]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP194:%.*]] = load i32, ptr [[TMP193]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP194]], ptr getelementptr inbounds ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i32 15), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP195:%.*]] = getelementptr i32, ptr [[TMP192]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP196:%.*]] = load i32, ptr [[TMP195]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP196]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP197:%.*]] = getelementptr i32, ptr [[TMP192]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP198:%.*]] = load i32, ptr [[TMP197]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP198]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP199:%.*]] = getelementptr i32, ptr [[TMP192]], i64 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP200:%.*]] = load i32, ptr [[TMP199]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP200]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP201:%.*]] = getelementptr i32, ptr [[TMP192]], i64 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP202:%.*]] = load i32, ptr [[TMP201]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP202]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP203:%.*]] = getelementptr i32, ptr [[TMP192]], i64 5
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP204:%.*]] = load i32, ptr [[TMP203]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP204]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP205:%.*]] = getelementptr i32, ptr [[TMP192]], i64 6
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP206:%.*]] = load i32, ptr [[TMP205]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP206]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP207:%.*]] = getelementptr i32, ptr [[TMP192]], i64 7
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP208:%.*]] = load i32, ptr [[TMP207]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP208]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP209:%.*]] = getelementptr i32, ptr [[TMP192]], i64 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP210:%.*]] = load i32, ptr [[TMP209]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP210]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP211:%.*]] = getelementptr i32, ptr [[TMP192]], i64 9
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP212:%.*]] = load i32, ptr [[TMP211]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP212]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP213:%.*]] = getelementptr i32, ptr [[TMP192]], i64 10
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP214:%.*]] = load i32, ptr [[TMP213]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP214]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP215:%.*]] = getelementptr i32, ptr [[TMP192]], i64 11
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP216:%.*]] = load i32, ptr [[TMP215]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP216]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP217:%.*]] = getelementptr i32, ptr [[TMP192]], i64 12
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP218:%.*]] = load i32, ptr [[TMP217]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP218]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP219:%.*]] = getelementptr i32, ptr [[TMP192]], i64 13
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP220:%.*]] = load i32, ptr [[TMP219]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP220]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP221:%.*]] = getelementptr i32, ptr [[TMP192]], i64 14
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP222:%.*]] = load i32, ptr [[TMP221]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP222]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP223:%.*]] = call ptr inttoptr (i64 2 to ptr)([[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I]]), !continuation.registercount [[META24]], !continuation.returnedRegistercount !24
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP224:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @await.struct.DispatchSystemData(ptr [[TMP223]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP158:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP159:%.*]] = getelementptr i32, ptr [[TMP158]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP160:%.*]] = getelementptr i32, ptr [[TMP159]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP161:%.*]] = load i32, ptr [[TMP160]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP161]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP162:%.*]] = getelementptr i32, ptr [[TMP159]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP163:%.*]] = load i32, ptr [[TMP162]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP163]], ptr getelementptr (i32, ptr @PAYLOAD, i64 1), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP164:%.*]] = getelementptr i32, ptr [[TMP159]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP165:%.*]] = load i32, ptr [[TMP164]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP165]], ptr getelementptr (i32, ptr @PAYLOAD, i64 2), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP166:%.*]] = getelementptr i32, ptr [[TMP159]], i64 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP167:%.*]] = load i32, ptr [[TMP166]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP167]], ptr getelementptr (i32, ptr @PAYLOAD, i64 3), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP168:%.*]] = getelementptr i32, ptr [[TMP159]], i64 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP169:%.*]] = load i32, ptr [[TMP168]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP169]], ptr getelementptr (i32, ptr @PAYLOAD, i64 4), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP170:%.*]] = getelementptr i32, ptr [[TMP159]], i64 5
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP171:%.*]] = load i32, ptr [[TMP170]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP171]], ptr getelementptr (i32, ptr @PAYLOAD, i64 5), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP172:%.*]] = getelementptr i32, ptr [[TMP159]], i64 6
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP173:%.*]] = load i32, ptr [[TMP172]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP173]], ptr getelementptr (i32, ptr @PAYLOAD, i64 6), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP174:%.*]] = getelementptr i32, ptr [[TMP159]], i64 7
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP175:%.*]] = load i32, ptr [[TMP174]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP175]], ptr getelementptr (i32, ptr @PAYLOAD, i64 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP176:%.*]] = getelementptr i32, ptr [[TMP159]], i64 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP177:%.*]] = load i32, ptr [[TMP176]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP177]], ptr getelementptr (i32, ptr @PAYLOAD, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP178:%.*]] = getelementptr i32, ptr [[TMP159]], i64 9
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP179:%.*]] = load i32, ptr [[TMP178]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP179]], ptr getelementptr (i32, ptr @PAYLOAD, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP180:%.*]] = getelementptr i32, ptr [[TMP159]], i64 10
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP181:%.*]] = load i32, ptr [[TMP180]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP181]], ptr getelementptr (i32, ptr @PAYLOAD, i64 10), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP182:%.*]] = getelementptr i32, ptr [[TMP159]], i64 11
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP183:%.*]] = load i32, ptr [[TMP182]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP183]], ptr getelementptr (i32, ptr @PAYLOAD, i64 11), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP184:%.*]] = getelementptr i32, ptr [[TMP159]], i64 12
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP185:%.*]] = load i32, ptr [[TMP184]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP185]], ptr getelementptr (i32, ptr @PAYLOAD, i64 12), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP186:%.*]] = getelementptr i32, ptr [[TMP159]], i64 13
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP187:%.*]] = load i32, ptr [[TMP186]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP187]], ptr getelementptr (i32, ptr @PAYLOAD, i64 13), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP188:%.*]] = getelementptr i32, ptr [[TMP159]], i64 14
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP189:%.*]] = load i32, ptr [[TMP188]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP189]], ptr getelementptr (i32, ptr @PAYLOAD, i64 14), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP190:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP191:%.*]] = getelementptr i32, ptr [[TMP190]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP192:%.*]] = getelementptr i32, ptr [[TMP191]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP193:%.*]] = load i32, ptr [[TMP192]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP193]], ptr getelementptr inbounds ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i32 15), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP194:%.*]] = getelementptr i32, ptr [[TMP191]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP195:%.*]] = load i32, ptr [[TMP194]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP195]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP196:%.*]] = getelementptr i32, ptr [[TMP191]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP197:%.*]] = load i32, ptr [[TMP196]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP197]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP198:%.*]] = getelementptr i32, ptr [[TMP191]], i64 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP199:%.*]] = load i32, ptr [[TMP198]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP199]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP200:%.*]] = getelementptr i32, ptr [[TMP191]], i64 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP201:%.*]] = load i32, ptr [[TMP200]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP201]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP202:%.*]] = getelementptr i32, ptr [[TMP191]], i64 5
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP203:%.*]] = load i32, ptr [[TMP202]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP203]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP204:%.*]] = getelementptr i32, ptr [[TMP191]], i64 6
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP205:%.*]] = load i32, ptr [[TMP204]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP205]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP206:%.*]] = getelementptr i32, ptr [[TMP191]], i64 7
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP207:%.*]] = load i32, ptr [[TMP206]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP207]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP208:%.*]] = getelementptr i32, ptr [[TMP191]], i64 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP209:%.*]] = load i32, ptr [[TMP208]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP209]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP210:%.*]] = getelementptr i32, ptr [[TMP191]], i64 9
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP211:%.*]] = load i32, ptr [[TMP210]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP211]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP212:%.*]] = getelementptr i32, ptr [[TMP191]], i64 10
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP213:%.*]] = load i32, ptr [[TMP212]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP213]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP214:%.*]] = getelementptr i32, ptr [[TMP191]], i64 11
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP215:%.*]] = load i32, ptr [[TMP214]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP215]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP216:%.*]] = getelementptr i32, ptr [[TMP191]], i64 12
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP217:%.*]] = load i32, ptr [[TMP216]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP217]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP218:%.*]] = getelementptr i32, ptr [[TMP191]], i64 13
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP219:%.*]] = load i32, ptr [[TMP218]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP219]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP220:%.*]] = getelementptr i32, ptr [[TMP191]], i64 14
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP221:%.*]] = load i32, ptr [[TMP220]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP221]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP222:%.*]] = call ptr inttoptr (i64 2 to ptr)([[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I]]), !continuation.registercount [[META24]], !continuation.returnedRegistercount !24
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP223:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @await.struct.DispatchSystemData(ptr [[TMP222]])
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_OUTERPAYLOAD]] poison, ptr [[TMP2]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP225:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP226:%.*]] = getelementptr i32, ptr [[TMP225]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP227:%.*]] = getelementptr i32, ptr [[TMP226]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP228:%.*]] = load i32, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP228]], ptr [[TMP227]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP229:%.*]] = getelementptr i32, ptr [[TMP226]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP230:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 1), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP230]], ptr [[TMP229]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP231:%.*]] = getelementptr i32, ptr [[TMP226]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP232:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 2), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP232]], ptr [[TMP231]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP233:%.*]] = getelementptr i32, ptr [[TMP226]], i64 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP234:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 3), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP234]], ptr [[TMP233]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP235:%.*]] = getelementptr i32, ptr [[TMP226]], i64 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP236:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 4), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP236]], ptr [[TMP235]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP237:%.*]] = getelementptr i32, ptr [[TMP226]], i64 5
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP238:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 5), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP238]], ptr [[TMP237]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP239:%.*]] = getelementptr i32, ptr [[TMP226]], i64 6
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP240:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 6), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP240]], ptr [[TMP239]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP241:%.*]] = getelementptr i32, ptr [[TMP226]], i64 7
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP242:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP242]], ptr [[TMP241]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP243:%.*]] = getelementptr i32, ptr [[TMP226]], i64 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP244:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP244]], ptr [[TMP243]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP245:%.*]] = getelementptr i32, ptr [[TMP226]], i64 9
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP246:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP246]], ptr [[TMP245]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP247:%.*]] = getelementptr i32, ptr [[TMP226]], i64 10
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP248:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 10), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP248]], ptr [[TMP247]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP249:%.*]] = getelementptr i32, ptr [[TMP226]], i64 11
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP250:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 11), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP250]], ptr [[TMP249]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP251:%.*]] = getelementptr i32, ptr [[TMP226]], i64 12
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP252:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 12), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP252]], ptr [[TMP251]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP253:%.*]] = getelementptr i32, ptr [[TMP226]], i64 13
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP254:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 13), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP254]], ptr [[TMP253]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP255:%.*]] = getelementptr i32, ptr [[TMP226]], i64 14
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP256:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 14), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP256]], ptr [[TMP255]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP257:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP258:%.*]] = getelementptr i32, ptr [[TMP257]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP259:%.*]] = getelementptr i32, ptr [[TMP258]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP260:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i32 15), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP260]], ptr [[TMP259]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP261:%.*]] = getelementptr i32, ptr [[TMP258]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP262:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP262]], ptr [[TMP261]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP263:%.*]] = getelementptr i32, ptr [[TMP258]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP264:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP264]], ptr [[TMP263]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP265:%.*]] = getelementptr i32, ptr [[TMP258]], i64 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP266:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP266]], ptr [[TMP265]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP267:%.*]] = getelementptr i32, ptr [[TMP258]], i64 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP268:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP268]], ptr [[TMP267]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP269:%.*]] = getelementptr i32, ptr [[TMP258]], i64 5
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP270:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP270]], ptr [[TMP269]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP271:%.*]] = getelementptr i32, ptr [[TMP258]], i64 6
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP272:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP272]], ptr [[TMP271]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP273:%.*]] = getelementptr i32, ptr [[TMP258]], i64 7
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP274:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP274]], ptr [[TMP273]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP275:%.*]] = getelementptr i32, ptr [[TMP258]], i64 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP276:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP276]], ptr [[TMP275]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP277:%.*]] = getelementptr i32, ptr [[TMP258]], i64 9
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP278:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP278]], ptr [[TMP277]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP279:%.*]] = getelementptr i32, ptr [[TMP258]], i64 10
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP280:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP280]], ptr [[TMP279]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP281:%.*]] = getelementptr i32, ptr [[TMP258]], i64 11
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP282:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP282]], ptr [[TMP281]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP283:%.*]] = getelementptr i32, ptr [[TMP258]], i64 12
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP284:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP284]], ptr [[TMP283]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP285:%.*]] = getelementptr i32, ptr [[TMP258]], i64 13
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP286:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP286]], ptr [[TMP285]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP287:%.*]] = getelementptr i32, ptr [[TMP258]], i64 14
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP288:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP288]], ptr [[TMP287]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP224]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP224:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP225:%.*]] = getelementptr i32, ptr [[TMP224]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP226:%.*]] = getelementptr i32, ptr [[TMP225]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP227:%.*]] = load i32, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP227]], ptr [[TMP226]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP228:%.*]] = getelementptr i32, ptr [[TMP225]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP229:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 1), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP229]], ptr [[TMP228]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP230:%.*]] = getelementptr i32, ptr [[TMP225]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP231:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 2), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP231]], ptr [[TMP230]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP232:%.*]] = getelementptr i32, ptr [[TMP225]], i64 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP233:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 3), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP233]], ptr [[TMP232]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP234:%.*]] = getelementptr i32, ptr [[TMP225]], i64 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP235:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 4), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP235]], ptr [[TMP234]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP236:%.*]] = getelementptr i32, ptr [[TMP225]], i64 5
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP237:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 5), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP237]], ptr [[TMP236]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP238:%.*]] = getelementptr i32, ptr [[TMP225]], i64 6
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP239:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 6), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP239]], ptr [[TMP238]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP240:%.*]] = getelementptr i32, ptr [[TMP225]], i64 7
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP241:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP241]], ptr [[TMP240]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP242:%.*]] = getelementptr i32, ptr [[TMP225]], i64 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP243:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP243]], ptr [[TMP242]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP244:%.*]] = getelementptr i32, ptr [[TMP225]], i64 9
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP245:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP245]], ptr [[TMP244]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP246:%.*]] = getelementptr i32, ptr [[TMP225]], i64 10
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP247:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 10), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP247]], ptr [[TMP246]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP248:%.*]] = getelementptr i32, ptr [[TMP225]], i64 11
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP249:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 11), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP249]], ptr [[TMP248]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP250:%.*]] = getelementptr i32, ptr [[TMP225]], i64 12
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP251:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 12), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP251]], ptr [[TMP250]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP252:%.*]] = getelementptr i32, ptr [[TMP225]], i64 13
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP253:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 13), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP253]], ptr [[TMP252]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP254:%.*]] = getelementptr i32, ptr [[TMP225]], i64 14
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP255:%.*]] = load i32, ptr getelementptr (i32, ptr @PAYLOAD, i64 14), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP255]], ptr [[TMP254]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP256:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP2]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP257:%.*]] = getelementptr i32, ptr [[TMP256]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP258:%.*]] = getelementptr i32, ptr [[TMP257]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP259:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i32 15), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP259]], ptr [[TMP258]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP260:%.*]] = getelementptr i32, ptr [[TMP257]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP261:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP261]], ptr [[TMP260]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP262:%.*]] = getelementptr i32, ptr [[TMP257]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP263:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP263]], ptr [[TMP262]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP264:%.*]] = getelementptr i32, ptr [[TMP257]], i64 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP265:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP265]], ptr [[TMP264]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP266:%.*]] = getelementptr i32, ptr [[TMP257]], i64 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP267:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP267]], ptr [[TMP266]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP268:%.*]] = getelementptr i32, ptr [[TMP257]], i64 5
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP269:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP269]], ptr [[TMP268]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP270:%.*]] = getelementptr i32, ptr [[TMP257]], i64 6
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP271:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP271]], ptr [[TMP270]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP272:%.*]] = getelementptr i32, ptr [[TMP257]], i64 7
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP273:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP273]], ptr [[TMP272]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP274:%.*]] = getelementptr i32, ptr [[TMP257]], i64 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP275:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP275]], ptr [[TMP274]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP276:%.*]] = getelementptr i32, ptr [[TMP257]], i64 9
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP277:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP277]], ptr [[TMP276]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP278:%.*]] = getelementptr i32, ptr [[TMP257]], i64 10
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP279:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP279]], ptr [[TMP278]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP280:%.*]] = getelementptr i32, ptr [[TMP257]], i64 11
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP281:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP281]], ptr [[TMP280]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP282:%.*]] = getelementptr i32, ptr [[TMP257]], i64 12
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP283:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP283]], ptr [[TMP282]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP284:%.*]] = getelementptr i32, ptr [[TMP257]], i64 13
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP285:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP285]], ptr [[TMP284]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP286:%.*]] = getelementptr i32, ptr [[TMP257]], i64 14
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP287:%.*]] = load i32, ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP287]], ptr [[TMP286]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP223]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; LOWERRAYTRACINGPIPELINE-NEXT: br label [[DOTSPLIT:%.*]]
; LOWERRAYTRACINGPIPELINE: .split:
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP289:%.*]] = load float, ptr [[TMP69]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP289]], ptr [[TMP70]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP290:%.*]] = load float, ptr [[TMP72]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP290]], ptr [[TMP73]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP291:%.*]] = load float, ptr [[TMP75]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP291]], ptr [[TMP76]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP292:%.*]] = load float, ptr [[TMP78]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP292]], ptr [[TMP79]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP293:%.*]] = load float, ptr [[TMP81]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP293]], ptr [[TMP82]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP294:%.*]] = load float, ptr [[TMP84]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP294]], ptr [[TMP85]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP295:%.*]] = load float, ptr [[TMP87]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP295]], ptr [[TMP88]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP296:%.*]] = load float, ptr [[TMP90]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP296]], ptr [[TMP91]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP297:%.*]] = load float, ptr [[TMP93]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP297]], ptr [[TMP94]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP298:%.*]] = load float, ptr [[TMP96]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP298]], ptr [[TMP97]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP299:%.*]] = load float, ptr [[TMP99]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP299]], ptr [[TMP100]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP300:%.*]] = load float, ptr [[TMP102]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP300]], ptr [[TMP103]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP301:%.*]] = load float, ptr [[TMP105]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP301]], ptr [[TMP106]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP302:%.*]] = load float, ptr [[TMP108]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP302]], ptr [[TMP109]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP303:%.*]] = load float, ptr [[TMP111]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP303]], ptr [[TMP112]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP304:%.*]] = load float, ptr [[TMP114]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP304]], ptr [[TMP115]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP305:%.*]] = load float, ptr [[TMP117]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP305]], ptr [[TMP118]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP306:%.*]] = load float, ptr [[TMP120]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP306]], ptr [[TMP121]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP307:%.*]] = load float, ptr [[TMP123]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP307]], ptr [[TMP124]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP308:%.*]] = load float, ptr [[TMP126]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP308]], ptr [[TMP127]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP309:%.*]] = load float, ptr [[TMP129]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP309]], ptr [[TMP130]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP310:%.*]] = load float, ptr [[TMP132]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP310]], ptr [[TMP133]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP311:%.*]] = load float, ptr [[TMP135]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP311]], ptr [[TMP136]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP312:%.*]] = load float, ptr [[TMP138]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP312]], ptr [[TMP139]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP313:%.*]] = load float, ptr [[TMP141]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP313]], ptr [[TMP142]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP314:%.*]] = load float, ptr [[TMP144]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP314]], ptr [[TMP145]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP315:%.*]] = load float, ptr [[TMP147]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP315]], ptr [[TMP148]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP316:%.*]] = load float, ptr [[TMP150]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP316]], ptr [[TMP151]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP317:%.*]] = load float, ptr [[TMP153]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP317]], ptr [[TMP154]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP318:%.*]] = load float, ptr [[TMP156]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP318]], ptr [[TMP157]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP288:%.*]] = load float, ptr [[TMP68]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP288]], ptr [[TMP69]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP289:%.*]] = load float, ptr [[TMP71]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP289]], ptr [[TMP72]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP290:%.*]] = load float, ptr [[TMP74]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP290]], ptr [[TMP75]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP291:%.*]] = load float, ptr [[TMP77]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP291]], ptr [[TMP78]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP292:%.*]] = load float, ptr [[TMP80]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP292]], ptr [[TMP81]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP293:%.*]] = load float, ptr [[TMP83]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP293]], ptr [[TMP84]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP294:%.*]] = load float, ptr [[TMP86]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP294]], ptr [[TMP87]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP295:%.*]] = load float, ptr [[TMP89]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP295]], ptr [[TMP90]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP296:%.*]] = load float, ptr [[TMP92]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP296]], ptr [[TMP93]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP297:%.*]] = load float, ptr [[TMP95]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP297]], ptr [[TMP96]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP298:%.*]] = load float, ptr [[TMP98]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP298]], ptr [[TMP99]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP299:%.*]] = load float, ptr [[TMP101]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP299]], ptr [[TMP102]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP300:%.*]] = load float, ptr [[TMP104]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP300]], ptr [[TMP105]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP301:%.*]] = load float, ptr [[TMP107]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP301]], ptr [[TMP108]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP302:%.*]] = load float, ptr [[TMP110]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP302]], ptr [[TMP111]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP303:%.*]] = load float, ptr [[TMP113]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP303]], ptr [[TMP114]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP304:%.*]] = load float, ptr [[TMP116]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP304]], ptr [[TMP117]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP305:%.*]] = load float, ptr [[TMP119]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP305]], ptr [[TMP120]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP306:%.*]] = load float, ptr [[TMP122]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP306]], ptr [[TMP123]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP307:%.*]] = load float, ptr [[TMP125]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP307]], ptr [[TMP126]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP308:%.*]] = load float, ptr [[TMP128]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP308]], ptr [[TMP129]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP309:%.*]] = load float, ptr [[TMP131]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP309]], ptr [[TMP132]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP310:%.*]] = load float, ptr [[TMP134]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP310]], ptr [[TMP135]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP311:%.*]] = load float, ptr [[TMP137]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP311]], ptr [[TMP138]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP312:%.*]] = load float, ptr [[TMP140]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP312]], ptr [[TMP141]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP313:%.*]] = load float, ptr [[TMP143]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP313]], ptr [[TMP144]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP314:%.*]] = load float, ptr [[TMP146]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP314]], ptr [[TMP147]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP315:%.*]] = load float, ptr [[TMP149]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP315]], ptr [[TMP150]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP316:%.*]] = load float, ptr [[TMP152]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP316]], ptr [[TMP153]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP317:%.*]] = load float, ptr [[TMP155]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store float [[TMP317]], ptr [[TMP156]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP319:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP320:%.*]] = getelementptr i32, ptr [[TMP319]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP321:%.*]] = getelementptr i32, ptr [[TMP320]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP322:%.*]] = load i32, ptr [[TMP321]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP322]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP323:%.*]] = getelementptr i32, ptr [[TMP320]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP324:%.*]] = load i32, ptr [[TMP323]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP324]], ptr getelementptr (i32, ptr @PAYLOAD, i64 1), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP325:%.*]] = getelementptr i32, ptr [[TMP320]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP326:%.*]] = load i32, ptr [[TMP325]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP326]], ptr getelementptr (i32, ptr @PAYLOAD, i64 2), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP327:%.*]] = getelementptr i32, ptr [[TMP320]], i64 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP328:%.*]] = load i32, ptr [[TMP327]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP328]], ptr getelementptr (i32, ptr @PAYLOAD, i64 3), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP329:%.*]] = getelementptr i32, ptr [[TMP320]], i64 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP330:%.*]] = load i32, ptr [[TMP329]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP330]], ptr getelementptr (i32, ptr @PAYLOAD, i64 4), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP331:%.*]] = getelementptr i32, ptr [[TMP320]], i64 5
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP332:%.*]] = load i32, ptr [[TMP331]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP332]], ptr getelementptr (i32, ptr @PAYLOAD, i64 5), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP333:%.*]] = getelementptr i32, ptr [[TMP320]], i64 6
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP334:%.*]] = load i32, ptr [[TMP333]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP334]], ptr getelementptr (i32, ptr @PAYLOAD, i64 6), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP335:%.*]] = getelementptr i32, ptr [[TMP320]], i64 7
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP336:%.*]] = load i32, ptr [[TMP335]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP336]], ptr getelementptr (i32, ptr @PAYLOAD, i64 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP337:%.*]] = getelementptr i32, ptr [[TMP320]], i64 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP338:%.*]] = load i32, ptr [[TMP337]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP338]], ptr getelementptr (i32, ptr @PAYLOAD, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP339:%.*]] = getelementptr i32, ptr [[TMP320]], i64 9
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP340:%.*]] = load i32, ptr [[TMP339]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP340]], ptr getelementptr (i32, ptr @PAYLOAD, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP341:%.*]] = getelementptr i32, ptr [[TMP320]], i64 10
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP342:%.*]] = load i32, ptr [[TMP341]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP342]], ptr getelementptr (i32, ptr @PAYLOAD, i64 10), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP343:%.*]] = getelementptr i32, ptr [[TMP320]], i64 11
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP344:%.*]] = load i32, ptr [[TMP343]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP344]], ptr getelementptr (i32, ptr @PAYLOAD, i64 11), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP345:%.*]] = getelementptr i32, ptr [[TMP320]], i64 12
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP346:%.*]] = load i32, ptr [[TMP345]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP346]], ptr getelementptr (i32, ptr @PAYLOAD, i64 12), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP347:%.*]] = getelementptr i32, ptr [[TMP320]], i64 13
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP348:%.*]] = load i32, ptr [[TMP347]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP348]], ptr getelementptr (i32, ptr @PAYLOAD, i64 13), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP349:%.*]] = getelementptr i32, ptr [[TMP320]], i64 14
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP350:%.*]] = load i32, ptr [[TMP349]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP350]], ptr getelementptr (i32, ptr @PAYLOAD, i64 14), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP351:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP352:%.*]] = getelementptr i32, ptr [[TMP351]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP353:%.*]] = getelementptr i32, ptr [[TMP352]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP354:%.*]] = load i32, ptr [[TMP353]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP354]], ptr getelementptr inbounds ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i32 15), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP355:%.*]] = getelementptr i32, ptr [[TMP352]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP356:%.*]] = load i32, ptr [[TMP355]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP356]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP357:%.*]] = getelementptr i32, ptr [[TMP352]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP358:%.*]] = load i32, ptr [[TMP357]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP358]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP359:%.*]] = getelementptr i32, ptr [[TMP352]], i64 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP360:%.*]] = load i32, ptr [[TMP359]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP360]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP361:%.*]] = getelementptr i32, ptr [[TMP352]], i64 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP362:%.*]] = load i32, ptr [[TMP361]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP362]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP363:%.*]] = getelementptr i32, ptr [[TMP352]], i64 5
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP364:%.*]] = load i32, ptr [[TMP363]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP364]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP365:%.*]] = getelementptr i32, ptr [[TMP352]], i64 6
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP366:%.*]] = load i32, ptr [[TMP365]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP366]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP367:%.*]] = getelementptr i32, ptr [[TMP352]], i64 7
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP368:%.*]] = load i32, ptr [[TMP367]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP368]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP369:%.*]] = getelementptr i32, ptr [[TMP352]], i64 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP370:%.*]] = load i32, ptr [[TMP369]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP370]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP371:%.*]] = getelementptr i32, ptr [[TMP352]], i64 9
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP372:%.*]] = load i32, ptr [[TMP371]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP372]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP373:%.*]] = getelementptr i32, ptr [[TMP352]], i64 10
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP374:%.*]] = load i32, ptr [[TMP373]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP374]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP375:%.*]] = getelementptr i32, ptr [[TMP352]], i64 11
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP376:%.*]] = load i32, ptr [[TMP375]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP376]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP377:%.*]] = getelementptr i32, ptr [[TMP352]], i64 12
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP378:%.*]] = load i32, ptr [[TMP377]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP378]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP379:%.*]] = getelementptr i32, ptr [[TMP352]], i64 13
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP380:%.*]] = load i32, ptr [[TMP379]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP380]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP381:%.*]] = getelementptr i32, ptr [[TMP352]], i64 14
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP382:%.*]] = load i32, ptr [[TMP381]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP382]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP383:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP383]], !continuation.registercount [[META24]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP318:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP319:%.*]] = getelementptr i32, ptr [[TMP318]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP320:%.*]] = getelementptr i32, ptr [[TMP319]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP321:%.*]] = load i32, ptr [[TMP320]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP321]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP322:%.*]] = getelementptr i32, ptr [[TMP319]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP323:%.*]] = load i32, ptr [[TMP322]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP323]], ptr getelementptr (i32, ptr @PAYLOAD, i64 1), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP324:%.*]] = getelementptr i32, ptr [[TMP319]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP325:%.*]] = load i32, ptr [[TMP324]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP325]], ptr getelementptr (i32, ptr @PAYLOAD, i64 2), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP326:%.*]] = getelementptr i32, ptr [[TMP319]], i64 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP327:%.*]] = load i32, ptr [[TMP326]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP327]], ptr getelementptr (i32, ptr @PAYLOAD, i64 3), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP328:%.*]] = getelementptr i32, ptr [[TMP319]], i64 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP329:%.*]] = load i32, ptr [[TMP328]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP329]], ptr getelementptr (i32, ptr @PAYLOAD, i64 4), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP330:%.*]] = getelementptr i32, ptr [[TMP319]], i64 5
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP331:%.*]] = load i32, ptr [[TMP330]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP331]], ptr getelementptr (i32, ptr @PAYLOAD, i64 5), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP332:%.*]] = getelementptr i32, ptr [[TMP319]], i64 6
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP333:%.*]] = load i32, ptr [[TMP332]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP333]], ptr getelementptr (i32, ptr @PAYLOAD, i64 6), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP334:%.*]] = getelementptr i32, ptr [[TMP319]], i64 7
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP335:%.*]] = load i32, ptr [[TMP334]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP335]], ptr getelementptr (i32, ptr @PAYLOAD, i64 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP336:%.*]] = getelementptr i32, ptr [[TMP319]], i64 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP337:%.*]] = load i32, ptr [[TMP336]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP337]], ptr getelementptr (i32, ptr @PAYLOAD, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP338:%.*]] = getelementptr i32, ptr [[TMP319]], i64 9
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP339:%.*]] = load i32, ptr [[TMP338]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP339]], ptr getelementptr (i32, ptr @PAYLOAD, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP340:%.*]] = getelementptr i32, ptr [[TMP319]], i64 10
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP341:%.*]] = load i32, ptr [[TMP340]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP341]], ptr getelementptr (i32, ptr @PAYLOAD, i64 10), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP342:%.*]] = getelementptr i32, ptr [[TMP319]], i64 11
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP343:%.*]] = load i32, ptr [[TMP342]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP343]], ptr getelementptr (i32, ptr @PAYLOAD, i64 11), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP344:%.*]] = getelementptr i32, ptr [[TMP319]], i64 12
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP345:%.*]] = load i32, ptr [[TMP344]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP345]], ptr getelementptr (i32, ptr @PAYLOAD, i64 12), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP346:%.*]] = getelementptr i32, ptr [[TMP319]], i64 13
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP347:%.*]] = load i32, ptr [[TMP346]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP347]], ptr getelementptr (i32, ptr @PAYLOAD, i64 13), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP348:%.*]] = getelementptr i32, ptr [[TMP319]], i64 14
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP349:%.*]] = load i32, ptr [[TMP348]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP349]], ptr getelementptr (i32, ptr @PAYLOAD, i64 14), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP350:%.*]] = getelementptr inbounds [[STRUCT_OUTERPAYLOAD]], ptr [[TMP3]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP351:%.*]] = getelementptr i32, ptr [[TMP350]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP352:%.*]] = getelementptr i32, ptr [[TMP351]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP353:%.*]] = load i32, ptr [[TMP352]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP353]], ptr getelementptr inbounds ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i32 15), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP354:%.*]] = getelementptr i32, ptr [[TMP351]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP355:%.*]] = load i32, ptr [[TMP354]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP355]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP356:%.*]] = getelementptr i32, ptr [[TMP351]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP357:%.*]] = load i32, ptr [[TMP356]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP357]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP358:%.*]] = getelementptr i32, ptr [[TMP351]], i64 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP359:%.*]] = load i32, ptr [[TMP358]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP359]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP360:%.*]] = getelementptr i32, ptr [[TMP351]], i64 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP361:%.*]] = load i32, ptr [[TMP360]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP361]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP362:%.*]] = getelementptr i32, ptr [[TMP351]], i64 5
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP363:%.*]] = load i32, ptr [[TMP362]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP363]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP364:%.*]] = getelementptr i32, ptr [[TMP351]], i64 6
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP365:%.*]] = load i32, ptr [[TMP364]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP365]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP366:%.*]] = getelementptr i32, ptr [[TMP351]], i64 7
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP367:%.*]] = load i32, ptr [[TMP366]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP367]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP368:%.*]] = getelementptr i32, ptr [[TMP351]], i64 8
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP369:%.*]] = load i32, ptr [[TMP368]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP369]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP370:%.*]] = getelementptr i32, ptr [[TMP351]], i64 9
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP371:%.*]] = load i32, ptr [[TMP370]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP371]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP372:%.*]] = getelementptr i32, ptr [[TMP351]], i64 10
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP373:%.*]] = load i32, ptr [[TMP372]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP373]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP374:%.*]] = getelementptr i32, ptr [[TMP351]], i64 11
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP375:%.*]] = load i32, ptr [[TMP374]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP375]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP376:%.*]] = getelementptr i32, ptr [[TMP351]], i64 12
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP377:%.*]] = load i32, ptr [[TMP376]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP377]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP378:%.*]] = getelementptr i32, ptr [[TMP351]], i64 13
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP379:%.*]] = load i32, ptr [[TMP378]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP379]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP380:%.*]] = getelementptr i32, ptr [[TMP351]], i64 14
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP381:%.*]] = load i32, ptr [[TMP380]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP381]], ptr getelementptr ([[STRUCT_OUTERPAYLOAD_LAYOUT_CALLSHADER]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP382:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP382]], !continuation.registercount [[META24]]
;
%1 = alloca %struct.OuterPayload, align 8
%2 = getelementptr inbounds %struct.OuterPayload, %struct.OuterPayload* %1, i32 0, i32 0, i32 0
diff --git a/shared/continuations/test/dx/payload.ll b/shared/continuations/test/dx/payload.ll
index 5f460e66bf..334310a35d 100644
--- a/shared/continuations/test/dx/payload.ll
+++ b/shared/continuations/test/dx/payload.ll
@@ -1,16 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --include-generated-funcs --version 3
-; RUN: opt --verify-each -passes='dxil-cont-lgc-rt-op-converter,lint,inline,lint,lower-raytracing-pipeline,lint,sroa,lint,lower-await,lint,coro-early,dxil-coro-split,coro-cleanup,lint,legacy-cleanup-continuations,lint,remove-types-metadata' -S %s 2> %t0.stderr | FileCheck -check-prefix=CLEANUP %s
+; RUN: grep -v SKIP_GLOBAL_ADDRSPACE %s | opt --verify-each -passes='dxil-cont-lgc-rt-op-converter,lint,inline,lint,lower-raytracing-pipeline,lint,sroa,lint,lower-await,lint,coro-early,dxil-coro-split,coro-cleanup,lint,legacy-cleanup-continuations,lint,remove-types-metadata' -S 2> %t0.stderr | FileCheck -check-prefix=CLEANUP %s
; RUN: count 0 < %t0.stderr
-; RUN: opt --verify-each -passes='dxil-cont-lgc-rt-op-converter,lint,inline,lint,lower-raytracing-pipeline,lint,sroa,lint,lower-await,lint,coro-early,dxil-coro-split,coro-cleanup,lint,legacy-cleanup-continuations,lint,register-buffer,lint,save-continuation-state,lint,dxil-cont-post-process,lint,remove-types-metadata' \
-; RUN: -S %s 2> %t1.stderr | FileCheck -check-prefix=POST-PROCESS %s
+; RUN: grep -v SKIP_GLOBAL_ADDRSPACE %s | opt --verify-each -passes='dxil-cont-lgc-rt-op-converter,lint,inline,lint,lower-raytracing-pipeline,lint,sroa,lint,lower-await,lint,coro-early,dxil-coro-split,coro-cleanup,lint,legacy-cleanup-continuations,lint,register-buffer,lint,save-continuation-state,lint,dxil-cont-post-process,lint,remove-types-metadata' \
+; RUN: -S 2> %t1.stderr | FileCheck -check-prefix=POST-PROCESS %s
; RUN: count 0 < %t1.stderr
+; RUN: opt --verify-each -passes='dxil-cont-lgc-rt-op-converter,lint,inline,lint,lower-raytracing-pipeline,lint,sroa,lint,lower-await,lint,coro-early,dxil-coro-split,coro-cleanup,lint,legacy-cleanup-continuations,lint,register-buffer,lint,save-continuation-state,lint,dxil-cont-post-process,lint,remove-types-metadata' \
+; RUN: -S %s 2> %t2.stderr | FileCheck -check-prefix=POST-PROCESS-GLOBAL %s
+; RUN: count 0 < %t2.stderr
target datalayout = "e-m:e-p:64:32-p20:32:32-p21:32:32-i1:32-i8:8-i16:32-i32:32-i64:32-f16:32-f32:32-f64:32-v16:32-v32:32-v48:32-v64:32-v80:32-v96:32-v112:32-v128:32-v144:32-v160:32-v176:32-v192:32-v208:32-v224:32-v240:32-v256:32-n8:16:32"
%dx.types.Handle = type { i8* }
-%struct.DispatchSystemData = type { i32 }
-%struct.TraversalData = type { %struct.SystemData }
-%struct.SystemData = type { %struct.DispatchSystemData }
+%struct.DispatchSystemData = type { <3 x i32> }
+%struct.TraversalData = type { %struct.SystemData, %struct.HitData, <3 x float>, <3 x float>, float, i64 }
+%struct.SystemData = type { %struct.DispatchSystemData, %struct.BuiltInTriangleIntersectionAttributes }
%struct.AnyHitTraversalData = type { %struct.TraversalData, %struct.HitData }
%struct.HitData = type { float, i32 }
%struct.BuiltInTriangleIntersectionAttributes = type { <2 x float> }
@@ -36,8 +39,11 @@ declare %struct.DispatchSystemData @_AmdAwaitShader(i64, %struct.DispatchSystemD
; Function Attrs: alwaysinline
declare %struct.AnyHitTraversalData @_AmdAwaitAnyHit(i64, %struct.AnyHitTraversalData, float, i32) #0
-; Function Attrs: alwaysinline
-declare !types !17 %struct.BuiltInTriangleIntersectionAttributes @_cont_GetTriangleHitAttributes(%struct.SystemData*) #0
+define %struct.BuiltInTriangleIntersectionAttributes @_cont_GetTriangleHitAttributes(%struct.SystemData* %data) #0 !types !17 {
+ %addr = getelementptr %struct.SystemData, %struct.SystemData* %data, i32 0, i32 1
+ %val = load %struct.BuiltInTriangleIntersectionAttributes, %struct.BuiltInTriangleIntersectionAttributes* %addr, align 4
+ ret %struct.BuiltInTriangleIntersectionAttributes %val
+}
; Function Attrs: alwaysinline
declare !types !19 void @_cont_SetTriangleHitAttributes(%struct.SystemData*, %struct.BuiltInTriangleIntersectionAttributes) #0
@@ -62,6 +68,8 @@ define i32 @_cont_GetLocalRootIndex(%struct.DispatchSystemData* %data) #0 !types
ret i32 5
}
+declare i64 @_cont_GetContinuationStackGlobalMemBase()
+
; Function Attrs: alwaysinline
define void @_cont_TraceRay(%struct.DispatchSystemData* %data, i64 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, float %6, float %7, float %8, float %9, float %10, float %11, float %12, float %13) #0 !types !29 {
%dis_data = load %struct.DispatchSystemData, %struct.DispatchSystemData* %data, align 4
@@ -136,6 +144,7 @@ attributes #3 = { nounwind }
!dx.valver = !{!1}
!dx.shaderModel = !{!2}
!dx.entryPoints = !{!3, !6, !13, !15}
+!continuation.stackAddrspace = !{!36} ; SKIP_GLOBAL_ADDRSPACE
!0 = !{!"clang version 3.7.0 (tags/RELEASE_370/final)"}
!1 = !{i32 1, i32 6}
@@ -173,27 +182,34 @@ attributes #3 = { nounwind }
!33 = !{i32 0, %struct.RayPayload poison}
!34 = !{i32 0, %struct.BuiltInTriangleIntersectionAttributes poison}
!35 = !{!"function", !"void", i32 poison, %dx.types.Handle poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, !33}
-; CLEANUP-LABEL: define i32 @_cont_GetLocalRootIndex(
+!36 = !{i32 22}
+; CLEANUP-LABEL: define %struct.BuiltInTriangleIntersectionAttributes @_cont_GetTriangleHitAttributes(
; CLEANUP-SAME: ptr [[DATA:%.*]]) #[[ATTR0:[0-9]+]] {
+; CLEANUP-NEXT: [[ADDR:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[DATA]], i32 0, i32 1
+; CLEANUP-NEXT: [[VAL:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]], ptr [[ADDR]], align 4
+; CLEANUP-NEXT: ret [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[VAL]]
+;
+;
+; CLEANUP-LABEL: define i32 @_cont_GetLocalRootIndex(
+; CLEANUP-SAME: ptr [[DATA:%.*]]) #[[ATTR0]] {
; CLEANUP-NEXT: ret i32 5
;
;
-; CLEANUP-LABEL: define void @main() !lgc.rt.shaderstage !9 !continuation.entry !20 !continuation.registercount !9 !continuation !21 !continuation.stacksize !22 !continuation.state !9 {
+; CLEANUP-LABEL: define void @main(
+; CLEANUP-SAME: [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage [[META9:![0-9]+]] !continuation.entry [[META20:![0-9]+]] !continuation.registercount [[META9]] !continuation [[META21:![0-9]+]] !continuation.stacksize [[META22:![0-9]+]] !continuation.state [[META9]] {
; CLEANUP-NEXT: AllocaSpillBB:
-; CLEANUP-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
-; CLEANUP-NEXT: [[TMP0:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA:%.*]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
; CLEANUP-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], 0
-; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; CLEANUP-NEXT: [[TMP1:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CLEANUP-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
; CLEANUP-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], 108
; CLEANUP-NEXT: store i32 [[TMP3]], ptr [[TMP1]], align 4
+; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; CLEANUP-NEXT: [[TMP4:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
; CLEANUP-NEXT: [[TMP5:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
; CLEANUP-NEXT: [[TMP6:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP4]])
; CLEANUP-NEXT: [[TMP7:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP6]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
; CLEANUP-NEXT: [[TMP8:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[TMP7]])
-; CLEANUP-NEXT: [[DIS_DATA_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, i32 [[DOTFCA_0_EXTRACT]], 0
+; CLEANUP-NEXT: [[DIS_DATA_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, <3 x i32> [[DOTFCA_0_EXTRACT]], 0
; CLEANUP-NEXT: [[SYS_DATA_I:%.*]] = insertvalue [[STRUCT_SYSTEMDATA:%.*]] undef, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I_FCA_0_INSERT]], 0
; CLEANUP-NEXT: [[TRAV_DATA_I:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA:%.*]] undef, [[STRUCT_SYSTEMDATA]] [[SYS_DATA_I]], 0
; CLEANUP-NEXT: [[TMP9:%.*]] = call ptr @continuation.getContinuationStackOffset()
@@ -253,14 +269,13 @@ attributes #3 = { nounwind }
; CLEANUP-NEXT: store i32 undef, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 56), align 4
; CLEANUP-NEXT: [[TMP12:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CLEANUP-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4
-; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 4, i32 [[TMP13]], i64 ptrtoint (ptr @main.resume.0 to i64), [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]]), !continuation.registercount !18, !continuation.returnedRegistercount !18
+; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 4, i32 [[TMP13]], i64 ptrtoint (ptr @main.resume.0 to i64), [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]]), !continuation.registercount [[META18:![0-9]+]], !continuation.returnedRegistercount !18
; CLEANUP-NEXT: unreachable
;
;
; CLEANUP-LABEL: define dso_local void @main.resume.0(
-; CLEANUP-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.shaderstage !9 !continuation.registercount !18 !continuation !21 {
+; CLEANUP-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.shaderstage [[META9]] !continuation.registercount [[META18]] !continuation [[META21]] {
; CLEANUP-NEXT: entryresume.0:
-; CLEANUP-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
; CLEANUP-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
; CLEANUP-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
; CLEANUP-NEXT: [[TMP4:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
@@ -312,7 +327,7 @@ attributes #3 = { nounwind }
; CLEANUP-NEXT: [[TMP50:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 55), align 4
; CLEANUP-NEXT: [[TMP51:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 56), align 4
; CLEANUP-NEXT: [[DOTFCA_0_EXTRACT1:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
-; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; CLEANUP-NEXT: [[TMP52:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CLEANUP-NEXT: [[TMP53:%.*]] = load i32, ptr [[TMP52]], align 4
; CLEANUP-NEXT: [[TMP54:%.*]] = add i32 [[TMP53]], -108
@@ -322,245 +337,284 @@ attributes #3 = { nounwind }
;
;
; CLEANUP-LABEL: define void @AnyHit(
-; CLEANUP-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_ANYHITTRAVERSALDATA:%.*]] [[TMP0:%.*]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] !lgc.rt.shaderstage !23 !continuation.registercount !18 !continuation !24 !continuation.state !9 {
+; CLEANUP-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_ANYHITTRAVERSALDATA:%.*]] [[TMP0:%.*]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] !lgc.rt.shaderstage [[META23:![0-9]+]] !continuation.registercount [[META18]] !continuation [[META24:![0-9]+]] !continuation.state [[META9]] {
; CLEANUP-NEXT: AllocaSpillBB:
; CLEANUP-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_ANYHITTRAVERSALDATA]], align 8
-; CLEANUP-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
-; CLEANUP-NEXT: [[TMP2:%.*]] = call [[STRUCT_ANYHITTRAVERSALDATA]] @continuations.getSystemData.s_struct.AnyHitTraversalDatas()
-; CLEANUP-NEXT: [[DOTFCA_0_0_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP2]], 0, 0, 0, 0
+; CLEANUP-NEXT: [[DOTFCA_0_0_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 0, 0, 0
; CLEANUP-NEXT: [[DOTFCA_0_0_0_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0, i32 0
-; CLEANUP-NEXT: store i32 [[DOTFCA_0_0_0_0_EXTRACT]], ptr [[DOTFCA_0_0_0_0_GEP]], align 4
-; CLEANUP-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP2]], 1, 0
+; CLEANUP-NEXT: store <3 x i32> [[DOTFCA_0_0_0_0_EXTRACT]], ptr [[DOTFCA_0_0_0_0_GEP]], align 4
+; CLEANUP-NEXT: [[DOTFCA_0_0_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 0, 1, 0
+; CLEANUP-NEXT: [[DOTFCA_0_0_1_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 1, i32 0
+; CLEANUP-NEXT: store <2 x float> [[DOTFCA_0_0_1_0_EXTRACT]], ptr [[DOTFCA_0_0_1_0_GEP]], align 4
+; CLEANUP-NEXT: [[DOTFCA_0_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 1, 0
+; CLEANUP-NEXT: [[DOTFCA_0_1_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 1, i32 0
+; CLEANUP-NEXT: store float [[DOTFCA_0_1_0_EXTRACT]], ptr [[DOTFCA_0_1_0_GEP]], align 4
+; CLEANUP-NEXT: [[DOTFCA_0_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 1, 1
+; CLEANUP-NEXT: [[DOTFCA_0_1_1_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 1, i32 1
+; CLEANUP-NEXT: store i32 [[DOTFCA_0_1_1_EXTRACT]], ptr [[DOTFCA_0_1_1_GEP]], align 4
+; CLEANUP-NEXT: [[DOTFCA_0_2_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 2
+; CLEANUP-NEXT: [[DOTFCA_0_2_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 2
+; CLEANUP-NEXT: store <3 x float> [[DOTFCA_0_2_EXTRACT]], ptr [[DOTFCA_0_2_GEP]], align 4
+; CLEANUP-NEXT: [[DOTFCA_0_3_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 3
+; CLEANUP-NEXT: [[DOTFCA_0_3_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 3
+; CLEANUP-NEXT: store <3 x float> [[DOTFCA_0_3_EXTRACT]], ptr [[DOTFCA_0_3_GEP]], align 4
+; CLEANUP-NEXT: [[DOTFCA_0_4_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 4
+; CLEANUP-NEXT: [[DOTFCA_0_4_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 4
+; CLEANUP-NEXT: store float [[DOTFCA_0_4_EXTRACT]], ptr [[DOTFCA_0_4_GEP]], align 4
+; CLEANUP-NEXT: [[DOTFCA_0_5_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 5
+; CLEANUP-NEXT: [[DOTFCA_0_5_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 5
+; CLEANUP-NEXT: store i64 [[DOTFCA_0_5_EXTRACT]], ptr [[DOTFCA_0_5_GEP]], align 4
+; CLEANUP-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 1, 0
; CLEANUP-NEXT: [[DOTFCA_1_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 0
; CLEANUP-NEXT: store float [[DOTFCA_1_0_EXTRACT]], ptr [[DOTFCA_1_0_GEP]], align 4
-; CLEANUP-NEXT: [[DOTFCA_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP2]], 1, 1
+; CLEANUP-NEXT: [[DOTFCA_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 1, 1
; CLEANUP-NEXT: [[DOTFCA_1_1_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 1
; CLEANUP-NEXT: store i32 [[DOTFCA_1_1_EXTRACT]], ptr [[DOTFCA_1_1_GEP]], align 4
-; CLEANUP-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; CLEANUP-NEXT: [[TMP4:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; CLEANUP-NEXT: [[TMP5:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; CLEANUP-NEXT: [[TMP6:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; CLEANUP-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 10), align 4
-; CLEANUP-NEXT: [[TMP8:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 11), align 4
-; CLEANUP-NEXT: [[TMP9:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 12), align 4
-; CLEANUP-NEXT: [[TMP10:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 13), align 4
-; CLEANUP-NEXT: [[TMP11:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 14), align 4
-; CLEANUP-NEXT: [[TMP12:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 15), align 4
-; CLEANUP-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
-; CLEANUP-NEXT: [[TMP14:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
-; CLEANUP-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
-; CLEANUP-NEXT: [[TMP16:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
-; CLEANUP-NEXT: [[TMP17:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
-; CLEANUP-NEXT: [[TMP18:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
-; CLEANUP-NEXT: [[TMP19:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
-; CLEANUP-NEXT: [[TMP20:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
-; CLEANUP-NEXT: [[TMP21:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
-; CLEANUP-NEXT: [[TMP22:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
-; CLEANUP-NEXT: [[TMP23:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
-; CLEANUP-NEXT: [[TMP24:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
-; CLEANUP-NEXT: [[TMP25:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
-; CLEANUP-NEXT: [[TMP26:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
-; CLEANUP-NEXT: [[TMP27:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 30), align 4
-; CLEANUP-NEXT: [[TMP28:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 31), align 4
-; CLEANUP-NEXT: [[TMP29:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 32), align 4
-; CLEANUP-NEXT: [[TMP30:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 33), align 4
-; CLEANUP-NEXT: [[TMP31:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 34), align 4
-; CLEANUP-NEXT: [[TMP32:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 35), align 4
-; CLEANUP-NEXT: [[TMP33:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 36), align 4
-; CLEANUP-NEXT: [[TMP34:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 37), align 4
-; CLEANUP-NEXT: [[TMP35:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 38), align 4
-; CLEANUP-NEXT: [[TMP36:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 39), align 4
-; CLEANUP-NEXT: [[TMP37:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 40), align 4
-; CLEANUP-NEXT: [[TMP38:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 41), align 4
-; CLEANUP-NEXT: [[TMP39:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 42), align 4
-; CLEANUP-NEXT: [[TMP40:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 43), align 4
-; CLEANUP-NEXT: [[TMP41:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 44), align 4
-; CLEANUP-NEXT: [[TMP42:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 45), align 4
-; CLEANUP-NEXT: [[TMP43:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 46), align 4
-; CLEANUP-NEXT: [[TMP44:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 47), align 4
-; CLEANUP-NEXT: [[TMP45:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 48), align 4
-; CLEANUP-NEXT: [[TMP46:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 49), align 4
-; CLEANUP-NEXT: [[TMP47:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 50), align 4
-; CLEANUP-NEXT: [[TMP48:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 51), align 4
-; CLEANUP-NEXT: [[TMP49:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 52), align 4
-; CLEANUP-NEXT: [[TMP50:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 53), align 4
-; CLEANUP-NEXT: [[TMP51:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 54), align 4
-; CLEANUP-NEXT: [[TMP52:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 55), align 4
-; CLEANUP-NEXT: [[TMP53:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 56), align 4
+; CLEANUP-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; CLEANUP-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; CLEANUP-NEXT: [[TMP4:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; CLEANUP-NEXT: [[TMP5:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; CLEANUP-NEXT: [[TMP6:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 10), align 4
+; CLEANUP-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 11), align 4
+; CLEANUP-NEXT: [[TMP8:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 12), align 4
+; CLEANUP-NEXT: [[TMP9:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 13), align 4
+; CLEANUP-NEXT: [[TMP10:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 14), align 4
+; CLEANUP-NEXT: [[TMP11:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 15), align 4
+; CLEANUP-NEXT: [[TMP12:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
+; CLEANUP-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
+; CLEANUP-NEXT: [[TMP14:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
+; CLEANUP-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
+; CLEANUP-NEXT: [[TMP16:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
+; CLEANUP-NEXT: [[TMP17:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
+; CLEANUP-NEXT: [[TMP18:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
+; CLEANUP-NEXT: [[TMP19:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
+; CLEANUP-NEXT: [[TMP20:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
+; CLEANUP-NEXT: [[TMP21:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
+; CLEANUP-NEXT: [[TMP22:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
+; CLEANUP-NEXT: [[TMP23:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
+; CLEANUP-NEXT: [[TMP24:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
+; CLEANUP-NEXT: [[TMP25:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
+; CLEANUP-NEXT: [[TMP26:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 30), align 4
+; CLEANUP-NEXT: [[TMP27:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 31), align 4
+; CLEANUP-NEXT: [[TMP28:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 32), align 4
+; CLEANUP-NEXT: [[TMP29:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 33), align 4
+; CLEANUP-NEXT: [[TMP30:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 34), align 4
+; CLEANUP-NEXT: [[TMP31:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 35), align 4
+; CLEANUP-NEXT: [[TMP32:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 36), align 4
+; CLEANUP-NEXT: [[TMP33:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 37), align 4
+; CLEANUP-NEXT: [[TMP34:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 38), align 4
+; CLEANUP-NEXT: [[TMP35:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 39), align 4
+; CLEANUP-NEXT: [[TMP36:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 40), align 4
+; CLEANUP-NEXT: [[TMP37:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 41), align 4
+; CLEANUP-NEXT: [[TMP38:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 42), align 4
+; CLEANUP-NEXT: [[TMP39:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 43), align 4
+; CLEANUP-NEXT: [[TMP40:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 44), align 4
+; CLEANUP-NEXT: [[TMP41:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 45), align 4
+; CLEANUP-NEXT: [[TMP42:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 46), align 4
+; CLEANUP-NEXT: [[TMP43:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 47), align 4
+; CLEANUP-NEXT: [[TMP44:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 48), align 4
+; CLEANUP-NEXT: [[TMP45:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 49), align 4
+; CLEANUP-NEXT: [[TMP46:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 50), align 4
+; CLEANUP-NEXT: [[TMP47:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 51), align 4
+; CLEANUP-NEXT: [[TMP48:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 52), align 4
+; CLEANUP-NEXT: [[TMP49:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 53), align 4
+; CLEANUP-NEXT: [[TMP50:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 54), align 4
+; CLEANUP-NEXT: [[TMP51:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 55), align 4
+; CLEANUP-NEXT: [[TMP52:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 56), align 4
; CLEANUP-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; CLEANUP-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; CLEANUP-NEXT: [[TMP55:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[TMP54]])
-; CLEANUP-NEXT: [[DOTFCA_0_EXTRACT4:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP55]], 0
-; CLEANUP-NEXT: [[DOTSROA_05_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT4]], i32 0
-; CLEANUP-NEXT: [[TMP56:%.*]] = bitcast float [[DOTSROA_05_0_VEC_EXTRACT]] to i32
-; CLEANUP-NEXT: [[DOTSROA_05_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT4]], i32 1
-; CLEANUP-NEXT: [[TMP57:%.*]] = bitcast float [[DOTSROA_05_4_VEC_EXTRACT]] to i32
+; CLEANUP-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; CLEANUP-NEXT: [[ADDR_I:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[TMP53]], i32 0, i32 1
+; CLEANUP-NEXT: [[VAL_I_FCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[ADDR_I]], i32 0, i32 0
+; CLEANUP-NEXT: [[VAL_I_FCA_0_LOAD:%.*]] = load <2 x float>, ptr [[VAL_I_FCA_0_GEP]], align 4
+; CLEANUP-NEXT: [[VAL_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] poison, <2 x float> [[VAL_I_FCA_0_LOAD]], 0
+; CLEANUP-NEXT: [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[VAL_I_FCA_0_INSERT]], 0
+; CLEANUP-NEXT: [[DOTSROA_011_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT]], i32 0
+; CLEANUP-NEXT: [[TMP54:%.*]] = bitcast float [[DOTSROA_011_0_VEC_EXTRACT]] to i32
+; CLEANUP-NEXT: [[DOTSROA_011_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT]], i32 1
+; CLEANUP-NEXT: [[TMP55:%.*]] = bitcast float [[DOTSROA_011_4_VEC_EXTRACT]] to i32
; CLEANUP-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP1]], 0
+; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; CLEANUP-NEXT: call void @_cont_AcceptHit(ptr [[SYSTEM_DATA_ALLOCA]])
; CLEANUP-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; CLEANUP-NEXT: store i32 [[TMP4]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; CLEANUP-NEXT: store i32 [[TMP5]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; CLEANUP-NEXT: store i32 [[TMP6]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; CLEANUP-NEXT: store i32 [[TMP7]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 10), align 4
-; CLEANUP-NEXT: store i32 [[TMP8]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 11), align 4
-; CLEANUP-NEXT: store i32 [[TMP9]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 12), align 4
-; CLEANUP-NEXT: store i32 [[TMP10]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 13), align 4
-; CLEANUP-NEXT: store i32 [[TMP11]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 14), align 4
-; CLEANUP-NEXT: store i32 [[TMP12]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 15), align 4
-; CLEANUP-NEXT: store i32 [[TMP13]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
-; CLEANUP-NEXT: store i32 [[TMP14]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
-; CLEANUP-NEXT: store i32 [[TMP15]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
-; CLEANUP-NEXT: store i32 [[TMP16]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
-; CLEANUP-NEXT: store i32 [[TMP17]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
-; CLEANUP-NEXT: store i32 [[TMP18]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
-; CLEANUP-NEXT: store i32 [[TMP19]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
-; CLEANUP-NEXT: store i32 [[TMP20]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
-; CLEANUP-NEXT: store i32 [[TMP21]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
-; CLEANUP-NEXT: store i32 [[TMP22]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
-; CLEANUP-NEXT: store i32 [[TMP23]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
-; CLEANUP-NEXT: store i32 [[TMP24]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
-; CLEANUP-NEXT: store i32 [[TMP25]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
-; CLEANUP-NEXT: store i32 [[TMP26]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
-; CLEANUP-NEXT: store i32 [[TMP27]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 30), align 4
-; CLEANUP-NEXT: store i32 [[TMP28]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 31), align 4
-; CLEANUP-NEXT: store i32 [[TMP29]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 32), align 4
-; CLEANUP-NEXT: store i32 [[TMP30]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 33), align 4
-; CLEANUP-NEXT: store i32 [[TMP31]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 34), align 4
-; CLEANUP-NEXT: store i32 [[TMP32]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 35), align 4
-; CLEANUP-NEXT: store i32 [[TMP33]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 36), align 4
-; CLEANUP-NEXT: store i32 [[TMP34]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 37), align 4
-; CLEANUP-NEXT: store i32 [[TMP35]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 38), align 4
-; CLEANUP-NEXT: store i32 [[TMP36]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 39), align 4
-; CLEANUP-NEXT: store i32 [[TMP37]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 40), align 4
-; CLEANUP-NEXT: store i32 [[TMP38]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 41), align 4
-; CLEANUP-NEXT: store i32 [[TMP39]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 42), align 4
-; CLEANUP-NEXT: store i32 [[TMP40]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 43), align 4
-; CLEANUP-NEXT: store i32 [[TMP41]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 44), align 4
-; CLEANUP-NEXT: store i32 [[TMP42]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 45), align 4
-; CLEANUP-NEXT: store i32 [[TMP43]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 46), align 4
-; CLEANUP-NEXT: store i32 [[TMP44]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 47), align 4
-; CLEANUP-NEXT: store i32 [[TMP45]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 48), align 4
-; CLEANUP-NEXT: store i32 [[TMP46]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 49), align 4
-; CLEANUP-NEXT: store i32 [[TMP47]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 50), align 4
-; CLEANUP-NEXT: store i32 [[TMP48]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 51), align 4
-; CLEANUP-NEXT: store i32 [[TMP49]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 52), align 4
-; CLEANUP-NEXT: store i32 [[TMP50]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 53), align 4
-; CLEANUP-NEXT: store i32 [[TMP51]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 54), align 4
-; CLEANUP-NEXT: store i32 [[TMP52]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 55), align 4
-; CLEANUP-NEXT: store i32 [[TMP53]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 56), align 4
+; CLEANUP-NEXT: store i32 [[TMP3]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; CLEANUP-NEXT: store i32 [[TMP4]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; CLEANUP-NEXT: store i32 [[TMP5]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; CLEANUP-NEXT: store i32 [[TMP6]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 10), align 4
+; CLEANUP-NEXT: store i32 [[TMP7]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 11), align 4
+; CLEANUP-NEXT: store i32 [[TMP8]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 12), align 4
+; CLEANUP-NEXT: store i32 [[TMP9]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 13), align 4
+; CLEANUP-NEXT: store i32 [[TMP10]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 14), align 4
+; CLEANUP-NEXT: store i32 [[TMP11]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 15), align 4
+; CLEANUP-NEXT: store i32 [[TMP12]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
+; CLEANUP-NEXT: store i32 [[TMP13]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
+; CLEANUP-NEXT: store i32 [[TMP14]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
+; CLEANUP-NEXT: store i32 [[TMP15]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
+; CLEANUP-NEXT: store i32 [[TMP16]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
+; CLEANUP-NEXT: store i32 [[TMP17]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
+; CLEANUP-NEXT: store i32 [[TMP18]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
+; CLEANUP-NEXT: store i32 [[TMP19]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
+; CLEANUP-NEXT: store i32 [[TMP20]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
+; CLEANUP-NEXT: store i32 [[TMP21]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
+; CLEANUP-NEXT: store i32 [[TMP22]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
+; CLEANUP-NEXT: store i32 [[TMP23]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
+; CLEANUP-NEXT: store i32 [[TMP24]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
+; CLEANUP-NEXT: store i32 [[TMP25]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
+; CLEANUP-NEXT: store i32 [[TMP26]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 30), align 4
+; CLEANUP-NEXT: store i32 [[TMP27]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 31), align 4
+; CLEANUP-NEXT: store i32 [[TMP28]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 32), align 4
+; CLEANUP-NEXT: store i32 [[TMP29]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 33), align 4
+; CLEANUP-NEXT: store i32 [[TMP30]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 34), align 4
+; CLEANUP-NEXT: store i32 [[TMP31]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 35), align 4
+; CLEANUP-NEXT: store i32 [[TMP32]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 36), align 4
+; CLEANUP-NEXT: store i32 [[TMP33]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 37), align 4
+; CLEANUP-NEXT: store i32 [[TMP34]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 38), align 4
+; CLEANUP-NEXT: store i32 [[TMP35]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 39), align 4
+; CLEANUP-NEXT: store i32 [[TMP36]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 40), align 4
+; CLEANUP-NEXT: store i32 [[TMP37]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 41), align 4
+; CLEANUP-NEXT: store i32 [[TMP38]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 42), align 4
+; CLEANUP-NEXT: store i32 [[TMP39]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 43), align 4
+; CLEANUP-NEXT: store i32 [[TMP40]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 44), align 4
+; CLEANUP-NEXT: store i32 [[TMP41]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 45), align 4
+; CLEANUP-NEXT: store i32 [[TMP42]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 46), align 4
+; CLEANUP-NEXT: store i32 [[TMP43]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 47), align 4
+; CLEANUP-NEXT: store i32 [[TMP44]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 48), align 4
+; CLEANUP-NEXT: store i32 [[TMP45]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 49), align 4
+; CLEANUP-NEXT: store i32 [[TMP46]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 50), align 4
+; CLEANUP-NEXT: store i32 [[TMP47]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 51), align 4
+; CLEANUP-NEXT: store i32 [[TMP48]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 52), align 4
+; CLEANUP-NEXT: store i32 [[TMP49]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 53), align 4
+; CLEANUP-NEXT: store i32 [[TMP50]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 54), align 4
+; CLEANUP-NEXT: store i32 [[TMP51]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 55), align 4
+; CLEANUP-NEXT: store i32 [[TMP52]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 56), align 4
; CLEANUP-NEXT: [[HITATTRSALLOCA_SROA_0_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT]], i32 0
-; CLEANUP-NEXT: [[TMP58:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_0_VEC_EXTRACT]] to i32
-; CLEANUP-NEXT: [[TMP59:%.*]] = bitcast i32 [[TMP58]] to float
-; CLEANUP-NEXT: [[DOTSROA_06_0_VEC_INSERT:%.*]] = insertelement <2 x float> undef, float [[TMP59]], i32 0
+; CLEANUP-NEXT: [[TMP56:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_0_VEC_EXTRACT]] to i32
+; CLEANUP-NEXT: [[TMP57:%.*]] = bitcast i32 [[TMP56]] to float
+; CLEANUP-NEXT: [[DOTSROA_012_0_VEC_INSERT:%.*]] = insertelement <2 x float> undef, float [[TMP57]], i32 0
; CLEANUP-NEXT: [[HITATTRSALLOCA_SROA_0_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT]], i32 1
-; CLEANUP-NEXT: [[TMP60:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_4_VEC_EXTRACT]] to i32
-; CLEANUP-NEXT: [[TMP61:%.*]] = bitcast i32 [[TMP60]] to float
-; CLEANUP-NEXT: [[DOTSROA_06_4_VEC_INSERT:%.*]] = insertelement <2 x float> [[DOTSROA_06_0_VEC_INSERT]], float [[TMP61]], i32 1
-; CLEANUP-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] poison, <2 x float> [[DOTSROA_06_4_VEC_INSERT]], 0
-; CLEANUP-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; CLEANUP-NEXT: call void @_cont_SetTriangleHitAttributes(ptr [[TMP62]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_INSERT]])
+; CLEANUP-NEXT: [[TMP58:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_4_VEC_EXTRACT]] to i32
+; CLEANUP-NEXT: [[TMP59:%.*]] = bitcast i32 [[TMP58]] to float
+; CLEANUP-NEXT: [[DOTSROA_012_4_VEC_INSERT:%.*]] = insertelement <2 x float> [[DOTSROA_012_0_VEC_INSERT]], float [[TMP59]], i32 1
+; CLEANUP-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] poison, <2 x float> [[DOTSROA_012_4_VEC_INSERT]], 0
+; CLEANUP-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; CLEANUP-NEXT: call void @_cont_SetTriangleHitAttributes(ptr [[TMP60]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_INSERT]])
; CLEANUP-NEXT: [[DOTFCA_0_0_0_0_GEP1:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0, i32 0
-; CLEANUP-NEXT: [[DOTFCA_0_0_0_0_LOAD:%.*]] = load i32, ptr [[DOTFCA_0_0_0_0_GEP1]], align 4
-; CLEANUP-NEXT: [[DOTFCA_0_0_0_0_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] poison, i32 [[DOTFCA_0_0_0_0_LOAD]], 0, 0, 0, 0
-; CLEANUP-NEXT: [[DOTFCA_1_0_GEP2:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 0
-; CLEANUP-NEXT: [[DOTFCA_1_0_LOAD:%.*]] = load float, ptr [[DOTFCA_1_0_GEP2]], align 4
-; CLEANUP-NEXT: [[DOTFCA_1_0_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_0_0_0_INSERT]], float [[DOTFCA_1_0_LOAD]], 1, 0
-; CLEANUP-NEXT: [[DOTFCA_1_1_GEP3:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 1
-; CLEANUP-NEXT: [[DOTFCA_1_1_LOAD:%.*]] = load i32, ptr [[DOTFCA_1_1_GEP3]], align 4
+; CLEANUP-NEXT: [[DOTFCA_0_0_0_0_LOAD:%.*]] = load <3 x i32>, ptr [[DOTFCA_0_0_0_0_GEP1]], align 4
+; CLEANUP-NEXT: [[DOTFCA_0_0_0_0_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] poison, <3 x i32> [[DOTFCA_0_0_0_0_LOAD]], 0, 0, 0, 0
+; CLEANUP-NEXT: [[DOTFCA_0_0_1_0_GEP2:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 1, i32 0
+; CLEANUP-NEXT: [[DOTFCA_0_0_1_0_LOAD:%.*]] = load <2 x float>, ptr [[DOTFCA_0_0_1_0_GEP2]], align 4
+; CLEANUP-NEXT: [[DOTFCA_0_0_1_0_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_0_0_0_INSERT]], <2 x float> [[DOTFCA_0_0_1_0_LOAD]], 0, 0, 1, 0
+; CLEANUP-NEXT: [[DOTFCA_0_1_0_GEP3:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 1, i32 0
+; CLEANUP-NEXT: [[DOTFCA_0_1_0_LOAD:%.*]] = load float, ptr [[DOTFCA_0_1_0_GEP3]], align 4
+; CLEANUP-NEXT: [[DOTFCA_0_1_0_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_0_1_0_INSERT]], float [[DOTFCA_0_1_0_LOAD]], 0, 1, 0
+; CLEANUP-NEXT: [[DOTFCA_0_1_1_GEP4:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 1, i32 1
+; CLEANUP-NEXT: [[DOTFCA_0_1_1_LOAD:%.*]] = load i32, ptr [[DOTFCA_0_1_1_GEP4]], align 4
+; CLEANUP-NEXT: [[DOTFCA_0_1_1_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_1_0_INSERT]], i32 [[DOTFCA_0_1_1_LOAD]], 0, 1, 1
+; CLEANUP-NEXT: [[DOTFCA_0_2_GEP5:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 2
+; CLEANUP-NEXT: [[DOTFCA_0_2_LOAD:%.*]] = load <3 x float>, ptr [[DOTFCA_0_2_GEP5]], align 4
+; CLEANUP-NEXT: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_1_1_INSERT]], <3 x float> [[DOTFCA_0_2_LOAD]], 0, 2
+; CLEANUP-NEXT: [[DOTFCA_0_3_GEP6:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 3
+; CLEANUP-NEXT: [[DOTFCA_0_3_LOAD:%.*]] = load <3 x float>, ptr [[DOTFCA_0_3_GEP6]], align 4
+; CLEANUP-NEXT: [[DOTFCA_0_3_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_2_INSERT]], <3 x float> [[DOTFCA_0_3_LOAD]], 0, 3
+; CLEANUP-NEXT: [[DOTFCA_0_4_GEP7:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 4
+; CLEANUP-NEXT: [[DOTFCA_0_4_LOAD:%.*]] = load float, ptr [[DOTFCA_0_4_GEP7]], align 4
+; CLEANUP-NEXT: [[DOTFCA_0_4_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_3_INSERT]], float [[DOTFCA_0_4_LOAD]], 0, 4
+; CLEANUP-NEXT: [[DOTFCA_0_5_GEP8:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 5
+; CLEANUP-NEXT: [[DOTFCA_0_5_LOAD:%.*]] = load i64, ptr [[DOTFCA_0_5_GEP8]], align 4
+; CLEANUP-NEXT: [[DOTFCA_0_5_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_4_INSERT]], i64 [[DOTFCA_0_5_LOAD]], 0, 5
+; CLEANUP-NEXT: [[DOTFCA_1_0_GEP9:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 0
+; CLEANUP-NEXT: [[DOTFCA_1_0_LOAD:%.*]] = load float, ptr [[DOTFCA_1_0_GEP9]], align 4
+; CLEANUP-NEXT: [[DOTFCA_1_0_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_5_INSERT]], float [[DOTFCA_1_0_LOAD]], 1, 0
+; CLEANUP-NEXT: [[DOTFCA_1_1_GEP10:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 1
+; CLEANUP-NEXT: [[DOTFCA_1_1_LOAD:%.*]] = load i32, ptr [[DOTFCA_1_1_GEP10]], align 4
; CLEANUP-NEXT: [[DOTFCA_1_1_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_1_0_INSERT]], i32 [[DOTFCA_1_1_LOAD]], 1, 1
-; CLEANUP-NEXT: [[TMP63:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANUP-NEXT: [[TMP64:%.*]] = load i32, ptr [[TMP63]], align 4
-; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP64]], [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_1_1_INSERT]]), !continuation.registercount !18
+; CLEANUP-NEXT: [[TMP61:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP62:%.*]] = load i32, ptr [[TMP61]], align 4
+; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP62]], [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_1_1_INSERT]]), !continuation.registercount [[META18]]
; CLEANUP-NEXT: unreachable
;
;
; CLEANUP-LABEL: define void @ClosestHit(
-; CLEANUP-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR3]] !lgc.rt.shaderstage !25 !continuation.registercount !18 !continuation !26 !continuation.stacksize !27 !continuation.state !28 {
+; CLEANUP-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR3]] !lgc.rt.shaderstage [[META25:![0-9]+]] !continuation.registercount [[META18]] !continuation [[META26:![0-9]+]] !continuation.stacksize [[META27:![0-9]+]] !continuation.state [[META28:![0-9]+]] {
; CLEANUP-NEXT: AllocaSpillBB:
-; CLEANUP-NEXT: [[CONT_STATE:%.*]] = alloca [4 x i32], align 4
-; CLEANUP-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANUP-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME]], ptr [[CONT_STATE]], i32 0, i32 1
-; CLEANUP-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
-; CLEANUP-NEXT: [[TMP1:%.*]] = call [[STRUCT_SYSTEMDATA]] @continuations.getSystemData.s_struct.SystemDatas()
-; CLEANUP-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP1]], 0, 0
-; CLEANUP-NEXT: [[DOTFCA_0_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; CLEANUP-NEXT: store i32 [[DOTFCA_0_0_EXTRACT]], ptr [[DOTFCA_0_0_GEP]], align 4
-; CLEANUP-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; CLEANUP-NEXT: [[TMP3:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANUP-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-; CLEANUP-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], 108
-; CLEANUP-NEXT: store i32 [[TMP5]], ptr [[TMP3]], align 4
-; CLEANUP-NEXT: [[TMP6:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; CLEANUP-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; CLEANUP-NEXT: [[TMP8:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; CLEANUP-NEXT: [[TMP9:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 10), align 4
-; CLEANUP-NEXT: [[TMP10:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 11), align 4
-; CLEANUP-NEXT: [[TMP11:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 12), align 4
-; CLEANUP-NEXT: [[TMP12:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 13), align 4
-; CLEANUP-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 14), align 4
-; CLEANUP-NEXT: [[TMP14:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 15), align 4
-; CLEANUP-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
-; CLEANUP-NEXT: [[TMP16:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
-; CLEANUP-NEXT: [[TMP17:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
-; CLEANUP-NEXT: [[TMP18:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
-; CLEANUP-NEXT: [[TMP19:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
-; CLEANUP-NEXT: [[TMP20:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
-; CLEANUP-NEXT: [[TMP21:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
-; CLEANUP-NEXT: [[TMP22:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
-; CLEANUP-NEXT: [[TMP23:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
-; CLEANUP-NEXT: [[TMP24:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
-; CLEANUP-NEXT: [[TMP25:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
-; CLEANUP-NEXT: [[TMP26:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
-; CLEANUP-NEXT: [[TMP27:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
-; CLEANUP-NEXT: [[TMP28:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
-; CLEANUP-NEXT: [[TMP29:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 30), align 4
-; CLEANUP-NEXT: [[TMP30:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 31), align 4
-; CLEANUP-NEXT: [[TMP31:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 32), align 4
-; CLEANUP-NEXT: [[TMP32:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 33), align 4
-; CLEANUP-NEXT: [[TMP33:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 34), align 4
-; CLEANUP-NEXT: [[TMP34:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 35), align 4
-; CLEANUP-NEXT: [[TMP35:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 36), align 4
-; CLEANUP-NEXT: [[TMP36:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 37), align 4
-; CLEANUP-NEXT: [[TMP37:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 38), align 4
-; CLEANUP-NEXT: [[TMP38:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 39), align 4
-; CLEANUP-NEXT: [[TMP39:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 40), align 4
-; CLEANUP-NEXT: [[TMP40:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 41), align 4
-; CLEANUP-NEXT: [[TMP41:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 42), align 4
-; CLEANUP-NEXT: [[TMP42:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 43), align 4
-; CLEANUP-NEXT: [[TMP43:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 44), align 4
-; CLEANUP-NEXT: [[TMP44:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 45), align 4
-; CLEANUP-NEXT: [[TMP45:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 46), align 4
-; CLEANUP-NEXT: [[TMP46:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 47), align 4
-; CLEANUP-NEXT: [[TMP47:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 48), align 4
-; CLEANUP-NEXT: [[TMP48:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 49), align 4
-; CLEANUP-NEXT: [[TMP49:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 50), align 4
-; CLEANUP-NEXT: [[TMP50:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 51), align 4
-; CLEANUP-NEXT: [[TMP51:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 52), align 4
-; CLEANUP-NEXT: [[TMP52:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 53), align 4
-; CLEANUP-NEXT: [[TMP53:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 54), align 4
-; CLEANUP-NEXT: [[TMP54:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 55), align 4
-; CLEANUP-NEXT: [[TMP55:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 56), align 4
+; CLEANUP-NEXT: [[TMP1:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
+; CLEANUP-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(21)
+; CLEANUP-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP3]], i64 108
+; CLEANUP-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME:%.*]], ptr addrspace(21) [[TMP4]], i32 0, i32 0
+; CLEANUP-NEXT: store i64 [[RETURNADDR]], ptr addrspace(21) [[RETURNADDR_SPILL_ADDR]], align 4
+; CLEANUP-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP0]], 0, 0
+; CLEANUP-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP0]], 1, 0
+; CLEANUP-NEXT: [[TMP5:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
+; CLEANUP-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], 108
+; CLEANUP-NEXT: store i32 [[TMP7]], ptr [[TMP5]], align 4
+; CLEANUP-NEXT: [[TMP8:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; CLEANUP-NEXT: [[TMP9:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; CLEANUP-NEXT: [[TMP10:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; CLEANUP-NEXT: [[TMP11:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 10), align 4
+; CLEANUP-NEXT: [[TMP12:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 11), align 4
+; CLEANUP-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 12), align 4
+; CLEANUP-NEXT: [[TMP14:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 13), align 4
+; CLEANUP-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 14), align 4
+; CLEANUP-NEXT: [[TMP16:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 15), align 4
+; CLEANUP-NEXT: [[TMP17:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
+; CLEANUP-NEXT: [[TMP18:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
+; CLEANUP-NEXT: [[TMP19:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
+; CLEANUP-NEXT: [[TMP20:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
+; CLEANUP-NEXT: [[TMP21:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
+; CLEANUP-NEXT: [[TMP22:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
+; CLEANUP-NEXT: [[TMP23:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
+; CLEANUP-NEXT: [[TMP24:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
+; CLEANUP-NEXT: [[TMP25:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
+; CLEANUP-NEXT: [[TMP26:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
+; CLEANUP-NEXT: [[TMP27:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
+; CLEANUP-NEXT: [[TMP28:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
+; CLEANUP-NEXT: [[TMP29:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
+; CLEANUP-NEXT: [[TMP30:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
+; CLEANUP-NEXT: [[TMP31:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 30), align 4
+; CLEANUP-NEXT: [[TMP32:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 31), align 4
+; CLEANUP-NEXT: [[TMP33:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 32), align 4
+; CLEANUP-NEXT: [[TMP34:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 33), align 4
+; CLEANUP-NEXT: [[TMP35:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 34), align 4
+; CLEANUP-NEXT: [[TMP36:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 35), align 4
+; CLEANUP-NEXT: [[TMP37:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 36), align 4
+; CLEANUP-NEXT: [[TMP38:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 37), align 4
+; CLEANUP-NEXT: [[TMP39:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 38), align 4
+; CLEANUP-NEXT: [[TMP40:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 39), align 4
+; CLEANUP-NEXT: [[TMP41:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 40), align 4
+; CLEANUP-NEXT: [[TMP42:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 41), align 4
+; CLEANUP-NEXT: [[TMP43:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 42), align 4
+; CLEANUP-NEXT: [[TMP44:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 43), align 4
+; CLEANUP-NEXT: [[TMP45:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 44), align 4
+; CLEANUP-NEXT: [[TMP46:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 45), align 4
+; CLEANUP-NEXT: [[TMP47:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 46), align 4
+; CLEANUP-NEXT: [[TMP48:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 47), align 4
+; CLEANUP-NEXT: [[TMP49:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 48), align 4
+; CLEANUP-NEXT: [[TMP50:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 49), align 4
+; CLEANUP-NEXT: [[TMP51:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 50), align 4
+; CLEANUP-NEXT: [[TMP52:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 51), align 4
+; CLEANUP-NEXT: [[TMP53:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 52), align 4
+; CLEANUP-NEXT: [[TMP54:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 53), align 4
+; CLEANUP-NEXT: [[TMP55:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 54), align 4
+; CLEANUP-NEXT: [[TMP56:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 55), align 4
+; CLEANUP-NEXT: [[TMP57:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 56), align 4
; CLEANUP-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; CLEANUP-NEXT: [[TMP56:%.*]] = load i32, ptr @PAYLOAD, align 4
-; CLEANUP-NEXT: [[DOTSPILL_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME]], ptr [[CONT_STATE]], i32 0, i32 2
-; CLEANUP-NEXT: store i32 [[TMP56]], ptr [[DOTSPILL_ADDR]], align 4
-; CLEANUP-NEXT: [[TMP57:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
-; CLEANUP-NEXT: [[DOTFCA_0_EXTRACT52:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP57]], 0
-; CLEANUP-NEXT: [[DOTSROA_054_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT52]], i32 0
-; CLEANUP-NEXT: [[TMP58:%.*]] = bitcast float [[DOTSROA_054_0_VEC_EXTRACT]] to i32
-; CLEANUP-NEXT: [[DOTSROA_054_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT52]], i32 1
-; CLEANUP-NEXT: [[TMP59:%.*]] = bitcast float [[DOTSROA_054_4_VEC_EXTRACT]] to i32
-; CLEANUP-NEXT: [[TMP60:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
-; CLEANUP-NEXT: [[TMP61:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
-; CLEANUP-NEXT: [[TMP62:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP60]])
-; CLEANUP-NEXT: [[TMP63:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP62]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
-; CLEANUP-NEXT: [[TMP64:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[TMP63]])
-; CLEANUP-NEXT: [[TMP65:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; CLEANUP-NEXT: [[DIS_DATA_I_FCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP65]], i32 0, i32 0
-; CLEANUP-NEXT: [[DIS_DATA_I_FCA_0_LOAD:%.*]] = load i32, ptr [[DIS_DATA_I_FCA_0_GEP]], align 4
-; CLEANUP-NEXT: [[DIS_DATA_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, i32 [[DIS_DATA_I_FCA_0_LOAD]], 0
+; CLEANUP-NEXT: [[TMP58:%.*]] = load i32, ptr @PAYLOAD, align 4
+; CLEANUP-NEXT: [[DOTSPILL_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME]], ptr addrspace(21) [[TMP4]], i32 0, i32 1
+; CLEANUP-NEXT: store i32 [[TMP58]], ptr addrspace(21) [[DOTSPILL_ADDR]], align 4
+; CLEANUP-NEXT: [[VAL_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] poison, <2 x float> [[DOTFCA_1_0_EXTRACT]], 0
+; CLEANUP-NEXT: [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[VAL_I_FCA_0_INSERT]], 0
+; CLEANUP-NEXT: [[DOTSROA_053_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT]], i32 0
+; CLEANUP-NEXT: [[TMP59:%.*]] = bitcast float [[DOTSROA_053_0_VEC_EXTRACT]] to i32
+; CLEANUP-NEXT: [[DOTSROA_053_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT]], i32 1
+; CLEANUP-NEXT: [[TMP60:%.*]] = bitcast float [[DOTSROA_053_4_VEC_EXTRACT]] to i32
+; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; CLEANUP-NEXT: [[TMP61:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
+; CLEANUP-NEXT: [[TMP62:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
+; CLEANUP-NEXT: [[TMP63:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP61]])
+; CLEANUP-NEXT: [[TMP64:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP63]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
+; CLEANUP-NEXT: [[TMP65:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[TMP64]])
+; CLEANUP-NEXT: [[DIS_DATA_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA:%.*]] poison, <3 x i32> [[DOTFCA_0_0_EXTRACT]], 0
; CLEANUP-NEXT: [[SYS_DATA_I:%.*]] = insertvalue [[STRUCT_SYSTEMDATA]] undef, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I_FCA_0_INSERT]], 0
; CLEANUP-NEXT: [[TRAV_DATA_I:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA:%.*]] undef, [[STRUCT_SYSTEMDATA]] [[SYS_DATA_I]], 0
; CLEANUP-NEXT: [[TMP66:%.*]] = call ptr @continuation.getContinuationStackOffset()
@@ -568,268 +622,231 @@ attributes #3 = { nounwind }
; CLEANUP-NEXT: [[TMP68:%.*]] = add i32 [[TMP67]], -108
; CLEANUP-NEXT: store i32 [[TMP68]], ptr @PAYLOAD, align 4
; CLEANUP-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; CLEANUP-NEXT: store i32 [[TMP6]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; CLEANUP-NEXT: store i32 [[TMP7]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; CLEANUP-NEXT: store i32 [[TMP8]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; CLEANUP-NEXT: store i32 [[TMP9]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 10), align 4
-; CLEANUP-NEXT: store i32 [[TMP10]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 11), align 4
-; CLEANUP-NEXT: store i32 [[TMP11]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 12), align 4
-; CLEANUP-NEXT: store i32 [[TMP12]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 13), align 4
-; CLEANUP-NEXT: store i32 [[TMP13]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 14), align 4
-; CLEANUP-NEXT: store i32 [[TMP14]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 15), align 4
-; CLEANUP-NEXT: store i32 [[TMP15]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
-; CLEANUP-NEXT: store i32 [[TMP16]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
-; CLEANUP-NEXT: store i32 [[TMP17]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
-; CLEANUP-NEXT: store i32 [[TMP18]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
-; CLEANUP-NEXT: store i32 [[TMP19]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
-; CLEANUP-NEXT: store i32 [[TMP20]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
-; CLEANUP-NEXT: store i32 [[TMP21]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
-; CLEANUP-NEXT: store i32 [[TMP22]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
-; CLEANUP-NEXT: store i32 [[TMP23]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
-; CLEANUP-NEXT: store i32 [[TMP24]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
-; CLEANUP-NEXT: store i32 [[TMP25]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
-; CLEANUP-NEXT: store i32 [[TMP26]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
-; CLEANUP-NEXT: store i32 [[TMP27]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
-; CLEANUP-NEXT: store i32 [[TMP28]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
-; CLEANUP-NEXT: store i32 [[TMP29]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 30), align 4
-; CLEANUP-NEXT: store i32 [[TMP30]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 31), align 4
-; CLEANUP-NEXT: store i32 [[TMP31]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 32), align 4
-; CLEANUP-NEXT: store i32 [[TMP32]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 33), align 4
-; CLEANUP-NEXT: store i32 [[TMP33]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 34), align 4
-; CLEANUP-NEXT: store i32 [[TMP34]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 35), align 4
-; CLEANUP-NEXT: store i32 [[TMP35]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 36), align 4
-; CLEANUP-NEXT: store i32 [[TMP36]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 37), align 4
-; CLEANUP-NEXT: store i32 [[TMP37]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 38), align 4
-; CLEANUP-NEXT: store i32 [[TMP38]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 39), align 4
-; CLEANUP-NEXT: store i32 [[TMP39]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 40), align 4
-; CLEANUP-NEXT: store i32 [[TMP40]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 41), align 4
-; CLEANUP-NEXT: store i32 [[TMP41]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 42), align 4
-; CLEANUP-NEXT: store i32 [[TMP42]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 43), align 4
-; CLEANUP-NEXT: store i32 [[TMP43]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 44), align 4
-; CLEANUP-NEXT: store i32 [[TMP44]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 45), align 4
-; CLEANUP-NEXT: store i32 [[TMP45]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 46), align 4
-; CLEANUP-NEXT: store i32 [[TMP46]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 47), align 4
-; CLEANUP-NEXT: store i32 [[TMP47]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 48), align 4
-; CLEANUP-NEXT: store i32 [[TMP48]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 49), align 4
-; CLEANUP-NEXT: store i32 [[TMP49]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 50), align 4
-; CLEANUP-NEXT: store i32 [[TMP50]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 51), align 4
-; CLEANUP-NEXT: store i32 [[TMP51]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 52), align 4
-; CLEANUP-NEXT: store i32 [[TMP52]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 53), align 4
-; CLEANUP-NEXT: store i32 [[TMP53]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 54), align 4
-; CLEANUP-NEXT: store i32 [[TMP54]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 55), align 4
-; CLEANUP-NEXT: store i32 [[TMP55]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 56), align 4
+; CLEANUP-NEXT: store i32 [[TMP8]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; CLEANUP-NEXT: store i32 [[TMP9]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; CLEANUP-NEXT: store i32 [[TMP10]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; CLEANUP-NEXT: store i32 [[TMP11]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 10), align 4
+; CLEANUP-NEXT: store i32 [[TMP12]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 11), align 4
+; CLEANUP-NEXT: store i32 [[TMP13]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 12), align 4
+; CLEANUP-NEXT: store i32 [[TMP14]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 13), align 4
+; CLEANUP-NEXT: store i32 [[TMP15]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 14), align 4
+; CLEANUP-NEXT: store i32 [[TMP16]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 15), align 4
+; CLEANUP-NEXT: store i32 [[TMP17]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
+; CLEANUP-NEXT: store i32 [[TMP18]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
+; CLEANUP-NEXT: store i32 [[TMP19]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
+; CLEANUP-NEXT: store i32 [[TMP20]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
+; CLEANUP-NEXT: store i32 [[TMP21]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
+; CLEANUP-NEXT: store i32 [[TMP22]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
+; CLEANUP-NEXT: store i32 [[TMP23]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
+; CLEANUP-NEXT: store i32 [[TMP24]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
+; CLEANUP-NEXT: store i32 [[TMP25]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
+; CLEANUP-NEXT: store i32 [[TMP26]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
+; CLEANUP-NEXT: store i32 [[TMP27]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
+; CLEANUP-NEXT: store i32 [[TMP28]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
+; CLEANUP-NEXT: store i32 [[TMP29]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
+; CLEANUP-NEXT: store i32 [[TMP30]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
+; CLEANUP-NEXT: store i32 [[TMP31]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 30), align 4
+; CLEANUP-NEXT: store i32 [[TMP32]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 31), align 4
+; CLEANUP-NEXT: store i32 [[TMP33]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 32), align 4
+; CLEANUP-NEXT: store i32 [[TMP34]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 33), align 4
+; CLEANUP-NEXT: store i32 [[TMP35]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 34), align 4
+; CLEANUP-NEXT: store i32 [[TMP36]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 35), align 4
+; CLEANUP-NEXT: store i32 [[TMP37]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 36), align 4
+; CLEANUP-NEXT: store i32 [[TMP38]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 37), align 4
+; CLEANUP-NEXT: store i32 [[TMP39]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 38), align 4
+; CLEANUP-NEXT: store i32 [[TMP40]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 39), align 4
+; CLEANUP-NEXT: store i32 [[TMP41]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 40), align 4
+; CLEANUP-NEXT: store i32 [[TMP42]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 41), align 4
+; CLEANUP-NEXT: store i32 [[TMP43]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 42), align 4
+; CLEANUP-NEXT: store i32 [[TMP44]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 43), align 4
+; CLEANUP-NEXT: store i32 [[TMP45]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 44), align 4
+; CLEANUP-NEXT: store i32 [[TMP46]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 45), align 4
+; CLEANUP-NEXT: store i32 [[TMP47]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 46), align 4
+; CLEANUP-NEXT: store i32 [[TMP48]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 47), align 4
+; CLEANUP-NEXT: store i32 [[TMP49]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 48), align 4
+; CLEANUP-NEXT: store i32 [[TMP50]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 49), align 4
+; CLEANUP-NEXT: store i32 [[TMP51]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 50), align 4
+; CLEANUP-NEXT: store i32 [[TMP52]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 51), align 4
+; CLEANUP-NEXT: store i32 [[TMP53]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 52), align 4
+; CLEANUP-NEXT: store i32 [[TMP54]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 53), align 4
+; CLEANUP-NEXT: store i32 [[TMP55]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 54), align 4
+; CLEANUP-NEXT: store i32 [[TMP56]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 55), align 4
+; CLEANUP-NEXT: store i32 [[TMP57]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 56), align 4
; CLEANUP-NEXT: [[TMP69:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CLEANUP-NEXT: [[TMP70:%.*]] = load i32, ptr [[TMP69]], align 4
-; CLEANUP-NEXT: [[TMP71:%.*]] = add i32 [[TMP70]], 16
+; CLEANUP-NEXT: [[TMP71:%.*]] = add i32 [[TMP70]], 12
; CLEANUP-NEXT: store i32 [[TMP71]], ptr [[TMP69]], align 4
-; CLEANUP-NEXT: [[TMP72:%.*]] = inttoptr i32 [[TMP70]] to ptr addrspace(21)
-; CLEANUP-NEXT: [[TMP73:%.*]] = getelementptr inbounds [4 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANUP-NEXT: [[TMP74:%.*]] = getelementptr inbounds [4 x i32], ptr addrspace(21) [[TMP72]], i32 0, i32 0
-; CLEANUP-NEXT: [[TMP75:%.*]] = load i32, ptr [[TMP73]], align 4
-; CLEANUP-NEXT: store i32 [[TMP75]], ptr addrspace(21) [[TMP74]], align 4
-; CLEANUP-NEXT: [[TMP76:%.*]] = getelementptr inbounds [4 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CLEANUP-NEXT: [[TMP77:%.*]] = getelementptr inbounds [4 x i32], ptr addrspace(21) [[TMP72]], i32 0, i32 1
-; CLEANUP-NEXT: [[TMP78:%.*]] = load i32, ptr [[TMP76]], align 4
-; CLEANUP-NEXT: store i32 [[TMP78]], ptr addrspace(21) [[TMP77]], align 4
-; CLEANUP-NEXT: [[TMP79:%.*]] = getelementptr inbounds [4 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; CLEANUP-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i32], ptr addrspace(21) [[TMP72]], i32 0, i32 2
-; CLEANUP-NEXT: [[TMP81:%.*]] = load i32, ptr [[TMP79]], align 4
-; CLEANUP-NEXT: store i32 [[TMP81]], ptr addrspace(21) [[TMP80]], align 4
-; CLEANUP-NEXT: [[TMP82:%.*]] = getelementptr inbounds [4 x i32], ptr [[CONT_STATE]], i32 0, i32 3
-; CLEANUP-NEXT: [[TMP83:%.*]] = getelementptr inbounds [4 x i32], ptr addrspace(21) [[TMP72]], i32 0, i32 3
-; CLEANUP-NEXT: [[TMP84:%.*]] = load i32, ptr [[TMP82]], align 4
-; CLEANUP-NEXT: store i32 [[TMP84]], ptr addrspace(21) [[TMP83]], align 4
-; CLEANUP-NEXT: [[TMP85:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANUP-NEXT: [[TMP86:%.*]] = load i32, ptr [[TMP85]], align 4
-; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 4, i32 [[TMP86]], i64 ptrtoint (ptr @ClosestHit.resume.0 to i64), [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]]), !continuation.registercount !18, !continuation.returnedRegistercount !18
+; CLEANUP-NEXT: [[TMP72:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP73:%.*]] = load i32, ptr [[TMP72]], align 4
+; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 4, i32 [[TMP73]], i64 ptrtoint (ptr @ClosestHit.resume.0 to i64), [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]]), !continuation.registercount [[META18]], !continuation.returnedRegistercount !18
; CLEANUP-NEXT: unreachable
;
;
; CLEANUP-LABEL: define dso_local void @ClosestHit.resume.0(
-; CLEANUP-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.shaderstage !25 !continuation.registercount !18 !continuation !26 {
+; CLEANUP-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.shaderstage [[META25]] !continuation.registercount [[META18]] !continuation [[META26]] {
; CLEANUP-NEXT: entryresume.0:
-; CLEANUP-NEXT: [[CONT_STATE:%.*]] = alloca [4 x i32], align 4
; CLEANUP-NEXT: [[TMP2:%.*]] = call ptr @continuation.getContinuationStackOffset()
; CLEANUP-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-; CLEANUP-NEXT: [[TMP4:%.*]] = inttoptr i32 [[TMP3]] to ptr addrspace(21)
-; CLEANUP-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP4]], i64 -16
-; CLEANUP-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i32], ptr addrspace(21) [[TMP5]], i32 0, i32 0
-; CLEANUP-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANUP-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(21) [[TMP6]], align 4
-; CLEANUP-NEXT: store i32 [[TMP8]], ptr [[TMP7]], align 4
-; CLEANUP-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i32], ptr addrspace(21) [[TMP5]], i32 0, i32 1
-; CLEANUP-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; CLEANUP-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(21) [[TMP9]], align 4
-; CLEANUP-NEXT: store i32 [[TMP11]], ptr [[TMP10]], align 4
-; CLEANUP-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i32], ptr addrspace(21) [[TMP5]], i32 0, i32 2
-; CLEANUP-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; CLEANUP-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(21) [[TMP12]], align 4
-; CLEANUP-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4
-; CLEANUP-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i32], ptr addrspace(21) [[TMP5]], i32 0, i32 3
-; CLEANUP-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i32], ptr [[CONT_STATE]], i32 0, i32 3
-; CLEANUP-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(21) [[TMP15]], align 4
-; CLEANUP-NEXT: store i32 [[TMP17]], ptr [[TMP16]], align 4
-; CLEANUP-NEXT: [[TMP18:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANUP-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
-; CLEANUP-NEXT: [[TMP20:%.*]] = add i32 [[TMP19]], -16
-; CLEANUP-NEXT: store i32 [[TMP20]], ptr [[TMP18]], align 4
-; CLEANUP-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; CLEANUP-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA:%.*]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; CLEANUP-NEXT: [[TMP22:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; CLEANUP-NEXT: [[TMP23:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; CLEANUP-NEXT: [[TMP24:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; CLEANUP-NEXT: [[TMP25:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 10), align 4
-; CLEANUP-NEXT: [[TMP26:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 11), align 4
-; CLEANUP-NEXT: [[TMP27:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 12), align 4
-; CLEANUP-NEXT: [[TMP28:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 13), align 4
-; CLEANUP-NEXT: [[TMP29:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 14), align 4
-; CLEANUP-NEXT: [[TMP30:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 15), align 4
-; CLEANUP-NEXT: [[TMP31:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
-; CLEANUP-NEXT: [[TMP32:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
-; CLEANUP-NEXT: [[TMP33:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
-; CLEANUP-NEXT: [[TMP34:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
-; CLEANUP-NEXT: [[TMP35:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
-; CLEANUP-NEXT: [[TMP36:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
-; CLEANUP-NEXT: [[TMP37:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
-; CLEANUP-NEXT: [[TMP38:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
-; CLEANUP-NEXT: [[TMP39:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
-; CLEANUP-NEXT: [[TMP40:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
-; CLEANUP-NEXT: [[TMP41:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
-; CLEANUP-NEXT: [[TMP42:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
-; CLEANUP-NEXT: [[TMP43:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
-; CLEANUP-NEXT: [[TMP44:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
-; CLEANUP-NEXT: [[TMP45:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 30), align 4
-; CLEANUP-NEXT: [[TMP46:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 31), align 4
-; CLEANUP-NEXT: [[TMP47:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 32), align 4
-; CLEANUP-NEXT: [[TMP48:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 33), align 4
-; CLEANUP-NEXT: [[TMP49:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 34), align 4
-; CLEANUP-NEXT: [[TMP50:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 35), align 4
-; CLEANUP-NEXT: [[TMP51:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 36), align 4
-; CLEANUP-NEXT: [[TMP52:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 37), align 4
-; CLEANUP-NEXT: [[TMP53:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 38), align 4
-; CLEANUP-NEXT: [[TMP54:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 39), align 4
-; CLEANUP-NEXT: [[TMP55:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 40), align 4
-; CLEANUP-NEXT: [[TMP56:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 41), align 4
-; CLEANUP-NEXT: [[TMP57:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 42), align 4
-; CLEANUP-NEXT: [[TMP58:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 43), align 4
-; CLEANUP-NEXT: [[TMP59:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 44), align 4
-; CLEANUP-NEXT: [[TMP60:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 45), align 4
-; CLEANUP-NEXT: [[TMP61:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 46), align 4
-; CLEANUP-NEXT: [[TMP62:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 47), align 4
-; CLEANUP-NEXT: [[TMP63:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 48), align 4
-; CLEANUP-NEXT: [[TMP64:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 49), align 4
-; CLEANUP-NEXT: [[TMP65:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 50), align 4
-; CLEANUP-NEXT: [[TMP66:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 51), align 4
-; CLEANUP-NEXT: [[TMP67:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 52), align 4
-; CLEANUP-NEXT: [[TMP68:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 53), align 4
-; CLEANUP-NEXT: [[TMP69:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 54), align 4
-; CLEANUP-NEXT: [[TMP70:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 55), align 4
-; CLEANUP-NEXT: [[TMP71:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 56), align 4
+; CLEANUP-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], -12
+; CLEANUP-NEXT: store i32 [[TMP4]], ptr [[TMP2]], align 4
+; CLEANUP-NEXT: [[TMP5:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
+; CLEANUP-NEXT: [[TMP7:%.*]] = inttoptr i32 [[TMP6]] to ptr addrspace(21)
+; CLEANUP-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP7]], i64 0
+; CLEANUP-NEXT: [[TMP9:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; CLEANUP-NEXT: [[TMP10:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; CLEANUP-NEXT: [[TMP11:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; CLEANUP-NEXT: [[TMP12:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 10), align 4
+; CLEANUP-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 11), align 4
+; CLEANUP-NEXT: [[TMP14:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 12), align 4
+; CLEANUP-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 13), align 4
+; CLEANUP-NEXT: [[TMP16:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 14), align 4
+; CLEANUP-NEXT: [[TMP17:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 15), align 4
+; CLEANUP-NEXT: [[TMP18:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
+; CLEANUP-NEXT: [[TMP19:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
+; CLEANUP-NEXT: [[TMP20:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
+; CLEANUP-NEXT: [[TMP21:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
+; CLEANUP-NEXT: [[TMP22:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
+; CLEANUP-NEXT: [[TMP23:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
+; CLEANUP-NEXT: [[TMP24:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
+; CLEANUP-NEXT: [[TMP25:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
+; CLEANUP-NEXT: [[TMP26:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
+; CLEANUP-NEXT: [[TMP27:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
+; CLEANUP-NEXT: [[TMP28:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
+; CLEANUP-NEXT: [[TMP29:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
+; CLEANUP-NEXT: [[TMP30:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
+; CLEANUP-NEXT: [[TMP31:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
+; CLEANUP-NEXT: [[TMP32:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 30), align 4
+; CLEANUP-NEXT: [[TMP33:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 31), align 4
+; CLEANUP-NEXT: [[TMP34:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 32), align 4
+; CLEANUP-NEXT: [[TMP35:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 33), align 4
+; CLEANUP-NEXT: [[TMP36:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 34), align 4
+; CLEANUP-NEXT: [[TMP37:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 35), align 4
+; CLEANUP-NEXT: [[TMP38:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 36), align 4
+; CLEANUP-NEXT: [[TMP39:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 37), align 4
+; CLEANUP-NEXT: [[TMP40:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 38), align 4
+; CLEANUP-NEXT: [[TMP41:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 39), align 4
+; CLEANUP-NEXT: [[TMP42:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 40), align 4
+; CLEANUP-NEXT: [[TMP43:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 41), align 4
+; CLEANUP-NEXT: [[TMP44:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 42), align 4
+; CLEANUP-NEXT: [[TMP45:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 43), align 4
+; CLEANUP-NEXT: [[TMP46:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 44), align 4
+; CLEANUP-NEXT: [[TMP47:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 45), align 4
+; CLEANUP-NEXT: [[TMP48:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 46), align 4
+; CLEANUP-NEXT: [[TMP49:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 47), align 4
+; CLEANUP-NEXT: [[TMP50:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 48), align 4
+; CLEANUP-NEXT: [[TMP51:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 49), align 4
+; CLEANUP-NEXT: [[TMP52:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 50), align 4
+; CLEANUP-NEXT: [[TMP53:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 51), align 4
+; CLEANUP-NEXT: [[TMP54:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 52), align 4
+; CLEANUP-NEXT: [[TMP55:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 53), align 4
+; CLEANUP-NEXT: [[TMP56:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 54), align 4
+; CLEANUP-NEXT: [[TMP57:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 55), align 4
+; CLEANUP-NEXT: [[TMP58:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 56), align 4
; CLEANUP-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
-; CLEANUP-NEXT: [[DOTFCA_0_GEP51:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[TMP21]], i32 0, i32 0
-; CLEANUP-NEXT: store i32 [[DOTFCA_0_EXTRACT]], ptr [[DOTFCA_0_GEP51]], align 4
; CLEANUP-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; CLEANUP-NEXT: [[DOTRELOAD_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME]], ptr [[CONT_STATE]], i32 0, i32 2
-; CLEANUP-NEXT: [[DOTRELOAD:%.*]] = load i32, ptr [[DOTRELOAD_ADDR]], align 4
-; CLEANUP-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME]], ptr [[CONT_STATE]], i32 0, i32 1
-; CLEANUP-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr [[RETURNADDR_RELOAD_ADDR]], align 4
+; CLEANUP-NEXT: [[DOTRELOAD_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME:%.*]], ptr addrspace(21) [[TMP8]], i32 0, i32 1
+; CLEANUP-NEXT: [[DOTRELOAD:%.*]] = load i32, ptr addrspace(21) [[DOTRELOAD_ADDR]], align 4
+; CLEANUP-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME]], ptr addrspace(21) [[TMP8]], i32 0, i32 0
+; CLEANUP-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr addrspace(21) [[RETURNADDR_RELOAD_ADDR]], align 4
; CLEANUP-NEXT: store i32 [[DOTRELOAD]], ptr @PAYLOAD, align 4
; CLEANUP-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; CLEANUP-NEXT: store i32 [[TMP22]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; CLEANUP-NEXT: store i32 [[TMP23]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; CLEANUP-NEXT: store i32 [[TMP24]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; CLEANUP-NEXT: store i32 [[TMP25]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 10), align 4
-; CLEANUP-NEXT: store i32 [[TMP26]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 11), align 4
-; CLEANUP-NEXT: store i32 [[TMP27]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 12), align 4
-; CLEANUP-NEXT: store i32 [[TMP28]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 13), align 4
-; CLEANUP-NEXT: store i32 [[TMP29]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 14), align 4
-; CLEANUP-NEXT: store i32 [[TMP30]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 15), align 4
-; CLEANUP-NEXT: store i32 [[TMP31]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
-; CLEANUP-NEXT: store i32 [[TMP32]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
-; CLEANUP-NEXT: store i32 [[TMP33]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
-; CLEANUP-NEXT: store i32 [[TMP34]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
-; CLEANUP-NEXT: store i32 [[TMP35]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
-; CLEANUP-NEXT: store i32 [[TMP36]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
-; CLEANUP-NEXT: store i32 [[TMP37]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
-; CLEANUP-NEXT: store i32 [[TMP38]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
-; CLEANUP-NEXT: store i32 [[TMP39]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
-; CLEANUP-NEXT: store i32 [[TMP40]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
-; CLEANUP-NEXT: store i32 [[TMP41]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
-; CLEANUP-NEXT: store i32 [[TMP42]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
-; CLEANUP-NEXT: store i32 [[TMP43]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
-; CLEANUP-NEXT: store i32 [[TMP44]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
-; CLEANUP-NEXT: store i32 [[TMP45]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 30), align 4
-; CLEANUP-NEXT: store i32 [[TMP46]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 31), align 4
-; CLEANUP-NEXT: store i32 [[TMP47]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 32), align 4
-; CLEANUP-NEXT: store i32 [[TMP48]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 33), align 4
-; CLEANUP-NEXT: store i32 [[TMP49]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 34), align 4
-; CLEANUP-NEXT: store i32 [[TMP50]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 35), align 4
-; CLEANUP-NEXT: store i32 [[TMP51]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 36), align 4
-; CLEANUP-NEXT: store i32 [[TMP52]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 37), align 4
-; CLEANUP-NEXT: store i32 [[TMP53]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 38), align 4
-; CLEANUP-NEXT: store i32 [[TMP54]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 39), align 4
-; CLEANUP-NEXT: store i32 [[TMP55]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 40), align 4
-; CLEANUP-NEXT: store i32 [[TMP56]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 41), align 4
-; CLEANUP-NEXT: store i32 [[TMP57]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 42), align 4
-; CLEANUP-NEXT: store i32 [[TMP58]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 43), align 4
-; CLEANUP-NEXT: store i32 [[TMP59]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 44), align 4
-; CLEANUP-NEXT: store i32 [[TMP60]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 45), align 4
-; CLEANUP-NEXT: store i32 [[TMP61]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 46), align 4
-; CLEANUP-NEXT: store i32 [[TMP62]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 47), align 4
-; CLEANUP-NEXT: store i32 [[TMP63]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 48), align 4
-; CLEANUP-NEXT: store i32 [[TMP64]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 49), align 4
-; CLEANUP-NEXT: store i32 [[TMP65]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 50), align 4
-; CLEANUP-NEXT: store i32 [[TMP66]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 51), align 4
-; CLEANUP-NEXT: store i32 [[TMP67]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 52), align 4
-; CLEANUP-NEXT: store i32 [[TMP68]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 53), align 4
-; CLEANUP-NEXT: store i32 [[TMP69]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 54), align 4
-; CLEANUP-NEXT: store i32 [[TMP70]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 55), align 4
-; CLEANUP-NEXT: store i32 [[TMP71]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 56), align 4
-; CLEANUP-NEXT: [[TMP72:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANUP-NEXT: [[TMP73:%.*]] = load i32, ptr [[TMP72]], align 4
-; CLEANUP-NEXT: [[TMP74:%.*]] = add i32 [[TMP73]], -108
-; CLEANUP-NEXT: store i32 [[TMP74]], ptr [[TMP72]], align 4
-; CLEANUP-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; CLEANUP-NEXT: [[DOTFCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[TMP75]], i32 0, i32 0
-; CLEANUP-NEXT: [[DOTFCA_0_LOAD:%.*]] = load i32, ptr [[DOTFCA_0_GEP]], align 4
-; CLEANUP-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, i32 [[DOTFCA_0_LOAD]], 0
-; CLEANUP-NEXT: [[TMP76:%.*]] = call ptr @continuation.getContinuationStackOffset()
-; CLEANUP-NEXT: [[TMP77:%.*]] = load i32, ptr [[TMP76]], align 4
-; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP77]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount !18
+; CLEANUP-NEXT: store i32 [[TMP9]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; CLEANUP-NEXT: store i32 [[TMP10]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; CLEANUP-NEXT: store i32 [[TMP11]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; CLEANUP-NEXT: store i32 [[TMP12]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 10), align 4
+; CLEANUP-NEXT: store i32 [[TMP13]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 11), align 4
+; CLEANUP-NEXT: store i32 [[TMP14]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 12), align 4
+; CLEANUP-NEXT: store i32 [[TMP15]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 13), align 4
+; CLEANUP-NEXT: store i32 [[TMP16]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 14), align 4
+; CLEANUP-NEXT: store i32 [[TMP17]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 15), align 4
+; CLEANUP-NEXT: store i32 [[TMP18]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 16), align 4
+; CLEANUP-NEXT: store i32 [[TMP19]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 17), align 4
+; CLEANUP-NEXT: store i32 [[TMP20]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 18), align 4
+; CLEANUP-NEXT: store i32 [[TMP21]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 19), align 4
+; CLEANUP-NEXT: store i32 [[TMP22]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 20), align 4
+; CLEANUP-NEXT: store i32 [[TMP23]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 21), align 4
+; CLEANUP-NEXT: store i32 [[TMP24]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 22), align 4
+; CLEANUP-NEXT: store i32 [[TMP25]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 23), align 4
+; CLEANUP-NEXT: store i32 [[TMP26]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 24), align 4
+; CLEANUP-NEXT: store i32 [[TMP27]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 25), align 4
+; CLEANUP-NEXT: store i32 [[TMP28]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 26), align 4
+; CLEANUP-NEXT: store i32 [[TMP29]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 27), align 4
+; CLEANUP-NEXT: store i32 [[TMP30]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 28), align 4
+; CLEANUP-NEXT: store i32 [[TMP31]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 29), align 4
+; CLEANUP-NEXT: store i32 [[TMP32]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 30), align 4
+; CLEANUP-NEXT: store i32 [[TMP33]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 31), align 4
+; CLEANUP-NEXT: store i32 [[TMP34]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 32), align 4
+; CLEANUP-NEXT: store i32 [[TMP35]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 33), align 4
+; CLEANUP-NEXT: store i32 [[TMP36]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 34), align 4
+; CLEANUP-NEXT: store i32 [[TMP37]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 35), align 4
+; CLEANUP-NEXT: store i32 [[TMP38]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 36), align 4
+; CLEANUP-NEXT: store i32 [[TMP39]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 37), align 4
+; CLEANUP-NEXT: store i32 [[TMP40]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 38), align 4
+; CLEANUP-NEXT: store i32 [[TMP41]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 39), align 4
+; CLEANUP-NEXT: store i32 [[TMP42]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 40), align 4
+; CLEANUP-NEXT: store i32 [[TMP43]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 41), align 4
+; CLEANUP-NEXT: store i32 [[TMP44]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 42), align 4
+; CLEANUP-NEXT: store i32 [[TMP45]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 43), align 4
+; CLEANUP-NEXT: store i32 [[TMP46]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 44), align 4
+; CLEANUP-NEXT: store i32 [[TMP47]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 45), align 4
+; CLEANUP-NEXT: store i32 [[TMP48]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 46), align 4
+; CLEANUP-NEXT: store i32 [[TMP49]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 47), align 4
+; CLEANUP-NEXT: store i32 [[TMP50]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 48), align 4
+; CLEANUP-NEXT: store i32 [[TMP51]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 49), align 4
+; CLEANUP-NEXT: store i32 [[TMP52]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 50), align 4
+; CLEANUP-NEXT: store i32 [[TMP53]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 51), align 4
+; CLEANUP-NEXT: store i32 [[TMP54]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 52), align 4
+; CLEANUP-NEXT: store i32 [[TMP55]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 53), align 4
+; CLEANUP-NEXT: store i32 [[TMP56]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 54), align 4
+; CLEANUP-NEXT: store i32 [[TMP57]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 55), align 4
+; CLEANUP-NEXT: store i32 [[TMP58]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 56), align 4
+; CLEANUP-NEXT: [[TMP59:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP60:%.*]] = load i32, ptr [[TMP59]], align 4
+; CLEANUP-NEXT: [[TMP61:%.*]] = add i32 [[TMP60]], -108
+; CLEANUP-NEXT: store i32 [[TMP61]], ptr [[TMP59]], align 4
+; CLEANUP-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, <3 x i32> [[DOTFCA_0_EXTRACT]], 0
+; CLEANUP-NEXT: [[TMP62:%.*]] = call ptr @continuation.getContinuationStackOffset()
+; CLEANUP-NEXT: [[TMP63:%.*]] = load i32, ptr [[TMP62]], align 4
+; CLEANUP-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP63]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META18]]
; CLEANUP-NEXT: unreachable
;
;
-; POST-PROCESS-LABEL: define i32 @_cont_GetLocalRootIndex(
+; POST-PROCESS-LABEL: define %struct.BuiltInTriangleIntersectionAttributes @_cont_GetTriangleHitAttributes(
; POST-PROCESS-SAME: ptr [[DATA:%.*]]) #[[ATTR0:[0-9]+]] {
+; POST-PROCESS-NEXT: [[ADDR:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[DATA]], i32 0, i32 1
+; POST-PROCESS-NEXT: [[VAL:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]], ptr [[ADDR]], align 4
+; POST-PROCESS-NEXT: ret [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[VAL]]
+;
+;
+; POST-PROCESS-LABEL: define i32 @_cont_GetLocalRootIndex(
+; POST-PROCESS-SAME: ptr [[DATA:%.*]]) #[[ATTR0]] {
; POST-PROCESS-NEXT: ret i32 5
;
;
-; POST-PROCESS-LABEL: define void @main() !lgc.rt.shaderstage !8 !continuation.entry !19 !continuation.registercount !8 !continuation !20 !continuation.stacksize !21 !continuation.state !8 {
+; POST-PROCESS-LABEL: define void @main(
+; POST-PROCESS-SAME: ) !lgc.rt.shaderstage [[META8:![0-9]+]] !continuation.entry [[META19:![0-9]+]] !continuation.registercount [[META8]] !continuation [[META20:![0-9]+]] !continuation.stacksize [[META21:![0-9]+]] !continuation.state [[META8]] {
; POST-PROCESS-NEXT: AllocaSpillBB:
-; POST-PROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
-; POST-PROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
; POST-PROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; POST-PROCESS-NEXT: [[TMP0:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @_cont_SetupRayGen()
-; POST-PROCESS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
-; POST-PROCESS-NEXT: [[TMP1:%.*]] = call i32 @_cont_GetContinuationStackAddr()
-; POST-PROCESS-NEXT: store i32 [[TMP1]], ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP2:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA]], align 4
-; POST-PROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP2]], 0
-; POST-PROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; POST-PROCESS-NEXT: [[TMP3:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], 108
-; POST-PROCESS-NEXT: store i32 [[TMP4]], ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP5:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
-; POST-PROCESS-NEXT: [[TMP6:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
-; POST-PROCESS-NEXT: [[TMP7:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP5]])
-; POST-PROCESS-NEXT: [[TMP8:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP7]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
-; POST-PROCESS-NEXT: [[TMP9:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[TMP8]])
-; POST-PROCESS-NEXT: [[DIS_DATA_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, i32 [[DOTFCA_0_EXTRACT]], 0
+; POST-PROCESS-NEXT: [[SYSTEM_DATA:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA:%.*]] @_cont_SetupRayGen()
+; POST-PROCESS-NEXT: [[TMP0:%.*]] = call i32 @_cont_GetContinuationStackAddr()
+; POST-PROCESS-NEXT: store i32 [[TMP0]], ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[SYSTEM_DATA]], 0
+; POST-PROCESS-NEXT: [[TMP1:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 108
+; POST-PROCESS-NEXT: store i32 [[TMP2]], ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
+; POST-PROCESS-NEXT: [[TMP3:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
+; POST-PROCESS-NEXT: [[TMP4:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
+; POST-PROCESS-NEXT: [[TMP5:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP3]])
+; POST-PROCESS-NEXT: [[TMP6:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP5]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
+; POST-PROCESS-NEXT: [[TMP7:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[TMP6]])
+; POST-PROCESS-NEXT: [[DIS_DATA_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, <3 x i32> [[DOTFCA_0_EXTRACT]], 0
; POST-PROCESS-NEXT: [[SYS_DATA_I:%.*]] = insertvalue [[STRUCT_SYSTEMDATA:%.*]] undef, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I_FCA_0_INSERT]], 0
; POST-PROCESS-NEXT: [[TRAV_DATA_I:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA:%.*]] undef, [[STRUCT_SYSTEMDATA]] [[SYS_DATA_I]], 0
-; POST-PROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP11:%.*]] = add i32 [[TMP10]], -108
-; POST-PROCESS-NEXT: store i32 [[TMP11]], ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP8:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP9:%.*]] = add i32 [[TMP8]], -108
+; POST-PROCESS-NEXT: store i32 [[TMP9]], ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
@@ -853,154 +870,151 @@ attributes #3 = { nounwind }
; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP13:%.*]] = inttoptr i32 [[TMP12]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP13]], i32 -30
-; POST-PROCESS-NEXT: [[TMP15:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP14]], i32 0, i32 0, i64 30
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP15]], align 4
-; POST-PROCESS-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP17:%.*]] = inttoptr i32 [[TMP16]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP18:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP17]], i32 -30
-; POST-PROCESS-NEXT: [[TMP19:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP18]], i32 0, i32 0, i64 31
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP19]], align 4
-; POST-PROCESS-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP21:%.*]] = inttoptr i32 [[TMP20]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP21]], i32 -30
-; POST-PROCESS-NEXT: [[TMP23:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP22]], i32 0, i32 0, i64 32
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP23]], align 4
-; POST-PROCESS-NEXT: [[TMP24:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP25:%.*]] = inttoptr i32 [[TMP24]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP25]], i32 -30
-; POST-PROCESS-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP26]], i32 0, i32 0, i64 33
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP27]], align 4
-; POST-PROCESS-NEXT: [[TMP28:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP29:%.*]] = inttoptr i32 [[TMP28]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP30:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP29]], i32 -30
-; POST-PROCESS-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP30]], i32 0, i32 0, i64 34
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP31]], align 4
-; POST-PROCESS-NEXT: [[TMP32:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP33:%.*]] = inttoptr i32 [[TMP32]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP34:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP33]], i32 -30
-; POST-PROCESS-NEXT: [[TMP35:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP34]], i32 0, i32 0, i64 35
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP35]], align 4
-; POST-PROCESS-NEXT: [[TMP36:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP37:%.*]] = inttoptr i32 [[TMP36]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP38:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP37]], i32 -30
-; POST-PROCESS-NEXT: [[TMP39:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP38]], i32 0, i32 0, i64 36
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP39]], align 4
-; POST-PROCESS-NEXT: [[TMP40:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP41:%.*]] = inttoptr i32 [[TMP40]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP42:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP41]], i32 -30
-; POST-PROCESS-NEXT: [[TMP43:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP42]], i32 0, i32 0, i64 37
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP43]], align 4
-; POST-PROCESS-NEXT: [[TMP44:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP45:%.*]] = inttoptr i32 [[TMP44]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP46:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP45]], i32 -30
-; POST-PROCESS-NEXT: [[TMP47:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP46]], i32 0, i32 0, i64 38
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP47]], align 4
-; POST-PROCESS-NEXT: [[TMP48:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP49:%.*]] = inttoptr i32 [[TMP48]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP50:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP49]], i32 -30
-; POST-PROCESS-NEXT: [[TMP51:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP50]], i32 0, i32 0, i64 39
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP51]], align 4
-; POST-PROCESS-NEXT: [[TMP52:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP53:%.*]] = inttoptr i32 [[TMP52]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP54:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP53]], i32 -30
-; POST-PROCESS-NEXT: [[TMP55:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP54]], i32 0, i32 0, i64 40
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP55]], align 4
-; POST-PROCESS-NEXT: [[TMP56:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP57:%.*]] = inttoptr i32 [[TMP56]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP58:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP57]], i32 -30
-; POST-PROCESS-NEXT: [[TMP59:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP58]], i32 0, i32 0, i64 41
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP59]], align 4
-; POST-PROCESS-NEXT: [[TMP60:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP61:%.*]] = inttoptr i32 [[TMP60]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP62:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP61]], i32 -30
-; POST-PROCESS-NEXT: [[TMP63:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP62]], i32 0, i32 0, i64 42
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP63]], align 4
-; POST-PROCESS-NEXT: [[TMP64:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP65:%.*]] = inttoptr i32 [[TMP64]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP66:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP65]], i32 -30
-; POST-PROCESS-NEXT: [[TMP67:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP66]], i32 0, i32 0, i64 43
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP67]], align 4
-; POST-PROCESS-NEXT: [[TMP68:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP69:%.*]] = inttoptr i32 [[TMP68]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP70:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP69]], i32 -30
-; POST-PROCESS-NEXT: [[TMP71:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP70]], i32 0, i32 0, i64 44
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP71]], align 4
-; POST-PROCESS-NEXT: [[TMP72:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP73:%.*]] = inttoptr i32 [[TMP72]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP74:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP73]], i32 -30
-; POST-PROCESS-NEXT: [[TMP75:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP74]], i32 0, i32 0, i64 45
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP75]], align 4
-; POST-PROCESS-NEXT: [[TMP76:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP77:%.*]] = inttoptr i32 [[TMP76]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP78:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP77]], i32 -30
-; POST-PROCESS-NEXT: [[TMP79:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP78]], i32 0, i32 0, i64 46
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP79]], align 4
-; POST-PROCESS-NEXT: [[TMP80:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP81:%.*]] = inttoptr i32 [[TMP80]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP82:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP81]], i32 -30
-; POST-PROCESS-NEXT: [[TMP83:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP82]], i32 0, i32 0, i64 47
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP83]], align 4
-; POST-PROCESS-NEXT: [[TMP84:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP85:%.*]] = inttoptr i32 [[TMP84]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP86:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP85]], i32 -30
-; POST-PROCESS-NEXT: [[TMP87:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP86]], i32 0, i32 0, i64 48
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP87]], align 4
-; POST-PROCESS-NEXT: [[TMP88:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP89:%.*]] = inttoptr i32 [[TMP88]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP90:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP89]], i32 -30
-; POST-PROCESS-NEXT: [[TMP91:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP90]], i32 0, i32 0, i64 49
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP91]], align 4
-; POST-PROCESS-NEXT: [[TMP92:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP93:%.*]] = inttoptr i32 [[TMP92]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP94:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP93]], i32 -30
-; POST-PROCESS-NEXT: [[TMP95:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP94]], i32 0, i32 0, i64 50
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP95]], align 4
-; POST-PROCESS-NEXT: [[TMP96:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP97:%.*]] = inttoptr i32 [[TMP96]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP98:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP97]], i32 -30
-; POST-PROCESS-NEXT: [[TMP99:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP98]], i32 0, i32 0, i64 51
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP99]], align 4
-; POST-PROCESS-NEXT: [[TMP100:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP101:%.*]] = inttoptr i32 [[TMP100]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP102:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP101]], i32 -30
-; POST-PROCESS-NEXT: [[TMP103:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP102]], i32 0, i32 0, i64 52
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP103]], align 4
-; POST-PROCESS-NEXT: [[TMP104:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP105:%.*]] = inttoptr i32 [[TMP104]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP106:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP105]], i32 -30
-; POST-PROCESS-NEXT: [[TMP107:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP106]], i32 0, i32 0, i64 53
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP107]], align 4
-; POST-PROCESS-NEXT: [[TMP108:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP109:%.*]] = inttoptr i32 [[TMP108]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP110:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP109]], i32 -30
-; POST-PROCESS-NEXT: [[TMP111:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP110]], i32 0, i32 0, i64 54
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP111]], align 4
-; POST-PROCESS-NEXT: [[TMP112:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP113:%.*]] = inttoptr i32 [[TMP112]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP114:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP113]], i32 -30
-; POST-PROCESS-NEXT: [[TMP115:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP114]], i32 0, i32 0, i64 55
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP115]], align 4
-; POST-PROCESS-NEXT: [[TMP116:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP117:%.*]] = inttoptr i32 [[TMP116]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP118:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP117]], i32 -30
-; POST-PROCESS-NEXT: [[TMP119:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP118]], i32 0, i32 0, i64 56
-; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP119]], align 4
-; POST-PROCESS-NEXT: [[TMP120:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP121:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @main.resume.0 to i64))
-; POST-PROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 4, i32 [[TMP120]], i64 [[TMP121]], [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]]), !continuation.registercount !17, !continuation.returnedRegistercount !17
+; POST-PROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP10]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP11]], i32 -30
+; POST-PROCESS-NEXT: [[TMP13:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP12]], i32 0, i32 0, i64 30
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP13]], align 4
+; POST-PROCESS-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP15:%.*]] = inttoptr i32 [[TMP14]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP15]], i32 -30
+; POST-PROCESS-NEXT: [[TMP17:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP16]], i32 0, i32 0, i64 31
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP17]], align 4
+; POST-PROCESS-NEXT: [[TMP18:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP19:%.*]] = inttoptr i32 [[TMP18]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP19]], i32 -30
+; POST-PROCESS-NEXT: [[TMP21:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP20]], i32 0, i32 0, i64 32
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP21]], align 4
+; POST-PROCESS-NEXT: [[TMP22:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP22]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP23]], i32 -30
+; POST-PROCESS-NEXT: [[TMP25:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP24]], i32 0, i32 0, i64 33
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP25]], align 4
+; POST-PROCESS-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP27:%.*]] = inttoptr i32 [[TMP26]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP28:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP27]], i32 -30
+; POST-PROCESS-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP28]], i32 0, i32 0, i64 34
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP29]], align 4
+; POST-PROCESS-NEXT: [[TMP30:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP31:%.*]] = inttoptr i32 [[TMP30]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP32:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP31]], i32 -30
+; POST-PROCESS-NEXT: [[TMP33:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP32]], i32 0, i32 0, i64 35
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP33]], align 4
+; POST-PROCESS-NEXT: [[TMP34:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP35:%.*]] = inttoptr i32 [[TMP34]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP36:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP35]], i32 -30
+; POST-PROCESS-NEXT: [[TMP37:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP36]], i32 0, i32 0, i64 36
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP37]], align 4
+; POST-PROCESS-NEXT: [[TMP38:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP39:%.*]] = inttoptr i32 [[TMP38]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP40:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP39]], i32 -30
+; POST-PROCESS-NEXT: [[TMP41:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP40]], i32 0, i32 0, i64 37
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP41]], align 4
+; POST-PROCESS-NEXT: [[TMP42:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP43:%.*]] = inttoptr i32 [[TMP42]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP44:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP43]], i32 -30
+; POST-PROCESS-NEXT: [[TMP45:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP44]], i32 0, i32 0, i64 38
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP45]], align 4
+; POST-PROCESS-NEXT: [[TMP46:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP47:%.*]] = inttoptr i32 [[TMP46]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP48:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP47]], i32 -30
+; POST-PROCESS-NEXT: [[TMP49:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP48]], i32 0, i32 0, i64 39
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP49]], align 4
+; POST-PROCESS-NEXT: [[TMP50:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP51:%.*]] = inttoptr i32 [[TMP50]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP52:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP51]], i32 -30
+; POST-PROCESS-NEXT: [[TMP53:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP52]], i32 0, i32 0, i64 40
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP53]], align 4
+; POST-PROCESS-NEXT: [[TMP54:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP55:%.*]] = inttoptr i32 [[TMP54]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP56:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP55]], i32 -30
+; POST-PROCESS-NEXT: [[TMP57:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP56]], i32 0, i32 0, i64 41
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP57]], align 4
+; POST-PROCESS-NEXT: [[TMP58:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP59:%.*]] = inttoptr i32 [[TMP58]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP60:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP59]], i32 -30
+; POST-PROCESS-NEXT: [[TMP61:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP60]], i32 0, i32 0, i64 42
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP61]], align 4
+; POST-PROCESS-NEXT: [[TMP62:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP63:%.*]] = inttoptr i32 [[TMP62]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP63]], i32 -30
+; POST-PROCESS-NEXT: [[TMP65:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP64]], i32 0, i32 0, i64 43
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP65]], align 4
+; POST-PROCESS-NEXT: [[TMP66:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP67:%.*]] = inttoptr i32 [[TMP66]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP68:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP67]], i32 -30
+; POST-PROCESS-NEXT: [[TMP69:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP68]], i32 0, i32 0, i64 44
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP69]], align 4
+; POST-PROCESS-NEXT: [[TMP70:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP71:%.*]] = inttoptr i32 [[TMP70]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP72:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP71]], i32 -30
+; POST-PROCESS-NEXT: [[TMP73:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP72]], i32 0, i32 0, i64 45
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP73]], align 4
+; POST-PROCESS-NEXT: [[TMP74:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP75:%.*]] = inttoptr i32 [[TMP74]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP76:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP75]], i32 -30
+; POST-PROCESS-NEXT: [[TMP77:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP76]], i32 0, i32 0, i64 46
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP77]], align 4
+; POST-PROCESS-NEXT: [[TMP78:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP79:%.*]] = inttoptr i32 [[TMP78]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP80:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP79]], i32 -30
+; POST-PROCESS-NEXT: [[TMP81:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP80]], i32 0, i32 0, i64 47
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP81]], align 4
+; POST-PROCESS-NEXT: [[TMP82:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP83:%.*]] = inttoptr i32 [[TMP82]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP84:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP83]], i32 -30
+; POST-PROCESS-NEXT: [[TMP85:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP84]], i32 0, i32 0, i64 48
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP85]], align 4
+; POST-PROCESS-NEXT: [[TMP86:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP87:%.*]] = inttoptr i32 [[TMP86]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP88:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP87]], i32 -30
+; POST-PROCESS-NEXT: [[TMP89:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP88]], i32 0, i32 0, i64 49
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP89]], align 4
+; POST-PROCESS-NEXT: [[TMP90:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP91:%.*]] = inttoptr i32 [[TMP90]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP92:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP91]], i32 -30
+; POST-PROCESS-NEXT: [[TMP93:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP92]], i32 0, i32 0, i64 50
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP93]], align 4
+; POST-PROCESS-NEXT: [[TMP94:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP95:%.*]] = inttoptr i32 [[TMP94]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP96:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP95]], i32 -30
+; POST-PROCESS-NEXT: [[TMP97:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP96]], i32 0, i32 0, i64 51
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP97]], align 4
+; POST-PROCESS-NEXT: [[TMP98:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP99:%.*]] = inttoptr i32 [[TMP98]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP100:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP99]], i32 -30
+; POST-PROCESS-NEXT: [[TMP101:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP100]], i32 0, i32 0, i64 52
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP101]], align 4
+; POST-PROCESS-NEXT: [[TMP102:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP103:%.*]] = inttoptr i32 [[TMP102]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP104:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP103]], i32 -30
+; POST-PROCESS-NEXT: [[TMP105:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP104]], i32 0, i32 0, i64 53
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP105]], align 4
+; POST-PROCESS-NEXT: [[TMP106:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP107:%.*]] = inttoptr i32 [[TMP106]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP108:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP107]], i32 -30
+; POST-PROCESS-NEXT: [[TMP109:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP108]], i32 0, i32 0, i64 54
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP109]], align 4
+; POST-PROCESS-NEXT: [[TMP110:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP111:%.*]] = inttoptr i32 [[TMP110]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP112:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP111]], i32 -30
+; POST-PROCESS-NEXT: [[TMP113:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP112]], i32 0, i32 0, i64 55
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP113]], align 4
+; POST-PROCESS-NEXT: [[TMP114:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP115:%.*]] = inttoptr i32 [[TMP114]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP116:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP115]], i32 -30
+; POST-PROCESS-NEXT: [[TMP117:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP116]], i32 0, i32 0, i64 56
+; POST-PROCESS-NEXT: store i32 undef, ptr addrspace(21) [[TMP117]], align 4
+; POST-PROCESS-NEXT: [[TMP118:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP119:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @main.resume.0 to i64))
+; POST-PROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 4, i32 [[TMP118]], i64 [[TMP119]], [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]]), !continuation.registercount [[META17:![0-9]+]], !continuation.returnedRegistercount !17
; POST-PROCESS-NEXT: unreachable
;
;
; POST-PROCESS-LABEL: define dso_local void @main.resume.0(
-; POST-PROCESS-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.shaderstage !8 !continuation.registercount !17 !continuation !20 {
+; POST-PROCESS-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.shaderstage [[META8]] !continuation.registercount [[META17]] !continuation [[META20]] {
; POST-PROCESS-NEXT: entryresume.0:
-; POST-PROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
-; POST-PROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
; POST-PROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; POST-PROCESS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA]], align 4
; POST-PROCESS-NEXT: store i32 [[TMP0]], ptr [[CSP]], align 4
; POST-PROCESS-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
; POST-PROCESS-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
@@ -1161,7 +1175,7 @@ attributes #3 = { nounwind }
; POST-PROCESS-NEXT: [[TMP158:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP157]], i32 0, i32 0, i64 56
; POST-PROCESS-NEXT: [[TMP159:%.*]] = load i32, ptr addrspace(21) [[TMP158]], align 4
; POST-PROCESS-NEXT: [[DOTFCA_0_EXTRACT1:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
-; POST-PROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; POST-PROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; POST-PROCESS-NEXT: [[TMP160:%.*]] = load i32, ptr [[CSP]], align 4
; POST-PROCESS-NEXT: [[TMP161:%.*]] = add i32 [[TMP160]], -108
; POST-PROCESS-NEXT: store i32 [[TMP161]], ptr [[CSP]], align 4
@@ -1170,1126 +1184,3040 @@ attributes #3 = { nounwind }
;
;
; POST-PROCESS-LABEL: define void @AnyHit(
-; POST-PROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_ANYHITTRAVERSALDATA:%.*]] [[TMP0:%.*]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] !lgc.rt.shaderstage !22 !continuation.registercount !17 !continuation !23 !continuation.state !8 {
+; POST-PROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_ANYHITTRAVERSALDATA:%.*]] [[TMP0:%.*]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] !lgc.rt.shaderstage [[META22:![0-9]+]] !continuation.registercount [[META17]] !continuation [[META23:![0-9]+]] !continuation.state [[META8]] {
; POST-PROCESS-NEXT: AllocaSpillBB:
-; POST-PROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_ANYHITTRAVERSALDATA]], align 8
; POST-PROCESS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_ANYHITTRAVERSALDATA]], align 8
-; POST-PROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
; POST-PROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; POST-PROCESS-NEXT: store [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
; POST-PROCESS-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP2:%.*]] = load [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA]], align 4
-; POST-PROCESS-NEXT: [[DOTFCA_0_0_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP2]], 0, 0, 0, 0
+; POST-PROCESS-NEXT: [[DOTFCA_0_0_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 0, 0, 0
; POST-PROCESS-NEXT: [[DOTFCA_0_0_0_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0, i32 0
-; POST-PROCESS-NEXT: store i32 [[DOTFCA_0_0_0_0_EXTRACT]], ptr [[DOTFCA_0_0_0_0_GEP]], align 4
-; POST-PROCESS-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP2]], 1, 0
+; POST-PROCESS-NEXT: store <3 x i32> [[DOTFCA_0_0_0_0_EXTRACT]], ptr [[DOTFCA_0_0_0_0_GEP]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_0_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 0, 1, 0
+; POST-PROCESS-NEXT: [[DOTFCA_0_0_1_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 1, i32 0
+; POST-PROCESS-NEXT: store <2 x float> [[DOTFCA_0_0_1_0_EXTRACT]], ptr [[DOTFCA_0_0_1_0_GEP]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 1, 0
+; POST-PROCESS-NEXT: [[DOTFCA_0_1_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 1, i32 0
+; POST-PROCESS-NEXT: store float [[DOTFCA_0_1_0_EXTRACT]], ptr [[DOTFCA_0_1_0_GEP]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 1, 1
+; POST-PROCESS-NEXT: [[DOTFCA_0_1_1_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 1, i32 1
+; POST-PROCESS-NEXT: store i32 [[DOTFCA_0_1_1_EXTRACT]], ptr [[DOTFCA_0_1_1_GEP]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_2_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 2
+; POST-PROCESS-NEXT: [[DOTFCA_0_2_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 2
+; POST-PROCESS-NEXT: store <3 x float> [[DOTFCA_0_2_EXTRACT]], ptr [[DOTFCA_0_2_GEP]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_3_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 3
+; POST-PROCESS-NEXT: [[DOTFCA_0_3_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 3
+; POST-PROCESS-NEXT: store <3 x float> [[DOTFCA_0_3_EXTRACT]], ptr [[DOTFCA_0_3_GEP]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_4_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_4_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 4
+; POST-PROCESS-NEXT: store float [[DOTFCA_0_4_EXTRACT]], ptr [[DOTFCA_0_4_GEP]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_5_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 5
+; POST-PROCESS-NEXT: [[DOTFCA_0_5_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 5
+; POST-PROCESS-NEXT: store i64 [[DOTFCA_0_5_EXTRACT]], ptr [[DOTFCA_0_5_GEP]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 1, 0
; POST-PROCESS-NEXT: [[DOTFCA_1_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 0
; POST-PROCESS-NEXT: store float [[DOTFCA_1_0_EXTRACT]], ptr [[DOTFCA_1_0_GEP]], align 4
-; POST-PROCESS-NEXT: [[DOTFCA_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP2]], 1, 1
+; POST-PROCESS-NEXT: [[DOTFCA_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 1, 1
; POST-PROCESS-NEXT: [[DOTFCA_1_1_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 1
; POST-PROCESS-NEXT: store i32 [[DOTFCA_1_1_EXTRACT]], ptr [[DOTFCA_1_1_GEP]], align 4
-; POST-PROCESS-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
-; POST-PROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; POST-PROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP5:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP18:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP19:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP22:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP23:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP24:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP25:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP27:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP28:%.*]] = inttoptr i32 [[TMP27]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP28]], i32 -30
-; POST-PROCESS-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP29]], i32 0, i32 0, i64 30
-; POST-PROCESS-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(21) [[TMP30]], align 4
-; POST-PROCESS-NEXT: [[TMP32:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP33:%.*]] = inttoptr i32 [[TMP32]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP34:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP33]], i32 -30
-; POST-PROCESS-NEXT: [[TMP35:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP34]], i32 0, i32 0, i64 31
-; POST-PROCESS-NEXT: [[TMP36:%.*]] = load i32, ptr addrspace(21) [[TMP35]], align 4
-; POST-PROCESS-NEXT: [[TMP37:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP38:%.*]] = inttoptr i32 [[TMP37]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP39:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP38]], i32 -30
-; POST-PROCESS-NEXT: [[TMP40:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP39]], i32 0, i32 0, i64 32
-; POST-PROCESS-NEXT: [[TMP41:%.*]] = load i32, ptr addrspace(21) [[TMP40]], align 4
-; POST-PROCESS-NEXT: [[TMP42:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP43:%.*]] = inttoptr i32 [[TMP42]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP44:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP43]], i32 -30
-; POST-PROCESS-NEXT: [[TMP45:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP44]], i32 0, i32 0, i64 33
-; POST-PROCESS-NEXT: [[TMP46:%.*]] = load i32, ptr addrspace(21) [[TMP45]], align 4
-; POST-PROCESS-NEXT: [[TMP47:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP48:%.*]] = inttoptr i32 [[TMP47]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP49:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP48]], i32 -30
-; POST-PROCESS-NEXT: [[TMP50:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP49]], i32 0, i32 0, i64 34
-; POST-PROCESS-NEXT: [[TMP51:%.*]] = load i32, ptr addrspace(21) [[TMP50]], align 4
-; POST-PROCESS-NEXT: [[TMP52:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP53:%.*]] = inttoptr i32 [[TMP52]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP54:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP53]], i32 -30
-; POST-PROCESS-NEXT: [[TMP55:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP54]], i32 0, i32 0, i64 35
-; POST-PROCESS-NEXT: [[TMP56:%.*]] = load i32, ptr addrspace(21) [[TMP55]], align 4
-; POST-PROCESS-NEXT: [[TMP57:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP58:%.*]] = inttoptr i32 [[TMP57]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP59:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP58]], i32 -30
-; POST-PROCESS-NEXT: [[TMP60:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP59]], i32 0, i32 0, i64 36
-; POST-PROCESS-NEXT: [[TMP61:%.*]] = load i32, ptr addrspace(21) [[TMP60]], align 4
-; POST-PROCESS-NEXT: [[TMP62:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP63:%.*]] = inttoptr i32 [[TMP62]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP63]], i32 -30
-; POST-PROCESS-NEXT: [[TMP65:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP64]], i32 0, i32 0, i64 37
-; POST-PROCESS-NEXT: [[TMP66:%.*]] = load i32, ptr addrspace(21) [[TMP65]], align 4
-; POST-PROCESS-NEXT: [[TMP67:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP68:%.*]] = inttoptr i32 [[TMP67]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP69:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP68]], i32 -30
-; POST-PROCESS-NEXT: [[TMP70:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP69]], i32 0, i32 0, i64 38
-; POST-PROCESS-NEXT: [[TMP71:%.*]] = load i32, ptr addrspace(21) [[TMP70]], align 4
-; POST-PROCESS-NEXT: [[TMP72:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP73:%.*]] = inttoptr i32 [[TMP72]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP74:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP73]], i32 -30
-; POST-PROCESS-NEXT: [[TMP75:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP74]], i32 0, i32 0, i64 39
-; POST-PROCESS-NEXT: [[TMP76:%.*]] = load i32, ptr addrspace(21) [[TMP75]], align 4
-; POST-PROCESS-NEXT: [[TMP77:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP78:%.*]] = inttoptr i32 [[TMP77]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP79:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP78]], i32 -30
-; POST-PROCESS-NEXT: [[TMP80:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP79]], i32 0, i32 0, i64 40
-; POST-PROCESS-NEXT: [[TMP81:%.*]] = load i32, ptr addrspace(21) [[TMP80]], align 4
-; POST-PROCESS-NEXT: [[TMP82:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP83:%.*]] = inttoptr i32 [[TMP82]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP84:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP83]], i32 -30
-; POST-PROCESS-NEXT: [[TMP85:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP84]], i32 0, i32 0, i64 41
-; POST-PROCESS-NEXT: [[TMP86:%.*]] = load i32, ptr addrspace(21) [[TMP85]], align 4
-; POST-PROCESS-NEXT: [[TMP87:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP88:%.*]] = inttoptr i32 [[TMP87]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP89:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP88]], i32 -30
-; POST-PROCESS-NEXT: [[TMP90:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP89]], i32 0, i32 0, i64 42
-; POST-PROCESS-NEXT: [[TMP91:%.*]] = load i32, ptr addrspace(21) [[TMP90]], align 4
-; POST-PROCESS-NEXT: [[TMP92:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP93:%.*]] = inttoptr i32 [[TMP92]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP94:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP93]], i32 -30
-; POST-PROCESS-NEXT: [[TMP95:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP94]], i32 0, i32 0, i64 43
-; POST-PROCESS-NEXT: [[TMP96:%.*]] = load i32, ptr addrspace(21) [[TMP95]], align 4
-; POST-PROCESS-NEXT: [[TMP97:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP98:%.*]] = inttoptr i32 [[TMP97]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP99:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP98]], i32 -30
-; POST-PROCESS-NEXT: [[TMP100:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP99]], i32 0, i32 0, i64 44
-; POST-PROCESS-NEXT: [[TMP101:%.*]] = load i32, ptr addrspace(21) [[TMP100]], align 4
-; POST-PROCESS-NEXT: [[TMP102:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP103:%.*]] = inttoptr i32 [[TMP102]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP104:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP103]], i32 -30
-; POST-PROCESS-NEXT: [[TMP105:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP104]], i32 0, i32 0, i64 45
-; POST-PROCESS-NEXT: [[TMP106:%.*]] = load i32, ptr addrspace(21) [[TMP105]], align 4
-; POST-PROCESS-NEXT: [[TMP107:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP108:%.*]] = inttoptr i32 [[TMP107]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP109:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP108]], i32 -30
-; POST-PROCESS-NEXT: [[TMP110:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP109]], i32 0, i32 0, i64 46
-; POST-PROCESS-NEXT: [[TMP111:%.*]] = load i32, ptr addrspace(21) [[TMP110]], align 4
-; POST-PROCESS-NEXT: [[TMP112:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP113:%.*]] = inttoptr i32 [[TMP112]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP114:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP113]], i32 -30
-; POST-PROCESS-NEXT: [[TMP115:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP114]], i32 0, i32 0, i64 47
-; POST-PROCESS-NEXT: [[TMP116:%.*]] = load i32, ptr addrspace(21) [[TMP115]], align 4
-; POST-PROCESS-NEXT: [[TMP117:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP118:%.*]] = inttoptr i32 [[TMP117]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP119:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP118]], i32 -30
-; POST-PROCESS-NEXT: [[TMP120:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP119]], i32 0, i32 0, i64 48
-; POST-PROCESS-NEXT: [[TMP121:%.*]] = load i32, ptr addrspace(21) [[TMP120]], align 4
-; POST-PROCESS-NEXT: [[TMP122:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP123:%.*]] = inttoptr i32 [[TMP122]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP124:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP123]], i32 -30
-; POST-PROCESS-NEXT: [[TMP125:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP124]], i32 0, i32 0, i64 49
-; POST-PROCESS-NEXT: [[TMP126:%.*]] = load i32, ptr addrspace(21) [[TMP125]], align 4
-; POST-PROCESS-NEXT: [[TMP127:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP128:%.*]] = inttoptr i32 [[TMP127]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP129:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP128]], i32 -30
-; POST-PROCESS-NEXT: [[TMP130:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP129]], i32 0, i32 0, i64 50
-; POST-PROCESS-NEXT: [[TMP131:%.*]] = load i32, ptr addrspace(21) [[TMP130]], align 4
-; POST-PROCESS-NEXT: [[TMP132:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP133:%.*]] = inttoptr i32 [[TMP132]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP134:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP133]], i32 -30
-; POST-PROCESS-NEXT: [[TMP135:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP134]], i32 0, i32 0, i64 51
-; POST-PROCESS-NEXT: [[TMP136:%.*]] = load i32, ptr addrspace(21) [[TMP135]], align 4
-; POST-PROCESS-NEXT: [[TMP137:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP138:%.*]] = inttoptr i32 [[TMP137]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP139:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP138]], i32 -30
-; POST-PROCESS-NEXT: [[TMP140:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP139]], i32 0, i32 0, i64 52
-; POST-PROCESS-NEXT: [[TMP141:%.*]] = load i32, ptr addrspace(21) [[TMP140]], align 4
-; POST-PROCESS-NEXT: [[TMP142:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP143:%.*]] = inttoptr i32 [[TMP142]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP144:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP143]], i32 -30
-; POST-PROCESS-NEXT: [[TMP145:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP144]], i32 0, i32 0, i64 53
-; POST-PROCESS-NEXT: [[TMP146:%.*]] = load i32, ptr addrspace(21) [[TMP145]], align 4
-; POST-PROCESS-NEXT: [[TMP147:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP148:%.*]] = inttoptr i32 [[TMP147]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP149:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP148]], i32 -30
-; POST-PROCESS-NEXT: [[TMP150:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP149]], i32 0, i32 0, i64 54
-; POST-PROCESS-NEXT: [[TMP151:%.*]] = load i32, ptr addrspace(21) [[TMP150]], align 4
-; POST-PROCESS-NEXT: [[TMP152:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP153:%.*]] = inttoptr i32 [[TMP152]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP154:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP153]], i32 -30
-; POST-PROCESS-NEXT: [[TMP155:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP154]], i32 0, i32 0, i64 55
-; POST-PROCESS-NEXT: [[TMP156:%.*]] = load i32, ptr addrspace(21) [[TMP155]], align 4
-; POST-PROCESS-NEXT: [[TMP157:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP158:%.*]] = inttoptr i32 [[TMP157]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP159:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP158]], i32 -30
-; POST-PROCESS-NEXT: [[TMP160:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP159]], i32 0, i32 0, i64 56
-; POST-PROCESS-NEXT: [[TMP161:%.*]] = load i32, ptr addrspace(21) [[TMP160]], align 4
-; POST-PROCESS-NEXT: [[TMP162:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; POST-PROCESS-NEXT: [[TMP163:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] @_cont_GetTriangleHitAttributes(ptr [[TMP162]])
-; POST-PROCESS-NEXT: [[DOTFCA_0_EXTRACT4:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP163]], 0
-; POST-PROCESS-NEXT: [[DOTSROA_05_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT4]], i32 0
-; POST-PROCESS-NEXT: [[TMP164:%.*]] = bitcast float [[DOTSROA_05_0_VEC_EXTRACT]] to i32
-; POST-PROCESS-NEXT: [[DOTSROA_05_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT4]], i32 1
-; POST-PROCESS-NEXT: [[TMP165:%.*]] = bitcast float [[DOTSROA_05_4_VEC_EXTRACT]] to i32
+; POST-PROCESS-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; POST-PROCESS-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP5:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP18:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP19:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP22:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP23:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP24:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP25:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP27:%.*]] = inttoptr i32 [[TMP26]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP28:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP27]], i32 -30
+; POST-PROCESS-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP28]], i32 0, i32 0, i64 30
+; POST-PROCESS-NEXT: [[TMP30:%.*]] = load i32, ptr addrspace(21) [[TMP29]], align 4
+; POST-PROCESS-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP32:%.*]] = inttoptr i32 [[TMP31]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP33:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP32]], i32 -30
+; POST-PROCESS-NEXT: [[TMP34:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP33]], i32 0, i32 0, i64 31
+; POST-PROCESS-NEXT: [[TMP35:%.*]] = load i32, ptr addrspace(21) [[TMP34]], align 4
+; POST-PROCESS-NEXT: [[TMP36:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP37:%.*]] = inttoptr i32 [[TMP36]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP38:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP37]], i32 -30
+; POST-PROCESS-NEXT: [[TMP39:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP38]], i32 0, i32 0, i64 32
+; POST-PROCESS-NEXT: [[TMP40:%.*]] = load i32, ptr addrspace(21) [[TMP39]], align 4
+; POST-PROCESS-NEXT: [[TMP41:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP42:%.*]] = inttoptr i32 [[TMP41]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP43:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP42]], i32 -30
+; POST-PROCESS-NEXT: [[TMP44:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP43]], i32 0, i32 0, i64 33
+; POST-PROCESS-NEXT: [[TMP45:%.*]] = load i32, ptr addrspace(21) [[TMP44]], align 4
+; POST-PROCESS-NEXT: [[TMP46:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP47:%.*]] = inttoptr i32 [[TMP46]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP48:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP47]], i32 -30
+; POST-PROCESS-NEXT: [[TMP49:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP48]], i32 0, i32 0, i64 34
+; POST-PROCESS-NEXT: [[TMP50:%.*]] = load i32, ptr addrspace(21) [[TMP49]], align 4
+; POST-PROCESS-NEXT: [[TMP51:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP52:%.*]] = inttoptr i32 [[TMP51]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP53:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP52]], i32 -30
+; POST-PROCESS-NEXT: [[TMP54:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP53]], i32 0, i32 0, i64 35
+; POST-PROCESS-NEXT: [[TMP55:%.*]] = load i32, ptr addrspace(21) [[TMP54]], align 4
+; POST-PROCESS-NEXT: [[TMP56:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP57:%.*]] = inttoptr i32 [[TMP56]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP58:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP57]], i32 -30
+; POST-PROCESS-NEXT: [[TMP59:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP58]], i32 0, i32 0, i64 36
+; POST-PROCESS-NEXT: [[TMP60:%.*]] = load i32, ptr addrspace(21) [[TMP59]], align 4
+; POST-PROCESS-NEXT: [[TMP61:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP62:%.*]] = inttoptr i32 [[TMP61]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP63:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP62]], i32 -30
+; POST-PROCESS-NEXT: [[TMP64:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP63]], i32 0, i32 0, i64 37
+; POST-PROCESS-NEXT: [[TMP65:%.*]] = load i32, ptr addrspace(21) [[TMP64]], align 4
+; POST-PROCESS-NEXT: [[TMP66:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP67:%.*]] = inttoptr i32 [[TMP66]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP68:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP67]], i32 -30
+; POST-PROCESS-NEXT: [[TMP69:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP68]], i32 0, i32 0, i64 38
+; POST-PROCESS-NEXT: [[TMP70:%.*]] = load i32, ptr addrspace(21) [[TMP69]], align 4
+; POST-PROCESS-NEXT: [[TMP71:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP72:%.*]] = inttoptr i32 [[TMP71]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP73:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP72]], i32 -30
+; POST-PROCESS-NEXT: [[TMP74:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP73]], i32 0, i32 0, i64 39
+; POST-PROCESS-NEXT: [[TMP75:%.*]] = load i32, ptr addrspace(21) [[TMP74]], align 4
+; POST-PROCESS-NEXT: [[TMP76:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP77:%.*]] = inttoptr i32 [[TMP76]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP78:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP77]], i32 -30
+; POST-PROCESS-NEXT: [[TMP79:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP78]], i32 0, i32 0, i64 40
+; POST-PROCESS-NEXT: [[TMP80:%.*]] = load i32, ptr addrspace(21) [[TMP79]], align 4
+; POST-PROCESS-NEXT: [[TMP81:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP82:%.*]] = inttoptr i32 [[TMP81]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP83:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP82]], i32 -30
+; POST-PROCESS-NEXT: [[TMP84:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP83]], i32 0, i32 0, i64 41
+; POST-PROCESS-NEXT: [[TMP85:%.*]] = load i32, ptr addrspace(21) [[TMP84]], align 4
+; POST-PROCESS-NEXT: [[TMP86:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP87:%.*]] = inttoptr i32 [[TMP86]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP88:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP87]], i32 -30
+; POST-PROCESS-NEXT: [[TMP89:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP88]], i32 0, i32 0, i64 42
+; POST-PROCESS-NEXT: [[TMP90:%.*]] = load i32, ptr addrspace(21) [[TMP89]], align 4
+; POST-PROCESS-NEXT: [[TMP91:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP92:%.*]] = inttoptr i32 [[TMP91]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP93:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP92]], i32 -30
+; POST-PROCESS-NEXT: [[TMP94:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP93]], i32 0, i32 0, i64 43
+; POST-PROCESS-NEXT: [[TMP95:%.*]] = load i32, ptr addrspace(21) [[TMP94]], align 4
+; POST-PROCESS-NEXT: [[TMP96:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP97:%.*]] = inttoptr i32 [[TMP96]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP98:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP97]], i32 -30
+; POST-PROCESS-NEXT: [[TMP99:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP98]], i32 0, i32 0, i64 44
+; POST-PROCESS-NEXT: [[TMP100:%.*]] = load i32, ptr addrspace(21) [[TMP99]], align 4
+; POST-PROCESS-NEXT: [[TMP101:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP102:%.*]] = inttoptr i32 [[TMP101]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP103:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP102]], i32 -30
+; POST-PROCESS-NEXT: [[TMP104:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP103]], i32 0, i32 0, i64 45
+; POST-PROCESS-NEXT: [[TMP105:%.*]] = load i32, ptr addrspace(21) [[TMP104]], align 4
+; POST-PROCESS-NEXT: [[TMP106:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP107:%.*]] = inttoptr i32 [[TMP106]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP108:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP107]], i32 -30
+; POST-PROCESS-NEXT: [[TMP109:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP108]], i32 0, i32 0, i64 46
+; POST-PROCESS-NEXT: [[TMP110:%.*]] = load i32, ptr addrspace(21) [[TMP109]], align 4
+; POST-PROCESS-NEXT: [[TMP111:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP112:%.*]] = inttoptr i32 [[TMP111]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP113:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP112]], i32 -30
+; POST-PROCESS-NEXT: [[TMP114:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP113]], i32 0, i32 0, i64 47
+; POST-PROCESS-NEXT: [[TMP115:%.*]] = load i32, ptr addrspace(21) [[TMP114]], align 4
+; POST-PROCESS-NEXT: [[TMP116:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP117:%.*]] = inttoptr i32 [[TMP116]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP118:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP117]], i32 -30
+; POST-PROCESS-NEXT: [[TMP119:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP118]], i32 0, i32 0, i64 48
+; POST-PROCESS-NEXT: [[TMP120:%.*]] = load i32, ptr addrspace(21) [[TMP119]], align 4
+; POST-PROCESS-NEXT: [[TMP121:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP122:%.*]] = inttoptr i32 [[TMP121]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP123:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP122]], i32 -30
+; POST-PROCESS-NEXT: [[TMP124:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP123]], i32 0, i32 0, i64 49
+; POST-PROCESS-NEXT: [[TMP125:%.*]] = load i32, ptr addrspace(21) [[TMP124]], align 4
+; POST-PROCESS-NEXT: [[TMP126:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP127:%.*]] = inttoptr i32 [[TMP126]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP128:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP127]], i32 -30
+; POST-PROCESS-NEXT: [[TMP129:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP128]], i32 0, i32 0, i64 50
+; POST-PROCESS-NEXT: [[TMP130:%.*]] = load i32, ptr addrspace(21) [[TMP129]], align 4
+; POST-PROCESS-NEXT: [[TMP131:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP132:%.*]] = inttoptr i32 [[TMP131]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP133:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP132]], i32 -30
+; POST-PROCESS-NEXT: [[TMP134:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP133]], i32 0, i32 0, i64 51
+; POST-PROCESS-NEXT: [[TMP135:%.*]] = load i32, ptr addrspace(21) [[TMP134]], align 4
+; POST-PROCESS-NEXT: [[TMP136:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP137:%.*]] = inttoptr i32 [[TMP136]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP138:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP137]], i32 -30
+; POST-PROCESS-NEXT: [[TMP139:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP138]], i32 0, i32 0, i64 52
+; POST-PROCESS-NEXT: [[TMP140:%.*]] = load i32, ptr addrspace(21) [[TMP139]], align 4
+; POST-PROCESS-NEXT: [[TMP141:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP142:%.*]] = inttoptr i32 [[TMP141]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP143:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP142]], i32 -30
+; POST-PROCESS-NEXT: [[TMP144:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP143]], i32 0, i32 0, i64 53
+; POST-PROCESS-NEXT: [[TMP145:%.*]] = load i32, ptr addrspace(21) [[TMP144]], align 4
+; POST-PROCESS-NEXT: [[TMP146:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP147:%.*]] = inttoptr i32 [[TMP146]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP148:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP147]], i32 -30
+; POST-PROCESS-NEXT: [[TMP149:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP148]], i32 0, i32 0, i64 54
+; POST-PROCESS-NEXT: [[TMP150:%.*]] = load i32, ptr addrspace(21) [[TMP149]], align 4
+; POST-PROCESS-NEXT: [[TMP151:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP152:%.*]] = inttoptr i32 [[TMP151]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP153:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP152]], i32 -30
+; POST-PROCESS-NEXT: [[TMP154:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP153]], i32 0, i32 0, i64 55
+; POST-PROCESS-NEXT: [[TMP155:%.*]] = load i32, ptr addrspace(21) [[TMP154]], align 4
+; POST-PROCESS-NEXT: [[TMP156:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP157:%.*]] = inttoptr i32 [[TMP156]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP158:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP157]], i32 -30
+; POST-PROCESS-NEXT: [[TMP159:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(21) [[TMP158]], i32 0, i32 0, i64 56
+; POST-PROCESS-NEXT: [[TMP160:%.*]] = load i32, ptr addrspace(21) [[TMP159]], align 4
+; POST-PROCESS-NEXT: [[TMP161:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; POST-PROCESS-NEXT: [[ADDR_I:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[TMP161]], i32 0, i32 1
+; POST-PROCESS-NEXT: [[VAL_I_FCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[ADDR_I]], i32 0, i32 0
+; POST-PROCESS-NEXT: [[VAL_I_FCA_0_LOAD:%.*]] = load <2 x float>, ptr [[VAL_I_FCA_0_GEP]], align 4
+; POST-PROCESS-NEXT: [[VAL_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] poison, <2 x float> [[VAL_I_FCA_0_LOAD]], 0
+; POST-PROCESS-NEXT: [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[VAL_I_FCA_0_INSERT]], 0
+; POST-PROCESS-NEXT: [[DOTSROA_011_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT]], i32 0
+; POST-PROCESS-NEXT: [[TMP162:%.*]] = bitcast float [[DOTSROA_011_0_VEC_EXTRACT]] to i32
+; POST-PROCESS-NEXT: [[DOTSROA_011_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT]], i32 1
+; POST-PROCESS-NEXT: [[TMP163:%.*]] = bitcast float [[DOTSROA_011_4_VEC_EXTRACT]] to i32
; POST-PROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP1]], 0
+; POST-PROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; POST-PROCESS-NEXT: call void @_cont_AcceptHit(ptr [[SYSTEM_DATA_ALLOCA]])
-; POST-PROCESS-NEXT: store i32 [[TMP4]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP5]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP6]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP7]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP8]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP9]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP10]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP11]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP12]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP13]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP14]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP15]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP16]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP17]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP18]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP19]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP20]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP21]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP22]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP23]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP24]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP25]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP26]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP166:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP167:%.*]] = inttoptr i32 [[TMP166]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP168:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP167]], i32 -30
-; POST-PROCESS-NEXT: [[TMP169:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP168]], i32 0, i32 0, i64 30
-; POST-PROCESS-NEXT: store i32 [[TMP31]], ptr addrspace(21) [[TMP169]], align 4
-; POST-PROCESS-NEXT: [[TMP170:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP171:%.*]] = inttoptr i32 [[TMP170]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP172:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP171]], i32 -30
-; POST-PROCESS-NEXT: [[TMP173:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP172]], i32 0, i32 0, i64 31
-; POST-PROCESS-NEXT: store i32 [[TMP36]], ptr addrspace(21) [[TMP173]], align 4
-; POST-PROCESS-NEXT: [[TMP174:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP175:%.*]] = inttoptr i32 [[TMP174]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP176:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP175]], i32 -30
-; POST-PROCESS-NEXT: [[TMP177:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP176]], i32 0, i32 0, i64 32
-; POST-PROCESS-NEXT: store i32 [[TMP41]], ptr addrspace(21) [[TMP177]], align 4
-; POST-PROCESS-NEXT: [[TMP178:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP179:%.*]] = inttoptr i32 [[TMP178]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP180:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP179]], i32 -30
-; POST-PROCESS-NEXT: [[TMP181:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP180]], i32 0, i32 0, i64 33
-; POST-PROCESS-NEXT: store i32 [[TMP46]], ptr addrspace(21) [[TMP181]], align 4
-; POST-PROCESS-NEXT: [[TMP182:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP183:%.*]] = inttoptr i32 [[TMP182]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP184:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP183]], i32 -30
-; POST-PROCESS-NEXT: [[TMP185:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP184]], i32 0, i32 0, i64 34
-; POST-PROCESS-NEXT: store i32 [[TMP51]], ptr addrspace(21) [[TMP185]], align 4
-; POST-PROCESS-NEXT: [[TMP186:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP187:%.*]] = inttoptr i32 [[TMP186]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP188:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP187]], i32 -30
-; POST-PROCESS-NEXT: [[TMP189:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP188]], i32 0, i32 0, i64 35
-; POST-PROCESS-NEXT: store i32 [[TMP56]], ptr addrspace(21) [[TMP189]], align 4
-; POST-PROCESS-NEXT: [[TMP190:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP191:%.*]] = inttoptr i32 [[TMP190]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP192:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP191]], i32 -30
-; POST-PROCESS-NEXT: [[TMP193:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP192]], i32 0, i32 0, i64 36
-; POST-PROCESS-NEXT: store i32 [[TMP61]], ptr addrspace(21) [[TMP193]], align 4
-; POST-PROCESS-NEXT: [[TMP194:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP195:%.*]] = inttoptr i32 [[TMP194]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP196:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP195]], i32 -30
-; POST-PROCESS-NEXT: [[TMP197:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP196]], i32 0, i32 0, i64 37
-; POST-PROCESS-NEXT: store i32 [[TMP66]], ptr addrspace(21) [[TMP197]], align 4
-; POST-PROCESS-NEXT: [[TMP198:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP199:%.*]] = inttoptr i32 [[TMP198]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP200:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP199]], i32 -30
-; POST-PROCESS-NEXT: [[TMP201:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP200]], i32 0, i32 0, i64 38
-; POST-PROCESS-NEXT: store i32 [[TMP71]], ptr addrspace(21) [[TMP201]], align 4
-; POST-PROCESS-NEXT: [[TMP202:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP203:%.*]] = inttoptr i32 [[TMP202]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP204:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP203]], i32 -30
-; POST-PROCESS-NEXT: [[TMP205:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP204]], i32 0, i32 0, i64 39
-; POST-PROCESS-NEXT: store i32 [[TMP76]], ptr addrspace(21) [[TMP205]], align 4
-; POST-PROCESS-NEXT: [[TMP206:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP207:%.*]] = inttoptr i32 [[TMP206]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP208:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP207]], i32 -30
-; POST-PROCESS-NEXT: [[TMP209:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP208]], i32 0, i32 0, i64 40
-; POST-PROCESS-NEXT: store i32 [[TMP81]], ptr addrspace(21) [[TMP209]], align 4
-; POST-PROCESS-NEXT: [[TMP210:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP211:%.*]] = inttoptr i32 [[TMP210]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP212:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP211]], i32 -30
-; POST-PROCESS-NEXT: [[TMP213:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP212]], i32 0, i32 0, i64 41
-; POST-PROCESS-NEXT: store i32 [[TMP86]], ptr addrspace(21) [[TMP213]], align 4
-; POST-PROCESS-NEXT: [[TMP214:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP215:%.*]] = inttoptr i32 [[TMP214]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP216:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP215]], i32 -30
-; POST-PROCESS-NEXT: [[TMP217:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP216]], i32 0, i32 0, i64 42
-; POST-PROCESS-NEXT: store i32 [[TMP91]], ptr addrspace(21) [[TMP217]], align 4
-; POST-PROCESS-NEXT: [[TMP218:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP219:%.*]] = inttoptr i32 [[TMP218]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP220:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP219]], i32 -30
-; POST-PROCESS-NEXT: [[TMP221:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP220]], i32 0, i32 0, i64 43
-; POST-PROCESS-NEXT: store i32 [[TMP96]], ptr addrspace(21) [[TMP221]], align 4
-; POST-PROCESS-NEXT: [[TMP222:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP223:%.*]] = inttoptr i32 [[TMP222]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP224:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP223]], i32 -30
-; POST-PROCESS-NEXT: [[TMP225:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP224]], i32 0, i32 0, i64 44
-; POST-PROCESS-NEXT: store i32 [[TMP101]], ptr addrspace(21) [[TMP225]], align 4
-; POST-PROCESS-NEXT: [[TMP226:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP227:%.*]] = inttoptr i32 [[TMP226]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP228:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP227]], i32 -30
-; POST-PROCESS-NEXT: [[TMP229:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP228]], i32 0, i32 0, i64 45
-; POST-PROCESS-NEXT: store i32 [[TMP106]], ptr addrspace(21) [[TMP229]], align 4
-; POST-PROCESS-NEXT: [[TMP230:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP231:%.*]] = inttoptr i32 [[TMP230]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP232:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP231]], i32 -30
-; POST-PROCESS-NEXT: [[TMP233:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP232]], i32 0, i32 0, i64 46
-; POST-PROCESS-NEXT: store i32 [[TMP111]], ptr addrspace(21) [[TMP233]], align 4
-; POST-PROCESS-NEXT: [[TMP234:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP235:%.*]] = inttoptr i32 [[TMP234]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP236:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP235]], i32 -30
-; POST-PROCESS-NEXT: [[TMP237:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP236]], i32 0, i32 0, i64 47
-; POST-PROCESS-NEXT: store i32 [[TMP116]], ptr addrspace(21) [[TMP237]], align 4
-; POST-PROCESS-NEXT: [[TMP238:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP239:%.*]] = inttoptr i32 [[TMP238]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP240:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP239]], i32 -30
-; POST-PROCESS-NEXT: [[TMP241:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP240]], i32 0, i32 0, i64 48
-; POST-PROCESS-NEXT: store i32 [[TMP121]], ptr addrspace(21) [[TMP241]], align 4
-; POST-PROCESS-NEXT: [[TMP242:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP243:%.*]] = inttoptr i32 [[TMP242]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP244:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP243]], i32 -30
-; POST-PROCESS-NEXT: [[TMP245:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP244]], i32 0, i32 0, i64 49
-; POST-PROCESS-NEXT: store i32 [[TMP126]], ptr addrspace(21) [[TMP245]], align 4
-; POST-PROCESS-NEXT: [[TMP246:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP247:%.*]] = inttoptr i32 [[TMP246]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP248:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP247]], i32 -30
-; POST-PROCESS-NEXT: [[TMP249:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP248]], i32 0, i32 0, i64 50
-; POST-PROCESS-NEXT: store i32 [[TMP131]], ptr addrspace(21) [[TMP249]], align 4
-; POST-PROCESS-NEXT: [[TMP250:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP251:%.*]] = inttoptr i32 [[TMP250]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP252:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP251]], i32 -30
-; POST-PROCESS-NEXT: [[TMP253:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP252]], i32 0, i32 0, i64 51
-; POST-PROCESS-NEXT: store i32 [[TMP136]], ptr addrspace(21) [[TMP253]], align 4
-; POST-PROCESS-NEXT: [[TMP254:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP255:%.*]] = inttoptr i32 [[TMP254]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP256:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP255]], i32 -30
-; POST-PROCESS-NEXT: [[TMP257:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP256]], i32 0, i32 0, i64 52
-; POST-PROCESS-NEXT: store i32 [[TMP141]], ptr addrspace(21) [[TMP257]], align 4
-; POST-PROCESS-NEXT: [[TMP258:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP259:%.*]] = inttoptr i32 [[TMP258]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP260:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP259]], i32 -30
-; POST-PROCESS-NEXT: [[TMP261:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP260]], i32 0, i32 0, i64 53
-; POST-PROCESS-NEXT: store i32 [[TMP146]], ptr addrspace(21) [[TMP261]], align 4
-; POST-PROCESS-NEXT: [[TMP262:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP263:%.*]] = inttoptr i32 [[TMP262]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP264:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP263]], i32 -30
-; POST-PROCESS-NEXT: [[TMP265:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP264]], i32 0, i32 0, i64 54
-; POST-PROCESS-NEXT: store i32 [[TMP151]], ptr addrspace(21) [[TMP265]], align 4
-; POST-PROCESS-NEXT: [[TMP266:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP267:%.*]] = inttoptr i32 [[TMP266]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP268:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP267]], i32 -30
-; POST-PROCESS-NEXT: [[TMP269:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP268]], i32 0, i32 0, i64 55
-; POST-PROCESS-NEXT: store i32 [[TMP156]], ptr addrspace(21) [[TMP269]], align 4
-; POST-PROCESS-NEXT: [[TMP270:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP271:%.*]] = inttoptr i32 [[TMP270]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP272:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP271]], i32 -30
-; POST-PROCESS-NEXT: [[TMP273:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP272]], i32 0, i32 0, i64 56
-; POST-PROCESS-NEXT: store i32 [[TMP161]], ptr addrspace(21) [[TMP273]], align 4
+; POST-PROCESS-NEXT: store i32 [[TMP3]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP4]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP5]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP6]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP7]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP8]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP9]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP10]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP11]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP12]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP13]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP14]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP15]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP16]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP17]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP18]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP19]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP20]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP21]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP22]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP23]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP24]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP25]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP164:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP165:%.*]] = inttoptr i32 [[TMP164]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP166:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP165]], i32 -30
+; POST-PROCESS-NEXT: [[TMP167:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP166]], i32 0, i32 0, i64 30
+; POST-PROCESS-NEXT: store i32 [[TMP30]], ptr addrspace(21) [[TMP167]], align 4
+; POST-PROCESS-NEXT: [[TMP168:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP169:%.*]] = inttoptr i32 [[TMP168]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP170:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP169]], i32 -30
+; POST-PROCESS-NEXT: [[TMP171:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP170]], i32 0, i32 0, i64 31
+; POST-PROCESS-NEXT: store i32 [[TMP35]], ptr addrspace(21) [[TMP171]], align 4
+; POST-PROCESS-NEXT: [[TMP172:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP173:%.*]] = inttoptr i32 [[TMP172]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP174:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP173]], i32 -30
+; POST-PROCESS-NEXT: [[TMP175:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP174]], i32 0, i32 0, i64 32
+; POST-PROCESS-NEXT: store i32 [[TMP40]], ptr addrspace(21) [[TMP175]], align 4
+; POST-PROCESS-NEXT: [[TMP176:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP177:%.*]] = inttoptr i32 [[TMP176]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP178:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP177]], i32 -30
+; POST-PROCESS-NEXT: [[TMP179:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP178]], i32 0, i32 0, i64 33
+; POST-PROCESS-NEXT: store i32 [[TMP45]], ptr addrspace(21) [[TMP179]], align 4
+; POST-PROCESS-NEXT: [[TMP180:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP181:%.*]] = inttoptr i32 [[TMP180]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP182:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP181]], i32 -30
+; POST-PROCESS-NEXT: [[TMP183:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP182]], i32 0, i32 0, i64 34
+; POST-PROCESS-NEXT: store i32 [[TMP50]], ptr addrspace(21) [[TMP183]], align 4
+; POST-PROCESS-NEXT: [[TMP184:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP185:%.*]] = inttoptr i32 [[TMP184]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP186:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP185]], i32 -30
+; POST-PROCESS-NEXT: [[TMP187:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP186]], i32 0, i32 0, i64 35
+; POST-PROCESS-NEXT: store i32 [[TMP55]], ptr addrspace(21) [[TMP187]], align 4
+; POST-PROCESS-NEXT: [[TMP188:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP189:%.*]] = inttoptr i32 [[TMP188]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP190:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP189]], i32 -30
+; POST-PROCESS-NEXT: [[TMP191:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP190]], i32 0, i32 0, i64 36
+; POST-PROCESS-NEXT: store i32 [[TMP60]], ptr addrspace(21) [[TMP191]], align 4
+; POST-PROCESS-NEXT: [[TMP192:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP193:%.*]] = inttoptr i32 [[TMP192]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP194:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP193]], i32 -30
+; POST-PROCESS-NEXT: [[TMP195:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP194]], i32 0, i32 0, i64 37
+; POST-PROCESS-NEXT: store i32 [[TMP65]], ptr addrspace(21) [[TMP195]], align 4
+; POST-PROCESS-NEXT: [[TMP196:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP197:%.*]] = inttoptr i32 [[TMP196]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP198:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP197]], i32 -30
+; POST-PROCESS-NEXT: [[TMP199:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP198]], i32 0, i32 0, i64 38
+; POST-PROCESS-NEXT: store i32 [[TMP70]], ptr addrspace(21) [[TMP199]], align 4
+; POST-PROCESS-NEXT: [[TMP200:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP201:%.*]] = inttoptr i32 [[TMP200]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP202:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP201]], i32 -30
+; POST-PROCESS-NEXT: [[TMP203:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP202]], i32 0, i32 0, i64 39
+; POST-PROCESS-NEXT: store i32 [[TMP75]], ptr addrspace(21) [[TMP203]], align 4
+; POST-PROCESS-NEXT: [[TMP204:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP205:%.*]] = inttoptr i32 [[TMP204]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP206:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP205]], i32 -30
+; POST-PROCESS-NEXT: [[TMP207:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP206]], i32 0, i32 0, i64 40
+; POST-PROCESS-NEXT: store i32 [[TMP80]], ptr addrspace(21) [[TMP207]], align 4
+; POST-PROCESS-NEXT: [[TMP208:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP209:%.*]] = inttoptr i32 [[TMP208]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP210:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP209]], i32 -30
+; POST-PROCESS-NEXT: [[TMP211:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP210]], i32 0, i32 0, i64 41
+; POST-PROCESS-NEXT: store i32 [[TMP85]], ptr addrspace(21) [[TMP211]], align 4
+; POST-PROCESS-NEXT: [[TMP212:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP213:%.*]] = inttoptr i32 [[TMP212]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP214:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP213]], i32 -30
+; POST-PROCESS-NEXT: [[TMP215:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP214]], i32 0, i32 0, i64 42
+; POST-PROCESS-NEXT: store i32 [[TMP90]], ptr addrspace(21) [[TMP215]], align 4
+; POST-PROCESS-NEXT: [[TMP216:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP217:%.*]] = inttoptr i32 [[TMP216]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP218:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP217]], i32 -30
+; POST-PROCESS-NEXT: [[TMP219:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP218]], i32 0, i32 0, i64 43
+; POST-PROCESS-NEXT: store i32 [[TMP95]], ptr addrspace(21) [[TMP219]], align 4
+; POST-PROCESS-NEXT: [[TMP220:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP221:%.*]] = inttoptr i32 [[TMP220]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP222:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP221]], i32 -30
+; POST-PROCESS-NEXT: [[TMP223:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP222]], i32 0, i32 0, i64 44
+; POST-PROCESS-NEXT: store i32 [[TMP100]], ptr addrspace(21) [[TMP223]], align 4
+; POST-PROCESS-NEXT: [[TMP224:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP225:%.*]] = inttoptr i32 [[TMP224]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP226:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP225]], i32 -30
+; POST-PROCESS-NEXT: [[TMP227:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP226]], i32 0, i32 0, i64 45
+; POST-PROCESS-NEXT: store i32 [[TMP105]], ptr addrspace(21) [[TMP227]], align 4
+; POST-PROCESS-NEXT: [[TMP228:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP229:%.*]] = inttoptr i32 [[TMP228]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP230:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP229]], i32 -30
+; POST-PROCESS-NEXT: [[TMP231:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP230]], i32 0, i32 0, i64 46
+; POST-PROCESS-NEXT: store i32 [[TMP110]], ptr addrspace(21) [[TMP231]], align 4
+; POST-PROCESS-NEXT: [[TMP232:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP233:%.*]] = inttoptr i32 [[TMP232]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP234:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP233]], i32 -30
+; POST-PROCESS-NEXT: [[TMP235:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP234]], i32 0, i32 0, i64 47
+; POST-PROCESS-NEXT: store i32 [[TMP115]], ptr addrspace(21) [[TMP235]], align 4
+; POST-PROCESS-NEXT: [[TMP236:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP237:%.*]] = inttoptr i32 [[TMP236]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP238:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP237]], i32 -30
+; POST-PROCESS-NEXT: [[TMP239:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP238]], i32 0, i32 0, i64 48
+; POST-PROCESS-NEXT: store i32 [[TMP120]], ptr addrspace(21) [[TMP239]], align 4
+; POST-PROCESS-NEXT: [[TMP240:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP241:%.*]] = inttoptr i32 [[TMP240]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP242:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP241]], i32 -30
+; POST-PROCESS-NEXT: [[TMP243:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP242]], i32 0, i32 0, i64 49
+; POST-PROCESS-NEXT: store i32 [[TMP125]], ptr addrspace(21) [[TMP243]], align 4
+; POST-PROCESS-NEXT: [[TMP244:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP245:%.*]] = inttoptr i32 [[TMP244]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP246:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP245]], i32 -30
+; POST-PROCESS-NEXT: [[TMP247:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP246]], i32 0, i32 0, i64 50
+; POST-PROCESS-NEXT: store i32 [[TMP130]], ptr addrspace(21) [[TMP247]], align 4
+; POST-PROCESS-NEXT: [[TMP248:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP249:%.*]] = inttoptr i32 [[TMP248]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP250:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP249]], i32 -30
+; POST-PROCESS-NEXT: [[TMP251:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP250]], i32 0, i32 0, i64 51
+; POST-PROCESS-NEXT: store i32 [[TMP135]], ptr addrspace(21) [[TMP251]], align 4
+; POST-PROCESS-NEXT: [[TMP252:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP253:%.*]] = inttoptr i32 [[TMP252]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP254:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP253]], i32 -30
+; POST-PROCESS-NEXT: [[TMP255:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP254]], i32 0, i32 0, i64 52
+; POST-PROCESS-NEXT: store i32 [[TMP140]], ptr addrspace(21) [[TMP255]], align 4
+; POST-PROCESS-NEXT: [[TMP256:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP257:%.*]] = inttoptr i32 [[TMP256]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP258:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP257]], i32 -30
+; POST-PROCESS-NEXT: [[TMP259:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP258]], i32 0, i32 0, i64 53
+; POST-PROCESS-NEXT: store i32 [[TMP145]], ptr addrspace(21) [[TMP259]], align 4
+; POST-PROCESS-NEXT: [[TMP260:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP261:%.*]] = inttoptr i32 [[TMP260]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP262:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP261]], i32 -30
+; POST-PROCESS-NEXT: [[TMP263:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP262]], i32 0, i32 0, i64 54
+; POST-PROCESS-NEXT: store i32 [[TMP150]], ptr addrspace(21) [[TMP263]], align 4
+; POST-PROCESS-NEXT: [[TMP264:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP265:%.*]] = inttoptr i32 [[TMP264]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP266:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP265]], i32 -30
+; POST-PROCESS-NEXT: [[TMP267:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP266]], i32 0, i32 0, i64 55
+; POST-PROCESS-NEXT: store i32 [[TMP155]], ptr addrspace(21) [[TMP267]], align 4
+; POST-PROCESS-NEXT: [[TMP268:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP269:%.*]] = inttoptr i32 [[TMP268]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP270:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP269]], i32 -30
+; POST-PROCESS-NEXT: [[TMP271:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP270]], i32 0, i32 0, i64 56
+; POST-PROCESS-NEXT: store i32 [[TMP160]], ptr addrspace(21) [[TMP271]], align 4
; POST-PROCESS-NEXT: [[HITATTRSALLOCA_SROA_0_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT]], i32 0
-; POST-PROCESS-NEXT: [[TMP274:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_0_VEC_EXTRACT]] to i32
-; POST-PROCESS-NEXT: [[TMP275:%.*]] = bitcast i32 [[TMP274]] to float
-; POST-PROCESS-NEXT: [[DOTSROA_06_0_VEC_INSERT:%.*]] = insertelement <2 x float> undef, float [[TMP275]], i32 0
+; POST-PROCESS-NEXT: [[TMP272:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_0_VEC_EXTRACT]] to i32
+; POST-PROCESS-NEXT: [[TMP273:%.*]] = bitcast i32 [[TMP272]] to float
+; POST-PROCESS-NEXT: [[DOTSROA_012_0_VEC_INSERT:%.*]] = insertelement <2 x float> undef, float [[TMP273]], i32 0
; POST-PROCESS-NEXT: [[HITATTRSALLOCA_SROA_0_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT]], i32 1
-; POST-PROCESS-NEXT: [[TMP276:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_4_VEC_EXTRACT]] to i32
-; POST-PROCESS-NEXT: [[TMP277:%.*]] = bitcast i32 [[TMP276]] to float
-; POST-PROCESS-NEXT: [[DOTSROA_06_4_VEC_INSERT:%.*]] = insertelement <2 x float> [[DOTSROA_06_0_VEC_INSERT]], float [[TMP277]], i32 1
-; POST-PROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] poison, <2 x float> [[DOTSROA_06_4_VEC_INSERT]], 0
-; POST-PROCESS-NEXT: [[TMP278:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; POST-PROCESS-NEXT: call void @_cont_SetTriangleHitAttributes(ptr [[TMP278]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_INSERT]])
+; POST-PROCESS-NEXT: [[TMP274:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_4_VEC_EXTRACT]] to i32
+; POST-PROCESS-NEXT: [[TMP275:%.*]] = bitcast i32 [[TMP274]] to float
+; POST-PROCESS-NEXT: [[DOTSROA_012_4_VEC_INSERT:%.*]] = insertelement <2 x float> [[DOTSROA_012_0_VEC_INSERT]], float [[TMP275]], i32 1
+; POST-PROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] poison, <2 x float> [[DOTSROA_012_4_VEC_INSERT]], 0
+; POST-PROCESS-NEXT: [[TMP276:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; POST-PROCESS-NEXT: call void @_cont_SetTriangleHitAttributes(ptr [[TMP276]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_INSERT]])
; POST-PROCESS-NEXT: [[DOTFCA_0_0_0_0_GEP1:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0, i32 0
-; POST-PROCESS-NEXT: [[DOTFCA_0_0_0_0_LOAD:%.*]] = load i32, ptr [[DOTFCA_0_0_0_0_GEP1]], align 4
-; POST-PROCESS-NEXT: [[DOTFCA_0_0_0_0_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] poison, i32 [[DOTFCA_0_0_0_0_LOAD]], 0, 0, 0, 0
-; POST-PROCESS-NEXT: [[DOTFCA_1_0_GEP2:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 0
-; POST-PROCESS-NEXT: [[DOTFCA_1_0_LOAD:%.*]] = load float, ptr [[DOTFCA_1_0_GEP2]], align 4
-; POST-PROCESS-NEXT: [[DOTFCA_1_0_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_0_0_0_INSERT]], float [[DOTFCA_1_0_LOAD]], 1, 0
-; POST-PROCESS-NEXT: [[DOTFCA_1_1_GEP3:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 1
-; POST-PROCESS-NEXT: [[DOTFCA_1_1_LOAD:%.*]] = load i32, ptr [[DOTFCA_1_1_GEP3]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_0_0_0_LOAD:%.*]] = load <3 x i32>, ptr [[DOTFCA_0_0_0_0_GEP1]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_0_0_0_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] poison, <3 x i32> [[DOTFCA_0_0_0_0_LOAD]], 0, 0, 0, 0
+; POST-PROCESS-NEXT: [[DOTFCA_0_0_1_0_GEP2:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 1, i32 0
+; POST-PROCESS-NEXT: [[DOTFCA_0_0_1_0_LOAD:%.*]] = load <2 x float>, ptr [[DOTFCA_0_0_1_0_GEP2]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_0_1_0_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_0_0_0_INSERT]], <2 x float> [[DOTFCA_0_0_1_0_LOAD]], 0, 0, 1, 0
+; POST-PROCESS-NEXT: [[DOTFCA_0_1_0_GEP3:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 1, i32 0
+; POST-PROCESS-NEXT: [[DOTFCA_0_1_0_LOAD:%.*]] = load float, ptr [[DOTFCA_0_1_0_GEP3]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_1_0_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_0_1_0_INSERT]], float [[DOTFCA_0_1_0_LOAD]], 0, 1, 0
+; POST-PROCESS-NEXT: [[DOTFCA_0_1_1_GEP4:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 1, i32 1
+; POST-PROCESS-NEXT: [[DOTFCA_0_1_1_LOAD:%.*]] = load i32, ptr [[DOTFCA_0_1_1_GEP4]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_1_1_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_1_0_INSERT]], i32 [[DOTFCA_0_1_1_LOAD]], 0, 1, 1
+; POST-PROCESS-NEXT: [[DOTFCA_0_2_GEP5:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 2
+; POST-PROCESS-NEXT: [[DOTFCA_0_2_LOAD:%.*]] = load <3 x float>, ptr [[DOTFCA_0_2_GEP5]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_1_1_INSERT]], <3 x float> [[DOTFCA_0_2_LOAD]], 0, 2
+; POST-PROCESS-NEXT: [[DOTFCA_0_3_GEP6:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 3
+; POST-PROCESS-NEXT: [[DOTFCA_0_3_LOAD:%.*]] = load <3 x float>, ptr [[DOTFCA_0_3_GEP6]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_3_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_2_INSERT]], <3 x float> [[DOTFCA_0_3_LOAD]], 0, 3
+; POST-PROCESS-NEXT: [[DOTFCA_0_4_GEP7:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_4_LOAD:%.*]] = load float, ptr [[DOTFCA_0_4_GEP7]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_4_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_3_INSERT]], float [[DOTFCA_0_4_LOAD]], 0, 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_5_GEP8:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 5
+; POST-PROCESS-NEXT: [[DOTFCA_0_5_LOAD:%.*]] = load i64, ptr [[DOTFCA_0_5_GEP8]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_5_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_4_INSERT]], i64 [[DOTFCA_0_5_LOAD]], 0, 5
+; POST-PROCESS-NEXT: [[DOTFCA_1_0_GEP9:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 0
+; POST-PROCESS-NEXT: [[DOTFCA_1_0_LOAD:%.*]] = load float, ptr [[DOTFCA_1_0_GEP9]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_1_0_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_5_INSERT]], float [[DOTFCA_1_0_LOAD]], 1, 0
+; POST-PROCESS-NEXT: [[DOTFCA_1_1_GEP10:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 1
+; POST-PROCESS-NEXT: [[DOTFCA_1_1_LOAD:%.*]] = load i32, ptr [[DOTFCA_1_1_GEP10]], align 4
; POST-PROCESS-NEXT: [[DOTFCA_1_1_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_1_0_INSERT]], i32 [[DOTFCA_1_1_LOAD]], 1, 1
-; POST-PROCESS-NEXT: [[TMP279:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP279]], [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_1_1_INSERT]]), !continuation.registercount !17
+; POST-PROCESS-NEXT: [[TMP277:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP277]], [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_1_1_INSERT]]), !continuation.registercount [[META17]]
; POST-PROCESS-NEXT: unreachable
;
;
; POST-PROCESS-LABEL: define void @ClosestHit(
-; POST-PROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR2]] !lgc.rt.shaderstage !24 !continuation.registercount !17 !continuation !25 !continuation.stacksize !26 !continuation.state !27 {
+; POST-PROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR2]] !lgc.rt.shaderstage [[META24:![0-9]+]] !continuation.registercount [[META17]] !continuation [[META25:![0-9]+]] !continuation.stacksize [[META26:![0-9]+]] !continuation.state [[META27:![0-9]+]] {
; POST-PROCESS-NEXT: AllocaSpillBB:
-; POST-PROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
-; POST-PROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [4 x i32], align 4
; POST-PROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; POST-PROCESS-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
; POST-PROCESS-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME]], ptr [[CONT_STATE]], i32 0, i32 1
-; POST-PROCESS-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
-; POST-PROCESS-NEXT: [[TMP1:%.*]] = load [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA]], align 4
-; POST-PROCESS-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP1]], 0, 0
-; POST-PROCESS-NEXT: [[DOTFCA_0_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; POST-PROCESS-NEXT: store i32 [[DOTFCA_0_0_EXTRACT]], ptr [[DOTFCA_0_0_GEP]], align 4
-; POST-PROCESS-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; POST-PROCESS-NEXT: [[TMP1:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP2]], i64 108
+; POST-PROCESS-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME:%.*]], ptr addrspace(21) [[TMP3]], i32 0, i32 0
+; POST-PROCESS-NEXT: store i64 [[RETURNADDR]], ptr addrspace(21) [[RETURNADDR_SPILL_ADDR]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP0]], 0, 0
+; POST-PROCESS-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP0]], 1, 0
+; POST-PROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], 108
+; POST-PROCESS-NEXT: store i32 [[TMP5]], ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP18:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP19:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP22:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP23:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP24:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP25:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP27:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP28:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP29:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP30:%.*]] = inttoptr i32 [[TMP29]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP31:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP30]], i32 -30
+; POST-PROCESS-NEXT: [[TMP32:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP31]], i32 0, i32 0, i64 30
+; POST-PROCESS-NEXT: [[TMP33:%.*]] = load i32, ptr addrspace(21) [[TMP32]], align 4
+; POST-PROCESS-NEXT: [[TMP34:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP35:%.*]] = inttoptr i32 [[TMP34]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP36:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP35]], i32 -30
+; POST-PROCESS-NEXT: [[TMP37:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP36]], i32 0, i32 0, i64 31
+; POST-PROCESS-NEXT: [[TMP38:%.*]] = load i32, ptr addrspace(21) [[TMP37]], align 4
+; POST-PROCESS-NEXT: [[TMP39:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP40:%.*]] = inttoptr i32 [[TMP39]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP41:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP40]], i32 -30
+; POST-PROCESS-NEXT: [[TMP42:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP41]], i32 0, i32 0, i64 32
+; POST-PROCESS-NEXT: [[TMP43:%.*]] = load i32, ptr addrspace(21) [[TMP42]], align 4
+; POST-PROCESS-NEXT: [[TMP44:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP45:%.*]] = inttoptr i32 [[TMP44]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP46:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP45]], i32 -30
+; POST-PROCESS-NEXT: [[TMP47:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP46]], i32 0, i32 0, i64 33
+; POST-PROCESS-NEXT: [[TMP48:%.*]] = load i32, ptr addrspace(21) [[TMP47]], align 4
+; POST-PROCESS-NEXT: [[TMP49:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP50:%.*]] = inttoptr i32 [[TMP49]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP51:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP50]], i32 -30
+; POST-PROCESS-NEXT: [[TMP52:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP51]], i32 0, i32 0, i64 34
+; POST-PROCESS-NEXT: [[TMP53:%.*]] = load i32, ptr addrspace(21) [[TMP52]], align 4
+; POST-PROCESS-NEXT: [[TMP54:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP55:%.*]] = inttoptr i32 [[TMP54]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP56:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP55]], i32 -30
+; POST-PROCESS-NEXT: [[TMP57:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP56]], i32 0, i32 0, i64 35
+; POST-PROCESS-NEXT: [[TMP58:%.*]] = load i32, ptr addrspace(21) [[TMP57]], align 4
+; POST-PROCESS-NEXT: [[TMP59:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP60:%.*]] = inttoptr i32 [[TMP59]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP61:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP60]], i32 -30
+; POST-PROCESS-NEXT: [[TMP62:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP61]], i32 0, i32 0, i64 36
+; POST-PROCESS-NEXT: [[TMP63:%.*]] = load i32, ptr addrspace(21) [[TMP62]], align 4
+; POST-PROCESS-NEXT: [[TMP64:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP65:%.*]] = inttoptr i32 [[TMP64]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP66:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP65]], i32 -30
+; POST-PROCESS-NEXT: [[TMP67:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP66]], i32 0, i32 0, i64 37
+; POST-PROCESS-NEXT: [[TMP68:%.*]] = load i32, ptr addrspace(21) [[TMP67]], align 4
+; POST-PROCESS-NEXT: [[TMP69:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP70:%.*]] = inttoptr i32 [[TMP69]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP71:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP70]], i32 -30
+; POST-PROCESS-NEXT: [[TMP72:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP71]], i32 0, i32 0, i64 38
+; POST-PROCESS-NEXT: [[TMP73:%.*]] = load i32, ptr addrspace(21) [[TMP72]], align 4
+; POST-PROCESS-NEXT: [[TMP74:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP75:%.*]] = inttoptr i32 [[TMP74]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP76:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP75]], i32 -30
+; POST-PROCESS-NEXT: [[TMP77:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP76]], i32 0, i32 0, i64 39
+; POST-PROCESS-NEXT: [[TMP78:%.*]] = load i32, ptr addrspace(21) [[TMP77]], align 4
+; POST-PROCESS-NEXT: [[TMP79:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP80:%.*]] = inttoptr i32 [[TMP79]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP81:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP80]], i32 -30
+; POST-PROCESS-NEXT: [[TMP82:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP81]], i32 0, i32 0, i64 40
+; POST-PROCESS-NEXT: [[TMP83:%.*]] = load i32, ptr addrspace(21) [[TMP82]], align 4
+; POST-PROCESS-NEXT: [[TMP84:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP85:%.*]] = inttoptr i32 [[TMP84]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP86:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP85]], i32 -30
+; POST-PROCESS-NEXT: [[TMP87:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP86]], i32 0, i32 0, i64 41
+; POST-PROCESS-NEXT: [[TMP88:%.*]] = load i32, ptr addrspace(21) [[TMP87]], align 4
+; POST-PROCESS-NEXT: [[TMP89:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP90:%.*]] = inttoptr i32 [[TMP89]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP91:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP90]], i32 -30
+; POST-PROCESS-NEXT: [[TMP92:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP91]], i32 0, i32 0, i64 42
+; POST-PROCESS-NEXT: [[TMP93:%.*]] = load i32, ptr addrspace(21) [[TMP92]], align 4
+; POST-PROCESS-NEXT: [[TMP94:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP95:%.*]] = inttoptr i32 [[TMP94]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP96:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP95]], i32 -30
+; POST-PROCESS-NEXT: [[TMP97:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP96]], i32 0, i32 0, i64 43
+; POST-PROCESS-NEXT: [[TMP98:%.*]] = load i32, ptr addrspace(21) [[TMP97]], align 4
+; POST-PROCESS-NEXT: [[TMP99:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP100:%.*]] = inttoptr i32 [[TMP99]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP101:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP100]], i32 -30
+; POST-PROCESS-NEXT: [[TMP102:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP101]], i32 0, i32 0, i64 44
+; POST-PROCESS-NEXT: [[TMP103:%.*]] = load i32, ptr addrspace(21) [[TMP102]], align 4
+; POST-PROCESS-NEXT: [[TMP104:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP105:%.*]] = inttoptr i32 [[TMP104]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP106:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP105]], i32 -30
+; POST-PROCESS-NEXT: [[TMP107:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP106]], i32 0, i32 0, i64 45
+; POST-PROCESS-NEXT: [[TMP108:%.*]] = load i32, ptr addrspace(21) [[TMP107]], align 4
+; POST-PROCESS-NEXT: [[TMP109:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP110:%.*]] = inttoptr i32 [[TMP109]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP111:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP110]], i32 -30
+; POST-PROCESS-NEXT: [[TMP112:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP111]], i32 0, i32 0, i64 46
+; POST-PROCESS-NEXT: [[TMP113:%.*]] = load i32, ptr addrspace(21) [[TMP112]], align 4
+; POST-PROCESS-NEXT: [[TMP114:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP115:%.*]] = inttoptr i32 [[TMP114]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP116:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP115]], i32 -30
+; POST-PROCESS-NEXT: [[TMP117:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP116]], i32 0, i32 0, i64 47
+; POST-PROCESS-NEXT: [[TMP118:%.*]] = load i32, ptr addrspace(21) [[TMP117]], align 4
+; POST-PROCESS-NEXT: [[TMP119:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP120:%.*]] = inttoptr i32 [[TMP119]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP121:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP120]], i32 -30
+; POST-PROCESS-NEXT: [[TMP122:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP121]], i32 0, i32 0, i64 48
+; POST-PROCESS-NEXT: [[TMP123:%.*]] = load i32, ptr addrspace(21) [[TMP122]], align 4
+; POST-PROCESS-NEXT: [[TMP124:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP125:%.*]] = inttoptr i32 [[TMP124]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP126:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP125]], i32 -30
+; POST-PROCESS-NEXT: [[TMP127:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP126]], i32 0, i32 0, i64 49
+; POST-PROCESS-NEXT: [[TMP128:%.*]] = load i32, ptr addrspace(21) [[TMP127]], align 4
+; POST-PROCESS-NEXT: [[TMP129:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP130:%.*]] = inttoptr i32 [[TMP129]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP131:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP130]], i32 -30
+; POST-PROCESS-NEXT: [[TMP132:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP131]], i32 0, i32 0, i64 50
+; POST-PROCESS-NEXT: [[TMP133:%.*]] = load i32, ptr addrspace(21) [[TMP132]], align 4
+; POST-PROCESS-NEXT: [[TMP134:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP135:%.*]] = inttoptr i32 [[TMP134]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP136:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP135]], i32 -30
+; POST-PROCESS-NEXT: [[TMP137:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP136]], i32 0, i32 0, i64 51
+; POST-PROCESS-NEXT: [[TMP138:%.*]] = load i32, ptr addrspace(21) [[TMP137]], align 4
+; POST-PROCESS-NEXT: [[TMP139:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP140:%.*]] = inttoptr i32 [[TMP139]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP141:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP140]], i32 -30
+; POST-PROCESS-NEXT: [[TMP142:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP141]], i32 0, i32 0, i64 52
+; POST-PROCESS-NEXT: [[TMP143:%.*]] = load i32, ptr addrspace(21) [[TMP142]], align 4
+; POST-PROCESS-NEXT: [[TMP144:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP145:%.*]] = inttoptr i32 [[TMP144]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP146:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP145]], i32 -30
+; POST-PROCESS-NEXT: [[TMP147:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP146]], i32 0, i32 0, i64 53
+; POST-PROCESS-NEXT: [[TMP148:%.*]] = load i32, ptr addrspace(21) [[TMP147]], align 4
+; POST-PROCESS-NEXT: [[TMP149:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP150:%.*]] = inttoptr i32 [[TMP149]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP151:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP150]], i32 -30
+; POST-PROCESS-NEXT: [[TMP152:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP151]], i32 0, i32 0, i64 54
+; POST-PROCESS-NEXT: [[TMP153:%.*]] = load i32, ptr addrspace(21) [[TMP152]], align 4
+; POST-PROCESS-NEXT: [[TMP154:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP155:%.*]] = inttoptr i32 [[TMP154]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP156:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP155]], i32 -30
+; POST-PROCESS-NEXT: [[TMP157:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP156]], i32 0, i32 0, i64 55
+; POST-PROCESS-NEXT: [[TMP158:%.*]] = load i32, ptr addrspace(21) [[TMP157]], align 4
+; POST-PROCESS-NEXT: [[TMP159:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP160:%.*]] = inttoptr i32 [[TMP159]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP161:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP160]], i32 -30
+; POST-PROCESS-NEXT: [[TMP162:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP161]], i32 0, i32 0, i64 56
+; POST-PROCESS-NEXT: [[TMP163:%.*]] = load i32, ptr addrspace(21) [[TMP162]], align 4
+; POST-PROCESS-NEXT: [[TMP164:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[DOTSPILL_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME]], ptr addrspace(21) [[TMP3]], i32 0, i32 1
+; POST-PROCESS-NEXT: store i32 [[TMP164]], ptr addrspace(21) [[DOTSPILL_ADDR]], align 4
+; POST-PROCESS-NEXT: [[VAL_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] poison, <2 x float> [[DOTFCA_1_0_EXTRACT]], 0
+; POST-PROCESS-NEXT: [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[VAL_I_FCA_0_INSERT]], 0
+; POST-PROCESS-NEXT: [[DOTSROA_053_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT]], i32 0
+; POST-PROCESS-NEXT: [[TMP165:%.*]] = bitcast float [[DOTSROA_053_0_VEC_EXTRACT]] to i32
+; POST-PROCESS-NEXT: [[DOTSROA_053_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT]], i32 1
+; POST-PROCESS-NEXT: [[TMP166:%.*]] = bitcast float [[DOTSROA_053_4_VEC_EXTRACT]] to i32
; POST-PROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; POST-PROCESS-NEXT: [[TMP3:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], 108
-; POST-PROCESS-NEXT: store i32 [[TMP4]], ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP5:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP18:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP19:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP22:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP23:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP24:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP25:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP27:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP28:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP29:%.*]] = inttoptr i32 [[TMP28]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP30:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP29]], i32 -30
-; POST-PROCESS-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP30]], i32 0, i32 0, i64 30
-; POST-PROCESS-NEXT: [[TMP32:%.*]] = load i32, ptr addrspace(21) [[TMP31]], align 4
-; POST-PROCESS-NEXT: [[TMP33:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP34:%.*]] = inttoptr i32 [[TMP33]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP35:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP34]], i32 -30
-; POST-PROCESS-NEXT: [[TMP36:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP35]], i32 0, i32 0, i64 31
-; POST-PROCESS-NEXT: [[TMP37:%.*]] = load i32, ptr addrspace(21) [[TMP36]], align 4
-; POST-PROCESS-NEXT: [[TMP38:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP39:%.*]] = inttoptr i32 [[TMP38]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP40:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP39]], i32 -30
-; POST-PROCESS-NEXT: [[TMP41:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP40]], i32 0, i32 0, i64 32
-; POST-PROCESS-NEXT: [[TMP42:%.*]] = load i32, ptr addrspace(21) [[TMP41]], align 4
-; POST-PROCESS-NEXT: [[TMP43:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP44:%.*]] = inttoptr i32 [[TMP43]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP45:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP44]], i32 -30
-; POST-PROCESS-NEXT: [[TMP46:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP45]], i32 0, i32 0, i64 33
-; POST-PROCESS-NEXT: [[TMP47:%.*]] = load i32, ptr addrspace(21) [[TMP46]], align 4
-; POST-PROCESS-NEXT: [[TMP48:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP49:%.*]] = inttoptr i32 [[TMP48]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP50:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP49]], i32 -30
-; POST-PROCESS-NEXT: [[TMP51:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP50]], i32 0, i32 0, i64 34
-; POST-PROCESS-NEXT: [[TMP52:%.*]] = load i32, ptr addrspace(21) [[TMP51]], align 4
-; POST-PROCESS-NEXT: [[TMP53:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP54:%.*]] = inttoptr i32 [[TMP53]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP55:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP54]], i32 -30
-; POST-PROCESS-NEXT: [[TMP56:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP55]], i32 0, i32 0, i64 35
-; POST-PROCESS-NEXT: [[TMP57:%.*]] = load i32, ptr addrspace(21) [[TMP56]], align 4
-; POST-PROCESS-NEXT: [[TMP58:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP59:%.*]] = inttoptr i32 [[TMP58]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP60:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP59]], i32 -30
-; POST-PROCESS-NEXT: [[TMP61:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP60]], i32 0, i32 0, i64 36
-; POST-PROCESS-NEXT: [[TMP62:%.*]] = load i32, ptr addrspace(21) [[TMP61]], align 4
-; POST-PROCESS-NEXT: [[TMP63:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP64:%.*]] = inttoptr i32 [[TMP63]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP65:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP64]], i32 -30
-; POST-PROCESS-NEXT: [[TMP66:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP65]], i32 0, i32 0, i64 37
-; POST-PROCESS-NEXT: [[TMP67:%.*]] = load i32, ptr addrspace(21) [[TMP66]], align 4
-; POST-PROCESS-NEXT: [[TMP68:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP69:%.*]] = inttoptr i32 [[TMP68]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP70:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP69]], i32 -30
-; POST-PROCESS-NEXT: [[TMP71:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP70]], i32 0, i32 0, i64 38
-; POST-PROCESS-NEXT: [[TMP72:%.*]] = load i32, ptr addrspace(21) [[TMP71]], align 4
-; POST-PROCESS-NEXT: [[TMP73:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP74:%.*]] = inttoptr i32 [[TMP73]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP75:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP74]], i32 -30
-; POST-PROCESS-NEXT: [[TMP76:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP75]], i32 0, i32 0, i64 39
-; POST-PROCESS-NEXT: [[TMP77:%.*]] = load i32, ptr addrspace(21) [[TMP76]], align 4
-; POST-PROCESS-NEXT: [[TMP78:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP79:%.*]] = inttoptr i32 [[TMP78]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP80:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP79]], i32 -30
-; POST-PROCESS-NEXT: [[TMP81:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP80]], i32 0, i32 0, i64 40
-; POST-PROCESS-NEXT: [[TMP82:%.*]] = load i32, ptr addrspace(21) [[TMP81]], align 4
-; POST-PROCESS-NEXT: [[TMP83:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP84:%.*]] = inttoptr i32 [[TMP83]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP85:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP84]], i32 -30
-; POST-PROCESS-NEXT: [[TMP86:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP85]], i32 0, i32 0, i64 41
-; POST-PROCESS-NEXT: [[TMP87:%.*]] = load i32, ptr addrspace(21) [[TMP86]], align 4
-; POST-PROCESS-NEXT: [[TMP88:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP89:%.*]] = inttoptr i32 [[TMP88]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP90:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP89]], i32 -30
-; POST-PROCESS-NEXT: [[TMP91:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP90]], i32 0, i32 0, i64 42
-; POST-PROCESS-NEXT: [[TMP92:%.*]] = load i32, ptr addrspace(21) [[TMP91]], align 4
-; POST-PROCESS-NEXT: [[TMP93:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP94:%.*]] = inttoptr i32 [[TMP93]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP95:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP94]], i32 -30
-; POST-PROCESS-NEXT: [[TMP96:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP95]], i32 0, i32 0, i64 43
-; POST-PROCESS-NEXT: [[TMP97:%.*]] = load i32, ptr addrspace(21) [[TMP96]], align 4
-; POST-PROCESS-NEXT: [[TMP98:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP99:%.*]] = inttoptr i32 [[TMP98]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP100:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP99]], i32 -30
-; POST-PROCESS-NEXT: [[TMP101:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP100]], i32 0, i32 0, i64 44
-; POST-PROCESS-NEXT: [[TMP102:%.*]] = load i32, ptr addrspace(21) [[TMP101]], align 4
-; POST-PROCESS-NEXT: [[TMP103:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP104:%.*]] = inttoptr i32 [[TMP103]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP105:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP104]], i32 -30
-; POST-PROCESS-NEXT: [[TMP106:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP105]], i32 0, i32 0, i64 45
-; POST-PROCESS-NEXT: [[TMP107:%.*]] = load i32, ptr addrspace(21) [[TMP106]], align 4
-; POST-PROCESS-NEXT: [[TMP108:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP109:%.*]] = inttoptr i32 [[TMP108]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP110:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP109]], i32 -30
-; POST-PROCESS-NEXT: [[TMP111:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP110]], i32 0, i32 0, i64 46
-; POST-PROCESS-NEXT: [[TMP112:%.*]] = load i32, ptr addrspace(21) [[TMP111]], align 4
-; POST-PROCESS-NEXT: [[TMP113:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP114:%.*]] = inttoptr i32 [[TMP113]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP115:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP114]], i32 -30
-; POST-PROCESS-NEXT: [[TMP116:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP115]], i32 0, i32 0, i64 47
-; POST-PROCESS-NEXT: [[TMP117:%.*]] = load i32, ptr addrspace(21) [[TMP116]], align 4
-; POST-PROCESS-NEXT: [[TMP118:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP119:%.*]] = inttoptr i32 [[TMP118]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP120:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP119]], i32 -30
-; POST-PROCESS-NEXT: [[TMP121:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP120]], i32 0, i32 0, i64 48
-; POST-PROCESS-NEXT: [[TMP122:%.*]] = load i32, ptr addrspace(21) [[TMP121]], align 4
-; POST-PROCESS-NEXT: [[TMP123:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP124:%.*]] = inttoptr i32 [[TMP123]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP125:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP124]], i32 -30
-; POST-PROCESS-NEXT: [[TMP126:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP125]], i32 0, i32 0, i64 49
-; POST-PROCESS-NEXT: [[TMP127:%.*]] = load i32, ptr addrspace(21) [[TMP126]], align 4
-; POST-PROCESS-NEXT: [[TMP128:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP129:%.*]] = inttoptr i32 [[TMP128]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP130:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP129]], i32 -30
-; POST-PROCESS-NEXT: [[TMP131:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP130]], i32 0, i32 0, i64 50
-; POST-PROCESS-NEXT: [[TMP132:%.*]] = load i32, ptr addrspace(21) [[TMP131]], align 4
-; POST-PROCESS-NEXT: [[TMP133:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP134:%.*]] = inttoptr i32 [[TMP133]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP135:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP134]], i32 -30
-; POST-PROCESS-NEXT: [[TMP136:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP135]], i32 0, i32 0, i64 51
-; POST-PROCESS-NEXT: [[TMP137:%.*]] = load i32, ptr addrspace(21) [[TMP136]], align 4
-; POST-PROCESS-NEXT: [[TMP138:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP139:%.*]] = inttoptr i32 [[TMP138]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP140:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP139]], i32 -30
-; POST-PROCESS-NEXT: [[TMP141:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP140]], i32 0, i32 0, i64 52
-; POST-PROCESS-NEXT: [[TMP142:%.*]] = load i32, ptr addrspace(21) [[TMP141]], align 4
-; POST-PROCESS-NEXT: [[TMP143:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP144:%.*]] = inttoptr i32 [[TMP143]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP145:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP144]], i32 -30
-; POST-PROCESS-NEXT: [[TMP146:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP145]], i32 0, i32 0, i64 53
-; POST-PROCESS-NEXT: [[TMP147:%.*]] = load i32, ptr addrspace(21) [[TMP146]], align 4
-; POST-PROCESS-NEXT: [[TMP148:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP149:%.*]] = inttoptr i32 [[TMP148]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP150:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP149]], i32 -30
-; POST-PROCESS-NEXT: [[TMP151:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP150]], i32 0, i32 0, i64 54
-; POST-PROCESS-NEXT: [[TMP152:%.*]] = load i32, ptr addrspace(21) [[TMP151]], align 4
-; POST-PROCESS-NEXT: [[TMP153:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP154:%.*]] = inttoptr i32 [[TMP153]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP155:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP154]], i32 -30
-; POST-PROCESS-NEXT: [[TMP156:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP155]], i32 0, i32 0, i64 55
-; POST-PROCESS-NEXT: [[TMP157:%.*]] = load i32, ptr addrspace(21) [[TMP156]], align 4
-; POST-PROCESS-NEXT: [[TMP158:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP159:%.*]] = inttoptr i32 [[TMP158]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP160:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP159]], i32 -30
-; POST-PROCESS-NEXT: [[TMP161:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(21) [[TMP160]], i32 0, i32 0, i64 56
-; POST-PROCESS-NEXT: [[TMP162:%.*]] = load i32, ptr addrspace(21) [[TMP161]], align 4
-; POST-PROCESS-NEXT: [[TMP163:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[DOTSPILL_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME]], ptr [[CONT_STATE]], i32 0, i32 2
-; POST-PROCESS-NEXT: store i32 [[TMP163]], ptr [[DOTSPILL_ADDR]], align 4
-; POST-PROCESS-NEXT: [[TMP164:%.*]] = call [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] @_cont_GetTriangleHitAttributes(ptr [[SYSTEM_DATA_ALLOCA]])
-; POST-PROCESS-NEXT: [[DOTFCA_0_EXTRACT52:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP164]], 0
-; POST-PROCESS-NEXT: [[DOTSROA_054_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT52]], i32 0
-; POST-PROCESS-NEXT: [[TMP165:%.*]] = bitcast float [[DOTSROA_054_0_VEC_EXTRACT]] to i32
-; POST-PROCESS-NEXT: [[DOTSROA_054_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT52]], i32 1
-; POST-PROCESS-NEXT: [[TMP166:%.*]] = bitcast float [[DOTSROA_054_4_VEC_EXTRACT]] to i32
; POST-PROCESS-NEXT: [[TMP167:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
; POST-PROCESS-NEXT: [[TMP168:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
; POST-PROCESS-NEXT: [[TMP169:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP167]])
; POST-PROCESS-NEXT: [[TMP170:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP169]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
; POST-PROCESS-NEXT: [[TMP171:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[TMP170]])
-; POST-PROCESS-NEXT: [[TMP172:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[DIS_DATA_I_FCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP172]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[DIS_DATA_I_FCA_0_LOAD:%.*]] = load i32, ptr [[DIS_DATA_I_FCA_0_GEP]], align 4
-; POST-PROCESS-NEXT: [[DIS_DATA_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, i32 [[DIS_DATA_I_FCA_0_LOAD]], 0
+; POST-PROCESS-NEXT: [[DIS_DATA_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA:%.*]] poison, <3 x i32> [[DOTFCA_0_0_EXTRACT]], 0
; POST-PROCESS-NEXT: [[SYS_DATA_I:%.*]] = insertvalue [[STRUCT_SYSTEMDATA]] undef, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I_FCA_0_INSERT]], 0
; POST-PROCESS-NEXT: [[TRAV_DATA_I:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA:%.*]] undef, [[STRUCT_SYSTEMDATA]] [[SYS_DATA_I]], 0
-; POST-PROCESS-NEXT: [[TMP173:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP174:%.*]] = add i32 [[TMP173]], -108
-; POST-PROCESS-NEXT: store i32 [[TMP174]], ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: store i32 [[TMP5]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP6]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP7]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP8]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP9]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP10]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP11]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP12]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP13]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP14]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP15]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP16]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP17]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP18]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP19]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP20]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP21]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP22]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP23]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP24]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP25]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP26]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP27]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP175:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP176:%.*]] = inttoptr i32 [[TMP175]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP177:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP176]], i32 -30
-; POST-PROCESS-NEXT: [[TMP178:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP177]], i32 0, i32 0, i64 30
-; POST-PROCESS-NEXT: store i32 [[TMP32]], ptr addrspace(21) [[TMP178]], align 4
-; POST-PROCESS-NEXT: [[TMP179:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP180:%.*]] = inttoptr i32 [[TMP179]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP181:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP180]], i32 -30
-; POST-PROCESS-NEXT: [[TMP182:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP181]], i32 0, i32 0, i64 31
-; POST-PROCESS-NEXT: store i32 [[TMP37]], ptr addrspace(21) [[TMP182]], align 4
-; POST-PROCESS-NEXT: [[TMP183:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP184:%.*]] = inttoptr i32 [[TMP183]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP185:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP184]], i32 -30
-; POST-PROCESS-NEXT: [[TMP186:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP185]], i32 0, i32 0, i64 32
-; POST-PROCESS-NEXT: store i32 [[TMP42]], ptr addrspace(21) [[TMP186]], align 4
-; POST-PROCESS-NEXT: [[TMP187:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP188:%.*]] = inttoptr i32 [[TMP187]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP189:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP188]], i32 -30
-; POST-PROCESS-NEXT: [[TMP190:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP189]], i32 0, i32 0, i64 33
-; POST-PROCESS-NEXT: store i32 [[TMP47]], ptr addrspace(21) [[TMP190]], align 4
-; POST-PROCESS-NEXT: [[TMP191:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP192:%.*]] = inttoptr i32 [[TMP191]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP193:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP192]], i32 -30
-; POST-PROCESS-NEXT: [[TMP194:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP193]], i32 0, i32 0, i64 34
-; POST-PROCESS-NEXT: store i32 [[TMP52]], ptr addrspace(21) [[TMP194]], align 4
-; POST-PROCESS-NEXT: [[TMP195:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP196:%.*]] = inttoptr i32 [[TMP195]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP197:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP196]], i32 -30
-; POST-PROCESS-NEXT: [[TMP198:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP197]], i32 0, i32 0, i64 35
-; POST-PROCESS-NEXT: store i32 [[TMP57]], ptr addrspace(21) [[TMP198]], align 4
-; POST-PROCESS-NEXT: [[TMP199:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP200:%.*]] = inttoptr i32 [[TMP199]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP201:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP200]], i32 -30
-; POST-PROCESS-NEXT: [[TMP202:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP201]], i32 0, i32 0, i64 36
-; POST-PROCESS-NEXT: store i32 [[TMP62]], ptr addrspace(21) [[TMP202]], align 4
-; POST-PROCESS-NEXT: [[TMP203:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP204:%.*]] = inttoptr i32 [[TMP203]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP205:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP204]], i32 -30
-; POST-PROCESS-NEXT: [[TMP206:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP205]], i32 0, i32 0, i64 37
-; POST-PROCESS-NEXT: store i32 [[TMP67]], ptr addrspace(21) [[TMP206]], align 4
-; POST-PROCESS-NEXT: [[TMP207:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP208:%.*]] = inttoptr i32 [[TMP207]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP209:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP208]], i32 -30
-; POST-PROCESS-NEXT: [[TMP210:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP209]], i32 0, i32 0, i64 38
-; POST-PROCESS-NEXT: store i32 [[TMP72]], ptr addrspace(21) [[TMP210]], align 4
-; POST-PROCESS-NEXT: [[TMP211:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP212:%.*]] = inttoptr i32 [[TMP211]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP213:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP212]], i32 -30
-; POST-PROCESS-NEXT: [[TMP214:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP213]], i32 0, i32 0, i64 39
-; POST-PROCESS-NEXT: store i32 [[TMP77]], ptr addrspace(21) [[TMP214]], align 4
-; POST-PROCESS-NEXT: [[TMP215:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP216:%.*]] = inttoptr i32 [[TMP215]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP217:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP216]], i32 -30
-; POST-PROCESS-NEXT: [[TMP218:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP217]], i32 0, i32 0, i64 40
-; POST-PROCESS-NEXT: store i32 [[TMP82]], ptr addrspace(21) [[TMP218]], align 4
-; POST-PROCESS-NEXT: [[TMP219:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP220:%.*]] = inttoptr i32 [[TMP219]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP221:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP220]], i32 -30
-; POST-PROCESS-NEXT: [[TMP222:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP221]], i32 0, i32 0, i64 41
-; POST-PROCESS-NEXT: store i32 [[TMP87]], ptr addrspace(21) [[TMP222]], align 4
-; POST-PROCESS-NEXT: [[TMP223:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP224:%.*]] = inttoptr i32 [[TMP223]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP225:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP224]], i32 -30
-; POST-PROCESS-NEXT: [[TMP226:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP225]], i32 0, i32 0, i64 42
-; POST-PROCESS-NEXT: store i32 [[TMP92]], ptr addrspace(21) [[TMP226]], align 4
-; POST-PROCESS-NEXT: [[TMP227:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP228:%.*]] = inttoptr i32 [[TMP227]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP229:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP228]], i32 -30
-; POST-PROCESS-NEXT: [[TMP230:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP229]], i32 0, i32 0, i64 43
-; POST-PROCESS-NEXT: store i32 [[TMP97]], ptr addrspace(21) [[TMP230]], align 4
-; POST-PROCESS-NEXT: [[TMP231:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP232:%.*]] = inttoptr i32 [[TMP231]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP233:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP232]], i32 -30
-; POST-PROCESS-NEXT: [[TMP234:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP233]], i32 0, i32 0, i64 44
-; POST-PROCESS-NEXT: store i32 [[TMP102]], ptr addrspace(21) [[TMP234]], align 4
-; POST-PROCESS-NEXT: [[TMP235:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP236:%.*]] = inttoptr i32 [[TMP235]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP237:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP236]], i32 -30
-; POST-PROCESS-NEXT: [[TMP238:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP237]], i32 0, i32 0, i64 45
-; POST-PROCESS-NEXT: store i32 [[TMP107]], ptr addrspace(21) [[TMP238]], align 4
-; POST-PROCESS-NEXT: [[TMP239:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP240:%.*]] = inttoptr i32 [[TMP239]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP241:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP240]], i32 -30
-; POST-PROCESS-NEXT: [[TMP242:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP241]], i32 0, i32 0, i64 46
-; POST-PROCESS-NEXT: store i32 [[TMP112]], ptr addrspace(21) [[TMP242]], align 4
-; POST-PROCESS-NEXT: [[TMP243:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP244:%.*]] = inttoptr i32 [[TMP243]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP245:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP244]], i32 -30
-; POST-PROCESS-NEXT: [[TMP246:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP245]], i32 0, i32 0, i64 47
-; POST-PROCESS-NEXT: store i32 [[TMP117]], ptr addrspace(21) [[TMP246]], align 4
-; POST-PROCESS-NEXT: [[TMP247:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP248:%.*]] = inttoptr i32 [[TMP247]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP249:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP248]], i32 -30
-; POST-PROCESS-NEXT: [[TMP250:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP249]], i32 0, i32 0, i64 48
-; POST-PROCESS-NEXT: store i32 [[TMP122]], ptr addrspace(21) [[TMP250]], align 4
-; POST-PROCESS-NEXT: [[TMP251:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP252:%.*]] = inttoptr i32 [[TMP251]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP253:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP252]], i32 -30
-; POST-PROCESS-NEXT: [[TMP254:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP253]], i32 0, i32 0, i64 49
-; POST-PROCESS-NEXT: store i32 [[TMP127]], ptr addrspace(21) [[TMP254]], align 4
-; POST-PROCESS-NEXT: [[TMP255:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP256:%.*]] = inttoptr i32 [[TMP255]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP257:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP256]], i32 -30
-; POST-PROCESS-NEXT: [[TMP258:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP257]], i32 0, i32 0, i64 50
-; POST-PROCESS-NEXT: store i32 [[TMP132]], ptr addrspace(21) [[TMP258]], align 4
-; POST-PROCESS-NEXT: [[TMP259:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP260:%.*]] = inttoptr i32 [[TMP259]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP261:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP260]], i32 -30
-; POST-PROCESS-NEXT: [[TMP262:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP261]], i32 0, i32 0, i64 51
-; POST-PROCESS-NEXT: store i32 [[TMP137]], ptr addrspace(21) [[TMP262]], align 4
-; POST-PROCESS-NEXT: [[TMP263:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP264:%.*]] = inttoptr i32 [[TMP263]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP265:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP264]], i32 -30
-; POST-PROCESS-NEXT: [[TMP266:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP265]], i32 0, i32 0, i64 52
-; POST-PROCESS-NEXT: store i32 [[TMP142]], ptr addrspace(21) [[TMP266]], align 4
-; POST-PROCESS-NEXT: [[TMP267:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP268:%.*]] = inttoptr i32 [[TMP267]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP269:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP268]], i32 -30
-; POST-PROCESS-NEXT: [[TMP270:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP269]], i32 0, i32 0, i64 53
-; POST-PROCESS-NEXT: store i32 [[TMP147]], ptr addrspace(21) [[TMP270]], align 4
-; POST-PROCESS-NEXT: [[TMP271:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP272:%.*]] = inttoptr i32 [[TMP271]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP273:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP272]], i32 -30
-; POST-PROCESS-NEXT: [[TMP274:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP273]], i32 0, i32 0, i64 54
-; POST-PROCESS-NEXT: store i32 [[TMP152]], ptr addrspace(21) [[TMP274]], align 4
-; POST-PROCESS-NEXT: [[TMP275:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP276:%.*]] = inttoptr i32 [[TMP275]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP277:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP276]], i32 -30
-; POST-PROCESS-NEXT: [[TMP278:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP277]], i32 0, i32 0, i64 55
-; POST-PROCESS-NEXT: store i32 [[TMP157]], ptr addrspace(21) [[TMP278]], align 4
-; POST-PROCESS-NEXT: [[TMP279:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP280:%.*]] = inttoptr i32 [[TMP279]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP281:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP280]], i32 -30
-; POST-PROCESS-NEXT: [[TMP282:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP281]], i32 0, i32 0, i64 56
-; POST-PROCESS-NEXT: store i32 [[TMP162]], ptr addrspace(21) [[TMP282]], align 4
-; POST-PROCESS-NEXT: [[TMP283:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP284:%.*]] = add i32 [[TMP283]], 16
-; POST-PROCESS-NEXT: store i32 [[TMP284]], ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP285:%.*]] = inttoptr i32 [[TMP283]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP286:%.*]] = getelementptr inbounds [4 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[TMP287:%.*]] = getelementptr inbounds [4 x i32], ptr addrspace(21) [[TMP285]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[TMP288:%.*]] = load i32, ptr [[TMP286]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP288]], ptr addrspace(21) [[TMP287]], align 4
-; POST-PROCESS-NEXT: [[TMP289:%.*]] = getelementptr inbounds [4 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; POST-PROCESS-NEXT: [[TMP290:%.*]] = getelementptr inbounds [4 x i32], ptr addrspace(21) [[TMP285]], i32 0, i32 1
-; POST-PROCESS-NEXT: [[TMP291:%.*]] = load i32, ptr [[TMP289]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP291]], ptr addrspace(21) [[TMP290]], align 4
-; POST-PROCESS-NEXT: [[TMP292:%.*]] = getelementptr inbounds [4 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; POST-PROCESS-NEXT: [[TMP293:%.*]] = getelementptr inbounds [4 x i32], ptr addrspace(21) [[TMP285]], i32 0, i32 2
-; POST-PROCESS-NEXT: [[TMP294:%.*]] = load i32, ptr [[TMP292]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP294]], ptr addrspace(21) [[TMP293]], align 4
-; POST-PROCESS-NEXT: [[TMP295:%.*]] = getelementptr inbounds [4 x i32], ptr [[CONT_STATE]], i32 0, i32 3
-; POST-PROCESS-NEXT: [[TMP296:%.*]] = getelementptr inbounds [4 x i32], ptr addrspace(21) [[TMP285]], i32 0, i32 3
-; POST-PROCESS-NEXT: [[TMP297:%.*]] = load i32, ptr [[TMP295]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP297]], ptr addrspace(21) [[TMP296]], align 4
-; POST-PROCESS-NEXT: [[TMP298:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP299:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @ClosestHit.resume.0 to i64))
-; POST-PROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 4, i32 [[TMP298]], i64 [[TMP299]], [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]]), !continuation.registercount !17, !continuation.returnedRegistercount !17
-; POST-PROCESS-NEXT: unreachable
-;
-;
-; POST-PROCESS-LABEL: define dso_local void @ClosestHit.resume.0(
-; POST-PROCESS-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.shaderstage !24 !continuation.registercount !17 !continuation !25 {
-; POST-PROCESS-NEXT: entryresume.0:
-; POST-PROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
-; POST-PROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [4 x i32], align 4
-; POST-PROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; POST-PROCESS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP0]], ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP2:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP3]], i64 -16
-; POST-PROCESS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(21) [[TMP5]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
-; POST-PROCESS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 1
-; POST-PROCESS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; POST-PROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(21) [[TMP8]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4
-; POST-PROCESS-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 2
-; POST-PROCESS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i32], ptr [[CONT_STATE]], i32 0, i32 2
-; POST-PROCESS-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(21) [[TMP11]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP13]], ptr [[TMP12]], align 4
-; POST-PROCESS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 3
-; POST-PROCESS-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i32], ptr [[CONT_STATE]], i32 0, i32 3
-; POST-PROCESS-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(21) [[TMP14]], align 4
-; POST-PROCESS-NEXT: store i32 [[TMP16]], ptr [[TMP15]], align 4
-; POST-PROCESS-NEXT: [[TMP17:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP18:%.*]] = add i32 [[TMP17]], -16
-; POST-PROCESS-NEXT: store i32 [[TMP18]], ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA:%.*]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP22:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP23:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP24:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP25:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP27:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP28:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP29:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP30:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP32:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP33:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP34:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP35:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP36:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP37:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP38:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP39:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP40:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP41:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP42:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: [[TMP43:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP44:%.*]] = inttoptr i32 [[TMP43]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP45:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP44]], i32 -30
-; POST-PROCESS-NEXT: [[TMP46:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP45]], i32 0, i32 0, i64 30
-; POST-PROCESS-NEXT: [[TMP47:%.*]] = load i32, ptr addrspace(21) [[TMP46]], align 4
-; POST-PROCESS-NEXT: [[TMP48:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP49:%.*]] = inttoptr i32 [[TMP48]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP50:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP49]], i32 -30
-; POST-PROCESS-NEXT: [[TMP51:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP50]], i32 0, i32 0, i64 31
-; POST-PROCESS-NEXT: [[TMP52:%.*]] = load i32, ptr addrspace(21) [[TMP51]], align 4
-; POST-PROCESS-NEXT: [[TMP53:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP54:%.*]] = inttoptr i32 [[TMP53]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP55:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP54]], i32 -30
-; POST-PROCESS-NEXT: [[TMP56:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP55]], i32 0, i32 0, i64 32
-; POST-PROCESS-NEXT: [[TMP57:%.*]] = load i32, ptr addrspace(21) [[TMP56]], align 4
-; POST-PROCESS-NEXT: [[TMP58:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP59:%.*]] = inttoptr i32 [[TMP58]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP60:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP59]], i32 -30
-; POST-PROCESS-NEXT: [[TMP61:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP60]], i32 0, i32 0, i64 33
-; POST-PROCESS-NEXT: [[TMP62:%.*]] = load i32, ptr addrspace(21) [[TMP61]], align 4
-; POST-PROCESS-NEXT: [[TMP63:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP64:%.*]] = inttoptr i32 [[TMP63]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP65:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP64]], i32 -30
-; POST-PROCESS-NEXT: [[TMP66:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP65]], i32 0, i32 0, i64 34
-; POST-PROCESS-NEXT: [[TMP67:%.*]] = load i32, ptr addrspace(21) [[TMP66]], align 4
-; POST-PROCESS-NEXT: [[TMP68:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP69:%.*]] = inttoptr i32 [[TMP68]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP70:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP69]], i32 -30
-; POST-PROCESS-NEXT: [[TMP71:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP70]], i32 0, i32 0, i64 35
-; POST-PROCESS-NEXT: [[TMP72:%.*]] = load i32, ptr addrspace(21) [[TMP71]], align 4
-; POST-PROCESS-NEXT: [[TMP73:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP74:%.*]] = inttoptr i32 [[TMP73]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP75:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP74]], i32 -30
-; POST-PROCESS-NEXT: [[TMP76:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP75]], i32 0, i32 0, i64 36
-; POST-PROCESS-NEXT: [[TMP77:%.*]] = load i32, ptr addrspace(21) [[TMP76]], align 4
-; POST-PROCESS-NEXT: [[TMP78:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP79:%.*]] = inttoptr i32 [[TMP78]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP80:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP79]], i32 -30
-; POST-PROCESS-NEXT: [[TMP81:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP80]], i32 0, i32 0, i64 37
-; POST-PROCESS-NEXT: [[TMP82:%.*]] = load i32, ptr addrspace(21) [[TMP81]], align 4
-; POST-PROCESS-NEXT: [[TMP83:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP84:%.*]] = inttoptr i32 [[TMP83]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP85:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP84]], i32 -30
-; POST-PROCESS-NEXT: [[TMP86:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP85]], i32 0, i32 0, i64 38
-; POST-PROCESS-NEXT: [[TMP87:%.*]] = load i32, ptr addrspace(21) [[TMP86]], align 4
-; POST-PROCESS-NEXT: [[TMP88:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP89:%.*]] = inttoptr i32 [[TMP88]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP90:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP89]], i32 -30
-; POST-PROCESS-NEXT: [[TMP91:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP90]], i32 0, i32 0, i64 39
-; POST-PROCESS-NEXT: [[TMP92:%.*]] = load i32, ptr addrspace(21) [[TMP91]], align 4
-; POST-PROCESS-NEXT: [[TMP93:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP94:%.*]] = inttoptr i32 [[TMP93]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP95:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP94]], i32 -30
-; POST-PROCESS-NEXT: [[TMP96:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP95]], i32 0, i32 0, i64 40
-; POST-PROCESS-NEXT: [[TMP97:%.*]] = load i32, ptr addrspace(21) [[TMP96]], align 4
-; POST-PROCESS-NEXT: [[TMP98:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP99:%.*]] = inttoptr i32 [[TMP98]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP100:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP99]], i32 -30
-; POST-PROCESS-NEXT: [[TMP101:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP100]], i32 0, i32 0, i64 41
-; POST-PROCESS-NEXT: [[TMP102:%.*]] = load i32, ptr addrspace(21) [[TMP101]], align 4
-; POST-PROCESS-NEXT: [[TMP103:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP104:%.*]] = inttoptr i32 [[TMP103]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP105:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP104]], i32 -30
-; POST-PROCESS-NEXT: [[TMP106:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP105]], i32 0, i32 0, i64 42
-; POST-PROCESS-NEXT: [[TMP107:%.*]] = load i32, ptr addrspace(21) [[TMP106]], align 4
-; POST-PROCESS-NEXT: [[TMP108:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP109:%.*]] = inttoptr i32 [[TMP108]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP110:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP109]], i32 -30
-; POST-PROCESS-NEXT: [[TMP111:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP110]], i32 0, i32 0, i64 43
-; POST-PROCESS-NEXT: [[TMP112:%.*]] = load i32, ptr addrspace(21) [[TMP111]], align 4
-; POST-PROCESS-NEXT: [[TMP113:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP114:%.*]] = inttoptr i32 [[TMP113]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP115:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP114]], i32 -30
-; POST-PROCESS-NEXT: [[TMP116:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP115]], i32 0, i32 0, i64 44
-; POST-PROCESS-NEXT: [[TMP117:%.*]] = load i32, ptr addrspace(21) [[TMP116]], align 4
-; POST-PROCESS-NEXT: [[TMP118:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP119:%.*]] = inttoptr i32 [[TMP118]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP120:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP119]], i32 -30
-; POST-PROCESS-NEXT: [[TMP121:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP120]], i32 0, i32 0, i64 45
-; POST-PROCESS-NEXT: [[TMP122:%.*]] = load i32, ptr addrspace(21) [[TMP121]], align 4
-; POST-PROCESS-NEXT: [[TMP123:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP124:%.*]] = inttoptr i32 [[TMP123]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP125:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP124]], i32 -30
-; POST-PROCESS-NEXT: [[TMP126:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP125]], i32 0, i32 0, i64 46
-; POST-PROCESS-NEXT: [[TMP127:%.*]] = load i32, ptr addrspace(21) [[TMP126]], align 4
-; POST-PROCESS-NEXT: [[TMP128:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP129:%.*]] = inttoptr i32 [[TMP128]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP130:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP129]], i32 -30
-; POST-PROCESS-NEXT: [[TMP131:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP130]], i32 0, i32 0, i64 47
-; POST-PROCESS-NEXT: [[TMP132:%.*]] = load i32, ptr addrspace(21) [[TMP131]], align 4
-; POST-PROCESS-NEXT: [[TMP133:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP134:%.*]] = inttoptr i32 [[TMP133]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP135:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP134]], i32 -30
-; POST-PROCESS-NEXT: [[TMP136:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP135]], i32 0, i32 0, i64 48
-; POST-PROCESS-NEXT: [[TMP137:%.*]] = load i32, ptr addrspace(21) [[TMP136]], align 4
-; POST-PROCESS-NEXT: [[TMP138:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP139:%.*]] = inttoptr i32 [[TMP138]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP140:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP139]], i32 -30
-; POST-PROCESS-NEXT: [[TMP141:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP140]], i32 0, i32 0, i64 49
-; POST-PROCESS-NEXT: [[TMP142:%.*]] = load i32, ptr addrspace(21) [[TMP141]], align 4
-; POST-PROCESS-NEXT: [[TMP143:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP144:%.*]] = inttoptr i32 [[TMP143]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP145:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP144]], i32 -30
-; POST-PROCESS-NEXT: [[TMP146:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP145]], i32 0, i32 0, i64 50
-; POST-PROCESS-NEXT: [[TMP147:%.*]] = load i32, ptr addrspace(21) [[TMP146]], align 4
-; POST-PROCESS-NEXT: [[TMP148:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP149:%.*]] = inttoptr i32 [[TMP148]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP150:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP149]], i32 -30
-; POST-PROCESS-NEXT: [[TMP151:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP150]], i32 0, i32 0, i64 51
-; POST-PROCESS-NEXT: [[TMP152:%.*]] = load i32, ptr addrspace(21) [[TMP151]], align 4
-; POST-PROCESS-NEXT: [[TMP153:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP154:%.*]] = inttoptr i32 [[TMP153]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP155:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP154]], i32 -30
-; POST-PROCESS-NEXT: [[TMP156:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP155]], i32 0, i32 0, i64 52
-; POST-PROCESS-NEXT: [[TMP157:%.*]] = load i32, ptr addrspace(21) [[TMP156]], align 4
-; POST-PROCESS-NEXT: [[TMP158:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP159:%.*]] = inttoptr i32 [[TMP158]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP160:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP159]], i32 -30
-; POST-PROCESS-NEXT: [[TMP161:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP160]], i32 0, i32 0, i64 53
-; POST-PROCESS-NEXT: [[TMP162:%.*]] = load i32, ptr addrspace(21) [[TMP161]], align 4
-; POST-PROCESS-NEXT: [[TMP163:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP164:%.*]] = inttoptr i32 [[TMP163]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP165:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP164]], i32 -30
-; POST-PROCESS-NEXT: [[TMP166:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP165]], i32 0, i32 0, i64 54
-; POST-PROCESS-NEXT: [[TMP167:%.*]] = load i32, ptr addrspace(21) [[TMP166]], align 4
-; POST-PROCESS-NEXT: [[TMP168:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP169:%.*]] = inttoptr i32 [[TMP168]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP170:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP169]], i32 -30
-; POST-PROCESS-NEXT: [[TMP171:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP170]], i32 0, i32 0, i64 55
-; POST-PROCESS-NEXT: [[TMP172:%.*]] = load i32, ptr addrspace(21) [[TMP171]], align 4
-; POST-PROCESS-NEXT: [[TMP173:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP174:%.*]] = inttoptr i32 [[TMP173]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP175:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP174]], i32 -30
-; POST-PROCESS-NEXT: [[TMP176:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP175]], i32 0, i32 0, i64 56
-; POST-PROCESS-NEXT: [[TMP177:%.*]] = load i32, ptr addrspace(21) [[TMP176]], align 4
-; POST-PROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
-; POST-PROCESS-NEXT: [[DOTFCA_0_GEP51:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[TMP19]], i32 0, i32 0
-; POST-PROCESS-NEXT: store i32 [[DOTFCA_0_EXTRACT]], ptr [[DOTFCA_0_GEP51]], align 4
-; POST-PROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; POST-PROCESS-NEXT: [[DOTRELOAD_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME]], ptr [[CONT_STATE]], i32 0, i32 2
-; POST-PROCESS-NEXT: [[DOTRELOAD:%.*]] = load i32, ptr [[DOTRELOAD_ADDR]], align 4
-; POST-PROCESS-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME]], ptr [[CONT_STATE]], i32 0, i32 1
-; POST-PROCESS-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr [[RETURNADDR_RELOAD_ADDR]], align 4
-; POST-PROCESS-NEXT: store i32 [[DOTRELOAD]], ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: store i32 [[TMP20]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP21]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP22]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP23]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP24]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP25]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP26]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP27]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP28]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP29]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP30]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP31]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP32]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP33]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP34]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP35]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP36]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP37]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP38]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP39]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP40]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP41]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
-; POST-PROCESS-NEXT: store i32 [[TMP42]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP172:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP173:%.*]] = add i32 [[TMP172]], -108
+; POST-PROCESS-NEXT: store i32 [[TMP173]], ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: store i32 [[TMP6]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP7]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP8]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP9]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP10]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP11]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP12]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP13]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP14]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP15]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP16]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP17]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP18]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP19]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP20]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP21]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP22]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP23]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP24]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP25]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP26]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP27]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP28]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP174:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP175:%.*]] = inttoptr i32 [[TMP174]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP176:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP175]], i32 -30
+; POST-PROCESS-NEXT: [[TMP177:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP176]], i32 0, i32 0, i64 30
+; POST-PROCESS-NEXT: store i32 [[TMP33]], ptr addrspace(21) [[TMP177]], align 4
; POST-PROCESS-NEXT: [[TMP178:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP179:%.*]] = inttoptr i32 [[TMP178]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP180:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP179]], i32 -30
-; POST-PROCESS-NEXT: [[TMP181:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP180]], i32 0, i32 0, i64 30
-; POST-PROCESS-NEXT: store i32 [[TMP47]], ptr addrspace(21) [[TMP181]], align 4
+; POST-PROCESS-NEXT: [[TMP181:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP180]], i32 0, i32 0, i64 31
+; POST-PROCESS-NEXT: store i32 [[TMP38]], ptr addrspace(21) [[TMP181]], align 4
; POST-PROCESS-NEXT: [[TMP182:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP183:%.*]] = inttoptr i32 [[TMP182]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP184:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP183]], i32 -30
-; POST-PROCESS-NEXT: [[TMP185:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP184]], i32 0, i32 0, i64 31
-; POST-PROCESS-NEXT: store i32 [[TMP52]], ptr addrspace(21) [[TMP185]], align 4
+; POST-PROCESS-NEXT: [[TMP185:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP184]], i32 0, i32 0, i64 32
+; POST-PROCESS-NEXT: store i32 [[TMP43]], ptr addrspace(21) [[TMP185]], align 4
; POST-PROCESS-NEXT: [[TMP186:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP187:%.*]] = inttoptr i32 [[TMP186]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP188:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP187]], i32 -30
-; POST-PROCESS-NEXT: [[TMP189:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP188]], i32 0, i32 0, i64 32
-; POST-PROCESS-NEXT: store i32 [[TMP57]], ptr addrspace(21) [[TMP189]], align 4
+; POST-PROCESS-NEXT: [[TMP189:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP188]], i32 0, i32 0, i64 33
+; POST-PROCESS-NEXT: store i32 [[TMP48]], ptr addrspace(21) [[TMP189]], align 4
; POST-PROCESS-NEXT: [[TMP190:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP191:%.*]] = inttoptr i32 [[TMP190]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP192:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP191]], i32 -30
-; POST-PROCESS-NEXT: [[TMP193:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP192]], i32 0, i32 0, i64 33
-; POST-PROCESS-NEXT: store i32 [[TMP62]], ptr addrspace(21) [[TMP193]], align 4
+; POST-PROCESS-NEXT: [[TMP193:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP192]], i32 0, i32 0, i64 34
+; POST-PROCESS-NEXT: store i32 [[TMP53]], ptr addrspace(21) [[TMP193]], align 4
; POST-PROCESS-NEXT: [[TMP194:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP195:%.*]] = inttoptr i32 [[TMP194]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP196:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP195]], i32 -30
-; POST-PROCESS-NEXT: [[TMP197:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP196]], i32 0, i32 0, i64 34
-; POST-PROCESS-NEXT: store i32 [[TMP67]], ptr addrspace(21) [[TMP197]], align 4
+; POST-PROCESS-NEXT: [[TMP197:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP196]], i32 0, i32 0, i64 35
+; POST-PROCESS-NEXT: store i32 [[TMP58]], ptr addrspace(21) [[TMP197]], align 4
; POST-PROCESS-NEXT: [[TMP198:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP199:%.*]] = inttoptr i32 [[TMP198]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP200:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP199]], i32 -30
-; POST-PROCESS-NEXT: [[TMP201:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP200]], i32 0, i32 0, i64 35
-; POST-PROCESS-NEXT: store i32 [[TMP72]], ptr addrspace(21) [[TMP201]], align 4
+; POST-PROCESS-NEXT: [[TMP201:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP200]], i32 0, i32 0, i64 36
+; POST-PROCESS-NEXT: store i32 [[TMP63]], ptr addrspace(21) [[TMP201]], align 4
; POST-PROCESS-NEXT: [[TMP202:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP203:%.*]] = inttoptr i32 [[TMP202]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP204:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP203]], i32 -30
-; POST-PROCESS-NEXT: [[TMP205:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP204]], i32 0, i32 0, i64 36
-; POST-PROCESS-NEXT: store i32 [[TMP77]], ptr addrspace(21) [[TMP205]], align 4
+; POST-PROCESS-NEXT: [[TMP205:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP204]], i32 0, i32 0, i64 37
+; POST-PROCESS-NEXT: store i32 [[TMP68]], ptr addrspace(21) [[TMP205]], align 4
; POST-PROCESS-NEXT: [[TMP206:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP207:%.*]] = inttoptr i32 [[TMP206]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP208:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP207]], i32 -30
-; POST-PROCESS-NEXT: [[TMP209:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP208]], i32 0, i32 0, i64 37
-; POST-PROCESS-NEXT: store i32 [[TMP82]], ptr addrspace(21) [[TMP209]], align 4
+; POST-PROCESS-NEXT: [[TMP209:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP208]], i32 0, i32 0, i64 38
+; POST-PROCESS-NEXT: store i32 [[TMP73]], ptr addrspace(21) [[TMP209]], align 4
; POST-PROCESS-NEXT: [[TMP210:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP211:%.*]] = inttoptr i32 [[TMP210]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP212:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP211]], i32 -30
-; POST-PROCESS-NEXT: [[TMP213:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP212]], i32 0, i32 0, i64 38
-; POST-PROCESS-NEXT: store i32 [[TMP87]], ptr addrspace(21) [[TMP213]], align 4
+; POST-PROCESS-NEXT: [[TMP213:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP212]], i32 0, i32 0, i64 39
+; POST-PROCESS-NEXT: store i32 [[TMP78]], ptr addrspace(21) [[TMP213]], align 4
; POST-PROCESS-NEXT: [[TMP214:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP215:%.*]] = inttoptr i32 [[TMP214]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP216:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP215]], i32 -30
-; POST-PROCESS-NEXT: [[TMP217:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP216]], i32 0, i32 0, i64 39
-; POST-PROCESS-NEXT: store i32 [[TMP92]], ptr addrspace(21) [[TMP217]], align 4
+; POST-PROCESS-NEXT: [[TMP217:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP216]], i32 0, i32 0, i64 40
+; POST-PROCESS-NEXT: store i32 [[TMP83]], ptr addrspace(21) [[TMP217]], align 4
; POST-PROCESS-NEXT: [[TMP218:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP219:%.*]] = inttoptr i32 [[TMP218]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP220:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP219]], i32 -30
-; POST-PROCESS-NEXT: [[TMP221:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP220]], i32 0, i32 0, i64 40
-; POST-PROCESS-NEXT: store i32 [[TMP97]], ptr addrspace(21) [[TMP221]], align 4
+; POST-PROCESS-NEXT: [[TMP221:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP220]], i32 0, i32 0, i64 41
+; POST-PROCESS-NEXT: store i32 [[TMP88]], ptr addrspace(21) [[TMP221]], align 4
; POST-PROCESS-NEXT: [[TMP222:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP223:%.*]] = inttoptr i32 [[TMP222]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP224:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP223]], i32 -30
-; POST-PROCESS-NEXT: [[TMP225:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP224]], i32 0, i32 0, i64 41
-; POST-PROCESS-NEXT: store i32 [[TMP102]], ptr addrspace(21) [[TMP225]], align 4
+; POST-PROCESS-NEXT: [[TMP225:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP224]], i32 0, i32 0, i64 42
+; POST-PROCESS-NEXT: store i32 [[TMP93]], ptr addrspace(21) [[TMP225]], align 4
; POST-PROCESS-NEXT: [[TMP226:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP227:%.*]] = inttoptr i32 [[TMP226]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP228:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP227]], i32 -30
-; POST-PROCESS-NEXT: [[TMP229:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP228]], i32 0, i32 0, i64 42
-; POST-PROCESS-NEXT: store i32 [[TMP107]], ptr addrspace(21) [[TMP229]], align 4
+; POST-PROCESS-NEXT: [[TMP229:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP228]], i32 0, i32 0, i64 43
+; POST-PROCESS-NEXT: store i32 [[TMP98]], ptr addrspace(21) [[TMP229]], align 4
; POST-PROCESS-NEXT: [[TMP230:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP231:%.*]] = inttoptr i32 [[TMP230]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP232:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP231]], i32 -30
-; POST-PROCESS-NEXT: [[TMP233:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP232]], i32 0, i32 0, i64 43
-; POST-PROCESS-NEXT: store i32 [[TMP112]], ptr addrspace(21) [[TMP233]], align 4
+; POST-PROCESS-NEXT: [[TMP233:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP232]], i32 0, i32 0, i64 44
+; POST-PROCESS-NEXT: store i32 [[TMP103]], ptr addrspace(21) [[TMP233]], align 4
; POST-PROCESS-NEXT: [[TMP234:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP235:%.*]] = inttoptr i32 [[TMP234]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP236:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP235]], i32 -30
-; POST-PROCESS-NEXT: [[TMP237:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP236]], i32 0, i32 0, i64 44
-; POST-PROCESS-NEXT: store i32 [[TMP117]], ptr addrspace(21) [[TMP237]], align 4
+; POST-PROCESS-NEXT: [[TMP237:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP236]], i32 0, i32 0, i64 45
+; POST-PROCESS-NEXT: store i32 [[TMP108]], ptr addrspace(21) [[TMP237]], align 4
; POST-PROCESS-NEXT: [[TMP238:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP239:%.*]] = inttoptr i32 [[TMP238]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP240:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP239]], i32 -30
-; POST-PROCESS-NEXT: [[TMP241:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP240]], i32 0, i32 0, i64 45
-; POST-PROCESS-NEXT: store i32 [[TMP122]], ptr addrspace(21) [[TMP241]], align 4
+; POST-PROCESS-NEXT: [[TMP241:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP240]], i32 0, i32 0, i64 46
+; POST-PROCESS-NEXT: store i32 [[TMP113]], ptr addrspace(21) [[TMP241]], align 4
; POST-PROCESS-NEXT: [[TMP242:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP243:%.*]] = inttoptr i32 [[TMP242]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP244:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP243]], i32 -30
-; POST-PROCESS-NEXT: [[TMP245:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP244]], i32 0, i32 0, i64 46
-; POST-PROCESS-NEXT: store i32 [[TMP127]], ptr addrspace(21) [[TMP245]], align 4
+; POST-PROCESS-NEXT: [[TMP245:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP244]], i32 0, i32 0, i64 47
+; POST-PROCESS-NEXT: store i32 [[TMP118]], ptr addrspace(21) [[TMP245]], align 4
; POST-PROCESS-NEXT: [[TMP246:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP247:%.*]] = inttoptr i32 [[TMP246]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP248:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP247]], i32 -30
-; POST-PROCESS-NEXT: [[TMP249:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP248]], i32 0, i32 0, i64 47
-; POST-PROCESS-NEXT: store i32 [[TMP132]], ptr addrspace(21) [[TMP249]], align 4
+; POST-PROCESS-NEXT: [[TMP249:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP248]], i32 0, i32 0, i64 48
+; POST-PROCESS-NEXT: store i32 [[TMP123]], ptr addrspace(21) [[TMP249]], align 4
; POST-PROCESS-NEXT: [[TMP250:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP251:%.*]] = inttoptr i32 [[TMP250]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP252:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP251]], i32 -30
-; POST-PROCESS-NEXT: [[TMP253:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP252]], i32 0, i32 0, i64 48
-; POST-PROCESS-NEXT: store i32 [[TMP137]], ptr addrspace(21) [[TMP253]], align 4
+; POST-PROCESS-NEXT: [[TMP253:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP252]], i32 0, i32 0, i64 49
+; POST-PROCESS-NEXT: store i32 [[TMP128]], ptr addrspace(21) [[TMP253]], align 4
; POST-PROCESS-NEXT: [[TMP254:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP255:%.*]] = inttoptr i32 [[TMP254]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP256:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP255]], i32 -30
-; POST-PROCESS-NEXT: [[TMP257:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP256]], i32 0, i32 0, i64 49
-; POST-PROCESS-NEXT: store i32 [[TMP142]], ptr addrspace(21) [[TMP257]], align 4
+; POST-PROCESS-NEXT: [[TMP257:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP256]], i32 0, i32 0, i64 50
+; POST-PROCESS-NEXT: store i32 [[TMP133]], ptr addrspace(21) [[TMP257]], align 4
; POST-PROCESS-NEXT: [[TMP258:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP259:%.*]] = inttoptr i32 [[TMP258]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP260:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP259]], i32 -30
-; POST-PROCESS-NEXT: [[TMP261:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP260]], i32 0, i32 0, i64 50
-; POST-PROCESS-NEXT: store i32 [[TMP147]], ptr addrspace(21) [[TMP261]], align 4
+; POST-PROCESS-NEXT: [[TMP261:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP260]], i32 0, i32 0, i64 51
+; POST-PROCESS-NEXT: store i32 [[TMP138]], ptr addrspace(21) [[TMP261]], align 4
; POST-PROCESS-NEXT: [[TMP262:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP263:%.*]] = inttoptr i32 [[TMP262]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP264:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP263]], i32 -30
-; POST-PROCESS-NEXT: [[TMP265:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP264]], i32 0, i32 0, i64 51
-; POST-PROCESS-NEXT: store i32 [[TMP152]], ptr addrspace(21) [[TMP265]], align 4
+; POST-PROCESS-NEXT: [[TMP265:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP264]], i32 0, i32 0, i64 52
+; POST-PROCESS-NEXT: store i32 [[TMP143]], ptr addrspace(21) [[TMP265]], align 4
; POST-PROCESS-NEXT: [[TMP266:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP267:%.*]] = inttoptr i32 [[TMP266]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP268:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP267]], i32 -30
-; POST-PROCESS-NEXT: [[TMP269:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP268]], i32 0, i32 0, i64 52
-; POST-PROCESS-NEXT: store i32 [[TMP157]], ptr addrspace(21) [[TMP269]], align 4
+; POST-PROCESS-NEXT: [[TMP269:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP268]], i32 0, i32 0, i64 53
+; POST-PROCESS-NEXT: store i32 [[TMP148]], ptr addrspace(21) [[TMP269]], align 4
; POST-PROCESS-NEXT: [[TMP270:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP271:%.*]] = inttoptr i32 [[TMP270]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP272:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP271]], i32 -30
-; POST-PROCESS-NEXT: [[TMP273:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP272]], i32 0, i32 0, i64 53
-; POST-PROCESS-NEXT: store i32 [[TMP162]], ptr addrspace(21) [[TMP273]], align 4
+; POST-PROCESS-NEXT: [[TMP273:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP272]], i32 0, i32 0, i64 54
+; POST-PROCESS-NEXT: store i32 [[TMP153]], ptr addrspace(21) [[TMP273]], align 4
; POST-PROCESS-NEXT: [[TMP274:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP275:%.*]] = inttoptr i32 [[TMP274]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP276:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP275]], i32 -30
-; POST-PROCESS-NEXT: [[TMP277:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP276]], i32 0, i32 0, i64 54
-; POST-PROCESS-NEXT: store i32 [[TMP167]], ptr addrspace(21) [[TMP277]], align 4
+; POST-PROCESS-NEXT: [[TMP277:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP276]], i32 0, i32 0, i64 55
+; POST-PROCESS-NEXT: store i32 [[TMP158]], ptr addrspace(21) [[TMP277]], align 4
; POST-PROCESS-NEXT: [[TMP278:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; POST-PROCESS-NEXT: [[TMP279:%.*]] = inttoptr i32 [[TMP278]] to ptr addrspace(21)
; POST-PROCESS-NEXT: [[TMP280:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP279]], i32 -30
-; POST-PROCESS-NEXT: [[TMP281:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP280]], i32 0, i32 0, i64 55
-; POST-PROCESS-NEXT: store i32 [[TMP172]], ptr addrspace(21) [[TMP281]], align 4
-; POST-PROCESS-NEXT: [[TMP282:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; POST-PROCESS-NEXT: [[TMP283:%.*]] = inttoptr i32 [[TMP282]] to ptr addrspace(21)
-; POST-PROCESS-NEXT: [[TMP284:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP283]], i32 -30
-; POST-PROCESS-NEXT: [[TMP285:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP284]], i32 0, i32 0, i64 56
-; POST-PROCESS-NEXT: store i32 [[TMP177]], ptr addrspace(21) [[TMP285]], align 4
-; POST-PROCESS-NEXT: [[TMP286:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP287:%.*]] = add i32 [[TMP286]], -108
-; POST-PROCESS-NEXT: store i32 [[TMP287]], ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: [[TMP288:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[DOTFCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[TMP288]], i32 0, i32 0
-; POST-PROCESS-NEXT: [[DOTFCA_0_LOAD:%.*]] = load i32, ptr [[DOTFCA_0_GEP]], align 4
-; POST-PROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, i32 [[DOTFCA_0_LOAD]], 0
-; POST-PROCESS-NEXT: [[TMP289:%.*]] = load i32, ptr [[CSP]], align 4
-; POST-PROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP289]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount !17
+; POST-PROCESS-NEXT: [[TMP281:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(21) [[TMP280]], i32 0, i32 0, i64 56
+; POST-PROCESS-NEXT: store i32 [[TMP163]], ptr addrspace(21) [[TMP281]], align 4
+; POST-PROCESS-NEXT: [[TMP282:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP283:%.*]] = add i32 [[TMP282]], 12
+; POST-PROCESS-NEXT: store i32 [[TMP283]], ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP284:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP285:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @ClosestHit.resume.0 to i64))
+; POST-PROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 4, i32 [[TMP284]], i64 [[TMP285]], [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]]), !continuation.registercount [[META17]], !continuation.returnedRegistercount !17
; POST-PROCESS-NEXT: unreachable
;
+;
+; POST-PROCESS-LABEL: define dso_local void @ClosestHit.resume.0(
+; POST-PROCESS-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.shaderstage [[META24]] !continuation.registercount [[META17]] !continuation [[META25]] {
+; POST-PROCESS-NEXT: entryresume.0:
+; POST-PROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
+; POST-PROCESS-NEXT: store i32 [[TMP0]], ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP2:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], -12
+; POST-PROCESS-NEXT: store i32 [[TMP3]], ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP4]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP5]], i64 0
+; POST-PROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP18:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP19:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP22:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP23:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP24:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP25:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP27:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP28:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP29:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP30:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP31:%.*]] = inttoptr i32 [[TMP30]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP32:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP31]], i32 -30
+; POST-PROCESS-NEXT: [[TMP33:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP32]], i32 0, i32 0, i64 30
+; POST-PROCESS-NEXT: [[TMP34:%.*]] = load i32, ptr addrspace(21) [[TMP33]], align 4
+; POST-PROCESS-NEXT: [[TMP35:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP36:%.*]] = inttoptr i32 [[TMP35]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP37:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP36]], i32 -30
+; POST-PROCESS-NEXT: [[TMP38:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP37]], i32 0, i32 0, i64 31
+; POST-PROCESS-NEXT: [[TMP39:%.*]] = load i32, ptr addrspace(21) [[TMP38]], align 4
+; POST-PROCESS-NEXT: [[TMP40:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP41:%.*]] = inttoptr i32 [[TMP40]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP42:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP41]], i32 -30
+; POST-PROCESS-NEXT: [[TMP43:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP42]], i32 0, i32 0, i64 32
+; POST-PROCESS-NEXT: [[TMP44:%.*]] = load i32, ptr addrspace(21) [[TMP43]], align 4
+; POST-PROCESS-NEXT: [[TMP45:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP46:%.*]] = inttoptr i32 [[TMP45]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP47:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP46]], i32 -30
+; POST-PROCESS-NEXT: [[TMP48:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP47]], i32 0, i32 0, i64 33
+; POST-PROCESS-NEXT: [[TMP49:%.*]] = load i32, ptr addrspace(21) [[TMP48]], align 4
+; POST-PROCESS-NEXT: [[TMP50:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP51:%.*]] = inttoptr i32 [[TMP50]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP52:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP51]], i32 -30
+; POST-PROCESS-NEXT: [[TMP53:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP52]], i32 0, i32 0, i64 34
+; POST-PROCESS-NEXT: [[TMP54:%.*]] = load i32, ptr addrspace(21) [[TMP53]], align 4
+; POST-PROCESS-NEXT: [[TMP55:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP56:%.*]] = inttoptr i32 [[TMP55]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP57:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP56]], i32 -30
+; POST-PROCESS-NEXT: [[TMP58:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP57]], i32 0, i32 0, i64 35
+; POST-PROCESS-NEXT: [[TMP59:%.*]] = load i32, ptr addrspace(21) [[TMP58]], align 4
+; POST-PROCESS-NEXT: [[TMP60:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP61:%.*]] = inttoptr i32 [[TMP60]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP62:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP61]], i32 -30
+; POST-PROCESS-NEXT: [[TMP63:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP62]], i32 0, i32 0, i64 36
+; POST-PROCESS-NEXT: [[TMP64:%.*]] = load i32, ptr addrspace(21) [[TMP63]], align 4
+; POST-PROCESS-NEXT: [[TMP65:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP66:%.*]] = inttoptr i32 [[TMP65]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP67:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP66]], i32 -30
+; POST-PROCESS-NEXT: [[TMP68:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP67]], i32 0, i32 0, i64 37
+; POST-PROCESS-NEXT: [[TMP69:%.*]] = load i32, ptr addrspace(21) [[TMP68]], align 4
+; POST-PROCESS-NEXT: [[TMP70:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP71:%.*]] = inttoptr i32 [[TMP70]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP72:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP71]], i32 -30
+; POST-PROCESS-NEXT: [[TMP73:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP72]], i32 0, i32 0, i64 38
+; POST-PROCESS-NEXT: [[TMP74:%.*]] = load i32, ptr addrspace(21) [[TMP73]], align 4
+; POST-PROCESS-NEXT: [[TMP75:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP76:%.*]] = inttoptr i32 [[TMP75]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP77:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP76]], i32 -30
+; POST-PROCESS-NEXT: [[TMP78:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP77]], i32 0, i32 0, i64 39
+; POST-PROCESS-NEXT: [[TMP79:%.*]] = load i32, ptr addrspace(21) [[TMP78]], align 4
+; POST-PROCESS-NEXT: [[TMP80:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP81:%.*]] = inttoptr i32 [[TMP80]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP82:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP81]], i32 -30
+; POST-PROCESS-NEXT: [[TMP83:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP82]], i32 0, i32 0, i64 40
+; POST-PROCESS-NEXT: [[TMP84:%.*]] = load i32, ptr addrspace(21) [[TMP83]], align 4
+; POST-PROCESS-NEXT: [[TMP85:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP86:%.*]] = inttoptr i32 [[TMP85]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP87:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP86]], i32 -30
+; POST-PROCESS-NEXT: [[TMP88:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP87]], i32 0, i32 0, i64 41
+; POST-PROCESS-NEXT: [[TMP89:%.*]] = load i32, ptr addrspace(21) [[TMP88]], align 4
+; POST-PROCESS-NEXT: [[TMP90:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP91:%.*]] = inttoptr i32 [[TMP90]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP92:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP91]], i32 -30
+; POST-PROCESS-NEXT: [[TMP93:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP92]], i32 0, i32 0, i64 42
+; POST-PROCESS-NEXT: [[TMP94:%.*]] = load i32, ptr addrspace(21) [[TMP93]], align 4
+; POST-PROCESS-NEXT: [[TMP95:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP96:%.*]] = inttoptr i32 [[TMP95]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP97:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP96]], i32 -30
+; POST-PROCESS-NEXT: [[TMP98:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP97]], i32 0, i32 0, i64 43
+; POST-PROCESS-NEXT: [[TMP99:%.*]] = load i32, ptr addrspace(21) [[TMP98]], align 4
+; POST-PROCESS-NEXT: [[TMP100:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP101:%.*]] = inttoptr i32 [[TMP100]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP102:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP101]], i32 -30
+; POST-PROCESS-NEXT: [[TMP103:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP102]], i32 0, i32 0, i64 44
+; POST-PROCESS-NEXT: [[TMP104:%.*]] = load i32, ptr addrspace(21) [[TMP103]], align 4
+; POST-PROCESS-NEXT: [[TMP105:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP106:%.*]] = inttoptr i32 [[TMP105]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP107:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP106]], i32 -30
+; POST-PROCESS-NEXT: [[TMP108:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP107]], i32 0, i32 0, i64 45
+; POST-PROCESS-NEXT: [[TMP109:%.*]] = load i32, ptr addrspace(21) [[TMP108]], align 4
+; POST-PROCESS-NEXT: [[TMP110:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP111:%.*]] = inttoptr i32 [[TMP110]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP112:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP111]], i32 -30
+; POST-PROCESS-NEXT: [[TMP113:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP112]], i32 0, i32 0, i64 46
+; POST-PROCESS-NEXT: [[TMP114:%.*]] = load i32, ptr addrspace(21) [[TMP113]], align 4
+; POST-PROCESS-NEXT: [[TMP115:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP116:%.*]] = inttoptr i32 [[TMP115]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP117:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP116]], i32 -30
+; POST-PROCESS-NEXT: [[TMP118:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP117]], i32 0, i32 0, i64 47
+; POST-PROCESS-NEXT: [[TMP119:%.*]] = load i32, ptr addrspace(21) [[TMP118]], align 4
+; POST-PROCESS-NEXT: [[TMP120:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP121:%.*]] = inttoptr i32 [[TMP120]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP122:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP121]], i32 -30
+; POST-PROCESS-NEXT: [[TMP123:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP122]], i32 0, i32 0, i64 48
+; POST-PROCESS-NEXT: [[TMP124:%.*]] = load i32, ptr addrspace(21) [[TMP123]], align 4
+; POST-PROCESS-NEXT: [[TMP125:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP126:%.*]] = inttoptr i32 [[TMP125]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP127:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP126]], i32 -30
+; POST-PROCESS-NEXT: [[TMP128:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP127]], i32 0, i32 0, i64 49
+; POST-PROCESS-NEXT: [[TMP129:%.*]] = load i32, ptr addrspace(21) [[TMP128]], align 4
+; POST-PROCESS-NEXT: [[TMP130:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP131:%.*]] = inttoptr i32 [[TMP130]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP132:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP131]], i32 -30
+; POST-PROCESS-NEXT: [[TMP133:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP132]], i32 0, i32 0, i64 50
+; POST-PROCESS-NEXT: [[TMP134:%.*]] = load i32, ptr addrspace(21) [[TMP133]], align 4
+; POST-PROCESS-NEXT: [[TMP135:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP136:%.*]] = inttoptr i32 [[TMP135]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP137:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP136]], i32 -30
+; POST-PROCESS-NEXT: [[TMP138:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP137]], i32 0, i32 0, i64 51
+; POST-PROCESS-NEXT: [[TMP139:%.*]] = load i32, ptr addrspace(21) [[TMP138]], align 4
+; POST-PROCESS-NEXT: [[TMP140:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP141:%.*]] = inttoptr i32 [[TMP140]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP142:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP141]], i32 -30
+; POST-PROCESS-NEXT: [[TMP143:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP142]], i32 0, i32 0, i64 52
+; POST-PROCESS-NEXT: [[TMP144:%.*]] = load i32, ptr addrspace(21) [[TMP143]], align 4
+; POST-PROCESS-NEXT: [[TMP145:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP146:%.*]] = inttoptr i32 [[TMP145]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP147:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP146]], i32 -30
+; POST-PROCESS-NEXT: [[TMP148:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP147]], i32 0, i32 0, i64 53
+; POST-PROCESS-NEXT: [[TMP149:%.*]] = load i32, ptr addrspace(21) [[TMP148]], align 4
+; POST-PROCESS-NEXT: [[TMP150:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP151:%.*]] = inttoptr i32 [[TMP150]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP152:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP151]], i32 -30
+; POST-PROCESS-NEXT: [[TMP153:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP152]], i32 0, i32 0, i64 54
+; POST-PROCESS-NEXT: [[TMP154:%.*]] = load i32, ptr addrspace(21) [[TMP153]], align 4
+; POST-PROCESS-NEXT: [[TMP155:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP156:%.*]] = inttoptr i32 [[TMP155]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP157:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP156]], i32 -30
+; POST-PROCESS-NEXT: [[TMP158:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP157]], i32 0, i32 0, i64 55
+; POST-PROCESS-NEXT: [[TMP159:%.*]] = load i32, ptr addrspace(21) [[TMP158]], align 4
+; POST-PROCESS-NEXT: [[TMP160:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP161:%.*]] = inttoptr i32 [[TMP160]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP162:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP161]], i32 -30
+; POST-PROCESS-NEXT: [[TMP163:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP162]], i32 0, i32 0, i64 56
+; POST-PROCESS-NEXT: [[TMP164:%.*]] = load i32, ptr addrspace(21) [[TMP163]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
+; POST-PROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; POST-PROCESS-NEXT: [[DOTRELOAD_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME:%.*]], ptr addrspace(21) [[TMP6]], i32 0, i32 1
+; POST-PROCESS-NEXT: [[DOTRELOAD:%.*]] = load i32, ptr addrspace(21) [[DOTRELOAD_ADDR]], align 4
+; POST-PROCESS-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME]], ptr addrspace(21) [[TMP6]], i32 0, i32 0
+; POST-PROCESS-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr addrspace(21) [[RETURNADDR_RELOAD_ADDR]], align 4
+; POST-PROCESS-NEXT: store i32 [[DOTRELOAD]], ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: store i32 [[TMP7]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP8]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP9]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP10]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP11]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP12]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP13]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP14]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP15]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP16]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP17]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP18]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP19]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP20]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP21]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP22]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP23]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP24]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP25]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP26]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP27]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP28]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: store i32 [[TMP29]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
+; POST-PROCESS-NEXT: [[TMP165:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP166:%.*]] = inttoptr i32 [[TMP165]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP167:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP166]], i32 -30
+; POST-PROCESS-NEXT: [[TMP168:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP167]], i32 0, i32 0, i64 30
+; POST-PROCESS-NEXT: store i32 [[TMP34]], ptr addrspace(21) [[TMP168]], align 4
+; POST-PROCESS-NEXT: [[TMP169:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP170:%.*]] = inttoptr i32 [[TMP169]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP171:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP170]], i32 -30
+; POST-PROCESS-NEXT: [[TMP172:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP171]], i32 0, i32 0, i64 31
+; POST-PROCESS-NEXT: store i32 [[TMP39]], ptr addrspace(21) [[TMP172]], align 4
+; POST-PROCESS-NEXT: [[TMP173:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP174:%.*]] = inttoptr i32 [[TMP173]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP175:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP174]], i32 -30
+; POST-PROCESS-NEXT: [[TMP176:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP175]], i32 0, i32 0, i64 32
+; POST-PROCESS-NEXT: store i32 [[TMP44]], ptr addrspace(21) [[TMP176]], align 4
+; POST-PROCESS-NEXT: [[TMP177:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP178:%.*]] = inttoptr i32 [[TMP177]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP179:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP178]], i32 -30
+; POST-PROCESS-NEXT: [[TMP180:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP179]], i32 0, i32 0, i64 33
+; POST-PROCESS-NEXT: store i32 [[TMP49]], ptr addrspace(21) [[TMP180]], align 4
+; POST-PROCESS-NEXT: [[TMP181:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP182:%.*]] = inttoptr i32 [[TMP181]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP183:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP182]], i32 -30
+; POST-PROCESS-NEXT: [[TMP184:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP183]], i32 0, i32 0, i64 34
+; POST-PROCESS-NEXT: store i32 [[TMP54]], ptr addrspace(21) [[TMP184]], align 4
+; POST-PROCESS-NEXT: [[TMP185:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP186:%.*]] = inttoptr i32 [[TMP185]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP187:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP186]], i32 -30
+; POST-PROCESS-NEXT: [[TMP188:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP187]], i32 0, i32 0, i64 35
+; POST-PROCESS-NEXT: store i32 [[TMP59]], ptr addrspace(21) [[TMP188]], align 4
+; POST-PROCESS-NEXT: [[TMP189:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP190:%.*]] = inttoptr i32 [[TMP189]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP191:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP190]], i32 -30
+; POST-PROCESS-NEXT: [[TMP192:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP191]], i32 0, i32 0, i64 36
+; POST-PROCESS-NEXT: store i32 [[TMP64]], ptr addrspace(21) [[TMP192]], align 4
+; POST-PROCESS-NEXT: [[TMP193:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP194:%.*]] = inttoptr i32 [[TMP193]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP195:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP194]], i32 -30
+; POST-PROCESS-NEXT: [[TMP196:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP195]], i32 0, i32 0, i64 37
+; POST-PROCESS-NEXT: store i32 [[TMP69]], ptr addrspace(21) [[TMP196]], align 4
+; POST-PROCESS-NEXT: [[TMP197:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP198:%.*]] = inttoptr i32 [[TMP197]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP199:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP198]], i32 -30
+; POST-PROCESS-NEXT: [[TMP200:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP199]], i32 0, i32 0, i64 38
+; POST-PROCESS-NEXT: store i32 [[TMP74]], ptr addrspace(21) [[TMP200]], align 4
+; POST-PROCESS-NEXT: [[TMP201:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP202:%.*]] = inttoptr i32 [[TMP201]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP203:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP202]], i32 -30
+; POST-PROCESS-NEXT: [[TMP204:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP203]], i32 0, i32 0, i64 39
+; POST-PROCESS-NEXT: store i32 [[TMP79]], ptr addrspace(21) [[TMP204]], align 4
+; POST-PROCESS-NEXT: [[TMP205:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP206:%.*]] = inttoptr i32 [[TMP205]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP207:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP206]], i32 -30
+; POST-PROCESS-NEXT: [[TMP208:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP207]], i32 0, i32 0, i64 40
+; POST-PROCESS-NEXT: store i32 [[TMP84]], ptr addrspace(21) [[TMP208]], align 4
+; POST-PROCESS-NEXT: [[TMP209:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP210:%.*]] = inttoptr i32 [[TMP209]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP211:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP210]], i32 -30
+; POST-PROCESS-NEXT: [[TMP212:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP211]], i32 0, i32 0, i64 41
+; POST-PROCESS-NEXT: store i32 [[TMP89]], ptr addrspace(21) [[TMP212]], align 4
+; POST-PROCESS-NEXT: [[TMP213:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP214:%.*]] = inttoptr i32 [[TMP213]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP215:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP214]], i32 -30
+; POST-PROCESS-NEXT: [[TMP216:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP215]], i32 0, i32 0, i64 42
+; POST-PROCESS-NEXT: store i32 [[TMP94]], ptr addrspace(21) [[TMP216]], align 4
+; POST-PROCESS-NEXT: [[TMP217:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP218:%.*]] = inttoptr i32 [[TMP217]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP219:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP218]], i32 -30
+; POST-PROCESS-NEXT: [[TMP220:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP219]], i32 0, i32 0, i64 43
+; POST-PROCESS-NEXT: store i32 [[TMP99]], ptr addrspace(21) [[TMP220]], align 4
+; POST-PROCESS-NEXT: [[TMP221:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP222:%.*]] = inttoptr i32 [[TMP221]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP223:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP222]], i32 -30
+; POST-PROCESS-NEXT: [[TMP224:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP223]], i32 0, i32 0, i64 44
+; POST-PROCESS-NEXT: store i32 [[TMP104]], ptr addrspace(21) [[TMP224]], align 4
+; POST-PROCESS-NEXT: [[TMP225:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP226:%.*]] = inttoptr i32 [[TMP225]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP227:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP226]], i32 -30
+; POST-PROCESS-NEXT: [[TMP228:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP227]], i32 0, i32 0, i64 45
+; POST-PROCESS-NEXT: store i32 [[TMP109]], ptr addrspace(21) [[TMP228]], align 4
+; POST-PROCESS-NEXT: [[TMP229:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP230:%.*]] = inttoptr i32 [[TMP229]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP231:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP230]], i32 -30
+; POST-PROCESS-NEXT: [[TMP232:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP231]], i32 0, i32 0, i64 46
+; POST-PROCESS-NEXT: store i32 [[TMP114]], ptr addrspace(21) [[TMP232]], align 4
+; POST-PROCESS-NEXT: [[TMP233:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP234:%.*]] = inttoptr i32 [[TMP233]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP235:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP234]], i32 -30
+; POST-PROCESS-NEXT: [[TMP236:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP235]], i32 0, i32 0, i64 47
+; POST-PROCESS-NEXT: store i32 [[TMP119]], ptr addrspace(21) [[TMP236]], align 4
+; POST-PROCESS-NEXT: [[TMP237:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP238:%.*]] = inttoptr i32 [[TMP237]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP239:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP238]], i32 -30
+; POST-PROCESS-NEXT: [[TMP240:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP239]], i32 0, i32 0, i64 48
+; POST-PROCESS-NEXT: store i32 [[TMP124]], ptr addrspace(21) [[TMP240]], align 4
+; POST-PROCESS-NEXT: [[TMP241:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP242:%.*]] = inttoptr i32 [[TMP241]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP243:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP242]], i32 -30
+; POST-PROCESS-NEXT: [[TMP244:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP243]], i32 0, i32 0, i64 49
+; POST-PROCESS-NEXT: store i32 [[TMP129]], ptr addrspace(21) [[TMP244]], align 4
+; POST-PROCESS-NEXT: [[TMP245:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP246:%.*]] = inttoptr i32 [[TMP245]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP247:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP246]], i32 -30
+; POST-PROCESS-NEXT: [[TMP248:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP247]], i32 0, i32 0, i64 50
+; POST-PROCESS-NEXT: store i32 [[TMP134]], ptr addrspace(21) [[TMP248]], align 4
+; POST-PROCESS-NEXT: [[TMP249:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP250:%.*]] = inttoptr i32 [[TMP249]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP251:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP250]], i32 -30
+; POST-PROCESS-NEXT: [[TMP252:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP251]], i32 0, i32 0, i64 51
+; POST-PROCESS-NEXT: store i32 [[TMP139]], ptr addrspace(21) [[TMP252]], align 4
+; POST-PROCESS-NEXT: [[TMP253:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP254:%.*]] = inttoptr i32 [[TMP253]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP255:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP254]], i32 -30
+; POST-PROCESS-NEXT: [[TMP256:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP255]], i32 0, i32 0, i64 52
+; POST-PROCESS-NEXT: store i32 [[TMP144]], ptr addrspace(21) [[TMP256]], align 4
+; POST-PROCESS-NEXT: [[TMP257:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP258:%.*]] = inttoptr i32 [[TMP257]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP259:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP258]], i32 -30
+; POST-PROCESS-NEXT: [[TMP260:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP259]], i32 0, i32 0, i64 53
+; POST-PROCESS-NEXT: store i32 [[TMP149]], ptr addrspace(21) [[TMP260]], align 4
+; POST-PROCESS-NEXT: [[TMP261:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP262:%.*]] = inttoptr i32 [[TMP261]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP263:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP262]], i32 -30
+; POST-PROCESS-NEXT: [[TMP264:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP263]], i32 0, i32 0, i64 54
+; POST-PROCESS-NEXT: store i32 [[TMP154]], ptr addrspace(21) [[TMP264]], align 4
+; POST-PROCESS-NEXT: [[TMP265:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP266:%.*]] = inttoptr i32 [[TMP265]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP267:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP266]], i32 -30
+; POST-PROCESS-NEXT: [[TMP268:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP267]], i32 0, i32 0, i64 55
+; POST-PROCESS-NEXT: store i32 [[TMP159]], ptr addrspace(21) [[TMP268]], align 4
+; POST-PROCESS-NEXT: [[TMP269:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-NEXT: [[TMP270:%.*]] = inttoptr i32 [[TMP269]] to ptr addrspace(21)
+; POST-PROCESS-NEXT: [[TMP271:%.*]] = getelementptr i32, ptr addrspace(21) [[TMP270]], i32 -30
+; POST-PROCESS-NEXT: [[TMP272:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(21) [[TMP271]], i32 0, i32 0, i64 56
+; POST-PROCESS-NEXT: store i32 [[TMP164]], ptr addrspace(21) [[TMP272]], align 4
+; POST-PROCESS-NEXT: [[TMP273:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[TMP274:%.*]] = add i32 [[TMP273]], -108
+; POST-PROCESS-NEXT: store i32 [[TMP274]], ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, <3 x i32> [[DOTFCA_0_EXTRACT]], 0
+; POST-PROCESS-NEXT: [[TMP275:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP275]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META17]]
+; POST-PROCESS-NEXT: unreachable
+;
+;
+; POST-PROCESS-GLOBAL-LABEL: define %struct.BuiltInTriangleIntersectionAttributes @_cont_GetTriangleHitAttributes(
+; POST-PROCESS-GLOBAL-SAME: ptr [[DATA:%.*]]) #[[ATTR0:[0-9]+]] {
+; POST-PROCESS-GLOBAL-NEXT: [[ADDR:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[DATA]], i32 0, i32 1
+; POST-PROCESS-GLOBAL-NEXT: [[VAL:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]], ptr [[ADDR]], align 4
+; POST-PROCESS-GLOBAL-NEXT: ret [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[VAL]]
+;
+;
+; POST-PROCESS-GLOBAL-LABEL: define i32 @_cont_GetLocalRootIndex(
+; POST-PROCESS-GLOBAL-SAME: ptr [[DATA:%.*]]) #[[ATTR0]] {
+; POST-PROCESS-GLOBAL-NEXT: ret i32 5
+;
+;
+; POST-PROCESS-GLOBAL-LABEL: define void @main(
+; POST-PROCESS-GLOBAL-SAME: ) !lgc.rt.shaderstage [[META8:![0-9]+]] !continuation.entry [[META19:![0-9]+]] !continuation.registercount [[META8]] !continuation [[META20:![0-9]+]] !continuation.stacksize [[META21:![0-9]+]] !continuation.state [[META8]] {
+; POST-PROCESS-GLOBAL-NEXT: AllocaSpillBB:
+; POST-PROCESS-GLOBAL-NEXT: [[CSP:%.*]] = alloca i32, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[SYSTEM_DATA:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA:%.*]] @_cont_SetupRayGen()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP0:%.*]] = call i32 @_cont_GetContinuationStackAddr()
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP0]], ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[SYSTEM_DATA]], 0
+; POST-PROCESS-GLOBAL-NEXT: [[TMP1:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 108
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP2]], ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP3:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP4:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP5:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP3]])
+; POST-PROCESS-GLOBAL-NEXT: [[TMP6:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP5]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
+; POST-PROCESS-GLOBAL-NEXT: [[TMP7:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[TMP6]])
+; POST-PROCESS-GLOBAL-NEXT: [[DIS_DATA_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, <3 x i32> [[DOTFCA_0_EXTRACT]], 0
+; POST-PROCESS-GLOBAL-NEXT: [[SYS_DATA_I:%.*]] = insertvalue [[STRUCT_SYSTEMDATA:%.*]] undef, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I_FCA_0_INSERT]], 0
+; POST-PROCESS-GLOBAL-NEXT: [[TRAV_DATA_I:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA:%.*]] undef, [[STRUCT_SYSTEMDATA]] [[SYS_DATA_I]], 0
+; POST-PROCESS-GLOBAL-NEXT: [[TMP8:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP9:%.*]] = add i32 [[TMP8]], -108
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP9]], ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP11:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP12]], i32 [[TMP10]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP13]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP15:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP14]], i32 0, i32 0, i64 30
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP15]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP17:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP18]], i32 [[TMP16]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP19]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP21:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP20]], i32 0, i32 0, i64 31
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP21]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP22:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP23:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP23]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP24]], i32 [[TMP22]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP25]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP27:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP26]], i32 0, i32 0, i64 32
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP27]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP28:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP29:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP30:%.*]] = inttoptr i64 [[TMP29]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP31:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP30]], i32 [[TMP28]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP32:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP31]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP33:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP32]], i32 0, i32 0, i64 33
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP33]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP34:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP35:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP36:%.*]] = inttoptr i64 [[TMP35]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP37:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP36]], i32 [[TMP34]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP38:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP37]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP39:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP38]], i32 0, i32 0, i64 34
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP39]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP40:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP41:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP42:%.*]] = inttoptr i64 [[TMP41]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP43:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP42]], i32 [[TMP40]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP44:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP43]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP45:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP44]], i32 0, i32 0, i64 35
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP45]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP46:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP47:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP48:%.*]] = inttoptr i64 [[TMP47]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP49:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP48]], i32 [[TMP46]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP50:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP49]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP51:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP50]], i32 0, i32 0, i64 36
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP51]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP52:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP53:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP54:%.*]] = inttoptr i64 [[TMP53]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP55:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP54]], i32 [[TMP52]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP56:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP55]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP57:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP56]], i32 0, i32 0, i64 37
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP57]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP58:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP59:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP60:%.*]] = inttoptr i64 [[TMP59]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP61:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP60]], i32 [[TMP58]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP62:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP61]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP63:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP62]], i32 0, i32 0, i64 38
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP63]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP64:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP65:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP66:%.*]] = inttoptr i64 [[TMP65]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP67:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP66]], i32 [[TMP64]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP68:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP67]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP69:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP68]], i32 0, i32 0, i64 39
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP69]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP70:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP71:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP72:%.*]] = inttoptr i64 [[TMP71]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP73:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP72]], i32 [[TMP70]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP74:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP73]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP75:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP74]], i32 0, i32 0, i64 40
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP75]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP76:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP77:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP78:%.*]] = inttoptr i64 [[TMP77]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP79:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP78]], i32 [[TMP76]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP80:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP79]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP81:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP80]], i32 0, i32 0, i64 41
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP81]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP82:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP83:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP84:%.*]] = inttoptr i64 [[TMP83]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP85:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP84]], i32 [[TMP82]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP86:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP85]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP87:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP86]], i32 0, i32 0, i64 42
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP87]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP88:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP89:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP90:%.*]] = inttoptr i64 [[TMP89]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP91:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP90]], i32 [[TMP88]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP92:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP91]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP93:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP92]], i32 0, i32 0, i64 43
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP93]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP94:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP95:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP96:%.*]] = inttoptr i64 [[TMP95]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP97:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP96]], i32 [[TMP94]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP98:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP97]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP99:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP98]], i32 0, i32 0, i64 44
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP99]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP100:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP101:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP102:%.*]] = inttoptr i64 [[TMP101]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP103:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP102]], i32 [[TMP100]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP104:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP103]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP105:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP104]], i32 0, i32 0, i64 45
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP105]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP106:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP107:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP108:%.*]] = inttoptr i64 [[TMP107]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP109:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP108]], i32 [[TMP106]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP110:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP109]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP111:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP110]], i32 0, i32 0, i64 46
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP111]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP112:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP113:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP114:%.*]] = inttoptr i64 [[TMP113]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP115:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP114]], i32 [[TMP112]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP116:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP115]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP117:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP116]], i32 0, i32 0, i64 47
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP117]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP118:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP119:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP120:%.*]] = inttoptr i64 [[TMP119]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP121:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP120]], i32 [[TMP118]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP122:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP121]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP123:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP122]], i32 0, i32 0, i64 48
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP123]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP124:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP125:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP126:%.*]] = inttoptr i64 [[TMP125]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP127:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP126]], i32 [[TMP124]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP128:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP127]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP129:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP128]], i32 0, i32 0, i64 49
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP129]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP130:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP131:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP132:%.*]] = inttoptr i64 [[TMP131]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP133:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP132]], i32 [[TMP130]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP134:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP133]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP135:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP134]], i32 0, i32 0, i64 50
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP135]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP136:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP137:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP138:%.*]] = inttoptr i64 [[TMP137]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP139:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP138]], i32 [[TMP136]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP140:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP139]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP141:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP140]], i32 0, i32 0, i64 51
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP141]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP142:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP143:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP144:%.*]] = inttoptr i64 [[TMP143]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP145:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP144]], i32 [[TMP142]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP146:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP145]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP147:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP146]], i32 0, i32 0, i64 52
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP147]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP148:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP149:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP150:%.*]] = inttoptr i64 [[TMP149]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP151:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP150]], i32 [[TMP148]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP152:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP151]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP153:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP152]], i32 0, i32 0, i64 53
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP153]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP154:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP155:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP156:%.*]] = inttoptr i64 [[TMP155]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP157:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP156]], i32 [[TMP154]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP158:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP157]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP159:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP158]], i32 0, i32 0, i64 54
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP159]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP160:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP161:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP162:%.*]] = inttoptr i64 [[TMP161]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP163:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP162]], i32 [[TMP160]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP164:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP163]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP165:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP164]], i32 0, i32 0, i64 55
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP165]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP166:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP167:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP168:%.*]] = inttoptr i64 [[TMP167]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP169:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP168]], i32 [[TMP166]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP170:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP169]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP171:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP170]], i32 0, i32 0, i64 56
+; POST-PROCESS-GLOBAL-NEXT: store i32 undef, ptr addrspace(22) [[TMP171]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP172:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP173:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @main.resume.0 to i64))
+; POST-PROCESS-GLOBAL-NEXT: call void (i64, ...) @continuation.continue(i64 4, i32 [[TMP172]], i64 [[TMP173]], [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]]), !continuation.registercount [[META18:![0-9]+]], !continuation.returnedRegistercount !18
+; POST-PROCESS-GLOBAL-NEXT: unreachable
+;
+;
+; POST-PROCESS-GLOBAL-LABEL: define dso_local void @main.resume.0(
+; POST-PROCESS-GLOBAL-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.shaderstage [[META8]] !continuation.registercount [[META18]] !continuation [[META20]] {
+; POST-PROCESS-GLOBAL-NEXT: entryresume.0:
+; POST-PROCESS-GLOBAL-NEXT: [[CSP:%.*]] = alloca i32, align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP0]], ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP5:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP18:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP19:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP22:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP23:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP24:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP25:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP26:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP27:%.*]] = inttoptr i64 [[TMP26]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP27]], i32 [[TMP25]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP28]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP30:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP29]], i32 0, i32 0, i64 30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(22) [[TMP30]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP32:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP33:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP34:%.*]] = inttoptr i64 [[TMP33]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP35:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP34]], i32 [[TMP32]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP36:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP35]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP37:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP36]], i32 0, i32 0, i64 31
+; POST-PROCESS-GLOBAL-NEXT: [[TMP38:%.*]] = load i32, ptr addrspace(22) [[TMP37]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP39:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP40:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP41:%.*]] = inttoptr i64 [[TMP40]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP42:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP41]], i32 [[TMP39]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP43:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP42]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP44:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP43]], i32 0, i32 0, i64 32
+; POST-PROCESS-GLOBAL-NEXT: [[TMP45:%.*]] = load i32, ptr addrspace(22) [[TMP44]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP46:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP47:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP48:%.*]] = inttoptr i64 [[TMP47]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP49:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP48]], i32 [[TMP46]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP50:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP49]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP51:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP50]], i32 0, i32 0, i64 33
+; POST-PROCESS-GLOBAL-NEXT: [[TMP52:%.*]] = load i32, ptr addrspace(22) [[TMP51]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP53:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP54:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP55:%.*]] = inttoptr i64 [[TMP54]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP55]], i32 [[TMP53]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP57:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP56]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP58:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP57]], i32 0, i32 0, i64 34
+; POST-PROCESS-GLOBAL-NEXT: [[TMP59:%.*]] = load i32, ptr addrspace(22) [[TMP58]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP60:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP61:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP62:%.*]] = inttoptr i64 [[TMP61]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP63:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP62]], i32 [[TMP60]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP63]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP65:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP64]], i32 0, i32 0, i64 35
+; POST-PROCESS-GLOBAL-NEXT: [[TMP66:%.*]] = load i32, ptr addrspace(22) [[TMP65]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP67:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP68:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP69:%.*]] = inttoptr i64 [[TMP68]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP70:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP69]], i32 [[TMP67]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP71:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP70]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP72:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP71]], i32 0, i32 0, i64 36
+; POST-PROCESS-GLOBAL-NEXT: [[TMP73:%.*]] = load i32, ptr addrspace(22) [[TMP72]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP74:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP75:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP76:%.*]] = inttoptr i64 [[TMP75]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP77:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP76]], i32 [[TMP74]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP78:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP77]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP79:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP78]], i32 0, i32 0, i64 37
+; POST-PROCESS-GLOBAL-NEXT: [[TMP80:%.*]] = load i32, ptr addrspace(22) [[TMP79]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP81:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP82:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP83:%.*]] = inttoptr i64 [[TMP82]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP84:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP83]], i32 [[TMP81]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP85:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP84]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP86:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP85]], i32 0, i32 0, i64 38
+; POST-PROCESS-GLOBAL-NEXT: [[TMP87:%.*]] = load i32, ptr addrspace(22) [[TMP86]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP88:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP89:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP90:%.*]] = inttoptr i64 [[TMP89]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP91:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP90]], i32 [[TMP88]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP92:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP91]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP93:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP92]], i32 0, i32 0, i64 39
+; POST-PROCESS-GLOBAL-NEXT: [[TMP94:%.*]] = load i32, ptr addrspace(22) [[TMP93]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP95:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP96:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP97:%.*]] = inttoptr i64 [[TMP96]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP98:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP97]], i32 [[TMP95]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP99:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP98]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP100:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP99]], i32 0, i32 0, i64 40
+; POST-PROCESS-GLOBAL-NEXT: [[TMP101:%.*]] = load i32, ptr addrspace(22) [[TMP100]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP102:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP103:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP104:%.*]] = inttoptr i64 [[TMP103]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP105:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP104]], i32 [[TMP102]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP106:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP105]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP107:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP106]], i32 0, i32 0, i64 41
+; POST-PROCESS-GLOBAL-NEXT: [[TMP108:%.*]] = load i32, ptr addrspace(22) [[TMP107]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP109:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP110:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP111:%.*]] = inttoptr i64 [[TMP110]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP112:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP111]], i32 [[TMP109]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP113:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP112]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP114:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP113]], i32 0, i32 0, i64 42
+; POST-PROCESS-GLOBAL-NEXT: [[TMP115:%.*]] = load i32, ptr addrspace(22) [[TMP114]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP116:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP117:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP118:%.*]] = inttoptr i64 [[TMP117]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP119:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP118]], i32 [[TMP116]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP120:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP119]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP121:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP120]], i32 0, i32 0, i64 43
+; POST-PROCESS-GLOBAL-NEXT: [[TMP122:%.*]] = load i32, ptr addrspace(22) [[TMP121]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP123:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP124:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP125:%.*]] = inttoptr i64 [[TMP124]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP126:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP125]], i32 [[TMP123]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP127:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP126]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP128:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP127]], i32 0, i32 0, i64 44
+; POST-PROCESS-GLOBAL-NEXT: [[TMP129:%.*]] = load i32, ptr addrspace(22) [[TMP128]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP130:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP131:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP132:%.*]] = inttoptr i64 [[TMP131]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP133:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP132]], i32 [[TMP130]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP134:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP133]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP135:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP134]], i32 0, i32 0, i64 45
+; POST-PROCESS-GLOBAL-NEXT: [[TMP136:%.*]] = load i32, ptr addrspace(22) [[TMP135]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP137:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP138:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP139:%.*]] = inttoptr i64 [[TMP138]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP140:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP139]], i32 [[TMP137]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP141:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP140]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP142:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP141]], i32 0, i32 0, i64 46
+; POST-PROCESS-GLOBAL-NEXT: [[TMP143:%.*]] = load i32, ptr addrspace(22) [[TMP142]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP144:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP145:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP146:%.*]] = inttoptr i64 [[TMP145]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP147:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP146]], i32 [[TMP144]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP148:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP147]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP149:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP148]], i32 0, i32 0, i64 47
+; POST-PROCESS-GLOBAL-NEXT: [[TMP150:%.*]] = load i32, ptr addrspace(22) [[TMP149]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP151:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP152:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP153:%.*]] = inttoptr i64 [[TMP152]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP154:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP153]], i32 [[TMP151]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP155:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP154]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP156:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP155]], i32 0, i32 0, i64 48
+; POST-PROCESS-GLOBAL-NEXT: [[TMP157:%.*]] = load i32, ptr addrspace(22) [[TMP156]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP158:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP159:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP160:%.*]] = inttoptr i64 [[TMP159]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP161:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP160]], i32 [[TMP158]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP162:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP161]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP163:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP162]], i32 0, i32 0, i64 49
+; POST-PROCESS-GLOBAL-NEXT: [[TMP164:%.*]] = load i32, ptr addrspace(22) [[TMP163]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP165:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP166:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP167:%.*]] = inttoptr i64 [[TMP166]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP168:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP167]], i32 [[TMP165]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP169:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP168]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP170:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP169]], i32 0, i32 0, i64 50
+; POST-PROCESS-GLOBAL-NEXT: [[TMP171:%.*]] = load i32, ptr addrspace(22) [[TMP170]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP172:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP173:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP174:%.*]] = inttoptr i64 [[TMP173]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP175:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP174]], i32 [[TMP172]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP176:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP175]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP177:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP176]], i32 0, i32 0, i64 51
+; POST-PROCESS-GLOBAL-NEXT: [[TMP178:%.*]] = load i32, ptr addrspace(22) [[TMP177]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP179:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP180:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP181:%.*]] = inttoptr i64 [[TMP180]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP182:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP181]], i32 [[TMP179]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP183:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP182]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP184:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP183]], i32 0, i32 0, i64 52
+; POST-PROCESS-GLOBAL-NEXT: [[TMP185:%.*]] = load i32, ptr addrspace(22) [[TMP184]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP186:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP187:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP188:%.*]] = inttoptr i64 [[TMP187]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP189:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP188]], i32 [[TMP186]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP190:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP189]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP191:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP190]], i32 0, i32 0, i64 53
+; POST-PROCESS-GLOBAL-NEXT: [[TMP192:%.*]] = load i32, ptr addrspace(22) [[TMP191]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP193:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP194:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP195:%.*]] = inttoptr i64 [[TMP194]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP196:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP195]], i32 [[TMP193]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP197:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP196]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP198:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP197]], i32 0, i32 0, i64 54
+; POST-PROCESS-GLOBAL-NEXT: [[TMP199:%.*]] = load i32, ptr addrspace(22) [[TMP198]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP200:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP201:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP202:%.*]] = inttoptr i64 [[TMP201]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP203:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP202]], i32 [[TMP200]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP204:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP203]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP205:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP204]], i32 0, i32 0, i64 55
+; POST-PROCESS-GLOBAL-NEXT: [[TMP206:%.*]] = load i32, ptr addrspace(22) [[TMP205]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP207:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP208:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP209:%.*]] = inttoptr i64 [[TMP208]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP210:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP209]], i32 [[TMP207]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP211:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP210]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP212:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP211]], i32 0, i32 0, i64 56
+; POST-PROCESS-GLOBAL-NEXT: [[TMP213:%.*]] = load i32, ptr addrspace(22) [[TMP212]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_EXTRACT1:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
+; POST-PROCESS-GLOBAL-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP214:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP215:%.*]] = add i32 [[TMP214]], -108
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP215]], ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: call void @continuation.complete()
+; POST-PROCESS-GLOBAL-NEXT: unreachable
+;
+;
+; POST-PROCESS-GLOBAL-LABEL: define void @AnyHit(
+; POST-PROCESS-GLOBAL-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_ANYHITTRAVERSALDATA:%.*]] [[TMP0:%.*]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] !lgc.rt.shaderstage [[META22:![0-9]+]] !continuation.registercount [[META18]] !continuation [[META23:![0-9]+]] !continuation.state [[META8]] {
+; POST-PROCESS-GLOBAL-NEXT: AllocaSpillBB:
+; POST-PROCESS-GLOBAL-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_ANYHITTRAVERSALDATA]], align 8
+; POST-PROCESS-GLOBAL-NEXT: [[CSP:%.*]] = alloca i32, align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_0_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 0, 0, 0
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_0_0_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0, i32 0
+; POST-PROCESS-GLOBAL-NEXT: store <3 x i32> [[DOTFCA_0_0_0_0_EXTRACT]], ptr [[DOTFCA_0_0_0_0_GEP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_0_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 0, 1, 0
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_0_1_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 1, i32 0
+; POST-PROCESS-GLOBAL-NEXT: store <2 x float> [[DOTFCA_0_0_1_0_EXTRACT]], ptr [[DOTFCA_0_0_1_0_GEP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 1, 0
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_1_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 1, i32 0
+; POST-PROCESS-GLOBAL-NEXT: store float [[DOTFCA_0_1_0_EXTRACT]], ptr [[DOTFCA_0_1_0_GEP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 1, 1
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_1_1_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 1, i32 1
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[DOTFCA_0_1_1_EXTRACT]], ptr [[DOTFCA_0_1_1_GEP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_2_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 2
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_2_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 2
+; POST-PROCESS-GLOBAL-NEXT: store <3 x float> [[DOTFCA_0_2_EXTRACT]], ptr [[DOTFCA_0_2_GEP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_3_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 3
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_3_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 3
+; POST-PROCESS-GLOBAL-NEXT: store <3 x float> [[DOTFCA_0_3_EXTRACT]], ptr [[DOTFCA_0_3_GEP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_4_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_4_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 4
+; POST-PROCESS-GLOBAL-NEXT: store float [[DOTFCA_0_4_EXTRACT]], ptr [[DOTFCA_0_4_GEP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_5_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 0, 5
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_5_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 5
+; POST-PROCESS-GLOBAL-NEXT: store i64 [[DOTFCA_0_5_EXTRACT]], ptr [[DOTFCA_0_5_GEP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 1, 0
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_1_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 0
+; POST-PROCESS-GLOBAL-NEXT: store float [[DOTFCA_1_0_EXTRACT]], ptr [[DOTFCA_1_0_GEP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[TMP0]], 1, 1
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_1_1_GEP:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 1
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[DOTFCA_1_1_EXTRACT]], ptr [[DOTFCA_1_1_GEP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
+; POST-PROCESS-GLOBAL-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP5:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP18:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP19:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP22:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP23:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP24:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP25:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP27:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP28:%.*]] = inttoptr i64 [[TMP27]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP28]], i32 [[TMP26]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP30:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP29]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP31:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP30]], i32 0, i32 0, i64 30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP32:%.*]] = load i32, ptr addrspace(22) [[TMP31]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP33:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP34:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP35:%.*]] = inttoptr i64 [[TMP34]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP35]], i32 [[TMP33]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP37:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP36]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP38:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP37]], i32 0, i32 0, i64 31
+; POST-PROCESS-GLOBAL-NEXT: [[TMP39:%.*]] = load i32, ptr addrspace(22) [[TMP38]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP40:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP41:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP42:%.*]] = inttoptr i64 [[TMP41]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP43:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP42]], i32 [[TMP40]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP44:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP43]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP45:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP44]], i32 0, i32 0, i64 32
+; POST-PROCESS-GLOBAL-NEXT: [[TMP46:%.*]] = load i32, ptr addrspace(22) [[TMP45]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP47:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP48:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP49:%.*]] = inttoptr i64 [[TMP48]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP50:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP49]], i32 [[TMP47]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP51:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP50]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP52:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP51]], i32 0, i32 0, i64 33
+; POST-PROCESS-GLOBAL-NEXT: [[TMP53:%.*]] = load i32, ptr addrspace(22) [[TMP52]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP54:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP55:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP56:%.*]] = inttoptr i64 [[TMP55]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP57:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP56]], i32 [[TMP54]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP58:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP57]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP59:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP58]], i32 0, i32 0, i64 34
+; POST-PROCESS-GLOBAL-NEXT: [[TMP60:%.*]] = load i32, ptr addrspace(22) [[TMP59]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP61:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP62:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP63:%.*]] = inttoptr i64 [[TMP62]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP64:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP63]], i32 [[TMP61]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP65:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP64]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP66:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP65]], i32 0, i32 0, i64 35
+; POST-PROCESS-GLOBAL-NEXT: [[TMP67:%.*]] = load i32, ptr addrspace(22) [[TMP66]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP68:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP69:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP70:%.*]] = inttoptr i64 [[TMP69]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP71:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP70]], i32 [[TMP68]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP72:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP71]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP73:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP72]], i32 0, i32 0, i64 36
+; POST-PROCESS-GLOBAL-NEXT: [[TMP74:%.*]] = load i32, ptr addrspace(22) [[TMP73]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP75:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP76:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP77:%.*]] = inttoptr i64 [[TMP76]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP78:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP77]], i32 [[TMP75]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP79:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP78]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP80:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP79]], i32 0, i32 0, i64 37
+; POST-PROCESS-GLOBAL-NEXT: [[TMP81:%.*]] = load i32, ptr addrspace(22) [[TMP80]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP82:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP83:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP84:%.*]] = inttoptr i64 [[TMP83]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP85:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP84]], i32 [[TMP82]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP86:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP85]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP87:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP86]], i32 0, i32 0, i64 38
+; POST-PROCESS-GLOBAL-NEXT: [[TMP88:%.*]] = load i32, ptr addrspace(22) [[TMP87]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP89:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP90:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP91:%.*]] = inttoptr i64 [[TMP90]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP92:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP91]], i32 [[TMP89]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP93:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP92]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP94:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP93]], i32 0, i32 0, i64 39
+; POST-PROCESS-GLOBAL-NEXT: [[TMP95:%.*]] = load i32, ptr addrspace(22) [[TMP94]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP96:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP97:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP98:%.*]] = inttoptr i64 [[TMP97]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP99:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP98]], i32 [[TMP96]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP100:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP99]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP101:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP100]], i32 0, i32 0, i64 40
+; POST-PROCESS-GLOBAL-NEXT: [[TMP102:%.*]] = load i32, ptr addrspace(22) [[TMP101]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP103:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP104:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP105:%.*]] = inttoptr i64 [[TMP104]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP106:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP105]], i32 [[TMP103]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP107:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP106]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP108:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP107]], i32 0, i32 0, i64 41
+; POST-PROCESS-GLOBAL-NEXT: [[TMP109:%.*]] = load i32, ptr addrspace(22) [[TMP108]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP110:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP111:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP112:%.*]] = inttoptr i64 [[TMP111]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP113:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP112]], i32 [[TMP110]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP114:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP113]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP115:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP114]], i32 0, i32 0, i64 42
+; POST-PROCESS-GLOBAL-NEXT: [[TMP116:%.*]] = load i32, ptr addrspace(22) [[TMP115]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP117:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP118:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP119:%.*]] = inttoptr i64 [[TMP118]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP120:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP119]], i32 [[TMP117]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP121:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP120]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP122:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP121]], i32 0, i32 0, i64 43
+; POST-PROCESS-GLOBAL-NEXT: [[TMP123:%.*]] = load i32, ptr addrspace(22) [[TMP122]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP124:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP125:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP126:%.*]] = inttoptr i64 [[TMP125]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP127:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP126]], i32 [[TMP124]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP128:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP127]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP129:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP128]], i32 0, i32 0, i64 44
+; POST-PROCESS-GLOBAL-NEXT: [[TMP130:%.*]] = load i32, ptr addrspace(22) [[TMP129]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP131:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP132:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP133:%.*]] = inttoptr i64 [[TMP132]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP134:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP133]], i32 [[TMP131]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP135:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP134]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP136:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP135]], i32 0, i32 0, i64 45
+; POST-PROCESS-GLOBAL-NEXT: [[TMP137:%.*]] = load i32, ptr addrspace(22) [[TMP136]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP138:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP139:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP140:%.*]] = inttoptr i64 [[TMP139]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP141:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP140]], i32 [[TMP138]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP142:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP141]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP143:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP142]], i32 0, i32 0, i64 46
+; POST-PROCESS-GLOBAL-NEXT: [[TMP144:%.*]] = load i32, ptr addrspace(22) [[TMP143]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP145:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP146:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP147:%.*]] = inttoptr i64 [[TMP146]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP148:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP147]], i32 [[TMP145]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP149:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP148]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP150:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP149]], i32 0, i32 0, i64 47
+; POST-PROCESS-GLOBAL-NEXT: [[TMP151:%.*]] = load i32, ptr addrspace(22) [[TMP150]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP152:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP153:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP154:%.*]] = inttoptr i64 [[TMP153]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP155:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP154]], i32 [[TMP152]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP156:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP155]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP157:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP156]], i32 0, i32 0, i64 48
+; POST-PROCESS-GLOBAL-NEXT: [[TMP158:%.*]] = load i32, ptr addrspace(22) [[TMP157]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP159:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP160:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP161:%.*]] = inttoptr i64 [[TMP160]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP162:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP161]], i32 [[TMP159]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP163:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP162]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP164:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP163]], i32 0, i32 0, i64 49
+; POST-PROCESS-GLOBAL-NEXT: [[TMP165:%.*]] = load i32, ptr addrspace(22) [[TMP164]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP166:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP167:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP168:%.*]] = inttoptr i64 [[TMP167]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP169:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP168]], i32 [[TMP166]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP170:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP169]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP171:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP170]], i32 0, i32 0, i64 50
+; POST-PROCESS-GLOBAL-NEXT: [[TMP172:%.*]] = load i32, ptr addrspace(22) [[TMP171]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP173:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP174:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP175:%.*]] = inttoptr i64 [[TMP174]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP176:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP175]], i32 [[TMP173]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP177:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP176]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP178:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP177]], i32 0, i32 0, i64 51
+; POST-PROCESS-GLOBAL-NEXT: [[TMP179:%.*]] = load i32, ptr addrspace(22) [[TMP178]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP180:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP181:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP182:%.*]] = inttoptr i64 [[TMP181]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP183:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP182]], i32 [[TMP180]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP184:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP183]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP185:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP184]], i32 0, i32 0, i64 52
+; POST-PROCESS-GLOBAL-NEXT: [[TMP186:%.*]] = load i32, ptr addrspace(22) [[TMP185]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP187:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP188:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP189:%.*]] = inttoptr i64 [[TMP188]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP190:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP189]], i32 [[TMP187]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP191:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP190]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP192:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP191]], i32 0, i32 0, i64 53
+; POST-PROCESS-GLOBAL-NEXT: [[TMP193:%.*]] = load i32, ptr addrspace(22) [[TMP192]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP194:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP195:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP196:%.*]] = inttoptr i64 [[TMP195]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP197:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP196]], i32 [[TMP194]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP198:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP197]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP199:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP198]], i32 0, i32 0, i64 54
+; POST-PROCESS-GLOBAL-NEXT: [[TMP200:%.*]] = load i32, ptr addrspace(22) [[TMP199]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP201:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP202:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP203:%.*]] = inttoptr i64 [[TMP202]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP204:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP203]], i32 [[TMP201]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP205:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP204]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP206:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP205]], i32 0, i32 0, i64 55
+; POST-PROCESS-GLOBAL-NEXT: [[TMP207:%.*]] = load i32, ptr addrspace(22) [[TMP206]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP208:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP209:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP210:%.*]] = inttoptr i64 [[TMP209]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP211:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP210]], i32 [[TMP208]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP212:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP211]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP213:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspace(22) [[TMP212]], i32 0, i32 0, i64 56
+; POST-PROCESS-GLOBAL-NEXT: [[TMP214:%.*]] = load i32, ptr addrspace(22) [[TMP213]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP215:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; POST-PROCESS-GLOBAL-NEXT: [[ADDR_I:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[TMP215]], i32 0, i32 1
+; POST-PROCESS-GLOBAL-NEXT: [[VAL_I_FCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[ADDR_I]], i32 0, i32 0
+; POST-PROCESS-GLOBAL-NEXT: [[VAL_I_FCA_0_LOAD:%.*]] = load <2 x float>, ptr [[VAL_I_FCA_0_GEP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[VAL_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] poison, <2 x float> [[VAL_I_FCA_0_LOAD]], 0
+; POST-PROCESS-GLOBAL-NEXT: [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[VAL_I_FCA_0_INSERT]], 0
+; POST-PROCESS-GLOBAL-NEXT: [[DOTSROA_011_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT]], i32 0
+; POST-PROCESS-GLOBAL-NEXT: [[TMP216:%.*]] = bitcast float [[DOTSROA_011_0_VEC_EXTRACT]] to i32
+; POST-PROCESS-GLOBAL-NEXT: [[DOTSROA_011_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT]], i32 1
+; POST-PROCESS-GLOBAL-NEXT: [[TMP217:%.*]] = bitcast float [[DOTSROA_011_4_VEC_EXTRACT]] to i32
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP1]], 0
+; POST-PROCESS-GLOBAL-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; POST-PROCESS-GLOBAL-NEXT: call void @_cont_AcceptHit(ptr [[SYSTEM_DATA_ALLOCA]])
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP3]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP4]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP5]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP6]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP7]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP8]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP9]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP10]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP11]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP12]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP13]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP14]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP15]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP16]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP17]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP18]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP19]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP20]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP21]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP22]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP23]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP24]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP25]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP218:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP219:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP220:%.*]] = inttoptr i64 [[TMP219]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP221:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP220]], i32 [[TMP218]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP222:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP221]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP223:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP222]], i32 0, i32 0, i64 30
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP32]], ptr addrspace(22) [[TMP223]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP224:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP225:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP226:%.*]] = inttoptr i64 [[TMP225]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP227:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP226]], i32 [[TMP224]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP228:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP227]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP229:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP228]], i32 0, i32 0, i64 31
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP39]], ptr addrspace(22) [[TMP229]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP230:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP231:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP232:%.*]] = inttoptr i64 [[TMP231]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP233:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP232]], i32 [[TMP230]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP234:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP233]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP235:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP234]], i32 0, i32 0, i64 32
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP46]], ptr addrspace(22) [[TMP235]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP236:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP237:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP238:%.*]] = inttoptr i64 [[TMP237]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP239:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP238]], i32 [[TMP236]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP240:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP239]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP241:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP240]], i32 0, i32 0, i64 33
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP53]], ptr addrspace(22) [[TMP241]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP242:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP243:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP244:%.*]] = inttoptr i64 [[TMP243]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP245:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP244]], i32 [[TMP242]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP246:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP245]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP247:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP246]], i32 0, i32 0, i64 34
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP60]], ptr addrspace(22) [[TMP247]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP248:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP249:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP250:%.*]] = inttoptr i64 [[TMP249]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP251:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP250]], i32 [[TMP248]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP252:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP251]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP253:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP252]], i32 0, i32 0, i64 35
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP67]], ptr addrspace(22) [[TMP253]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP254:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP255:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP256:%.*]] = inttoptr i64 [[TMP255]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP257:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP256]], i32 [[TMP254]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP258:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP257]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP259:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP258]], i32 0, i32 0, i64 36
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP74]], ptr addrspace(22) [[TMP259]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP260:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP261:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP262:%.*]] = inttoptr i64 [[TMP261]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP263:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP262]], i32 [[TMP260]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP264:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP263]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP265:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP264]], i32 0, i32 0, i64 37
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP81]], ptr addrspace(22) [[TMP265]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP266:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP267:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP268:%.*]] = inttoptr i64 [[TMP267]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP269:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP268]], i32 [[TMP266]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP270:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP269]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP271:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP270]], i32 0, i32 0, i64 38
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP88]], ptr addrspace(22) [[TMP271]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP272:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP273:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP274:%.*]] = inttoptr i64 [[TMP273]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP275:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP274]], i32 [[TMP272]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP276:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP275]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP277:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP276]], i32 0, i32 0, i64 39
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP95]], ptr addrspace(22) [[TMP277]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP278:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP279:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP280:%.*]] = inttoptr i64 [[TMP279]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP281:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP280]], i32 [[TMP278]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP282:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP281]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP283:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP282]], i32 0, i32 0, i64 40
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP102]], ptr addrspace(22) [[TMP283]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP284:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP285:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP286:%.*]] = inttoptr i64 [[TMP285]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP287:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP286]], i32 [[TMP284]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP288:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP287]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP289:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP288]], i32 0, i32 0, i64 41
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP109]], ptr addrspace(22) [[TMP289]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP290:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP291:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP292:%.*]] = inttoptr i64 [[TMP291]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP293:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP292]], i32 [[TMP290]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP294:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP293]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP295:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP294]], i32 0, i32 0, i64 42
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP116]], ptr addrspace(22) [[TMP295]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP296:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP297:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP298:%.*]] = inttoptr i64 [[TMP297]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP299:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP298]], i32 [[TMP296]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP300:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP299]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP301:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP300]], i32 0, i32 0, i64 43
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP123]], ptr addrspace(22) [[TMP301]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP302:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP303:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP304:%.*]] = inttoptr i64 [[TMP303]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP305:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP304]], i32 [[TMP302]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP306:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP305]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP307:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP306]], i32 0, i32 0, i64 44
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP130]], ptr addrspace(22) [[TMP307]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP308:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP309:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP310:%.*]] = inttoptr i64 [[TMP309]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP311:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP310]], i32 [[TMP308]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP312:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP311]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP313:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP312]], i32 0, i32 0, i64 45
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP137]], ptr addrspace(22) [[TMP313]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP314:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP315:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP316:%.*]] = inttoptr i64 [[TMP315]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP317:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP316]], i32 [[TMP314]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP318:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP317]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP319:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP318]], i32 0, i32 0, i64 46
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP144]], ptr addrspace(22) [[TMP319]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP320:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP321:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP322:%.*]] = inttoptr i64 [[TMP321]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP323:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP322]], i32 [[TMP320]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP324:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP323]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP325:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP324]], i32 0, i32 0, i64 47
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP151]], ptr addrspace(22) [[TMP325]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP326:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP327:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP328:%.*]] = inttoptr i64 [[TMP327]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP329:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP328]], i32 [[TMP326]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP330:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP329]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP331:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP330]], i32 0, i32 0, i64 48
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP158]], ptr addrspace(22) [[TMP331]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP332:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP333:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP334:%.*]] = inttoptr i64 [[TMP333]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP335:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP334]], i32 [[TMP332]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP336:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP335]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP337:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP336]], i32 0, i32 0, i64 49
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP165]], ptr addrspace(22) [[TMP337]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP338:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP339:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP340:%.*]] = inttoptr i64 [[TMP339]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP341:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP340]], i32 [[TMP338]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP342:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP341]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP343:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP342]], i32 0, i32 0, i64 50
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP172]], ptr addrspace(22) [[TMP343]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP344:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP345:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP346:%.*]] = inttoptr i64 [[TMP345]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP347:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP346]], i32 [[TMP344]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP348:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP347]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP349:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP348]], i32 0, i32 0, i64 51
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP179]], ptr addrspace(22) [[TMP349]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP350:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP351:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP352:%.*]] = inttoptr i64 [[TMP351]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP353:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP352]], i32 [[TMP350]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP354:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP353]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP355:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP354]], i32 0, i32 0, i64 52
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP186]], ptr addrspace(22) [[TMP355]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP356:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP357:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP358:%.*]] = inttoptr i64 [[TMP357]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP359:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP358]], i32 [[TMP356]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP360:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP359]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP361:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP360]], i32 0, i32 0, i64 53
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP193]], ptr addrspace(22) [[TMP361]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP362:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP363:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP364:%.*]] = inttoptr i64 [[TMP363]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP365:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP364]], i32 [[TMP362]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP366:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP365]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP367:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP366]], i32 0, i32 0, i64 54
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP200]], ptr addrspace(22) [[TMP367]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP368:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP369:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP370:%.*]] = inttoptr i64 [[TMP369]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP371:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP370]], i32 [[TMP368]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP372:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP371]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP373:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP372]], i32 0, i32 0, i64 55
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP207]], ptr addrspace(22) [[TMP373]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP374:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP375:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP376:%.*]] = inttoptr i64 [[TMP375]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP377:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP376]], i32 [[TMP374]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP378:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP377]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP379:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP378]], i32 0, i32 0, i64 56
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP214]], ptr addrspace(22) [[TMP379]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[HITATTRSALLOCA_SROA_0_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT]], i32 0
+; POST-PROCESS-GLOBAL-NEXT: [[TMP380:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_0_VEC_EXTRACT]] to i32
+; POST-PROCESS-GLOBAL-NEXT: [[TMP381:%.*]] = bitcast i32 [[TMP380]] to float
+; POST-PROCESS-GLOBAL-NEXT: [[DOTSROA_012_0_VEC_INSERT:%.*]] = insertelement <2 x float> undef, float [[TMP381]], i32 0
+; POST-PROCESS-GLOBAL-NEXT: [[HITATTRSALLOCA_SROA_0_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT]], i32 1
+; POST-PROCESS-GLOBAL-NEXT: [[TMP382:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_4_VEC_EXTRACT]] to i32
+; POST-PROCESS-GLOBAL-NEXT: [[TMP383:%.*]] = bitcast i32 [[TMP382]] to float
+; POST-PROCESS-GLOBAL-NEXT: [[DOTSROA_012_4_VEC_INSERT:%.*]] = insertelement <2 x float> [[DOTSROA_012_0_VEC_INSERT]], float [[TMP383]], i32 1
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] poison, <2 x float> [[DOTSROA_012_4_VEC_INSERT]], 0
+; POST-PROCESS-GLOBAL-NEXT: [[TMP384:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; POST-PROCESS-GLOBAL-NEXT: call void @_cont_SetTriangleHitAttributes(ptr [[TMP384]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_INSERT]])
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_0_0_0_GEP1:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0, i32 0
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_0_0_0_LOAD:%.*]] = load <3 x i32>, ptr [[DOTFCA_0_0_0_0_GEP1]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_0_0_0_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] poison, <3 x i32> [[DOTFCA_0_0_0_0_LOAD]], 0, 0, 0, 0
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_0_1_0_GEP2:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 1, i32 0
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_0_1_0_LOAD:%.*]] = load <2 x float>, ptr [[DOTFCA_0_0_1_0_GEP2]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_0_1_0_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_0_0_0_INSERT]], <2 x float> [[DOTFCA_0_0_1_0_LOAD]], 0, 0, 1, 0
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_1_0_GEP3:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 1, i32 0
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_1_0_LOAD:%.*]] = load float, ptr [[DOTFCA_0_1_0_GEP3]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_1_0_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_0_1_0_INSERT]], float [[DOTFCA_0_1_0_LOAD]], 0, 1, 0
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_1_1_GEP4:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 1, i32 1
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_1_1_LOAD:%.*]] = load i32, ptr [[DOTFCA_0_1_1_GEP4]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_1_1_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_1_0_INSERT]], i32 [[DOTFCA_0_1_1_LOAD]], 0, 1, 1
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_2_GEP5:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 2
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_2_LOAD:%.*]] = load <3 x float>, ptr [[DOTFCA_0_2_GEP5]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_1_1_INSERT]], <3 x float> [[DOTFCA_0_2_LOAD]], 0, 2
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_3_GEP6:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 3
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_3_LOAD:%.*]] = load <3 x float>, ptr [[DOTFCA_0_3_GEP6]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_3_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_2_INSERT]], <3 x float> [[DOTFCA_0_3_LOAD]], 0, 3
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_4_GEP7:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_4_LOAD:%.*]] = load float, ptr [[DOTFCA_0_4_GEP7]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_4_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_3_INSERT]], float [[DOTFCA_0_4_LOAD]], 0, 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_5_GEP8:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 5
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_5_LOAD:%.*]] = load i64, ptr [[DOTFCA_0_5_GEP8]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_5_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_4_INSERT]], i64 [[DOTFCA_0_5_LOAD]], 0, 5
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_1_0_GEP9:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 0
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_1_0_LOAD:%.*]] = load float, ptr [[DOTFCA_1_0_GEP9]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_1_0_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_0_5_INSERT]], float [[DOTFCA_1_0_LOAD]], 1, 0
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_1_1_GEP10:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 1
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_1_1_LOAD:%.*]] = load i32, ptr [[DOTFCA_1_1_GEP10]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_1_1_INSERT:%.*]] = insertvalue [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_1_0_INSERT]], i32 [[DOTFCA_1_1_LOAD]], 1, 1
+; POST-PROCESS-GLOBAL-NEXT: [[TMP385:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP385]], [[STRUCT_ANYHITTRAVERSALDATA]] [[DOTFCA_1_1_INSERT]]), !continuation.registercount [[META18]]
+; POST-PROCESS-GLOBAL-NEXT: unreachable
+;
+;
+; POST-PROCESS-GLOBAL-LABEL: define void @ClosestHit(
+; POST-PROCESS-GLOBAL-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR2]] !lgc.rt.shaderstage [[META24:![0-9]+]] !continuation.registercount [[META18]] !continuation [[META25:![0-9]+]] !continuation.stacksize [[META26:![0-9]+]] !continuation.state [[META27:![0-9]+]] {
+; POST-PROCESS-GLOBAL-NEXT: AllocaSpillBB:
+; POST-PROCESS-GLOBAL-NEXT: [[CSP:%.*]] = alloca i32, align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP1:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP2:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP3]], i32 [[TMP1]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP4]], i64 108
+; POST-PROCESS-GLOBAL-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME:%.*]], ptr addrspace(22) [[TMP5]], i32 0, i32 0
+; POST-PROCESS-GLOBAL-NEXT: store i64 [[RETURNADDR]], ptr addrspace(22) [[RETURNADDR_SPILL_ADDR]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP0]], 0, 0
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP0]], 1, 0
+; POST-PROCESS-GLOBAL-NEXT: [[TMP6:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], 108
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP7]], ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP18:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP19:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP22:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP23:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP24:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP25:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP27:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP28:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP29:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP30:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP32:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP33:%.*]] = inttoptr i64 [[TMP32]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP34:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP33]], i32 [[TMP31]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP35:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP34]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP36:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP35]], i32 0, i32 0, i64 30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP37:%.*]] = load i32, ptr addrspace(22) [[TMP36]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP38:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP39:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP40:%.*]] = inttoptr i64 [[TMP39]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP41:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP40]], i32 [[TMP38]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP42:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP41]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP43:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP42]], i32 0, i32 0, i64 31
+; POST-PROCESS-GLOBAL-NEXT: [[TMP44:%.*]] = load i32, ptr addrspace(22) [[TMP43]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP45:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP46:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP47:%.*]] = inttoptr i64 [[TMP46]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP48:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP47]], i32 [[TMP45]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP49:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP48]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP50:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP49]], i32 0, i32 0, i64 32
+; POST-PROCESS-GLOBAL-NEXT: [[TMP51:%.*]] = load i32, ptr addrspace(22) [[TMP50]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP52:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP53:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP54:%.*]] = inttoptr i64 [[TMP53]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP55:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP54]], i32 [[TMP52]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP56:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP55]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP57:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP56]], i32 0, i32 0, i64 33
+; POST-PROCESS-GLOBAL-NEXT: [[TMP58:%.*]] = load i32, ptr addrspace(22) [[TMP57]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP59:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP60:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP61:%.*]] = inttoptr i64 [[TMP60]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP62:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP61]], i32 [[TMP59]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP63:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP62]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP64:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP63]], i32 0, i32 0, i64 34
+; POST-PROCESS-GLOBAL-NEXT: [[TMP65:%.*]] = load i32, ptr addrspace(22) [[TMP64]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP66:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP67:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP68:%.*]] = inttoptr i64 [[TMP67]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP69:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP68]], i32 [[TMP66]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP70:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP69]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP71:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP70]], i32 0, i32 0, i64 35
+; POST-PROCESS-GLOBAL-NEXT: [[TMP72:%.*]] = load i32, ptr addrspace(22) [[TMP71]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP73:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP74:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP75:%.*]] = inttoptr i64 [[TMP74]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP76:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP75]], i32 [[TMP73]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP77:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP76]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP78:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP77]], i32 0, i32 0, i64 36
+; POST-PROCESS-GLOBAL-NEXT: [[TMP79:%.*]] = load i32, ptr addrspace(22) [[TMP78]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP80:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP81:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP82:%.*]] = inttoptr i64 [[TMP81]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP83:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP82]], i32 [[TMP80]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP84:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP83]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP85:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP84]], i32 0, i32 0, i64 37
+; POST-PROCESS-GLOBAL-NEXT: [[TMP86:%.*]] = load i32, ptr addrspace(22) [[TMP85]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP87:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP88:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP89:%.*]] = inttoptr i64 [[TMP88]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP90:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP89]], i32 [[TMP87]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP91:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP90]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP92:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP91]], i32 0, i32 0, i64 38
+; POST-PROCESS-GLOBAL-NEXT: [[TMP93:%.*]] = load i32, ptr addrspace(22) [[TMP92]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP94:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP95:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP96:%.*]] = inttoptr i64 [[TMP95]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP97:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP96]], i32 [[TMP94]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP98:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP97]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP99:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP98]], i32 0, i32 0, i64 39
+; POST-PROCESS-GLOBAL-NEXT: [[TMP100:%.*]] = load i32, ptr addrspace(22) [[TMP99]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP101:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP102:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP103:%.*]] = inttoptr i64 [[TMP102]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP104:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP103]], i32 [[TMP101]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP105:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP104]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP106:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP105]], i32 0, i32 0, i64 40
+; POST-PROCESS-GLOBAL-NEXT: [[TMP107:%.*]] = load i32, ptr addrspace(22) [[TMP106]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP108:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP109:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP110:%.*]] = inttoptr i64 [[TMP109]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP111:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP110]], i32 [[TMP108]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP112:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP111]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP113:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP112]], i32 0, i32 0, i64 41
+; POST-PROCESS-GLOBAL-NEXT: [[TMP114:%.*]] = load i32, ptr addrspace(22) [[TMP113]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP115:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP116:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP117:%.*]] = inttoptr i64 [[TMP116]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP118:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP117]], i32 [[TMP115]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP119:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP118]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP120:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP119]], i32 0, i32 0, i64 42
+; POST-PROCESS-GLOBAL-NEXT: [[TMP121:%.*]] = load i32, ptr addrspace(22) [[TMP120]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP122:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP123:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP124:%.*]] = inttoptr i64 [[TMP123]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP125:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP124]], i32 [[TMP122]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP126:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP125]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP127:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP126]], i32 0, i32 0, i64 43
+; POST-PROCESS-GLOBAL-NEXT: [[TMP128:%.*]] = load i32, ptr addrspace(22) [[TMP127]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP129:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP130:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP131:%.*]] = inttoptr i64 [[TMP130]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP132:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP131]], i32 [[TMP129]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP133:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP132]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP134:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP133]], i32 0, i32 0, i64 44
+; POST-PROCESS-GLOBAL-NEXT: [[TMP135:%.*]] = load i32, ptr addrspace(22) [[TMP134]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP136:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP137:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP138:%.*]] = inttoptr i64 [[TMP137]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP139:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP138]], i32 [[TMP136]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP140:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP139]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP141:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP140]], i32 0, i32 0, i64 45
+; POST-PROCESS-GLOBAL-NEXT: [[TMP142:%.*]] = load i32, ptr addrspace(22) [[TMP141]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP143:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP144:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP145:%.*]] = inttoptr i64 [[TMP144]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP146:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP145]], i32 [[TMP143]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP147:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP146]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP148:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP147]], i32 0, i32 0, i64 46
+; POST-PROCESS-GLOBAL-NEXT: [[TMP149:%.*]] = load i32, ptr addrspace(22) [[TMP148]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP150:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP151:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP152:%.*]] = inttoptr i64 [[TMP151]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP153:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP152]], i32 [[TMP150]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP154:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP153]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP155:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP154]], i32 0, i32 0, i64 47
+; POST-PROCESS-GLOBAL-NEXT: [[TMP156:%.*]] = load i32, ptr addrspace(22) [[TMP155]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP157:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP158:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP159:%.*]] = inttoptr i64 [[TMP158]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP160:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP159]], i32 [[TMP157]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP161:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP160]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP162:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP161]], i32 0, i32 0, i64 48
+; POST-PROCESS-GLOBAL-NEXT: [[TMP163:%.*]] = load i32, ptr addrspace(22) [[TMP162]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP164:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP165:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP166:%.*]] = inttoptr i64 [[TMP165]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP167:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP166]], i32 [[TMP164]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP168:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP167]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP169:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP168]], i32 0, i32 0, i64 49
+; POST-PROCESS-GLOBAL-NEXT: [[TMP170:%.*]] = load i32, ptr addrspace(22) [[TMP169]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP171:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP172:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP173:%.*]] = inttoptr i64 [[TMP172]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP174:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP173]], i32 [[TMP171]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP175:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP174]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP176:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP175]], i32 0, i32 0, i64 50
+; POST-PROCESS-GLOBAL-NEXT: [[TMP177:%.*]] = load i32, ptr addrspace(22) [[TMP176]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP178:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP179:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP180:%.*]] = inttoptr i64 [[TMP179]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP181:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP180]], i32 [[TMP178]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP182:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP181]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP183:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP182]], i32 0, i32 0, i64 51
+; POST-PROCESS-GLOBAL-NEXT: [[TMP184:%.*]] = load i32, ptr addrspace(22) [[TMP183]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP185:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP186:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP187:%.*]] = inttoptr i64 [[TMP186]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP188:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP187]], i32 [[TMP185]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP189:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP188]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP190:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP189]], i32 0, i32 0, i64 52
+; POST-PROCESS-GLOBAL-NEXT: [[TMP191:%.*]] = load i32, ptr addrspace(22) [[TMP190]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP192:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP193:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP194:%.*]] = inttoptr i64 [[TMP193]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP195:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP194]], i32 [[TMP192]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP196:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP195]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP197:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP196]], i32 0, i32 0, i64 53
+; POST-PROCESS-GLOBAL-NEXT: [[TMP198:%.*]] = load i32, ptr addrspace(22) [[TMP197]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP199:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP200:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP201:%.*]] = inttoptr i64 [[TMP200]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP202:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP201]], i32 [[TMP199]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP203:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP202]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP204:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP203]], i32 0, i32 0, i64 54
+; POST-PROCESS-GLOBAL-NEXT: [[TMP205:%.*]] = load i32, ptr addrspace(22) [[TMP204]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP206:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP207:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP208:%.*]] = inttoptr i64 [[TMP207]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP209:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP208]], i32 [[TMP206]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP210:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP209]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP211:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP210]], i32 0, i32 0, i64 55
+; POST-PROCESS-GLOBAL-NEXT: [[TMP212:%.*]] = load i32, ptr addrspace(22) [[TMP211]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP213:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP214:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP215:%.*]] = inttoptr i64 [[TMP214]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP216:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP215]], i32 [[TMP213]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP217:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP216]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP218:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspace(22) [[TMP217]], i32 0, i32 0, i64 56
+; POST-PROCESS-GLOBAL-NEXT: [[TMP219:%.*]] = load i32, ptr addrspace(22) [[TMP218]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP220:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTSPILL_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME]], ptr addrspace(22) [[TMP5]], i32 0, i32 1
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP220]], ptr addrspace(22) [[DOTSPILL_ADDR]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[VAL_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] poison, <2 x float> [[DOTFCA_1_0_EXTRACT]], 0
+; POST-PROCESS-GLOBAL-NEXT: [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[VAL_I_FCA_0_INSERT]], 0
+; POST-PROCESS-GLOBAL-NEXT: [[DOTSROA_053_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT]], i32 0
+; POST-PROCESS-GLOBAL-NEXT: [[TMP221:%.*]] = bitcast float [[DOTSROA_053_0_VEC_EXTRACT]] to i32
+; POST-PROCESS-GLOBAL-NEXT: [[DOTSROA_053_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT]], i32 1
+; POST-PROCESS-GLOBAL-NEXT: [[TMP222:%.*]] = bitcast float [[DOTSROA_053_4_VEC_EXTRACT]] to i32
+; POST-PROCESS-GLOBAL-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP223:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP224:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP225:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP223]])
+; POST-PROCESS-GLOBAL-NEXT: [[TMP226:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP225]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
+; POST-PROCESS-GLOBAL-NEXT: [[TMP227:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[TMP226]])
+; POST-PROCESS-GLOBAL-NEXT: [[DIS_DATA_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA:%.*]] poison, <3 x i32> [[DOTFCA_0_0_EXTRACT]], 0
+; POST-PROCESS-GLOBAL-NEXT: [[SYS_DATA_I:%.*]] = insertvalue [[STRUCT_SYSTEMDATA]] undef, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I_FCA_0_INSERT]], 0
+; POST-PROCESS-GLOBAL-NEXT: [[TRAV_DATA_I:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA:%.*]] undef, [[STRUCT_SYSTEMDATA]] [[SYS_DATA_I]], 0
+; POST-PROCESS-GLOBAL-NEXT: [[TMP228:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP229:%.*]] = add i32 [[TMP228]], -108
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP229]], ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP8]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP9]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP10]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP11]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP12]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP13]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP14]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP15]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP16]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP17]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP18]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP19]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP20]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP21]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP22]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP23]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP24]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP25]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP26]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP27]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP28]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP29]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP30]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP230:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP231:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP232:%.*]] = inttoptr i64 [[TMP231]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP233:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP232]], i32 [[TMP230]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP234:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP233]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP235:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP234]], i32 0, i32 0, i64 30
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP37]], ptr addrspace(22) [[TMP235]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP236:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP237:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP238:%.*]] = inttoptr i64 [[TMP237]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP239:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP238]], i32 [[TMP236]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP240:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP239]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP241:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP240]], i32 0, i32 0, i64 31
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP44]], ptr addrspace(22) [[TMP241]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP242:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP243:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP244:%.*]] = inttoptr i64 [[TMP243]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP245:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP244]], i32 [[TMP242]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP246:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP245]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP247:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP246]], i32 0, i32 0, i64 32
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP51]], ptr addrspace(22) [[TMP247]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP248:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP249:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP250:%.*]] = inttoptr i64 [[TMP249]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP251:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP250]], i32 [[TMP248]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP252:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP251]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP253:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP252]], i32 0, i32 0, i64 33
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP58]], ptr addrspace(22) [[TMP253]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP254:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP255:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP256:%.*]] = inttoptr i64 [[TMP255]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP257:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP256]], i32 [[TMP254]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP258:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP257]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP259:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP258]], i32 0, i32 0, i64 34
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP65]], ptr addrspace(22) [[TMP259]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP260:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP261:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP262:%.*]] = inttoptr i64 [[TMP261]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP263:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP262]], i32 [[TMP260]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP264:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP263]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP265:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP264]], i32 0, i32 0, i64 35
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP72]], ptr addrspace(22) [[TMP265]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP266:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP267:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP268:%.*]] = inttoptr i64 [[TMP267]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP269:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP268]], i32 [[TMP266]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP270:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP269]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP271:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP270]], i32 0, i32 0, i64 36
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP79]], ptr addrspace(22) [[TMP271]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP272:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP273:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP274:%.*]] = inttoptr i64 [[TMP273]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP275:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP274]], i32 [[TMP272]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP276:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP275]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP277:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP276]], i32 0, i32 0, i64 37
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP86]], ptr addrspace(22) [[TMP277]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP278:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP279:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP280:%.*]] = inttoptr i64 [[TMP279]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP281:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP280]], i32 [[TMP278]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP282:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP281]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP283:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP282]], i32 0, i32 0, i64 38
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP93]], ptr addrspace(22) [[TMP283]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP284:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP285:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP286:%.*]] = inttoptr i64 [[TMP285]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP287:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP286]], i32 [[TMP284]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP288:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP287]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP289:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP288]], i32 0, i32 0, i64 39
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP100]], ptr addrspace(22) [[TMP289]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP290:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP291:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP292:%.*]] = inttoptr i64 [[TMP291]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP293:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP292]], i32 [[TMP290]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP294:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP293]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP295:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP294]], i32 0, i32 0, i64 40
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP107]], ptr addrspace(22) [[TMP295]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP296:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP297:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP298:%.*]] = inttoptr i64 [[TMP297]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP299:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP298]], i32 [[TMP296]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP300:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP299]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP301:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP300]], i32 0, i32 0, i64 41
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP114]], ptr addrspace(22) [[TMP301]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP302:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP303:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP304:%.*]] = inttoptr i64 [[TMP303]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP305:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP304]], i32 [[TMP302]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP306:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP305]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP307:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP306]], i32 0, i32 0, i64 42
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP121]], ptr addrspace(22) [[TMP307]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP308:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP309:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP310:%.*]] = inttoptr i64 [[TMP309]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP311:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP310]], i32 [[TMP308]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP312:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP311]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP313:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP312]], i32 0, i32 0, i64 43
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP128]], ptr addrspace(22) [[TMP313]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP314:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP315:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP316:%.*]] = inttoptr i64 [[TMP315]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP317:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP316]], i32 [[TMP314]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP318:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP317]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP319:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP318]], i32 0, i32 0, i64 44
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP135]], ptr addrspace(22) [[TMP319]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP320:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP321:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP322:%.*]] = inttoptr i64 [[TMP321]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP323:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP322]], i32 [[TMP320]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP324:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP323]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP325:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP324]], i32 0, i32 0, i64 45
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP142]], ptr addrspace(22) [[TMP325]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP326:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP327:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP328:%.*]] = inttoptr i64 [[TMP327]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP329:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP328]], i32 [[TMP326]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP330:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP329]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP331:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP330]], i32 0, i32 0, i64 46
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP149]], ptr addrspace(22) [[TMP331]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP332:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP333:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP334:%.*]] = inttoptr i64 [[TMP333]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP335:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP334]], i32 [[TMP332]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP336:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP335]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP337:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP336]], i32 0, i32 0, i64 47
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP156]], ptr addrspace(22) [[TMP337]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP338:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP339:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP340:%.*]] = inttoptr i64 [[TMP339]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP341:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP340]], i32 [[TMP338]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP342:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP341]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP343:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP342]], i32 0, i32 0, i64 48
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP163]], ptr addrspace(22) [[TMP343]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP344:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP345:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP346:%.*]] = inttoptr i64 [[TMP345]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP347:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP346]], i32 [[TMP344]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP348:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP347]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP349:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP348]], i32 0, i32 0, i64 49
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP170]], ptr addrspace(22) [[TMP349]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP350:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP351:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP352:%.*]] = inttoptr i64 [[TMP351]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP353:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP352]], i32 [[TMP350]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP354:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP353]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP355:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP354]], i32 0, i32 0, i64 50
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP177]], ptr addrspace(22) [[TMP355]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP356:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP357:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP358:%.*]] = inttoptr i64 [[TMP357]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP359:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP358]], i32 [[TMP356]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP360:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP359]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP361:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP360]], i32 0, i32 0, i64 51
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP184]], ptr addrspace(22) [[TMP361]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP362:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP363:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP364:%.*]] = inttoptr i64 [[TMP363]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP365:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP364]], i32 [[TMP362]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP366:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP365]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP367:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP366]], i32 0, i32 0, i64 52
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP191]], ptr addrspace(22) [[TMP367]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP368:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP369:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP370:%.*]] = inttoptr i64 [[TMP369]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP371:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP370]], i32 [[TMP368]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP372:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP371]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP373:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP372]], i32 0, i32 0, i64 53
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP198]], ptr addrspace(22) [[TMP373]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP374:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP375:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP376:%.*]] = inttoptr i64 [[TMP375]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP377:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP376]], i32 [[TMP374]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP378:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP377]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP379:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP378]], i32 0, i32 0, i64 54
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP205]], ptr addrspace(22) [[TMP379]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP380:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP381:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP382:%.*]] = inttoptr i64 [[TMP381]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP383:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP382]], i32 [[TMP380]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP384:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP383]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP385:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP384]], i32 0, i32 0, i64 55
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP212]], ptr addrspace(22) [[TMP385]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP386:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP387:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP388:%.*]] = inttoptr i64 [[TMP387]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP389:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP388]], i32 [[TMP386]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP390:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP389]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP391:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspace(22) [[TMP390]], i32 0, i32 0, i64 56
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP219]], ptr addrspace(22) [[TMP391]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP392:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP393:%.*]] = add i32 [[TMP392]], 12
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP393]], ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP394:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP395:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @ClosestHit.resume.0 to i64))
+; POST-PROCESS-GLOBAL-NEXT: call void (i64, ...) @continuation.continue(i64 4, i32 [[TMP394]], i64 [[TMP395]], [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]]), !continuation.registercount [[META18]], !continuation.returnedRegistercount !18
+; POST-PROCESS-GLOBAL-NEXT: unreachable
+;
+;
+; POST-PROCESS-GLOBAL-LABEL: define dso_local void @ClosestHit.resume.0(
+; POST-PROCESS-GLOBAL-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.shaderstage [[META24]] !continuation.registercount [[META18]] !continuation [[META25]] {
+; POST-PROCESS-GLOBAL-NEXT: entryresume.0:
+; POST-PROCESS-GLOBAL-NEXT: [[CSP:%.*]] = alloca i32, align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP0]], ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP2:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], -12
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP3]], ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP4:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP5:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP6]], i32 [[TMP4]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP7]], i64 0
+; POST-PROCESS-GLOBAL-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP18:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP19:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP22:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP23:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP24:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP25:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP27:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP28:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP29:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP30:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP32:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP33:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP34:%.*]] = inttoptr i64 [[TMP33]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP35:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP34]], i32 [[TMP32]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP36:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP35]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP37:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP36]], i32 0, i32 0, i64 30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP38:%.*]] = load i32, ptr addrspace(22) [[TMP37]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP39:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP40:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP41:%.*]] = inttoptr i64 [[TMP40]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP42:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP41]], i32 [[TMP39]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP43:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP42]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP44:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP43]], i32 0, i32 0, i64 31
+; POST-PROCESS-GLOBAL-NEXT: [[TMP45:%.*]] = load i32, ptr addrspace(22) [[TMP44]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP46:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP47:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP48:%.*]] = inttoptr i64 [[TMP47]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP49:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP48]], i32 [[TMP46]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP50:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP49]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP51:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP50]], i32 0, i32 0, i64 32
+; POST-PROCESS-GLOBAL-NEXT: [[TMP52:%.*]] = load i32, ptr addrspace(22) [[TMP51]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP53:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP54:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP55:%.*]] = inttoptr i64 [[TMP54]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP56:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP55]], i32 [[TMP53]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP57:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP56]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP58:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP57]], i32 0, i32 0, i64 33
+; POST-PROCESS-GLOBAL-NEXT: [[TMP59:%.*]] = load i32, ptr addrspace(22) [[TMP58]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP60:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP61:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP62:%.*]] = inttoptr i64 [[TMP61]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP63:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP62]], i32 [[TMP60]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP63]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP65:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP64]], i32 0, i32 0, i64 34
+; POST-PROCESS-GLOBAL-NEXT: [[TMP66:%.*]] = load i32, ptr addrspace(22) [[TMP65]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP67:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP68:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP69:%.*]] = inttoptr i64 [[TMP68]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP70:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP69]], i32 [[TMP67]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP71:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP70]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP72:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP71]], i32 0, i32 0, i64 35
+; POST-PROCESS-GLOBAL-NEXT: [[TMP73:%.*]] = load i32, ptr addrspace(22) [[TMP72]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP74:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP75:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP76:%.*]] = inttoptr i64 [[TMP75]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP77:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP76]], i32 [[TMP74]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP78:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP77]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP79:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP78]], i32 0, i32 0, i64 36
+; POST-PROCESS-GLOBAL-NEXT: [[TMP80:%.*]] = load i32, ptr addrspace(22) [[TMP79]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP81:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP82:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP83:%.*]] = inttoptr i64 [[TMP82]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP84:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP83]], i32 [[TMP81]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP85:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP84]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP86:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP85]], i32 0, i32 0, i64 37
+; POST-PROCESS-GLOBAL-NEXT: [[TMP87:%.*]] = load i32, ptr addrspace(22) [[TMP86]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP88:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP89:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP90:%.*]] = inttoptr i64 [[TMP89]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP91:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP90]], i32 [[TMP88]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP92:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP91]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP93:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP92]], i32 0, i32 0, i64 38
+; POST-PROCESS-GLOBAL-NEXT: [[TMP94:%.*]] = load i32, ptr addrspace(22) [[TMP93]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP95:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP96:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP97:%.*]] = inttoptr i64 [[TMP96]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP98:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP97]], i32 [[TMP95]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP99:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP98]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP100:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP99]], i32 0, i32 0, i64 39
+; POST-PROCESS-GLOBAL-NEXT: [[TMP101:%.*]] = load i32, ptr addrspace(22) [[TMP100]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP102:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP103:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP104:%.*]] = inttoptr i64 [[TMP103]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP105:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP104]], i32 [[TMP102]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP106:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP105]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP107:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP106]], i32 0, i32 0, i64 40
+; POST-PROCESS-GLOBAL-NEXT: [[TMP108:%.*]] = load i32, ptr addrspace(22) [[TMP107]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP109:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP110:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP111:%.*]] = inttoptr i64 [[TMP110]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP112:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP111]], i32 [[TMP109]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP113:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP112]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP114:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP113]], i32 0, i32 0, i64 41
+; POST-PROCESS-GLOBAL-NEXT: [[TMP115:%.*]] = load i32, ptr addrspace(22) [[TMP114]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP116:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP117:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP118:%.*]] = inttoptr i64 [[TMP117]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP119:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP118]], i32 [[TMP116]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP120:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP119]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP121:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP120]], i32 0, i32 0, i64 42
+; POST-PROCESS-GLOBAL-NEXT: [[TMP122:%.*]] = load i32, ptr addrspace(22) [[TMP121]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP123:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP124:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP125:%.*]] = inttoptr i64 [[TMP124]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP126:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP125]], i32 [[TMP123]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP127:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP126]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP128:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP127]], i32 0, i32 0, i64 43
+; POST-PROCESS-GLOBAL-NEXT: [[TMP129:%.*]] = load i32, ptr addrspace(22) [[TMP128]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP130:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP131:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP132:%.*]] = inttoptr i64 [[TMP131]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP133:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP132]], i32 [[TMP130]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP134:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP133]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP135:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP134]], i32 0, i32 0, i64 44
+; POST-PROCESS-GLOBAL-NEXT: [[TMP136:%.*]] = load i32, ptr addrspace(22) [[TMP135]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP137:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP138:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP139:%.*]] = inttoptr i64 [[TMP138]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP140:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP139]], i32 [[TMP137]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP141:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP140]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP142:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP141]], i32 0, i32 0, i64 45
+; POST-PROCESS-GLOBAL-NEXT: [[TMP143:%.*]] = load i32, ptr addrspace(22) [[TMP142]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP144:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP145:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP146:%.*]] = inttoptr i64 [[TMP145]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP147:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP146]], i32 [[TMP144]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP148:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP147]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP149:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP148]], i32 0, i32 0, i64 46
+; POST-PROCESS-GLOBAL-NEXT: [[TMP150:%.*]] = load i32, ptr addrspace(22) [[TMP149]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP151:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP152:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP153:%.*]] = inttoptr i64 [[TMP152]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP154:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP153]], i32 [[TMP151]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP155:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP154]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP156:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP155]], i32 0, i32 0, i64 47
+; POST-PROCESS-GLOBAL-NEXT: [[TMP157:%.*]] = load i32, ptr addrspace(22) [[TMP156]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP158:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP159:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP160:%.*]] = inttoptr i64 [[TMP159]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP161:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP160]], i32 [[TMP158]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP162:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP161]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP163:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP162]], i32 0, i32 0, i64 48
+; POST-PROCESS-GLOBAL-NEXT: [[TMP164:%.*]] = load i32, ptr addrspace(22) [[TMP163]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP165:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP166:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP167:%.*]] = inttoptr i64 [[TMP166]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP168:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP167]], i32 [[TMP165]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP169:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP168]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP170:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP169]], i32 0, i32 0, i64 49
+; POST-PROCESS-GLOBAL-NEXT: [[TMP171:%.*]] = load i32, ptr addrspace(22) [[TMP170]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP172:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP173:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP174:%.*]] = inttoptr i64 [[TMP173]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP175:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP174]], i32 [[TMP172]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP176:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP175]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP177:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP176]], i32 0, i32 0, i64 50
+; POST-PROCESS-GLOBAL-NEXT: [[TMP178:%.*]] = load i32, ptr addrspace(22) [[TMP177]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP179:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP180:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP181:%.*]] = inttoptr i64 [[TMP180]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP182:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP181]], i32 [[TMP179]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP183:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP182]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP184:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP183]], i32 0, i32 0, i64 51
+; POST-PROCESS-GLOBAL-NEXT: [[TMP185:%.*]] = load i32, ptr addrspace(22) [[TMP184]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP186:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP187:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP188:%.*]] = inttoptr i64 [[TMP187]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP189:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP188]], i32 [[TMP186]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP190:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP189]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP191:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP190]], i32 0, i32 0, i64 52
+; POST-PROCESS-GLOBAL-NEXT: [[TMP192:%.*]] = load i32, ptr addrspace(22) [[TMP191]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP193:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP194:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP195:%.*]] = inttoptr i64 [[TMP194]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP196:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP195]], i32 [[TMP193]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP197:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP196]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP198:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP197]], i32 0, i32 0, i64 53
+; POST-PROCESS-GLOBAL-NEXT: [[TMP199:%.*]] = load i32, ptr addrspace(22) [[TMP198]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP200:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP201:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP202:%.*]] = inttoptr i64 [[TMP201]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP203:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP202]], i32 [[TMP200]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP204:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP203]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP205:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP204]], i32 0, i32 0, i64 54
+; POST-PROCESS-GLOBAL-NEXT: [[TMP206:%.*]] = load i32, ptr addrspace(22) [[TMP205]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP207:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP208:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP209:%.*]] = inttoptr i64 [[TMP208]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP210:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP209]], i32 [[TMP207]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP211:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP210]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP212:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP211]], i32 0, i32 0, i64 55
+; POST-PROCESS-GLOBAL-NEXT: [[TMP213:%.*]] = load i32, ptr addrspace(22) [[TMP212]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP214:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP215:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP216:%.*]] = inttoptr i64 [[TMP215]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP217:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP216]], i32 [[TMP214]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP218:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP217]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP219:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP218]], i32 0, i32 0, i64 56
+; POST-PROCESS-GLOBAL-NEXT: [[TMP220:%.*]] = load i32, ptr addrspace(22) [[TMP219]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
+; POST-PROCESS-GLOBAL-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; POST-PROCESS-GLOBAL-NEXT: [[DOTRELOAD_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME:%.*]], ptr addrspace(22) [[TMP8]], i32 0, i32 1
+; POST-PROCESS-GLOBAL-NEXT: [[DOTRELOAD:%.*]] = load i32, ptr addrspace(22) [[DOTRELOAD_ADDR]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[CLOSESTHIT_FRAME]], ptr addrspace(22) [[TMP8]], i32 0, i32 0
+; POST-PROCESS-GLOBAL-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr addrspace(22) [[RETURNADDR_RELOAD_ADDR]], align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[DOTRELOAD]], ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP9]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP10]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP11]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP12]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 10) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP13]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 11) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP14]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 12) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP15]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 13) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP16]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 14) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP17]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 15) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP18]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 16) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP19]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 17) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP20]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 18) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP21]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 19) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP22]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 20) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP23]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 21) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP24]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 22) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP25]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 23) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP26]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 24) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP27]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 25) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP28]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 26) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP29]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 27) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP30]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 28) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP31]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 29) to ptr addrspace(20)), align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP221:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP222:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP223:%.*]] = inttoptr i64 [[TMP222]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP224:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP223]], i32 [[TMP221]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP225:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP224]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP226:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP225]], i32 0, i32 0, i64 30
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP38]], ptr addrspace(22) [[TMP226]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP227:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP228:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP229:%.*]] = inttoptr i64 [[TMP228]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP230:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP229]], i32 [[TMP227]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP231:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP230]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP232:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP231]], i32 0, i32 0, i64 31
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP45]], ptr addrspace(22) [[TMP232]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP233:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP234:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP235:%.*]] = inttoptr i64 [[TMP234]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP236:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP235]], i32 [[TMP233]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP237:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP236]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP238:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP237]], i32 0, i32 0, i64 32
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP52]], ptr addrspace(22) [[TMP238]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP239:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP240:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP241:%.*]] = inttoptr i64 [[TMP240]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP242:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP241]], i32 [[TMP239]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP243:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP242]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP244:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP243]], i32 0, i32 0, i64 33
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP59]], ptr addrspace(22) [[TMP244]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP245:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP246:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP247:%.*]] = inttoptr i64 [[TMP246]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP248:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP247]], i32 [[TMP245]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP249:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP248]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP250:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP249]], i32 0, i32 0, i64 34
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP66]], ptr addrspace(22) [[TMP250]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP251:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP252:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP253:%.*]] = inttoptr i64 [[TMP252]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP254:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP253]], i32 [[TMP251]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP255:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP254]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP256:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP255]], i32 0, i32 0, i64 35
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP73]], ptr addrspace(22) [[TMP256]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP257:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP258:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP259:%.*]] = inttoptr i64 [[TMP258]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP260:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP259]], i32 [[TMP257]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP261:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP260]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP262:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP261]], i32 0, i32 0, i64 36
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP80]], ptr addrspace(22) [[TMP262]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP263:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP264:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP265:%.*]] = inttoptr i64 [[TMP264]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP266:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP265]], i32 [[TMP263]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP267:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP266]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP268:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP267]], i32 0, i32 0, i64 37
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP87]], ptr addrspace(22) [[TMP268]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP269:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP270:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP271:%.*]] = inttoptr i64 [[TMP270]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP272:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP271]], i32 [[TMP269]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP273:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP272]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP274:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP273]], i32 0, i32 0, i64 38
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP94]], ptr addrspace(22) [[TMP274]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP275:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP276:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP277:%.*]] = inttoptr i64 [[TMP276]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP278:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP277]], i32 [[TMP275]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP279:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP278]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP280:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP279]], i32 0, i32 0, i64 39
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP101]], ptr addrspace(22) [[TMP280]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP281:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP282:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP283:%.*]] = inttoptr i64 [[TMP282]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP284:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP283]], i32 [[TMP281]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP285:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP284]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP286:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP285]], i32 0, i32 0, i64 40
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP108]], ptr addrspace(22) [[TMP286]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP287:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP288:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP289:%.*]] = inttoptr i64 [[TMP288]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP290:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP289]], i32 [[TMP287]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP291:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP290]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP292:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP291]], i32 0, i32 0, i64 41
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP115]], ptr addrspace(22) [[TMP292]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP293:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP294:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP295:%.*]] = inttoptr i64 [[TMP294]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP296:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP295]], i32 [[TMP293]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP297:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP296]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP298:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP297]], i32 0, i32 0, i64 42
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP122]], ptr addrspace(22) [[TMP298]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP299:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP300:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP301:%.*]] = inttoptr i64 [[TMP300]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP302:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP301]], i32 [[TMP299]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP303:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP302]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP304:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP303]], i32 0, i32 0, i64 43
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP129]], ptr addrspace(22) [[TMP304]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP305:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP306:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP307:%.*]] = inttoptr i64 [[TMP306]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP308:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP307]], i32 [[TMP305]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP309:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP308]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP310:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP309]], i32 0, i32 0, i64 44
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP136]], ptr addrspace(22) [[TMP310]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP311:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP312:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP313:%.*]] = inttoptr i64 [[TMP312]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP314:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP313]], i32 [[TMP311]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP315:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP314]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP316:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP315]], i32 0, i32 0, i64 45
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP143]], ptr addrspace(22) [[TMP316]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP317:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP318:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP319:%.*]] = inttoptr i64 [[TMP318]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP320:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP319]], i32 [[TMP317]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP321:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP320]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP322:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP321]], i32 0, i32 0, i64 46
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP150]], ptr addrspace(22) [[TMP322]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP323:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP324:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP325:%.*]] = inttoptr i64 [[TMP324]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP326:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP325]], i32 [[TMP323]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP327:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP326]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP328:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP327]], i32 0, i32 0, i64 47
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP157]], ptr addrspace(22) [[TMP328]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP329:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP330:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP331:%.*]] = inttoptr i64 [[TMP330]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP332:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP331]], i32 [[TMP329]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP333:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP332]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP334:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP333]], i32 0, i32 0, i64 48
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP164]], ptr addrspace(22) [[TMP334]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP335:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP336:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP337:%.*]] = inttoptr i64 [[TMP336]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP338:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP337]], i32 [[TMP335]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP339:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP338]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP340:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP339]], i32 0, i32 0, i64 49
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP171]], ptr addrspace(22) [[TMP340]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP341:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP342:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP343:%.*]] = inttoptr i64 [[TMP342]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP344:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP343]], i32 [[TMP341]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP345:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP344]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP346:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP345]], i32 0, i32 0, i64 50
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP178]], ptr addrspace(22) [[TMP346]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP347:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP348:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP349:%.*]] = inttoptr i64 [[TMP348]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP350:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP349]], i32 [[TMP347]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP351:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP350]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP352:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP351]], i32 0, i32 0, i64 51
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP185]], ptr addrspace(22) [[TMP352]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP353:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP354:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP355:%.*]] = inttoptr i64 [[TMP354]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP356:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP355]], i32 [[TMP353]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP357:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP356]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP358:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP357]], i32 0, i32 0, i64 52
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP192]], ptr addrspace(22) [[TMP358]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP359:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP360:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP361:%.*]] = inttoptr i64 [[TMP360]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP362:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP361]], i32 [[TMP359]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP363:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP362]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP364:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP363]], i32 0, i32 0, i64 53
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP199]], ptr addrspace(22) [[TMP364]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP365:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP366:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP367:%.*]] = inttoptr i64 [[TMP366]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP368:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP367]], i32 [[TMP365]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP369:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP368]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP370:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP369]], i32 0, i32 0, i64 54
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP206]], ptr addrspace(22) [[TMP370]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP371:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP372:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP373:%.*]] = inttoptr i64 [[TMP372]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP374:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP373]], i32 [[TMP371]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP375:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP374]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP376:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP375]], i32 0, i32 0, i64 55
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP213]], ptr addrspace(22) [[TMP376]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP377:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP378:%.*]] = call i64 @_cont_GetContinuationStackGlobalMemBase()
+; POST-PROCESS-GLOBAL-NEXT: [[TMP379:%.*]] = inttoptr i64 [[TMP378]] to ptr addrspace(22)
+; POST-PROCESS-GLOBAL-NEXT: [[TMP380:%.*]] = getelementptr i8, ptr addrspace(22) [[TMP379]], i32 [[TMP377]]
+; POST-PROCESS-GLOBAL-NEXT: [[TMP381:%.*]] = getelementptr i32, ptr addrspace(22) [[TMP380]], i32 -30
+; POST-PROCESS-GLOBAL-NEXT: [[TMP382:%.*]] = getelementptr [[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspace(22) [[TMP381]], i32 0, i32 0, i64 56
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP220]], ptr addrspace(22) [[TMP382]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP383:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[TMP384:%.*]] = add i32 [[TMP383]], -108
+; POST-PROCESS-GLOBAL-NEXT: store i32 [[TMP384]], ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, <3 x i32> [[DOTFCA_0_EXTRACT]], 0
+; POST-PROCESS-GLOBAL-NEXT: [[TMP385:%.*]] = load i32, ptr [[CSP]], align 4
+; POST-PROCESS-GLOBAL-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP385]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META18]]
+; POST-PROCESS-GLOBAL-NEXT: unreachable
+;
diff --git a/shared/continuations/test/dx/register-buffer.ll b/shared/continuations/test/dx/register-buffer.ll
index ca58edbd1d..8b75660f34 100644
--- a/shared/continuations/test/dx/register-buffer.ll
+++ b/shared/continuations/test/dx/register-buffer.ll
@@ -15,8 +15,8 @@ declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
;.
-; CHECK: @[[GLOBAL:[a-zA-Z0-9_$"\\.-]+]] = external addrspace(20) global [15 x i32]
-; CHECK: @[[GLOBAL_NO_REGS:[a-zA-Z0-9_$"\\.-]+]] = external addrspace(20) global [0 x i32]
+; CHECK: @GLOBAL = external addrspace(20) global [15 x i32]
+; CHECK: @GLOBAL_NO_REGS = external addrspace(20) global [0 x i32]
;.
define i32 @load_i32_reg() {
; CHECK-LABEL: define i32 @load_i32_reg() {
diff --git a/shared/continuations/test/dx/remat-intrinsic.ll b/shared/continuations/test/dx/remat-intrinsic.ll
index 8073d3b6d8..973927526b 100644
--- a/shared/continuations/test/dx/remat-intrinsic.ll
+++ b/shared/continuations/test/dx/remat-intrinsic.ll
@@ -124,86 +124,69 @@ attributes #1 = { nounwind }
;
;
; SAVESTATE-LABEL: define void @called(
-; SAVESTATE-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !continuation !15 !lgc.rt.shaderstage !16 !continuation.registercount !17 !continuation.state !18 !continuation.stacksize !18 {
+; SAVESTATE-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !continuation [[META15:![0-9]+]] !lgc.rt.shaderstage [[META16:![0-9]+]] !continuation.registercount [[META17:![0-9]+]] !continuation.state [[META18:![0-9]+]] !continuation.stacksize [[META18]] {
; SAVESTATE-NEXT: AllocaSpillBB:
-; SAVESTATE-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
-; SAVESTATE-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
; SAVESTATE-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; SAVESTATE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
+; SAVESTATE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
+; SAVESTATE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
; SAVESTATE-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
-; SAVESTATE-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[CALLED_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; SAVESTATE-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
-; SAVESTATE-NEXT: [[TMP1:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA]], align 4
-; SAVESTATE-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
+; SAVESTATE-NEXT: [[TMP1:%.*]] = load i32, ptr [[CSP]], align 4
+; SAVESTATE-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
+; SAVESTATE-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP2]], i64 0
+; SAVESTATE-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[CALLED_FRAME:%.*]], ptr addrspace(21) [[TMP3]], i32 0, i32 0
+; SAVESTATE-NEXT: store i64 [[RETURNADDR]], ptr addrspace(21) [[RETURNADDR_SPILL_ADDR]], align 4
+; SAVESTATE-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], 0
+; SAVESTATE-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; SAVESTATE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; SAVESTATE-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; SAVESTATE-NEXT: [[TMP3:%.*]] = call <3 x i32> @_cont_DispatchRaysIndex3(ptr [[SYSTEM_DATA]])
-; SAVESTATE-NEXT: [[I:%.*]] = extractelement <3 x i32> [[TMP3]], i8 0
+; SAVESTATE-NEXT: [[TMP5:%.*]] = call <3 x i32> @_cont_DispatchRaysIndex3(ptr [[SYSTEM_DATA_ALLOCA]])
+; SAVESTATE-NEXT: [[I:%.*]] = extractelement <3 x i32> [[TMP5]], i8 0
; SAVESTATE-NEXT: [[UNPACKED:%.*]] = call [[DX_TYPES_FOURI32:%.*]] @dx.op.unpack4x8.i32(i32 219, i8 1, i32 [[I]])
; SAVESTATE-NEXT: [[HANDLE0:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
; SAVESTATE-NEXT: [[HANDLE1:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[HANDLE0]])
; SAVESTATE-NEXT: [[HANDLE2:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[HANDLE1]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
; SAVESTATE-NEXT: [[DIS_DATA_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, i32 [[DOTFCA_0_EXTRACT]], 0
-; SAVESTATE-NEXT: store i32 [[TMP2]], ptr addrspace(20) @REGISTERS, align 4
-; SAVESTATE-NEXT: [[TMP4:%.*]] = load i32, ptr [[CSP]], align 4
-; SAVESTATE-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], 8
-; SAVESTATE-NEXT: store i32 [[TMP5]], ptr [[CSP]], align 4
-; SAVESTATE-NEXT: [[TMP6:%.*]] = inttoptr i32 [[TMP4]] to ptr addrspace(21)
-; SAVESTATE-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; SAVESTATE-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP6]], i32 0, i32 0
-; SAVESTATE-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP7]], align 4
-; SAVESTATE-NEXT: store i32 [[TMP9]], ptr addrspace(21) [[TMP8]], align 4
-; SAVESTATE-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; SAVESTATE-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP6]], i32 0, i32 1
-; SAVESTATE-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP10]], align 4
-; SAVESTATE-NEXT: store i32 [[TMP12]], ptr addrspace(21) [[TMP11]], align 4
-; SAVESTATE-NEXT: [[TMP13:%.*]] = load i32, ptr [[CSP]], align 4
-; SAVESTATE-NEXT: [[TMP14:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @called.resume.0 to i64))
-; SAVESTATE-NEXT: call void (i64, ...) @continuation.continue(i64 2, i32 [[TMP13]], i64 [[TMP14]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I_FCA_0_INSERT]]), !continuation.registercount !17, !continuation.returnedRegistercount !17
+; SAVESTATE-NEXT: store i32 [[TMP4]], ptr addrspace(20) @REGISTERS, align 4
+; SAVESTATE-NEXT: [[TMP6:%.*]] = load i32, ptr [[CSP]], align 4
+; SAVESTATE-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], 8
+; SAVESTATE-NEXT: store i32 [[TMP7]], ptr [[CSP]], align 4
+; SAVESTATE-NEXT: [[TMP8:%.*]] = load i32, ptr [[CSP]], align 4
+; SAVESTATE-NEXT: [[TMP9:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @called.resume.0 to i64))
+; SAVESTATE-NEXT: call void (i64, ...) @continuation.continue(i64 2, i32 [[TMP8]], i64 [[TMP9]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I_FCA_0_INSERT]]), !continuation.registercount [[META17]], !continuation.returnedRegistercount !17
; SAVESTATE-NEXT: unreachable
;
;
; SAVESTATE-LABEL: define dso_local void @called.resume.0(
-; SAVESTATE-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !continuation !15 !lgc.rt.shaderstage !16 !continuation.registercount !17 {
+; SAVESTATE-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !continuation [[META15]] !lgc.rt.shaderstage [[META16]] !continuation.registercount [[META17]] {
; SAVESTATE-NEXT: entryresume.0:
-; SAVESTATE-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
-; SAVESTATE-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
; SAVESTATE-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; SAVESTATE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA]], align 4
+; SAVESTATE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
+; SAVESTATE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
; SAVESTATE-NEXT: store i32 [[TMP0]], ptr [[CSP]], align 4
; SAVESTATE-NEXT: [[TMP2:%.*]] = load i32, ptr [[CSP]], align 4
-; SAVESTATE-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(21)
-; SAVESTATE-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP3]], i64 -8
-; SAVESTATE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 0
-; SAVESTATE-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; SAVESTATE-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(21) [[TMP5]], align 4
-; SAVESTATE-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
-; SAVESTATE-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 1
-; SAVESTATE-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; SAVESTATE-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(21) [[TMP8]], align 4
-; SAVESTATE-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4
-; SAVESTATE-NEXT: [[TMP11:%.*]] = load i32, ptr [[CSP]], align 4
-; SAVESTATE-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], -8
-; SAVESTATE-NEXT: store i32 [[TMP12]], ptr [[CSP]], align 4
-; SAVESTATE-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; SAVESTATE-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], -8
+; SAVESTATE-NEXT: store i32 [[TMP3]], ptr [[CSP]], align 4
+; SAVESTATE-NEXT: [[TMP4:%.*]] = load i32, ptr [[CSP]], align 4
+; SAVESTATE-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP4]] to ptr addrspace(21)
+; SAVESTATE-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP5]], i64 0
+; SAVESTATE-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; SAVESTATE-NEXT: [[DOTFCA_0_EXTRACT3:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
; SAVESTATE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; SAVESTATE-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[CALLED_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; SAVESTATE-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr [[RETURNADDR_RELOAD_ADDR]], align 4
+; SAVESTATE-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[CALLED_FRAME:%.*]], ptr addrspace(21) [[TMP6]], i32 0, i32 0
+; SAVESTATE-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr addrspace(21) [[RETURNADDR_RELOAD_ADDR]], align 4
; SAVESTATE-NEXT: [[HANDLE011:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
; SAVESTATE-NEXT: [[HANDLE110:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[HANDLE011]])
; SAVESTATE-NEXT: [[HANDLE29:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[HANDLE110]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
-; SAVESTATE-NEXT: [[TMP14:%.*]] = call <3 x i32> @_cont_DispatchRaysIndex3(ptr [[SYSTEM_DATA]])
-; SAVESTATE-NEXT: [[I8:%.*]] = extractelement <3 x i32> [[TMP14]], i8 0
+; SAVESTATE-NEXT: [[TMP8:%.*]] = call <3 x i32> @_cont_DispatchRaysIndex3(ptr [[SYSTEM_DATA_ALLOCA]])
+; SAVESTATE-NEXT: [[I8:%.*]] = extractelement <3 x i32> [[TMP8]], i8 0
; SAVESTATE-NEXT: [[UNPACKED7:%.*]] = call [[DX_TYPES_FOURI32:%.*]] @dx.op.unpack4x8.i32(i32 219, i8 1, i32 [[I8]])
-; SAVESTATE-NEXT: [[TMP15:%.*]] = call <3 x i32> @_cont_DispatchRaysIndex3(ptr [[SYSTEM_DATA]])
-; SAVESTATE-NEXT: [[I6:%.*]] = extractelement <3 x i32> [[TMP15]], i8 0
+; SAVESTATE-NEXT: [[TMP9:%.*]] = call <3 x i32> @_cont_DispatchRaysIndex3(ptr [[SYSTEM_DATA_ALLOCA]])
+; SAVESTATE-NEXT: [[I6:%.*]] = extractelement <3 x i32> [[TMP9]], i8 0
; SAVESTATE-NEXT: [[UNPACKED5:%.*]] = call [[DX_TYPES_FOURI32]] @dx.op.unpack4x8.i32(i32 219, i8 1, i32 [[I6]])
-; SAVESTATE-NEXT: [[TMP16:%.*]] = call <3 x i32> @_cont_DispatchRaysIndex3(ptr [[SYSTEM_DATA]])
-; SAVESTATE-NEXT: [[I4:%.*]] = extractelement <3 x i32> [[TMP16]], i8 0
+; SAVESTATE-NEXT: [[TMP10:%.*]] = call <3 x i32> @_cont_DispatchRaysIndex3(ptr [[SYSTEM_DATA_ALLOCA]])
+; SAVESTATE-NEXT: [[I4:%.*]] = extractelement <3 x i32> [[TMP10]], i8 0
; SAVESTATE-NEXT: [[UNPACKED3:%.*]] = call [[DX_TYPES_FOURI32]] @dx.op.unpack4x8.i32(i32 219, i8 1, i32 [[I4]])
-; SAVESTATE-NEXT: [[TMP17:%.*]] = call <3 x i32> @_cont_DispatchRaysIndex3(ptr [[SYSTEM_DATA]])
-; SAVESTATE-NEXT: [[I2:%.*]] = extractelement <3 x i32> [[TMP17]], i8 0
+; SAVESTATE-NEXT: [[TMP11:%.*]] = call <3 x i32> @_cont_DispatchRaysIndex3(ptr [[SYSTEM_DATA_ALLOCA]])
+; SAVESTATE-NEXT: [[I2:%.*]] = extractelement <3 x i32> [[TMP11]], i8 0
; SAVESTATE-NEXT: [[UNPACKED1:%.*]] = call [[DX_TYPES_FOURI32]] @dx.op.unpack4x8.i32(i32 219, i8 1, i32 [[I2]])
; SAVESTATE-NEXT: [[A:%.*]] = extractvalue [[DX_TYPES_FOURI32]] [[UNPACKED7]], 0
; SAVESTATE-NEXT: [[B:%.*]] = extractvalue [[DX_TYPES_FOURI32]] [[UNPACKED5]], 1
@@ -213,7 +196,7 @@ attributes #1 = { nounwind }
; SAVESTATE-NEXT: call void @dx.op.textureStore.f32(i32 67, [[DX_TYPES_HANDLE]] [[HANDLE29]], i32 0, i32 0, i32 undef, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 1.000000e+00, i8 15)
; SAVESTATE-NEXT: store i32 [[PACKED]], ptr addrspace(20) @REGISTERS, align 4
; SAVESTATE-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, i32 [[DOTFCA_0_EXTRACT3]], 0
-; SAVESTATE-NEXT: [[TMP18:%.*]] = load i32, ptr [[CSP]], align 4
-; SAVESTATE-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP18]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount !17
+; SAVESTATE-NEXT: [[TMP12:%.*]] = load i32, ptr [[CSP]], align 4
+; SAVESTATE-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP12]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META17]]
; SAVESTATE-NEXT: unreachable
;
diff --git a/shared/continuations/test/dx/remove-types-metadata.ll b/shared/continuations/test/dx/remove-types-metadata.ll
index c46a10a41d..4b9eaa9587 100644
--- a/shared/continuations/test/dx/remove-types-metadata.ll
+++ b/shared/continuations/test/dx/remove-types-metadata.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-attributes --check-globals --version 2
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-attributes --check-globals --version 3
; RUN: opt --verify-each -passes='remove-types-metadata' -S %s 2> %t.stderr | FileCheck -check-prefix=METADATA %s
; RUN: count 0 < %t.stderr
@@ -65,8 +65,8 @@ declare !types !42 void @_cont_IgnoreHit(%struct.DispatchSystemData* nocapture r
declare !types !43 void @_AmdAcceptHitAttributes(%struct.AnyHitTraversalData* nocapture readnone) #1
define void @_cont_TraceRay(%struct.DispatchSystemData* %data, i64 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, float %6, float %7, float %8, float %9, float %10, float %11, float %12, float %13) #0 !types !44 {
-; METADATA-LABEL: define void @_cont_TraceRay
-; METADATA-SAME: (ptr [[DATA:%.*]], i64 [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]], i32 [[TMP3:%.*]], i32 [[TMP4:%.*]], i32 [[TMP5:%.*]], float [[TMP6:%.*]], float [[TMP7:%.*]], float [[TMP8:%.*]], float [[TMP9:%.*]], float [[TMP10:%.*]], float [[TMP11:%.*]], float [[TMP12:%.*]], float [[TMP13:%.*]]) #[[ATTR0:[0-9]+]] {
+; METADATA-LABEL: define void @_cont_TraceRay(
+; METADATA-SAME: ptr [[DATA:%.*]], i64 [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]], i32 [[TMP3:%.*]], i32 [[TMP4:%.*]], i32 [[TMP5:%.*]], float [[TMP6:%.*]], float [[TMP7:%.*]], float [[TMP8:%.*]], float [[TMP9:%.*]], float [[TMP10:%.*]], float [[TMP11:%.*]], float [[TMP12:%.*]], float [[TMP13:%.*]]) #[[ATTR0:[0-9]+]] {
; METADATA-NEXT: [[DIS_DATA:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[DATA]], align 4
; METADATA-NEXT: [[SYS_DATA:%.*]] = insertvalue [[STRUCT_SYSTEMDATA:%.*]] undef, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA]], 0
; METADATA-NEXT: [[TRAV_DATA:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA:%.*]] undef, [[STRUCT_SYSTEMDATA]] [[SYS_DATA]], 0
@@ -89,8 +89,8 @@ define void @_cont_TraceRay(%struct.DispatchSystemData* %data, i64 %0, i32 %1, i
}
define void @_cont_CallShader(%struct.DispatchSystemData* %data, i32 %0) #0 !types !45 {
-; METADATA-LABEL: define void @_cont_CallShader
-; METADATA-SAME: (ptr [[DATA:%.*]], i32 [[TMP0:%.*]]) #[[ATTR0]] {
+; METADATA-LABEL: define void @_cont_CallShader(
+; METADATA-SAME: ptr [[DATA:%.*]], i32 [[TMP0:%.*]]) #[[ATTR0]] {
; METADATA-NEXT: [[DIS_DATA:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[DATA]], align 4
; METADATA-NEXT: [[NEWDATA:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @_AmdAwaitShader(i64 2, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA]])
; METADATA-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[NEWDATA]], ptr [[DATA]], align 4
@@ -105,8 +105,8 @@ define void @_cont_CallShader(%struct.DispatchSystemData* %data, i32 %0) #0 !typ
}
define i1 @_cont_ReportHit(%struct.AnyHitTraversalData* %data, float %t, i32 %hitKind) #0 !types !46 {
-; METADATA-LABEL: define i1 @_cont_ReportHit
-; METADATA-SAME: (ptr [[DATA:%.*]], float [[T:%.*]], i32 [[HITKIND:%.*]]) #[[ATTR0]] {
+; METADATA-LABEL: define i1 @_cont_ReportHit(
+; METADATA-SAME: ptr [[DATA:%.*]], float [[T:%.*]], i32 [[HITKIND:%.*]]) #[[ATTR0]] {
; METADATA-NEXT: [[ORIGTPTR:%.*]] = getelementptr inbounds [[STRUCT_ANYHITTRAVERSALDATA:%.*]], ptr [[DATA]], i32 0, i32 0, i32 4
; METADATA-NEXT: [[ORIGT:%.*]] = load float, ptr [[ORIGTPTR]], align 4
; METADATA-NEXT: [[ISNOHIT:%.*]] = fcmp fast uge float [[T]], [[ORIGT]]
@@ -139,8 +139,8 @@ isEnd: ; preds = %0
}
define i32 @_cont_DispatchRaysIndex(%struct.DispatchSystemData* %data, i32 %i) !types !47 {
-; METADATA-LABEL: define i32 @_cont_DispatchRaysIndex
-; METADATA-SAME: (ptr [[DATA:%.*]], i32 [[I:%.*]]) {
+; METADATA-LABEL: define i32 @_cont_DispatchRaysIndex(
+; METADATA-SAME: ptr [[DATA:%.*]], i32 [[I:%.*]]) {
; METADATA-NEXT: [[RESPTR:%.*]] = getelementptr [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[DATA]], i32 0, i32 0, i32 [[I]]
; METADATA-NEXT: [[RES:%.*]] = load i32, ptr [[RESPTR]], align 4
; METADATA-NEXT: ret i32 [[RES]]
@@ -151,8 +151,8 @@ define i32 @_cont_DispatchRaysIndex(%struct.DispatchSystemData* %data, i32 %i) !
}
define float @_cont_ObjectRayOrigin(%struct.DispatchSystemData* nocapture readnone %data, %struct.HitData* %hitData, i32 %i) !types !48 {
-; METADATA-LABEL: define float @_cont_ObjectRayOrigin
-; METADATA-SAME: (ptr nocapture readnone [[DATA:%.*]], ptr [[HITDATA:%.*]], i32 [[I:%.*]]) {
+; METADATA-LABEL: define float @_cont_ObjectRayOrigin(
+; METADATA-SAME: ptr nocapture readnone [[DATA:%.*]], ptr [[HITDATA:%.*]], i32 [[I:%.*]]) {
; METADATA-NEXT: [[RESPTR:%.*]] = getelementptr [[STRUCT_HITDATA:%.*]], ptr [[HITDATA]], i32 0, i32 0, i32 [[I]]
; METADATA-NEXT: [[RES:%.*]] = load float, ptr [[RESPTR]], align 4
; METADATA-NEXT: ret float [[RES]]
@@ -163,8 +163,8 @@ define float @_cont_ObjectRayOrigin(%struct.DispatchSystemData* nocapture readno
}
define float @_cont_ObjectRayDirection(%struct.DispatchSystemData* nocapture readnone %data, %struct.HitData* %hitData, i32 %i) !types !48 {
-; METADATA-LABEL: define float @_cont_ObjectRayDirection
-; METADATA-SAME: (ptr nocapture readnone [[DATA:%.*]], ptr [[HITDATA:%.*]], i32 [[I:%.*]]) {
+; METADATA-LABEL: define float @_cont_ObjectRayDirection(
+; METADATA-SAME: ptr nocapture readnone [[DATA:%.*]], ptr [[HITDATA:%.*]], i32 [[I:%.*]]) {
; METADATA-NEXT: [[RESPTR:%.*]] = getelementptr [[STRUCT_HITDATA:%.*]], ptr [[HITDATA]], i32 0, i32 1, i32 [[I]]
; METADATA-NEXT: [[RES:%.*]] = load float, ptr [[RESPTR]], align 4
; METADATA-NEXT: ret float [[RES]]
@@ -175,8 +175,8 @@ define float @_cont_ObjectRayDirection(%struct.DispatchSystemData* nocapture rea
}
define float @_cont_RayTCurrent(%struct.DispatchSystemData* nocapture readnone %data, %struct.HitData* %hitData) !types !50 {
-; METADATA-LABEL: define float @_cont_RayTCurrent
-; METADATA-SAME: (ptr nocapture readnone [[DATA:%.*]], ptr [[HITDATA:%.*]]) {
+; METADATA-LABEL: define float @_cont_RayTCurrent(
+; METADATA-SAME: ptr nocapture readnone [[DATA:%.*]], ptr [[HITDATA:%.*]]) {
; METADATA-NEXT: [[RESPTR:%.*]] = getelementptr [[STRUCT_HITDATA:%.*]], ptr [[HITDATA]], i32 0, i32 2
; METADATA-NEXT: [[RES:%.*]] = load float, ptr [[RESPTR]], align 4
; METADATA-NEXT: ret float [[RES]]
@@ -189,8 +189,8 @@ define float @_cont_RayTCurrent(%struct.DispatchSystemData* nocapture readnone %
; Function Attrs: nounwind
define void @MyRayGen() #2 {
; METADATA: Function Attrs: nounwind
-; METADATA-LABEL: define void @MyRayGen
-; METADATA-SAME: () #[[ATTR2:[0-9]+]] {
+; METADATA-LABEL: define void @MyRayGen(
+; METADATA-SAME: ) #[[ATTR2:[0-9]+]] {
; METADATA-NEXT: [[TMP1:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
; METADATA-NEXT: [[TMP2:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
; METADATA-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 4
@@ -241,8 +241,8 @@ define void @MyRayGen() #2 {
; Function Attrs: nounwind
define void @MyClosestHitShader(%struct.RayPayload* noalias nocapture %payload, %struct.BuiltInTriangleIntersectionAttributes* nocapture readonly %attr) #2 !types !54 {
; METADATA: Function Attrs: nounwind
-; METADATA-LABEL: define void @MyClosestHitShader
-; METADATA-SAME: (ptr noalias nocapture [[PAYLOAD:%.*]], ptr nocapture readonly [[ATTR:%.*]]) #[[ATTR2]] {
+; METADATA-LABEL: define void @MyClosestHitShader(
+; METADATA-SAME: ptr noalias nocapture [[PAYLOAD:%.*]], ptr nocapture readonly [[ATTR:%.*]]) #[[ATTR2]] {
; METADATA-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]], ptr [[ATTR]], i32 0, i32 0
; METADATA-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[TMP1]], align 4
; METADATA-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
@@ -275,8 +275,8 @@ define void @MyClosestHitShader(%struct.RayPayload* noalias nocapture %payload,
; Function Attrs: nounwind
define void @MyAnyHitShader(%struct.RayPayload* noalias nocapture %payload, %struct.BuiltInTriangleIntersectionAttributes* nocapture readnone %attr) #2 !types !54 {
; METADATA: Function Attrs: nounwind
-; METADATA-LABEL: define void @MyAnyHitShader
-; METADATA-SAME: (ptr noalias nocapture [[PAYLOAD:%.*]], ptr nocapture readnone [[ATTR:%.*]]) #[[ATTR2]] {
+; METADATA-LABEL: define void @MyAnyHitShader(
+; METADATA-SAME: ptr noalias nocapture [[PAYLOAD:%.*]], ptr nocapture readnone [[ATTR:%.*]]) #[[ATTR2]] {
; METADATA-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD:%.*]], ptr [[PAYLOAD]], i32 0, i32 0
; METADATA-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[TMP1]], align 4
; METADATA-NEXT: [[TMP3:%.*]] = call float @dx.op.objectRayOrigin.f32(i32 149, i8 0)
@@ -357,8 +357,8 @@ define void @MyAnyHitShader(%struct.RayPayload* noalias nocapture %payload, %str
; Function Attrs: nounwind
define void @MyIntersectionShader() #2 {
; METADATA: Function Attrs: nounwind
-; METADATA-LABEL: define void @MyIntersectionShader
-; METADATA-SAME: () #[[ATTR2]] {
+; METADATA-LABEL: define void @MyIntersectionShader(
+; METADATA-SAME: ) #[[ATTR2]] {
; METADATA-NEXT: [[TMP1:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]], align 4
; METADATA-NEXT: [[TMP2:%.*]] = call float @dx.op.rayTCurrent.f32(i32 154)
; METADATA-NEXT: [[TMP3:%.*]] = bitcast ptr [[TMP1]] to ptr
@@ -379,8 +379,8 @@ define void @MyIntersectionShader() #2 {
; Function Attrs: nounwind
define void @MyMissShader(%struct.RayPayload* noalias nocapture %payload) #2 !types !57 {
; METADATA: Function Attrs: nounwind
-; METADATA-LABEL: define void @MyMissShader
-; METADATA-SAME: (ptr noalias nocapture [[PAYLOAD:%.*]]) #[[ATTR2]] {
+; METADATA-LABEL: define void @MyMissShader(
+; METADATA-SAME: ptr noalias nocapture [[PAYLOAD:%.*]]) #[[ATTR2]] {
; METADATA-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD:%.*]], ptr [[PAYLOAD]], i32 0, i32 0
; METADATA-NEXT: store <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, ptr [[TMP1]], align 4
; METADATA-NEXT: ret void
@@ -512,38 +512,38 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; METADATA: attributes #[[ATTR4:[0-9]+]] = { nounwind memory(read) }
; METADATA: attributes #[[ATTR5:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
;.
-; METADATA: [[META0:![0-9]+]] = !{!"clang version 3.7.0 (tags/RELEASE_370/final)"}
+; METADATA: [[META0:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
; METADATA: [[META1:![0-9]+]] = !{i32 1, i32 6}
; METADATA: [[META2:![0-9]+]] = !{!"lib", i32 6, i32 6}
-; METADATA: [[META3:![0-9]+]] = !{!4, !7, null, null}
-; METADATA: [[META4:![0-9]+]] = !{!5}
-; METADATA: [[META5:![0-9]+]] = !{i32 0, ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", !"Scene", i32 0, i32 0, i32 1, i32 16, i32 0, !6}
-; METADATA: [[META6:![0-9]+]] = !{i32 0, i32 4}
-; METADATA: [[META7:![0-9]+]] = !{!8}
-; METADATA: [[META8:![0-9]+]] = !{i32 0, ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", !"RenderTarget", i32 0, i32 0, i32 1, i32 2, i1 false, i1 false, i1 false, !9}
-; METADATA: [[META9:![0-9]+]] = !{i32 0, i32 9}
-; METADATA: [[META10:![0-9]+]] = !{i32 1, ptr @MyRayGen, !11, ptr @MyClosestHitShader, !14, ptr @MyAnyHitShader, !14, ptr @MyIntersectionShader, !11, ptr @MyMissShader, !17}
-; METADATA: [[META11:![0-9]+]] = !{!12}
-; METADATA: [[META12:![0-9]+]] = !{i32 1, !13, !13}
-; METADATA: [[META13:![0-9]+]] = !{}
-; METADATA: [[META14:![0-9]+]] = !{!12, !15, !16}
-; METADATA: [[META15:![0-9]+]] = !{i32 2, !13, !13}
-; METADATA: [[META16:![0-9]+]] = !{i32 0, !13, !13}
-; METADATA: [[META17:![0-9]+]] = !{!12, !15}
-; METADATA: [[META18:![0-9]+]] = !{null, !"", null, !3, !19}
-; METADATA: [[META19:![0-9]+]] = !{i32 0, i64 65536}
-; METADATA: [[META20:![0-9]+]] = !{ptr @MyAnyHitShader, !"MyAnyHitShader", null, null, !21}
-; METADATA: [[META21:![0-9]+]] = !{i32 8, i32 9, i32 6, i32 16, i32 7, i32 8, i32 5, !22}
-; METADATA: [[META22:![0-9]+]] = !{i32 0}
-; METADATA: [[META23:![0-9]+]] = !{ptr @MyClosestHitShader, !"MyClosestHitShader", null, null, !24}
-; METADATA: [[META24:![0-9]+]] = !{i32 8, i32 10, i32 6, i32 16, i32 7, i32 8, i32 5, !22}
-; METADATA: [[META25:![0-9]+]] = !{ptr @MyIntersectionShader, !"MyIntersectionShader", null, null, !26}
-; METADATA: [[META26:![0-9]+]] = !{i32 8, i32 8, i32 5, !22}
-; METADATA: [[META27:![0-9]+]] = !{ptr @MyMissShader, !"MyMissShader", null, null, !28}
-; METADATA: [[META28:![0-9]+]] = !{i32 8, i32 11, i32 6, i32 16, i32 5, !22}
-; METADATA: [[META29:![0-9]+]] = !{ptr @MyRayGen, !"MyRayGen", null, null, !30}
-; METADATA: [[META30:![0-9]+]] = !{i32 8, i32 7, i32 5, !22}
-; METADATA: [[TBAA31]] = !{!32, !32, i64 0}
-; METADATA: [[META32:![0-9]+]] = !{!"omnipotent char", !33, i64 0}
-; METADATA: [[META33:![0-9]+]] = !{!"Simple C/C++ TBAA"}
+; METADATA: [[META3:![0-9]+]] = !{[[META4:![0-9]+]], [[META7:![0-9]+]], null, null}
+; METADATA: [[META4]] = !{[[META5:![0-9]+]]}
+; METADATA: [[META5]] = !{i32 0, ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", !"Scene", i32 0, i32 0, i32 1, i32 16, i32 0, [[META6:![0-9]+]]}
+; METADATA: [[META6]] = !{i32 0, i32 4}
+; METADATA: [[META7]] = !{[[META8:![0-9]+]]}
+; METADATA: [[META8]] = !{i32 0, ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", !"RenderTarget", i32 0, i32 0, i32 1, i32 2, i1 false, i1 false, i1 false, [[META9:![0-9]+]]}
+; METADATA: [[META9]] = !{i32 0, i32 9}
+; METADATA: [[META10:![0-9]+]] = !{i32 1, ptr @MyRayGen, [[META11:![0-9]+]], ptr @MyClosestHitShader, [[META14:![0-9]+]], ptr @MyAnyHitShader, [[META14]], ptr @MyIntersectionShader, [[META11]], ptr @MyMissShader, [[META17:![0-9]+]]}
+; METADATA: [[META11]] = !{[[META12:![0-9]+]]}
+; METADATA: [[META12]] = !{i32 1, [[META13:![0-9]+]], [[META13]]}
+; METADATA: [[META13]] = !{}
+; METADATA: [[META14]] = !{[[META12]], [[META15:![0-9]+]], [[META16:![0-9]+]]}
+; METADATA: [[META15]] = !{i32 2, [[META13]], [[META13]]}
+; METADATA: [[META16]] = !{i32 0, [[META13]], [[META13]]}
+; METADATA: [[META17]] = !{[[META12]], [[META15]]}
+; METADATA: [[META18:![0-9]+]] = !{null, !"", null, [[META3]], [[META19:![0-9]+]]}
+; METADATA: [[META19]] = !{i32 0, i64 65536}
+; METADATA: [[META20:![0-9]+]] = !{ptr @MyAnyHitShader, !"MyAnyHitShader", null, null, [[META21:![0-9]+]]}
+; METADATA: [[META21]] = !{i32 8, i32 9, i32 6, i32 16, i32 7, i32 8, i32 5, [[META22:![0-9]+]]}
+; METADATA: [[META22]] = !{i32 0}
+; METADATA: [[META23:![0-9]+]] = !{ptr @MyClosestHitShader, !"MyClosestHitShader", null, null, [[META24:![0-9]+]]}
+; METADATA: [[META24]] = !{i32 8, i32 10, i32 6, i32 16, i32 7, i32 8, i32 5, [[META22]]}
+; METADATA: [[META25:![0-9]+]] = !{ptr @MyIntersectionShader, !"MyIntersectionShader", null, null, [[META26:![0-9]+]]}
+; METADATA: [[META26]] = !{i32 8, i32 8, i32 5, [[META22]]}
+; METADATA: [[META27:![0-9]+]] = !{ptr @MyMissShader, !"MyMissShader", null, null, [[META28:![0-9]+]]}
+; METADATA: [[META28]] = !{i32 8, i32 11, i32 6, i32 16, i32 5, [[META22]]}
+; METADATA: [[META29:![0-9]+]] = !{ptr @MyRayGen, !"MyRayGen", null, null, [[META30:![0-9]+]]}
+; METADATA: [[META30]] = !{i32 8, i32 7, i32 5, [[META22]]}
+; METADATA: [[TBAA31]] = !{[[META32:![0-9]+]], [[META32]], i64 0}
+; METADATA: [[META32]] = !{!"omnipotent char", [[META33:![0-9]+]], i64 0}
+; METADATA: [[META33]] = !{!"Simple C/C++ TBAA"}
;.
diff --git a/shared/continuations/test/dx/traceray.ll b/shared/continuations/test/dx/traceray.ll
index b45c2701b3..b86cca5a9d 100644
--- a/shared/continuations/test/dx/traceray.ll
+++ b/shared/continuations/test/dx/traceray.ll
@@ -408,11 +408,10 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
;
;
; LOWERRAYTRACINGPIPELINE-LABEL: define void @MyRayGen(
-; LOWERRAYTRACINGPIPELINE-SAME: ) #[[ATTR3:[0-9]+]] !lgc.rt.shaderstage [[META23:![0-9]+]] !continuation.entry [[META14:![0-9]+]] !continuation.registercount [[META23]] !continuation [[META35:![0-9]+]] {
-; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP1:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; LOWERRAYTRACINGPIPELINE-SAME: [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] !lgc.rt.shaderstage [[META23:![0-9]+]] !continuation.entry [[META14:![0-9]+]] !continuation.registercount [[META23]] !continuation [[META35:![0-9]+]] {
+; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP2:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 4
@@ -462,7 +461,7 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP33]], ptr [[TMP32]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP22]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; LOWERRAYTRACINGPIPELINE-NEXT: br label [[DOTSPLIT:%.*]]
; LOWERRAYTRACINGPIPELINE: .split:
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = load <4 x float>, ptr [[TMP6]], align 4, !tbaa [[TBAA36]]
@@ -487,68 +486,67 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[HITATTRS:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = call [[STRUCT_SYSTEMDATA]] @continuations.getSystemData.s_struct.SystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP4]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = load i32, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP9]], ptr [[TMP8]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP6]], i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP10]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP12]], ptr [[TMP11]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP10]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[TMP10]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP16]], ptr [[TMP15]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP5]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = load i32, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP8]], ptr [[TMP7]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[TMP5]], i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP9]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP11]], ptr [[TMP10]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP9]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP13]], ptr [[TMP12]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP9]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
; LOWERRAYTRACINGPIPELINE-NEXT: [[ADDR_I:%.*]] = getelementptr [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1
; LOWERRAYTRACINGPIPELINE-NEXT: [[VAL_I:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[ADDR_I]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[VAL_I]], ptr [[TMP2]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP19]], ptr [[TMP17]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP22]], ptr [[TMP20]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[HITATTRS]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = load <2 x float>, ptr [[TMP23]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = extractelement <2 x float> [[TMP24]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = fsub fast float 1.000000e+00, [[TMP25]]
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = extractelement <2 x float> [[TMP24]], i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = fsub fast float [[TMP26]], [[TMP27]]
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = insertelement <4 x float> undef, float [[TMP28]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = insertelement <4 x float> [[TMP29]], float [[TMP25]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = insertelement <4 x float> [[TMP30]], float [[TMP27]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = insertelement <4 x float> [[TMP31]], float 1.000000e+00, i64 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: store <4 x float> [[TMP32]], ptr [[TMP33]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP18]], ptr [[TMP16]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[HITATTRS]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP21]], ptr [[TMP19]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[HITATTRS]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = load <2 x float>, ptr [[TMP22]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = extractelement <2 x float> [[TMP23]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = fsub fast float 1.000000e+00, [[TMP24]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = extractelement <2 x float> [[TMP23]], i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = fsub fast float [[TMP25]], [[TMP26]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = insertelement <4 x float> undef, float [[TMP27]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = insertelement <4 x float> [[TMP28]], float [[TMP24]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = insertelement <4 x float> [[TMP29]], float [[TMP26]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = insertelement <4 x float> [[TMP30]], float 1.000000e+00, i64 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: store <4 x float> [[TMP31]], ptr [[TMP32]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = getelementptr i32, ptr [[TMP34]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = getelementptr i32, ptr [[TMP35]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP36]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP37]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = getelementptr i32, ptr [[TMP34]], i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP39:%.*]] = getelementptr i32, ptr [[TMP38]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP39]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP40]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP41:%.*]] = getelementptr i32, ptr [[TMP38]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP42:%.*]] = load i32, ptr [[TMP41]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP42]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP43:%.*]] = getelementptr i32, ptr [[TMP38]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP44]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP46:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP45]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP46]], !continuation.registercount [[META39]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = getelementptr i32, ptr [[TMP33]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = getelementptr i32, ptr [[TMP34]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP35]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP36]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = getelementptr i32, ptr [[TMP33]], i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = getelementptr i32, ptr [[TMP37]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP39:%.*]] = load i32, ptr [[TMP38]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP39]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP40:%.*]] = getelementptr i32, ptr [[TMP37]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP41]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP42:%.*]] = getelementptr i32, ptr [[TMP37]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP43:%.*]] = load i32, ptr [[TMP42]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP43]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP45:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP44]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP45]], !continuation.registercount [[META39]]
;
;
; LOWERRAYTRACINGPIPELINE-LABEL: define %struct.TraversalData @MyAnyHitShader(
@@ -563,129 +561,128 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[ORIGHITATTRS:%.*]] = alloca [8 x i32], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[HITATTRSALLOCA:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = call [[STRUCT_TRAVERSALDATA]] @continuations.getSystemData.s_struct.TraversalDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_TRAVERSALDATA]] [[TMP10]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP9]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP12]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP13]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = load i32, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP12]], i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[TMP16]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP18]], ptr [[TMP17]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = getelementptr i32, ptr [[TMP16]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP20]], ptr [[TMP19]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[TMP16]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP22]], ptr [[TMP21]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_TRAVERSALDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP9]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP11]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP12]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = load i32, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[TMP11]], i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP15]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP17]], ptr [[TMP16]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = getelementptr i32, ptr [[TMP15]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP19]], ptr [[TMP18]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[TMP15]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP21]], ptr [[TMP20]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[ADDR_I:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[TMP23]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[ADDR_I:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[TMP22]], i32 0, i32 1
; LOWERRAYTRACINGPIPELINE-NEXT: [[VAL_I:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[ADDR_I]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[VAL_I]], ptr [[TMP8]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP26]], ptr [[TMP24]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP29]], ptr [[TMP27]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP25]], ptr [[TMP23]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = getelementptr inbounds i32, ptr [[ORIGHITATTRS]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP28]], ptr [[TMP26]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP1]], ptr [[HITATTRSALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP9]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = load <4 x float>, ptr [[TMP30]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP9]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = load <4 x float>, ptr [[TMP29]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I3:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1
; LOWERRAYTRACINGPIPELINE-NEXT: [[RES_I4:%.*]] = load [[STRUCT_HITDATA]], ptr [[RESPTR_I3]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[RES_I4]], ptr [[TMP4]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = call <3 x float> @_cont_ObjectRayOrigin3(ptr [[TMP32]], ptr [[TMP4]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[EXTRACT1:%.*]] = extractelement <3 x float> [[TMP33]], i8 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = call <3 x float> @_cont_ObjectRayOrigin3(ptr [[TMP31]], ptr [[TMP4]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[EXTRACT1:%.*]] = extractelement <3 x float> [[TMP32]], i8 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1
; LOWERRAYTRACINGPIPELINE-NEXT: [[RES_I:%.*]] = load [[STRUCT_HITDATA]], ptr [[RESPTR_I]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[RES_I]], ptr [[TMP5]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = call <3 x float> @_cont_ObjectRayDirection3(ptr [[TMP34]], ptr [[TMP5]])
-; LOWERRAYTRACINGPIPELINE-NEXT: [[EXTRACT:%.*]] = extractelement <3 x float> [[TMP35]], i8 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = call <3 x float> @_cont_ObjectRayDirection3(ptr [[TMP33]], ptr [[TMP5]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[EXTRACT:%.*]] = extractelement <3 x float> [[TMP34]], i8 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I5:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1
; LOWERRAYTRACINGPIPELINE-NEXT: [[RES_I6:%.*]] = load [[STRUCT_HITDATA]], ptr [[RESPTR_I5]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[RES_I6]], ptr [[TMP3]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[RES_I7:%.*]] = load float, ptr [[TMP3]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = fmul fast float [[RES_I7]], [[EXTRACT]]
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = fadd fast float [[TMP37]], [[EXTRACT1]]
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP39:%.*]] = fcmp fast ogt float [[TMP38]], 0.000000e+00
-; LOWERRAYTRACINGPIPELINE-NEXT: br i1 [[TMP39]], label [[TMP40:%.*]], label [[TMP62:%.*]]
-; LOWERRAYTRACINGPIPELINE: 40:
-; LOWERRAYTRACINGPIPELINE-NEXT: store <4 x float> [[TMP31]], ptr [[TMP30]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @_cont_AcceptHitAndEndSearch(ptr [[TMP41]])
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP36:%.*]] = fmul fast float [[RES_I7]], [[EXTRACT]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP37:%.*]] = fadd fast float [[TMP36]], [[EXTRACT1]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP38:%.*]] = fcmp fast ogt float [[TMP37]], 0.000000e+00
+; LOWERRAYTRACINGPIPELINE-NEXT: br i1 [[TMP38]], label [[TMP39:%.*]], label [[TMP61:%.*]]
+; LOWERRAYTRACINGPIPELINE: 39:
+; LOWERRAYTRACINGPIPELINE-NEXT: store <4 x float> [[TMP30]], ptr [[TMP29]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @_cont_AcceptHitAndEndSearch(ptr [[TMP40]])
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP9]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP43:%.*]] = getelementptr i32, ptr [[TMP42]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP44:%.*]] = getelementptr i32, ptr [[TMP43]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP45:%.*]] = load i32, ptr [[TMP44]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP45]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP46:%.*]] = getelementptr i32, ptr [[TMP42]], i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP47:%.*]] = getelementptr i32, ptr [[TMP46]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP48:%.*]] = load i32, ptr [[TMP47]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP48]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP49:%.*]] = getelementptr i32, ptr [[TMP46]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP50:%.*]] = load i32, ptr [[TMP49]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP50]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP51:%.*]] = getelementptr i32, ptr [[TMP46]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP52:%.*]] = load i32, ptr [[TMP51]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP52]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP53:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP54:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP55:%.*]] = load i32, ptr [[TMP53]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP55]], ptr [[TMP54]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP56:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP57:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP58:%.*]] = load i32, ptr [[TMP56]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP58]], ptr [[TMP57]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP59:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP7]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[ADDR_I1:%.*]] = getelementptr [[STRUCT_SYSTEMDATA]], ptr [[TMP60]], i32 0, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP59]], ptr [[ADDR_I1]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP61:%.*]] = load [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_TRAVERSALDATA]] [[TMP61]], !continuation.registercount [[META39]]
-; LOWERRAYTRACINGPIPELINE: 62:
-; LOWERRAYTRACINGPIPELINE-NEXT: store <4 x float> [[TMP31]], ptr [[TMP30]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP9]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP42:%.*]] = getelementptr i32, ptr [[TMP41]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP43:%.*]] = getelementptr i32, ptr [[TMP42]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP44]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP45:%.*]] = getelementptr i32, ptr [[TMP41]], i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP46:%.*]] = getelementptr i32, ptr [[TMP45]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP47:%.*]] = load i32, ptr [[TMP46]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP47]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP48:%.*]] = getelementptr i32, ptr [[TMP45]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP49:%.*]] = load i32, ptr [[TMP48]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP49]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP50:%.*]] = getelementptr i32, ptr [[TMP45]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP51:%.*]] = load i32, ptr [[TMP50]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP51]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP52:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP53:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP54:%.*]] = load i32, ptr [[TMP52]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP54]], ptr [[TMP53]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP55:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP56:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP57:%.*]] = load i32, ptr [[TMP55]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP57]], ptr [[TMP56]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP58:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP7]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[ADDR_I1:%.*]] = getelementptr [[STRUCT_SYSTEMDATA]], ptr [[TMP59]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP58]], ptr [[ADDR_I1]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP60:%.*]] = load [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_TRAVERSALDATA]] [[TMP60]], !continuation.registercount [[META39]]
+; LOWERRAYTRACINGPIPELINE: 61:
+; LOWERRAYTRACINGPIPELINE-NEXT: store <4 x float> [[TMP30]], ptr [[TMP29]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void @_cont_AcceptHit(ptr [[SYSTEM_DATA_ALLOCA]])
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP63:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP9]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr [[TMP63]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP65:%.*]] = getelementptr i32, ptr [[TMP64]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP66:%.*]] = load i32, ptr [[TMP65]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP66]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP67:%.*]] = getelementptr i32, ptr [[TMP63]], i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP68:%.*]] = getelementptr i32, ptr [[TMP67]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP69:%.*]] = load i32, ptr [[TMP68]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP69]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP70:%.*]] = getelementptr i32, ptr [[TMP67]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP71:%.*]] = load i32, ptr [[TMP70]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP71]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP72:%.*]] = getelementptr i32, ptr [[TMP67]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP73:%.*]] = load i32, ptr [[TMP72]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP73]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP74:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP75:%.*]] = getelementptr inbounds i32, ptr [[TMP6]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP76:%.*]] = load i32, ptr [[TMP74]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP76]], ptr [[TMP75]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP77:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP78:%.*]] = getelementptr inbounds i32, ptr [[TMP6]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP79:%.*]] = load i32, ptr [[TMP77]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP79]], ptr [[TMP78]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP80:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP6]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[ADDR_I2:%.*]] = getelementptr [[STRUCT_SYSTEMDATA]], ptr [[TMP81]], i32 0, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP80]], ptr [[ADDR_I2]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP82:%.*]] = load [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_TRAVERSALDATA]] [[TMP82]], !continuation.registercount [[META39]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP9]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP63:%.*]] = getelementptr i32, ptr [[TMP62]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP64:%.*]] = getelementptr i32, ptr [[TMP63]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP65:%.*]] = load i32, ptr [[TMP64]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP65]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP66:%.*]] = getelementptr i32, ptr [[TMP62]], i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP67:%.*]] = getelementptr i32, ptr [[TMP66]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP68:%.*]] = load i32, ptr [[TMP67]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP68]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP69:%.*]] = getelementptr i32, ptr [[TMP66]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP70:%.*]] = load i32, ptr [[TMP69]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP70]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP71:%.*]] = getelementptr i32, ptr [[TMP66]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP72:%.*]] = load i32, ptr [[TMP71]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP72]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP73:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP74:%.*]] = getelementptr inbounds i32, ptr [[TMP6]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP75:%.*]] = load i32, ptr [[TMP73]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP75]], ptr [[TMP74]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP76:%.*]] = getelementptr inbounds i32, ptr [[HITATTRSALLOCA]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP77:%.*]] = getelementptr inbounds i32, ptr [[TMP6]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP78:%.*]] = load i32, ptr [[TMP76]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP78]], ptr [[TMP77]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP79:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP6]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[ADDR_I2:%.*]] = getelementptr [[STRUCT_SYSTEMDATA]], ptr [[TMP80]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP79]], ptr [[ADDR_I2]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP81:%.*]] = load [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_TRAVERSALDATA]] [[TMP81]], !continuation.registercount [[META39]]
;
;
; LOWERRAYTRACINGPIPELINE-LABEL: define %struct.TraversalData @MyIntersectionShader(
@@ -694,52 +691,51 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_TRAVERSALDATA]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = call [[STRUCT_TRAVERSALDATA]] @continuations.getSystemData.s_struct.TraversalDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_TRAVERSALDATA]] [[TMP5]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_TRAVERSALDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1
; LOWERRAYTRACINGPIPELINE-NEXT: [[RES_I:%.*]] = load [[STRUCT_HITDATA]], ptr [[RESPTR_I]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[RES_I]], ptr [[TMP2]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[RES_I1:%.*]] = load float, ptr [[TMP2]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = bitcast ptr [[TMP4]] to ptr
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @llvm.lifetime.start.p0(i64 8, ptr [[TMP8]]) #[[ATTR1]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = bitcast ptr [[TMP4]] to ptr
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @llvm.lifetime.start.p0(i64 8, ptr [[TMP7]]) #[[ATTR1]]
; LOWERRAYTRACINGPIPELINE-NEXT: [[DOANYHIT_I:%.*]] = fcmp fast ogt float [[RES_I1]], 0.000000e+00
; LOWERRAYTRACINGPIPELINE-NEXT: br i1 [[DOANYHIT_I]], label [[ANYHIT_I:%.*]], label [[ACCEPTHIT_I:%.*]]
; LOWERRAYTRACINGPIPELINE: anyhit.i:
; LOWERRAYTRACINGPIPELINE-NEXT: [[TRAV_DATA_I:%.*]] = load [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP4]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = call ptr inttoptr (i64 3 to ptr)([[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]], float [[RES_I1]], i32 0, [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP9]]), !continuation.registercount [[META33]], !continuation.returnedRegistercount !33
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = call [[STRUCT_TRAVERSALDATA]] @await.struct.TraversalData(ptr [[TMP10]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_TRAVERSALDATA]] [[TMP11]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP4]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = call ptr inttoptr (i64 3 to ptr)([[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]], float [[RES_I1]], i32 0, [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP8]]), !continuation.registercount [[META33]], !continuation.returnedRegistercount !33
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = call [[STRUCT_TRAVERSALDATA]] @await.struct.TraversalData(ptr [[TMP9]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_TRAVERSALDATA]] [[TMP10]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; LOWERRAYTRACINGPIPELINE-NEXT: br label [[_CONT_REPORTHIT_EXIT:%.*]]
; LOWERRAYTRACINGPIPELINE: accepthit.i:
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP13]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP18]], ptr [[TMP17]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP3]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[ADDR_I:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[TMP20]], i32 0, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP19]], ptr [[ADDR_I]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP12]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP15]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP17]], ptr [[TMP16]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP3]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[ADDR_I:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[TMP19]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP18]], ptr [[ADDR_I]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: br label [[_CONT_REPORTHIT_EXIT]]
; LOWERRAYTRACINGPIPELINE: _cont_ReportHit.exit:
; LOWERRAYTRACINGPIPELINE-NEXT: [[ISEND_I:%.*]] = call i1 @opaqueIsEnd()
-; LOWERRAYTRACINGPIPELINE-NEXT: br i1 [[ISEND_I]], label [[TMP21:%.*]], label [[TMP23:%.*]]
-; LOWERRAYTRACINGPIPELINE: 21:
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = load [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_TRAVERSALDATA]] [[TMP22]], !continuation.registercount [[META33]]
-; LOWERRAYTRACINGPIPELINE: 23:
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @llvm.lifetime.end.p0(i64 8, ptr [[TMP8]]) #[[ATTR1]]
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = load [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_TRAVERSALDATA]] [[TMP24]], !continuation.registercount [[META33]]
+; LOWERRAYTRACINGPIPELINE-NEXT: br i1 [[ISEND_I]], label [[TMP20:%.*]], label [[TMP22:%.*]]
+; LOWERRAYTRACINGPIPELINE: 20:
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = load [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_TRAVERSALDATA]] [[TMP21]], !continuation.registercount [[META33]]
+; LOWERRAYTRACINGPIPELINE: 22:
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @llvm.lifetime.end.p0(i64 8, ptr [[TMP7]]) #[[ATTR1]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = load [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_TRAVERSALDATA]] [[TMP23]], !continuation.registercount [[META33]]
;
;
; LOWERRAYTRACINGPIPELINE-LABEL: define %struct.TraversalData @MyIntersectionShaderLargeAttrs(
@@ -748,11 +744,10 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = alloca [[STRUCT_LARGEINTERSECTIONATTRIBUTES:%.*]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_TRAVERSALDATA]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = call [[STRUCT_TRAVERSALDATA]] @continuations.getSystemData.s_struct.TraversalDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_TRAVERSALDATA]] [[TMP5]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_TRAVERSALDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[RESPTR_I:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1
; LOWERRAYTRACINGPIPELINE-NEXT: [[RES_I:%.*]] = load [[STRUCT_HITDATA]], ptr [[RESPTR_I]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_HITDATA]] [[RES_I]], ptr [[TMP2]], align 4
@@ -771,105 +766,104 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: store i32 105, ptr [[PTR5]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[PTR6:%.*]] = getelementptr [[STRUCT_LARGEINTERSECTIONATTRIBUTES]], ptr [[TMP4]], i32 0, i32 0, i32 6
; LOWERRAYTRACINGPIPELINE-NEXT: store i32 106, ptr [[PTR6]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = bitcast ptr [[TMP4]] to ptr
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @llvm.lifetime.start.p0(i64 8, ptr [[TMP8]]) #[[ATTR1]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = bitcast ptr [[TMP4]] to ptr
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @llvm.lifetime.start.p0(i64 8, ptr [[TMP7]]) #[[ATTR1]]
; LOWERRAYTRACINGPIPELINE-NEXT: [[DOANYHIT_I:%.*]] = fcmp fast ogt float [[RES_I1]], 0.000000e+00
; LOWERRAYTRACINGPIPELINE-NEXT: br i1 [[DOANYHIT_I]], label [[ANYHIT_I:%.*]], label [[ACCEPTHIT_I:%.*]]
; LOWERRAYTRACINGPIPELINE: anyhit.i:
; LOWERRAYTRACINGPIPELINE-NEXT: [[TRAV_DATA_I:%.*]] = load [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = load [[STRUCT_LARGEINTERSECTIONATTRIBUTES]], ptr [[TMP4]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = call ptr inttoptr (i64 3 to ptr)([[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]], float [[RES_I1]], i32 0, [[STRUCT_LARGEINTERSECTIONATTRIBUTES]] [[TMP9]]), !continuation.registercount [[META33]], !continuation.returnedRegistercount !33
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = call [[STRUCT_TRAVERSALDATA]] @await.struct.TraversalData(ptr [[TMP10]])
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_TRAVERSALDATA]] [[TMP11]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = load [[STRUCT_LARGEINTERSECTIONATTRIBUTES]], ptr [[TMP4]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = call ptr inttoptr (i64 3 to ptr)([[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]], float [[RES_I1]], i32 0, [[STRUCT_LARGEINTERSECTIONATTRIBUTES]] [[TMP8]]), !continuation.registercount [[META33]], !continuation.returnedRegistercount !33
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = call [[STRUCT_TRAVERSALDATA]] @await.struct.TraversalData(ptr [[TMP9]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_TRAVERSALDATA]] [[TMP10]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; LOWERRAYTRACINGPIPELINE-NEXT: br label [[_CONT_REPORTHIT_EXIT:%.*]]
; LOWERRAYTRACINGPIPELINE: accepthit.i:
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP13]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP18]], ptr [[TMP17]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP20]], ptr getelementptr inbounds ([30 x i32], ptr @PAYLOAD, i32 0, i32 1), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 3
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP22]], ptr getelementptr inbounds ([30 x i32], ptr @PAYLOAD, i32 0, i64 2), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP24]], ptr getelementptr inbounds ([30 x i32], ptr @PAYLOAD, i32 0, i64 3), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 5
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP26]], ptr getelementptr inbounds ([30 x i32], ptr @PAYLOAD, i32 0, i64 4), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 6
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP28]], ptr getelementptr inbounds ([30 x i32], ptr @PAYLOAD, i32 0, i64 5), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP3]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[ADDR_I:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[TMP30]], i32 0, i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP29]], ptr [[ADDR_I]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP12]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP15]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP17]], ptr [[TMP16]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP19]], ptr getelementptr inbounds ([30 x i32], ptr @PAYLOAD, i32 0, i32 1), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 3
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP21]], ptr getelementptr inbounds ([30 x i32], ptr @PAYLOAD, i32 0, i64 2), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP23]], ptr getelementptr inbounds ([30 x i32], ptr @PAYLOAD, i32 0, i64 3), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 5
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP25]], ptr getelementptr inbounds ([30 x i32], ptr @PAYLOAD, i32 0, i64 4), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 6
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP27]], ptr getelementptr inbounds ([30 x i32], ptr @PAYLOAD, i32 0, i64 5), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = load [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[TMP3]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[ADDR_I:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[TMP29]], i32 0, i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP28]], ptr [[ADDR_I]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: br label [[_CONT_REPORTHIT_EXIT]]
; LOWERRAYTRACINGPIPELINE: _cont_ReportHit.exit:
; LOWERRAYTRACINGPIPELINE-NEXT: [[ISEND_I:%.*]] = call i1 @opaqueIsEnd()
-; LOWERRAYTRACINGPIPELINE-NEXT: br i1 [[ISEND_I]], label [[TMP31:%.*]], label [[TMP33:%.*]]
-; LOWERRAYTRACINGPIPELINE: 31:
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP32:%.*]] = load [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_TRAVERSALDATA]] [[TMP32]], !continuation.registercount [[META33]]
-; LOWERRAYTRACINGPIPELINE: 33:
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @llvm.lifetime.end.p0(i64 8, ptr [[TMP8]]) #[[ATTR1]]
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = load [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_TRAVERSALDATA]] [[TMP34]], !continuation.registercount [[META33]]
+; LOWERRAYTRACINGPIPELINE-NEXT: br i1 [[ISEND_I]], label [[TMP30:%.*]], label [[TMP32:%.*]]
+; LOWERRAYTRACINGPIPELINE: 30:
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP31:%.*]] = load [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_TRAVERSALDATA]] [[TMP31]], !continuation.registercount [[META33]]
+; LOWERRAYTRACINGPIPELINE: 32:
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @llvm.lifetime.end.p0(i64 8, ptr [[TMP7]]) #[[ATTR1]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = load [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_TRAVERSALDATA]] [[TMP33]], !continuation.registercount [[META33]]
;
;
; LOWERRAYTRACINGPIPELINE-LABEL: define %struct.DispatchSystemData @MyMissShader(
; LOWERRAYTRACINGPIPELINE-SAME: [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR3]] !lgc.rt.shaderstage [[META47:![0-9]+]] !continuation.registercount [[META39]] !continuation [[META48:![0-9]+]] {
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP2:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = call [[STRUCT_SYSTEMDATA]] @continuations.getSystemData.s_struct.SystemDatas()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP3]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[TMP4]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP5]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = load i32, ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP4]], i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[TMP8]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP8]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP12]], ptr [[TMP11]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP8]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP14]], ptr [[TMP13]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP5]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = load i32, ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP8]], ptr [[TMP7]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[TMP5]], i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP9]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP11:%.*]] = load i32, ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP11]], ptr [[TMP10]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP9]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP13]], ptr [[TMP12]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP9]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: store <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, ptr [[TMP15]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: store <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, ptr [[TMP16]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: call void (...) @registerbuffer.setpointerbarrier(ptr @PAYLOAD)
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP2]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = getelementptr i32, ptr [[TMP17]], i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = getelementptr i32, ptr [[TMP18]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP20]], ptr @PAYLOAD, align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[TMP17]], i32 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr [[TMP21]], i64 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP23]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr [[TMP21]], i64 1
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP25]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[TMP21]], i64 2
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP27]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP29:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP28]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP29]], !continuation.registercount [[META39]]
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[TMP16]], i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP18:%.*]] = getelementptr i32, ptr [[TMP17]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP19]], ptr @PAYLOAD, align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[TMP16]], i32 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[TMP20]], i64 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP22]], ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT:%.*]], ptr @PAYLOAD, i32 0, i32 0, i32 7), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = getelementptr i32, ptr [[TMP20]], i64 1
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP24]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 8), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[TMP20]], i64 2
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP26]], ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP28:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA:%.*]], ptr [[TMP27]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: ret [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP28]], !continuation.registercount [[META39]]
;
;
; DXILCONTPOSTPROCESS-LABEL: define i1 @_cont_IsEndSearch(
@@ -914,49 +908,44 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-LABEL: define void @MyRayGen(
; DXILCONTPOSTPROCESS-SAME: ) #[[ATTR3:[0-9]+]] !lgc.rt.shaderstage [[META22:![0-9]+]] !continuation.entry [[META13:![0-9]+]] !continuation.registercount [[META22]] !continuation [[META34:![0-9]+]] !continuation.state [[META22]] {
; DXILCONTPOSTPROCESS-NEXT: AllocaSpillBB:
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
; DXILCONTPOSTPROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP0:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @_cont_SetupRayGen()
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = call i32 @_cont_GetContinuationStackAddr()
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP1]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = load [[STRUCT_DISPATCHSYSTEMDATA]], ptr [[SYSTEM_DATA]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP2]], 0
-; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP3]])
-; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP5]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
-; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[TMP6]])
+; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA:%.*]] @_cont_SetupRayGen()
+; DXILCONTPOSTPROCESS-NEXT: [[TMP0:%.*]] = call i32 @_cont_GetContinuationStackAddr()
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP0]], ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[SYSTEM_DATA]], 0
+; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP1]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP3]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 16, i32 0 })
+; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[TMP4]])
; DXILCONTPOSTPROCESS-NEXT: [[DIS_DATA_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA]] poison, <3 x i32> [[DOTFCA_0_EXTRACT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[SYS_DATA_I:%.*]] = insertvalue [[STRUCT_SYSTEMDATA:%.*]] undef, [[STRUCT_DISPATCHSYSTEMDATA]] [[DIS_DATA_I_FCA_0_INSERT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[TRAV_DATA_I:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA:%.*]] undef, [[STRUCT_SYSTEMDATA]] [[SYS_DATA_I]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @MyRayGen.resume.0 to i64))
-; DXILCONTPOSTPROCESS-NEXT: [[TRAV_DATA2_I:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]], i64 [[TMP8]], 5
+; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @MyRayGen.resume.0 to i64))
+; DXILCONTPOSTPROCESS-NEXT: [[TRAV_DATA2_I:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I]], i64 [[TMP6]], 5
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_0_VEC_EXTRACT:%.*]] = extractelement <4 x float> zeroinitializer, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = bitcast float [[DOTSROA_0_0_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP9]], ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = bitcast float [[DOTSROA_0_0_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP7]], ptr addrspace(20) @REGISTERS, align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_4_VEC_EXTRACT:%.*]] = extractelement <4 x float> zeroinitializer, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = bitcast float [[DOTSROA_0_4_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP10]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = bitcast float [[DOTSROA_0_4_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP8]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_8_VEC_EXTRACT:%.*]] = extractelement <4 x float> zeroinitializer, i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = bitcast float [[DOTSROA_0_8_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP11]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = bitcast float [[DOTSROA_0_8_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP9]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_12_VEC_EXTRACT:%.*]] = extractelement <4 x float> zeroinitializer, i32 3
-; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = bitcast float [[DOTSROA_0_12_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP12]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, i64, ...) @continuation.waitContinue(i64 4, i64 -1, i32 [[TMP13]], [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA2_I]]), !continuation.registercount [[META35:![0-9]+]], !continuation.returnedRegistercount !35
+; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = bitcast float [[DOTSROA_0_12_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP10]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_0_CALLER_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, i64, ...) @continuation.waitContinue(i64 4, i64 -1, i32 [[TMP11]], [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA2_I]]), !continuation.registercount [[META35:![0-9]+]], !continuation.returnedRegistercount !35
; DXILCONTPOSTPROCESS-NEXT: unreachable
;
;
; DXILCONTPOSTPROCESS-LABEL: define dso_local void @MyRayGen.resume.0(
; DXILCONTPOSTPROCESS-SAME: i32 [[TMP0:%.*]], [[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.shaderstage [[META22]] !continuation.registercount [[META35]] !continuation [[META34]] {
; DXILCONTPOSTPROCESS-NEXT: entryresume.0:
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
+; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_0_VEC_INSERT:%.*]] = insertelement <4 x float> poison, float [[TMP3]], i32 0
@@ -970,11 +959,11 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = bitcast i32 [[TMP8]] to float
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_12_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_8_VEC_INSERT]], float [[TMP9]], i32 3
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT6:%.*]] = extractvalue [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP1]], 0
-; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = call <3 x i32> @_cont_DispatchRaysIndex3(ptr [[SYSTEM_DATA]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = call <3 x i32> @_cont_DispatchRaysIndex3(ptr [[SYSTEM_DATA_ALLOCA]])
; DXILCONTPOSTPROCESS-NEXT: [[EXTRACT:%.*]] = extractelement <3 x i32> [[TMP11]], i8 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = call <3 x i32> @_cont_DispatchRaysIndex3(ptr [[SYSTEM_DATA]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = call <3 x i32> @_cont_DispatchRaysIndex3(ptr [[SYSTEM_DATA_ALLOCA]])
; DXILCONTPOSTPROCESS-NEXT: [[EXTRACT1:%.*]] = extractelement <3 x i32> [[TMP12]], i8 1
; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.createHandleForLib.dx.types.Handle(i32 160, [[DX_TYPES_HANDLE]] [[TMP10]])
; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = call [[DX_TYPES_HANDLE]] @dx.op.annotateHandle(i32 216, [[DX_TYPES_HANDLE]] [[TMP13]], [[DX_TYPES_RESOURCEPROPERTIES:%.*]] { i32 4098, i32 1033 })
@@ -990,125 +979,117 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-LABEL: define void @MyClosestHitShader(
; DXILCONTPOSTPROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR3]] !lgc.rt.shaderstage [[META36:![0-9]+]] !continuation.registercount [[META35]] !continuation [[META37:![0-9]+]] !continuation.state [[META22]] {
; DXILCONTPOSTPROCESS-NEXT: AllocaSpillBB:
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
; DXILCONTPOSTPROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = load [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP1]], 0, 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP1]], 1, 0
-; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_0_VEC_INSERT:%.*]] = insertelement <4 x float> undef, float [[TMP3]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_4_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_0_VEC_INSERT]], float [[TMP5]], i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = bitcast i32 [[TMP6]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_8_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_4_VEC_INSERT]], float [[TMP7]], i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = bitcast i32 [[TMP8]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_12_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_8_VEC_INSERT]], float [[TMP9]], i32 3
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP0]], 0, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP0]], 1, 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_0_VEC_INSERT:%.*]] = insertelement <4 x float> undef, float [[TMP2]], i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = bitcast i32 [[TMP3]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_4_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_0_VEC_INSERT]], float [[TMP4]], i32 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = bitcast i32 [[TMP5]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_8_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_4_VEC_INSERT]], float [[TMP6]], i32 2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = bitcast i32 [[TMP7]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_12_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_8_VEC_INSERT]], float [[TMP8]], i32 3
; DXILCONTPOSTPROCESS-NEXT: [[VAL_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] poison, <2 x float> [[DOTFCA_1_0_EXTRACT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[VAL_I_FCA_0_INSERT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_06_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = bitcast float [[DOTSROA_06_0_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = bitcast i32 [[TMP10]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[HITATTRS_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x float> undef, float [[TMP11]], i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = bitcast float [[DOTSROA_06_0_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = bitcast i32 [[TMP9]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[HITATTRS_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x float> undef, float [[TMP10]], i32 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_06_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT]], i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = bitcast float [[DOTSROA_06_4_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = bitcast i32 [[TMP12]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[HITATTRS_SROA_0_4_VEC_INSERT:%.*]] = insertelement <2 x float> [[HITATTRS_SROA_0_0_VEC_INSERT]], float [[TMP13]], i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = extractelement <2 x float> [[HITATTRS_SROA_0_4_VEC_INSERT]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = fsub fast float 1.000000e+00, [[TMP14]]
-; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = extractelement <2 x float> [[HITATTRS_SROA_0_4_VEC_INSERT]], i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP17:%.*]] = fsub fast float [[TMP15]], [[TMP16]]
-; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = insertelement <4 x float> undef, float [[TMP17]], i64 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP19:%.*]] = insertelement <4 x float> [[TMP18]], float [[TMP14]], i64 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP20:%.*]] = insertelement <4 x float> [[TMP19]], float [[TMP16]], i64 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP21:%.*]] = insertelement <4 x float> [[TMP20]], float 1.000000e+00, i64 3
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_0_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[TMP21]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP22:%.*]] = bitcast float [[DOTSROA_0_0_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP22]], ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_4_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[TMP21]], i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP23:%.*]] = bitcast float [[DOTSROA_0_4_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP23]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_8_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[TMP21]], i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP24:%.*]] = bitcast float [[DOTSROA_0_8_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP24]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_12_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[TMP21]], i32 3
-; DXILCONTPOSTPROCESS-NEXT: [[TMP25:%.*]] = bitcast float [[DOTSROA_0_12_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP25]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = bitcast float [[DOTSROA_06_4_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = bitcast i32 [[TMP11]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[HITATTRS_SROA_0_4_VEC_INSERT:%.*]] = insertelement <2 x float> [[HITATTRS_SROA_0_0_VEC_INSERT]], float [[TMP12]], i32 1
+; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = extractelement <2 x float> [[HITATTRS_SROA_0_4_VEC_INSERT]], i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = fsub fast float 1.000000e+00, [[TMP13]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = extractelement <2 x float> [[HITATTRS_SROA_0_4_VEC_INSERT]], i32 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = fsub fast float [[TMP14]], [[TMP15]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP17:%.*]] = insertelement <4 x float> undef, float [[TMP16]], i64 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = insertelement <4 x float> [[TMP17]], float [[TMP13]], i64 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP19:%.*]] = insertelement <4 x float> [[TMP18]], float [[TMP15]], i64 2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP20:%.*]] = insertelement <4 x float> [[TMP19]], float 1.000000e+00, i64 3
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_0_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[TMP20]], i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP21:%.*]] = bitcast float [[DOTSROA_0_0_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP21]], ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_4_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[TMP20]], i32 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP22:%.*]] = bitcast float [[DOTSROA_0_4_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP22]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_8_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[TMP20]], i32 2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP23:%.*]] = bitcast float [[DOTSROA_0_8_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP23]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_12_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[TMP20]], i32 3
+; DXILCONTPOSTPROCESS-NEXT: [[TMP24:%.*]] = bitcast float [[DOTSROA_0_12_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP24]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA:%.*]] poison, <3 x i32> [[DOTFCA_0_0_EXTRACT]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP26:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP26]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META35]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP25:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP25]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META35]]
; DXILCONTPOSTPROCESS-NEXT: unreachable
;
;
; DXILCONTPOSTPROCESS-LABEL: define void @MyAnyHitShader(
; DXILCONTPOSTPROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_TRAVERSALDATA:%.*]] [[TMP0:%.*]], [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] [[TMP1:%.*]]) #[[ATTR3]] !lgc.rt.shaderstage [[META38:![0-9]+]] !continuation.registercount [[META35]] !continuation [[META39:![0-9]+]] !continuation.state [[META22]] {
; DXILCONTPOSTPROCESS-NEXT: AllocaSpillBB:
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_TRAVERSALDATA]], align 8
; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = alloca [[STRUCT_HITDATA:%.*]], align 8
; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_HITDATA]], align 8
; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_TRAVERSALDATA]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
; DXILCONTPOSTPROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_TRAVERSALDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP4]], 0, 0, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 0, 0, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: store <3 x i32> [[DOTFCA_0_0_0_EXTRACT]], ptr [[DOTFCA_0_0_0_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP4]], 0, 1, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 0, 1, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 1, i32 0
; DXILCONTPOSTPROCESS-NEXT: store <2 x float> [[DOTFCA_0_1_0_EXTRACT]], ptr [[DOTFCA_0_1_0_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP4]], 1, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 1, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 0
; DXILCONTPOSTPROCESS-NEXT: store float [[DOTFCA_1_0_EXTRACT]], ptr [[DOTFCA_1_0_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP4]], 1, 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 1, 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_1_GEP:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1, i32 1
; DXILCONTPOSTPROCESS-NEXT: store i32 [[DOTFCA_1_1_EXTRACT]], ptr [[DOTFCA_1_1_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_2_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP4]], 2
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_2_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 2
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_2_GEP:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 2
; DXILCONTPOSTPROCESS-NEXT: store <3 x float> [[DOTFCA_2_EXTRACT]], ptr [[DOTFCA_2_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP4]], 3
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 3
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_GEP:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 3
; DXILCONTPOSTPROCESS-NEXT: store <3 x float> [[DOTFCA_3_EXTRACT]], ptr [[DOTFCA_3_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_4_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP4]], 4
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_4_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_4_GEP:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 4
; DXILCONTPOSTPROCESS-NEXT: store float [[DOTFCA_4_EXTRACT]], ptr [[DOTFCA_4_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP4]], 5
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 5
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_GEP:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 5
; DXILCONTPOSTPROCESS-NEXT: store i64 [[DOTFCA_5_EXTRACT]], ptr [[DOTFCA_5_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = bitcast i32 [[TMP6]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_0_VEC_INSERT:%.*]] = insertelement <4 x float> undef, float [[TMP7]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = bitcast i32 [[TMP8]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_4_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_0_VEC_INSERT]], float [[TMP9]], i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = bitcast i32 [[TMP10]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_8_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_4_VEC_INSERT]], float [[TMP11]], i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = bitcast i32 [[TMP12]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_12_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_8_VEC_INSERT]], float [[TMP13]], i32 3
-; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[ADDR_I:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[TMP14]], i32 0, i32 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = bitcast i32 [[TMP5]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_0_VEC_INSERT:%.*]] = insertelement <4 x float> undef, float [[TMP6]], i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = bitcast i32 [[TMP7]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_4_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_0_VEC_INSERT]], float [[TMP8]], i32 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = bitcast i32 [[TMP9]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_8_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_4_VEC_INSERT]], float [[TMP10]], i32 2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_1_ANYHIT_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = bitcast i32 [[TMP11]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_12_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_8_VEC_INSERT]], float [[TMP12]], i32 3
+; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[ADDR_I:%.*]] = getelementptr [[STRUCT_SYSTEMDATA:%.*]], ptr [[TMP13]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: [[VAL_I_FCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[ADDR_I]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: [[VAL_I_FCA_0_LOAD:%.*]] = load <2 x float>, ptr [[VAL_I_FCA_0_GEP]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[VAL_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] poison, <2 x float> [[VAL_I_FCA_0_LOAD]], 0
; DXILCONTPOSTPROCESS-NEXT: [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[VAL_I_FCA_0_INSERT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_060_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = bitcast float [[DOTSROA_060_0_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = bitcast float [[DOTSROA_060_0_VEC_EXTRACT]] to i32
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_060_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[VAL_I_FCA_0_INSERT_FCA_0_EXTRACT]], i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = bitcast float [[DOTSROA_060_4_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = bitcast float [[DOTSROA_060_4_VEC_EXTRACT]] to i32
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[TMP1]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: [[RESPTR_I3:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: [[RES_I4_FCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[RESPTR_I3]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: [[RES_I4_FCA_0_LOAD:%.*]] = load float, ptr [[RES_I4_FCA_0_GEP]], align 4
@@ -1122,9 +1103,9 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-NEXT: [[RES_I4_FCA_1_INSERT_FCA_1_EXTRACT:%.*]] = extractvalue [[STRUCT_HITDATA]] [[RES_I4_FCA_1_INSERT]], 1
; DXILCONTPOSTPROCESS-NEXT: [[RES_I4_FCA_1_INSERT_FCA_1_GEP:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP2]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: store i32 [[RES_I4_FCA_1_INSERT_FCA_1_EXTRACT]], ptr [[RES_I4_FCA_1_INSERT_FCA_1_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = call <3 x float> @_cont_ObjectRayOrigin3(ptr [[TMP17]], ptr [[TMP2]])
-; DXILCONTPOSTPROCESS-NEXT: [[EXTRACT1:%.*]] = extractelement <3 x float> [[TMP18]], i8 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP17:%.*]] = call <3 x float> @_cont_ObjectRayOrigin3(ptr [[TMP16]], ptr [[TMP2]])
+; DXILCONTPOSTPROCESS-NEXT: [[EXTRACT1:%.*]] = extractelement <3 x float> [[TMP17]], i8 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: [[RESPTR_I:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: [[RES_I_FCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[RESPTR_I]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: [[RES_I_FCA_0_LOAD:%.*]] = load float, ptr [[RES_I_FCA_0_GEP]], align 4
@@ -1138,9 +1119,9 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-NEXT: [[RES_I_FCA_1_INSERT_FCA_1_EXTRACT:%.*]] = extractvalue [[STRUCT_HITDATA]] [[RES_I_FCA_1_INSERT]], 1
; DXILCONTPOSTPROCESS-NEXT: [[RES_I_FCA_1_INSERT_FCA_1_GEP:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[TMP3]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: store i32 [[RES_I_FCA_1_INSERT_FCA_1_EXTRACT]], ptr [[RES_I_FCA_1_INSERT_FCA_1_GEP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP20:%.*]] = call <3 x float> @_cont_ObjectRayDirection3(ptr [[TMP19]], ptr [[TMP3]])
-; DXILCONTPOSTPROCESS-NEXT: [[EXTRACT:%.*]] = extractelement <3 x float> [[TMP20]], i8 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP19:%.*]] = call <3 x float> @_cont_ObjectRayDirection3(ptr [[TMP18]], ptr [[TMP3]])
+; DXILCONTPOSTPROCESS-NEXT: [[EXTRACT:%.*]] = extractelement <3 x float> [[TMP19]], i8 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: [[RESPTR_I5:%.*]] = getelementptr [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: [[RES_I6_FCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_HITDATA]], ptr [[RESPTR_I5]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: [[RES_I6_FCA_0_LOAD:%.*]] = load float, ptr [[RES_I6_FCA_0_GEP]], align 4
@@ -1150,36 +1131,36 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-NEXT: [[RES_I6_FCA_1_INSERT:%.*]] = insertvalue [[STRUCT_HITDATA]] [[RES_I6_FCA_0_INSERT]], i32 [[RES_I6_FCA_1_LOAD]], 1
; DXILCONTPOSTPROCESS-NEXT: [[RES_I6_FCA_1_INSERT_FCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_HITDATA]] [[RES_I6_FCA_1_INSERT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[RES_I6_FCA_1_INSERT_FCA_1_EXTRACT:%.*]] = extractvalue [[STRUCT_HITDATA]] [[RES_I6_FCA_1_INSERT]], 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP22:%.*]] = fmul fast float [[RES_I6_FCA_1_INSERT_FCA_0_EXTRACT]], [[EXTRACT]]
-; DXILCONTPOSTPROCESS-NEXT: [[TMP23:%.*]] = fadd fast float [[TMP22]], [[EXTRACT1]]
-; DXILCONTPOSTPROCESS-NEXT: [[TMP24:%.*]] = fcmp fast ogt float [[TMP23]], 0.000000e+00
-; DXILCONTPOSTPROCESS-NEXT: br i1 [[TMP24]], label [[TMP25:%.*]], label [[TMP37:%.*]]
-; DXILCONTPOSTPROCESS: 25:
-; DXILCONTPOSTPROCESS-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: call void @_cont_AcceptHitAndEndSearch(ptr [[TMP26]])
+; DXILCONTPOSTPROCESS-NEXT: [[TMP21:%.*]] = fmul fast float [[RES_I6_FCA_1_INSERT_FCA_0_EXTRACT]], [[EXTRACT]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP22:%.*]] = fadd fast float [[TMP21]], [[EXTRACT1]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP23:%.*]] = fcmp fast ogt float [[TMP22]], 0.000000e+00
+; DXILCONTPOSTPROCESS-NEXT: br i1 [[TMP23]], label [[TMP24:%.*]], label [[TMP36:%.*]]
+; DXILCONTPOSTPROCESS: 24:
+; DXILCONTPOSTPROCESS-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: call void @_cont_AcceptHitAndEndSearch(ptr [[TMP25]])
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_0_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[DOTSROA_0_12_VEC_INSERT]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP27:%.*]] = bitcast float [[DOTSROA_0_0_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP27]], ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP26:%.*]] = bitcast float [[DOTSROA_0_0_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP26]], ptr addrspace(20) @REGISTERS, align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_4_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[DOTSROA_0_12_VEC_INSERT]], i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP28:%.*]] = bitcast float [[DOTSROA_0_4_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP28]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP27:%.*]] = bitcast float [[DOTSROA_0_4_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP27]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_8_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[DOTSROA_0_12_VEC_INSERT]], i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP29:%.*]] = bitcast float [[DOTSROA_0_8_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP29]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP28:%.*]] = bitcast float [[DOTSROA_0_8_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP28]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_12_VEC_EXTRACT:%.*]] = extractelement <4 x float> [[DOTSROA_0_12_VEC_INSERT]], i32 3
-; DXILCONTPOSTPROCESS-NEXT: [[TMP30:%.*]] = bitcast float [[DOTSROA_0_12_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP30]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP29:%.*]] = bitcast float [[DOTSROA_0_12_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP29]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_3_CLOSESTHIT_IN_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
; DXILCONTPOSTPROCESS-NEXT: [[HITATTRSALLOCA_SROA_0_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP31:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_0_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: [[TMP32:%.*]] = bitcast i32 [[TMP31]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_062_0_VEC_INSERT:%.*]] = insertelement <2 x float> undef, float [[TMP32]], i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP30:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_0_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP31:%.*]] = bitcast i32 [[TMP30]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_062_0_VEC_INSERT:%.*]] = insertelement <2 x float> undef, float [[TMP31]], i32 0
; DXILCONTPOSTPROCESS-NEXT: [[HITATTRSALLOCA_SROA_0_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT]], i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP33:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_4_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: [[TMP34:%.*]] = bitcast i32 [[TMP33]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_062_4_VEC_INSERT:%.*]] = insertelement <2 x float> [[DOTSROA_062_0_VEC_INSERT]], float [[TMP34]], i32 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP32:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_4_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP33:%.*]] = bitcast i32 [[TMP32]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_062_4_VEC_INSERT:%.*]] = insertelement <2 x float> [[DOTSROA_062_0_VEC_INSERT]], float [[TMP33]], i32 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] poison, <2 x float> [[DOTSROA_062_4_VEC_INSERT]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[ADDR_I1:%.*]] = getelementptr [[STRUCT_SYSTEMDATA]], ptr [[TMP35]], i32 0, i32 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[ADDR_I1:%.*]] = getelementptr [[STRUCT_SYSTEMDATA]], ptr [[TMP34]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT25:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_INSERT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP:%.*]] = getelementptr inbounds [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[ADDR_I1]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: store <2 x float> [[DOTFCA_0_EXTRACT25]], ptr [[DOTFCA_0_GEP]], align 4
@@ -1207,34 +1188,34 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_GEP33:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 5
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_LOAD:%.*]] = load i64, ptr [[DOTFCA_5_GEP33]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_4_INSERT]], i64 [[DOTFCA_5_LOAD]], 5
-; DXILCONTPOSTPROCESS-NEXT: [[TMP36:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP36]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT]]), !continuation.registercount [[META35]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP35:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP35]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT]]), !continuation.registercount [[META35]]
; DXILCONTPOSTPROCESS-NEXT: unreachable
-; DXILCONTPOSTPROCESS: 37:
+; DXILCONTPOSTPROCESS: 36:
; DXILCONTPOSTPROCESS-NEXT: call void @_cont_AcceptHit(ptr [[SYSTEM_DATA_ALLOCA]])
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_0_VEC_EXTRACT15:%.*]] = extractelement <4 x float> [[DOTSROA_0_12_VEC_INSERT]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP38:%.*]] = bitcast float [[DOTSROA_0_0_VEC_EXTRACT15]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP38]], ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP37:%.*]] = bitcast float [[DOTSROA_0_0_VEC_EXTRACT15]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP37]], ptr addrspace(20) @REGISTERS, align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_4_VEC_EXTRACT18:%.*]] = extractelement <4 x float> [[DOTSROA_0_12_VEC_INSERT]], i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP39:%.*]] = bitcast float [[DOTSROA_0_4_VEC_EXTRACT18]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP39]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP38:%.*]] = bitcast float [[DOTSROA_0_4_VEC_EXTRACT18]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP38]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_8_VEC_EXTRACT21:%.*]] = extractelement <4 x float> [[DOTSROA_0_12_VEC_INSERT]], i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP40:%.*]] = bitcast float [[DOTSROA_0_8_VEC_EXTRACT21]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP40]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP39:%.*]] = bitcast float [[DOTSROA_0_8_VEC_EXTRACT21]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP39]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_12_VEC_EXTRACT24:%.*]] = extractelement <4 x float> [[DOTSROA_0_12_VEC_INSERT]], i32 3
-; DXILCONTPOSTPROCESS-NEXT: [[TMP41:%.*]] = bitcast float [[DOTSROA_0_12_VEC_EXTRACT24]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP41]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP40:%.*]] = bitcast float [[DOTSROA_0_12_VEC_EXTRACT24]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP40]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_2_ANYHIT_OUT_ACCEPT_PAYLOAD_ATTR_0_I32S]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
; DXILCONTPOSTPROCESS-NEXT: [[HITATTRSALLOCA_SROA_0_0_VEC_EXTRACT9:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP42:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_0_VEC_EXTRACT9]] to i32
-; DXILCONTPOSTPROCESS-NEXT: [[TMP43:%.*]] = bitcast i32 [[TMP42]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_066_0_VEC_INSERT:%.*]] = insertelement <2 x float> undef, float [[TMP43]], i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP41:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_0_VEC_EXTRACT9]] to i32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP42:%.*]] = bitcast i32 [[TMP41]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_066_0_VEC_INSERT:%.*]] = insertelement <2 x float> undef, float [[TMP42]], i32 0
; DXILCONTPOSTPROCESS-NEXT: [[HITATTRSALLOCA_SROA_0_4_VEC_EXTRACT11:%.*]] = extractelement <2 x float> [[DOTFCA_0_EXTRACT]], i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP44:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_4_VEC_EXTRACT11]] to i32
-; DXILCONTPOSTPROCESS-NEXT: [[TMP45:%.*]] = bitcast i32 [[TMP44]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_066_4_VEC_INSERT:%.*]] = insertelement <2 x float> [[DOTSROA_066_0_VEC_INSERT]], float [[TMP45]], i32 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP43:%.*]] = bitcast float [[HITATTRSALLOCA_SROA_0_4_VEC_EXTRACT11]] to i32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP44:%.*]] = bitcast i32 [[TMP43]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_066_4_VEC_INSERT:%.*]] = insertelement <2 x float> [[DOTSROA_066_0_VEC_INSERT]], float [[TMP44]], i32 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT65:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] poison, <2 x float> [[DOTSROA_066_4_VEC_INSERT]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[ADDR_I2:%.*]] = getelementptr [[STRUCT_SYSTEMDATA]], ptr [[TMP46]], i32 0, i32 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[ADDR_I2:%.*]] = getelementptr [[STRUCT_SYSTEMDATA]], ptr [[TMP45]], i32 0, i32 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT34:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_INSERT65]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_GEP35:%.*]] = getelementptr inbounds [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[ADDR_I2]], i32 0, i32 0
; DXILCONTPOSTPROCESS-NEXT: store <2 x float> [[DOTFCA_0_EXTRACT34]], ptr [[DOTFCA_0_GEP35]], align 4
@@ -1262,30 +1243,29 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_GEP57:%.*]] = getelementptr inbounds [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 5
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_LOAD58:%.*]] = load i64, ptr [[DOTFCA_5_GEP57]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_INSERT59:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_4_INSERT56]], i64 [[DOTFCA_5_LOAD58]], 5
-; DXILCONTPOSTPROCESS-NEXT: [[TMP47:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP47]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT59]]), !continuation.registercount [[META35]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP46:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP46]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT59]]), !continuation.registercount [[META35]]
; DXILCONTPOSTPROCESS-NEXT: unreachable
;
;
; DXILCONTPOSTPROCESS-LABEL: define void @MyIntersectionShader(
; DXILCONTPOSTPROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_TRAVERSALDATA:%.*]] [[TMP0:%.*]]) #[[ATTR3]] !lgc.rt.shaderstage [[META40:![0-9]+]] !continuation.registercount [[META32:![0-9]+]] !continuation [[META41:![0-9]+]] !continuation.state [[META42:![0-9]+]] !continuation.stacksize [[META42]] {
; DXILCONTPOSTPROCESS-NEXT: AllocaSpillBB:
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_TRAVERSALDATA]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
; DXILCONTPOSTPROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_TRAVERSALDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[MYINTERSECTIONSHADER_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = load [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 0, 0, 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 0, 1, 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 1, 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 1, 1
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_2_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 2
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 3
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_4_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 5
+; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP2]], i64 0
+; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[MYINTERSECTIONSHADER_FRAME:%.*]], ptr addrspace(21) [[TMP3]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: store i64 [[RETURNADDR]], ptr addrspace(21) [[RETURNADDR_SPILL_ADDR]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 0, 0, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 0, 1, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 1, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 1, 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_2_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 2
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 3
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_4_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 4
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 5
; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; DXILCONTPOSTPROCESS-NEXT: [[RES_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_HITDATA:%.*]] poison, float [[DOTFCA_1_0_EXTRACT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[RES_I_FCA_1_INSERT:%.*]] = insertvalue [[STRUCT_HITDATA]] [[RES_I_FCA_0_INSERT]], i32 [[DOTFCA_1_1_EXTRACT]], 1
@@ -1303,38 +1283,27 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-NEXT: [[TRAV_DATA_I_FCA_4_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I_FCA_3_INSERT]], float [[DOTFCA_4_EXTRACT]], 4
; DXILCONTPOSTPROCESS-NEXT: [[TRAV_DATA_I_FCA_5_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I_FCA_4_INSERT]], i64 [[DOTFCA_5_EXTRACT]], 5
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] poison, <2 x float> undef, 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], 8
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP3]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP5]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP7]], ptr addrspace(21) [[TMP6]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP8]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP10]], ptr addrspace(21) [[TMP9]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @MyIntersectionShader.resume.0 to i64))
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 3, i32 [[TMP11]], i64 [[TMP12]], [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I_FCA_5_INSERT]], float [[RES_I_FCA_1_INSERT_FCA_0_EXTRACT]], i32 0, [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META32]], !continuation.returnedRegistercount !32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], 8
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP5]], ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @MyIntersectionShader.resume.0 to i64))
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 3, i32 [[TMP6]], i64 [[TMP7]], [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I_FCA_5_INSERT]], float [[RES_I_FCA_1_INSERT_FCA_0_EXTRACT]], i32 0, [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META32]], !continuation.returnedRegistercount !32
; DXILCONTPOSTPROCESS-NEXT: unreachable
; DXILCONTPOSTPROCESS: accepthit.i:
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_0_VEC_EXTRACT:%.*]] = extractelement <2 x float> undef, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = bitcast float [[DOTSROA_0_0_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = bitcast i32 [[TMP13]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_065_0_VEC_INSERT:%.*]] = insertelement <2 x float> undef, float [[TMP14]], i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = bitcast float [[DOTSROA_0_0_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = bitcast i32 [[TMP8]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_065_0_VEC_INSERT:%.*]] = insertelement <2 x float> undef, float [[TMP9]], i32 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_4_VEC_EXTRACT:%.*]] = extractelement <2 x float> undef, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = bitcast float [[DOTSROA_0_4_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = bitcast i32 [[TMP15]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_065_4_VEC_INSERT:%.*]] = insertelement <2 x float> [[DOTSROA_065_0_VEC_INSERT]], float [[TMP16]], i32 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = bitcast float [[DOTSROA_0_4_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = bitcast i32 [[TMP10]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_065_4_VEC_INSERT:%.*]] = insertelement <2 x float> [[DOTSROA_065_0_VEC_INSERT]], float [[TMP11]], i32 1
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT64:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] poison, <2 x float> [[DOTSROA_065_4_VEC_INSERT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_INSERT64]], 0
; DXILCONTPOSTPROCESS-NEXT: [[ISEND_I:%.*]] = call i1 @opaqueIsEnd()
-; DXILCONTPOSTPROCESS-NEXT: br i1 [[ISEND_I]], label [[TMP17:%.*]], label [[TMP19:%.*]]
-; DXILCONTPOSTPROCESS: 17:
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD_ADDR1:%.*]] = getelementptr inbounds [[MYINTERSECTIONSHADER_FRAME]], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD2:%.*]] = load i64, ptr [[RETURNADDR_RELOAD_ADDR1]], align 4
+; DXILCONTPOSTPROCESS-NEXT: br i1 [[ISEND_I]], label [[TMP12:%.*]], label [[TMP14:%.*]]
+; DXILCONTPOSTPROCESS: 12:
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_INSERT28:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] poison, <3 x i32> [[DOTFCA_0_0_0_EXTRACT]], 0, 0, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_INSERT31:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_0_0_0_INSERT28]], <2 x float> [[DOTFCA_0_EXTRACT]], 0, 1, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_INSERT34:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_0_1_0_INSERT31]], float [[DOTFCA_1_0_EXTRACT]], 1, 0
@@ -1343,12 +1312,10 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_INSERT43:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_2_INSERT40]], <3 x float> [[DOTFCA_3_EXTRACT]], 3
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_4_INSERT46:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_3_INSERT43]], float [[DOTFCA_4_EXTRACT]], 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_INSERT49:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_4_INSERT46]], i64 [[DOTFCA_5_EXTRACT]], 5
-; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD2]], i32 [[TMP18]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT49]]), !continuation.registercount [[META32]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP13]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT49]]), !continuation.registercount [[META32]]
; DXILCONTPOSTPROCESS-NEXT: unreachable
-; DXILCONTPOSTPROCESS: 19:
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[MYINTERSECTIONSHADER_FRAME]], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr [[RETURNADDR_RELOAD_ADDR]], align 4
+; DXILCONTPOSTPROCESS: 14:
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] poison, <3 x i32> [[DOTFCA_0_0_0_EXTRACT]], 0, 0, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_0_0_0_INSERT]], <2 x float> [[DOTFCA_0_EXTRACT]], 0, 1, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_0_1_0_INSERT]], float [[DOTFCA_1_0_EXTRACT]], 1, 0
@@ -1357,33 +1324,22 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_2_INSERT]], <3 x float> [[DOTFCA_3_EXTRACT]], 3
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_4_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_3_INSERT]], float [[DOTFCA_4_EXTRACT]], 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_4_INSERT]], i64 [[DOTFCA_5_EXTRACT]], 5
-; DXILCONTPOSTPROCESS-NEXT: [[TMP20:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP20]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT]]), !continuation.registercount [[META32]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP15:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP15]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT]]), !continuation.registercount [[META32]]
; DXILCONTPOSTPROCESS-NEXT: unreachable
;
;
; DXILCONTPOSTPROCESS-LABEL: define dso_local void @MyIntersectionShader.resume.0(
; DXILCONTPOSTPROCESS-SAME: i32 [[TMP0:%.*]], [[STRUCT_TRAVERSALDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.shaderstage [[META40]] !continuation.registercount [[META32]] !continuation [[META41]] {
; DXILCONTPOSTPROCESS-NEXT: entryresume.0:
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_TRAVERSALDATA]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
; DXILCONTPOSTPROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_TRAVERSALDATA]] [[TMP1]], ptr [[SYSTEM_DATA]], align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP0]], ptr [[CSP]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP3]], i64 -8
-; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(21) [[TMP5]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(21) [[TMP8]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], -8
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP12]], ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], -8
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP3]], ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP4]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP5]], i64 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_EXTRACT10:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 0, 0, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_EXTRACT12:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 0, 1, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_EXTRACT14:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 1, 0
@@ -1394,10 +1350,10 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_EXTRACT24:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 5
; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; DXILCONTPOSTPROCESS-NEXT: [[ISEND_I:%.*]] = call i1 @opaqueIsEnd()
-; DXILCONTPOSTPROCESS-NEXT: br i1 [[ISEND_I]], label [[TMP13:%.*]], label [[TMP15:%.*]]
-; DXILCONTPOSTPROCESS: 13:
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD_ADDR1:%.*]] = getelementptr inbounds [[MYINTERSECTIONSHADER_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD2:%.*]] = load i64, ptr [[RETURNADDR_RELOAD_ADDR1]], align 4
+; DXILCONTPOSTPROCESS-NEXT: br i1 [[ISEND_I]], label [[TMP7:%.*]], label [[TMP9:%.*]]
+; DXILCONTPOSTPROCESS: 7:
+; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD_ADDR1:%.*]] = getelementptr inbounds [[MYINTERSECTIONSHADER_FRAME:%.*]], ptr addrspace(21) [[TMP6]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD2:%.*]] = load i64, ptr addrspace(21) [[RETURNADDR_RELOAD_ADDR1]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_INSERT28:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] poison, <3 x i32> [[DOTFCA_0_0_0_EXTRACT10]], 0, 0, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_INSERT31:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_0_0_0_INSERT28]], <2 x float> [[DOTFCA_0_1_0_EXTRACT12]], 0, 1, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_INSERT34:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_0_1_0_INSERT31]], float [[DOTFCA_1_0_EXTRACT14]], 1, 0
@@ -1406,12 +1362,12 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_INSERT43:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_2_INSERT40]], <3 x float> [[DOTFCA_3_EXTRACT20]], 3
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_4_INSERT46:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_3_INSERT43]], float [[DOTFCA_4_EXTRACT22]], 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_INSERT49:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_4_INSERT46]], i64 [[DOTFCA_5_EXTRACT24]], 5
-; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD2]], i32 [[TMP14]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT49]]), !continuation.registercount [[META32]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD2]], i32 [[TMP8]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT49]]), !continuation.registercount [[META32]]
; DXILCONTPOSTPROCESS-NEXT: unreachable
-; DXILCONTPOSTPROCESS: 15:
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[MYINTERSECTIONSHADER_FRAME]], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr [[RETURNADDR_RELOAD_ADDR]], align 4
+; DXILCONTPOSTPROCESS: 9:
+; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[MYINTERSECTIONSHADER_FRAME]], ptr addrspace(21) [[TMP6]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr addrspace(21) [[RETURNADDR_RELOAD_ADDR]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] poison, <3 x i32> [[DOTFCA_0_0_0_EXTRACT10]], 0, 0, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_0_0_0_INSERT]], <2 x float> [[DOTFCA_0_1_0_EXTRACT12]], 0, 1, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_0_1_0_INSERT]], float [[DOTFCA_1_0_EXTRACT14]], 1, 0
@@ -1420,30 +1376,29 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_2_INSERT]], <3 x float> [[DOTFCA_3_EXTRACT20]], 3
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_4_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_3_INSERT]], float [[DOTFCA_4_EXTRACT22]], 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_4_INSERT]], i64 [[DOTFCA_5_EXTRACT24]], 5
-; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP16]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT]]), !continuation.registercount [[META32]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP10]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT]]), !continuation.registercount [[META32]]
; DXILCONTPOSTPROCESS-NEXT: unreachable
;
;
; DXILCONTPOSTPROCESS-LABEL: define void @MyIntersectionShaderLargeAttrs(
; DXILCONTPOSTPROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_TRAVERSALDATA:%.*]] [[TMP0:%.*]]) #[[ATTR3]] !lgc.rt.shaderstage [[META40]] !continuation.registercount [[META32]] !continuation [[META43:![0-9]+]] !continuation.state [[META42]] !continuation.stacksize [[META42]] {
; DXILCONTPOSTPROCESS-NEXT: AllocaSpillBB:
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_TRAVERSALDATA]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
; DXILCONTPOSTPROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_TRAVERSALDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[MYINTERSECTIONSHADERLARGEATTRS_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: store i64 [[RETURNADDR]], ptr [[RETURNADDR_SPILL_ADDR]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = load [[STRUCT_TRAVERSALDATA]], ptr [[SYSTEM_DATA]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 0, 0, 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 0, 1, 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 1, 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 1, 1
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_2_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 2
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 3
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_4_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 5
+; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP2]], i64 0
+; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_SPILL_ADDR:%.*]] = getelementptr inbounds [[MYINTERSECTIONSHADERLARGEATTRS_FRAME:%.*]], ptr addrspace(21) [[TMP3]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: store i64 [[RETURNADDR]], ptr addrspace(21) [[RETURNADDR_SPILL_ADDR]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 0, 0, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 0, 1, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 1, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_1_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 1, 1
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_2_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 2
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 3
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_4_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 4
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_EXTRACT:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP0]], 5
; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; DXILCONTPOSTPROCESS-NEXT: [[RES_I_FCA_0_INSERT:%.*]] = insertvalue [[STRUCT_HITDATA:%.*]] poison, float [[DOTFCA_1_0_EXTRACT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[RES_I_FCA_1_INSERT:%.*]] = insertvalue [[STRUCT_HITDATA]] [[RES_I_FCA_0_INSERT]], i32 [[DOTFCA_1_1_EXTRACT]], 1
@@ -1467,27 +1422,18 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_4_INSERT:%.*]] = insertvalue [[STRUCT_LARGEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_3_INSERT]], i32 104, 0, 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_5_INSERT:%.*]] = insertvalue [[STRUCT_LARGEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_4_INSERT]], i32 105, 0, 5
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_6_INSERT:%.*]] = insertvalue [[STRUCT_LARGEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_5_INSERT]], i32 106, 0, 6
-; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], 8
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP3]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP5]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP7]], ptr addrspace(21) [[TMP6]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP8]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP10]], ptr addrspace(21) [[TMP9]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @MyIntersectionShaderLargeAttrs.resume.0 to i64))
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 3, i32 [[TMP11]], i64 [[TMP12]], [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I_FCA_5_INSERT]], float [[RES_I_FCA_1_INSERT_FCA_0_EXTRACT]], i32 0, [[STRUCT_LARGEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_6_INSERT]]), !continuation.registercount [[META32]], !continuation.returnedRegistercount !32
+; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], 8
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP5]], ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = call i64 @continuation.getAddrAndMD(i64 ptrtoint (ptr @MyIntersectionShaderLargeAttrs.resume.0 to i64))
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 3, i32 [[TMP6]], i64 [[TMP7]], [[STRUCT_TRAVERSALDATA]] [[TRAV_DATA_I_FCA_5_INSERT]], float [[RES_I_FCA_1_INSERT_FCA_0_EXTRACT]], i32 0, [[STRUCT_LARGEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_6_INSERT]]), !continuation.registercount [[META32]], !continuation.returnedRegistercount !32
; DXILCONTPOSTPROCESS-NEXT: unreachable
; DXILCONTPOSTPROCESS: accepthit.i:
-; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = bitcast i32 100 to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_070_0_VEC_INSERT:%.*]] = insertelement <2 x float> undef, float [[TMP13]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = bitcast i32 101 to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_070_4_VEC_INSERT:%.*]] = insertelement <2 x float> [[DOTSROA_070_0_VEC_INSERT]], float [[TMP14]], i32 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = bitcast i32 100 to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_070_0_VEC_INSERT:%.*]] = insertelement <2 x float> undef, float [[TMP8]], i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = bitcast i32 101 to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_070_4_VEC_INSERT:%.*]] = insertelement <2 x float> [[DOTSROA_070_0_VEC_INSERT]], float [[TMP9]], i32 1
; DXILCONTPOSTPROCESS-NEXT: store i32 102, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([30 x i32], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 1) to ptr addrspace(20)), align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 103, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([30 x i32], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i64 2) to ptr addrspace(20)), align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 104, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([30 x i32], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i64 3) to ptr addrspace(20)), align 4
@@ -1496,10 +1442,8 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES:%.*]] poison, <2 x float> [[DOTSROA_070_4_VEC_INSERT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_EXTRACT:%.*]] = extractvalue [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]] [[DOTFCA_0_INSERT]], 0
; DXILCONTPOSTPROCESS-NEXT: [[ISEND_I:%.*]] = call i1 @opaqueIsEnd()
-; DXILCONTPOSTPROCESS-NEXT: br i1 [[ISEND_I]], label [[TMP15:%.*]], label [[TMP17:%.*]]
-; DXILCONTPOSTPROCESS: 15:
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD_ADDR1:%.*]] = getelementptr inbounds [[MYINTERSECTIONSHADERLARGEATTRS_FRAME]], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD2:%.*]] = load i64, ptr [[RETURNADDR_RELOAD_ADDR1]], align 4
+; DXILCONTPOSTPROCESS-NEXT: br i1 [[ISEND_I]], label [[TMP10:%.*]], label [[TMP12:%.*]]
+; DXILCONTPOSTPROCESS: 10:
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_INSERT28:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] poison, <3 x i32> [[DOTFCA_0_0_0_EXTRACT]], 0, 0, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_INSERT31:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_0_0_0_INSERT28]], <2 x float> [[DOTFCA_0_EXTRACT]], 0, 1, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_INSERT34:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_0_1_0_INSERT31]], float [[DOTFCA_1_0_EXTRACT]], 1, 0
@@ -1508,12 +1452,10 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_INSERT43:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_2_INSERT40]], <3 x float> [[DOTFCA_3_EXTRACT]], 3
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_4_INSERT46:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_3_INSERT43]], float [[DOTFCA_4_EXTRACT]], 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_INSERT49:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_4_INSERT46]], i64 [[DOTFCA_5_EXTRACT]], 5
-; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD2]], i32 [[TMP16]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT49]]), !continuation.registercount [[META32]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP11]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT49]]), !continuation.registercount [[META32]]
; DXILCONTPOSTPROCESS-NEXT: unreachable
-; DXILCONTPOSTPROCESS: 17:
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[MYINTERSECTIONSHADERLARGEATTRS_FRAME]], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr [[RETURNADDR_RELOAD_ADDR]], align 4
+; DXILCONTPOSTPROCESS: 12:
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] poison, <3 x i32> [[DOTFCA_0_0_0_EXTRACT]], 0, 0, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_0_0_0_INSERT]], <2 x float> [[DOTFCA_0_EXTRACT]], 0, 1, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_0_1_0_INSERT]], float [[DOTFCA_1_0_EXTRACT]], 1, 0
@@ -1522,33 +1464,22 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_2_INSERT]], <3 x float> [[DOTFCA_3_EXTRACT]], 3
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_4_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_3_INSERT]], float [[DOTFCA_4_EXTRACT]], 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_4_INSERT]], i64 [[DOTFCA_5_EXTRACT]], 5
-; DXILCONTPOSTPROCESS-NEXT: [[TMP18:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP18]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT]]), !continuation.registercount [[META32]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP13]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT]]), !continuation.registercount [[META32]]
; DXILCONTPOSTPROCESS-NEXT: unreachable
;
;
; DXILCONTPOSTPROCESS-LABEL: define dso_local void @MyIntersectionShaderLargeAttrs.resume.0(
; DXILCONTPOSTPROCESS-SAME: i32 [[TMP0:%.*]], [[STRUCT_TRAVERSALDATA:%.*]] [[TMP1:%.*]]) !lgc.rt.shaderstage [[META40]] !continuation.registercount [[META32]] !continuation [[META43]] {
; DXILCONTPOSTPROCESS-NEXT: entryresume.0:
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_TRAVERSALDATA]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [2 x i32], align 4
; DXILCONTPOSTPROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_TRAVERSALDATA]] [[TMP1]], ptr [[SYSTEM_DATA]], align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP0]], ptr [[CSP]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(21)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP3]], i64 -8
-; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(21) [[TMP5]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP7]], ptr [[TMP6]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(21) [[TMP4]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i32], ptr [[CONT_STATE]], i32 0, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(21) [[TMP8]], align 4
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], -8
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP12]], ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], -8
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP3]], ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP4]] to ptr addrspace(21)
+; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(21) [[TMP5]], i64 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_EXTRACT10:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 0, 0, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_EXTRACT12:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 0, 1, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_EXTRACT14:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 1, 0
@@ -1559,10 +1490,10 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_EXTRACT24:%.*]] = extractvalue [[STRUCT_TRAVERSALDATA]] [[TMP1]], 5
; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
; DXILCONTPOSTPROCESS-NEXT: [[ISEND_I:%.*]] = call i1 @opaqueIsEnd()
-; DXILCONTPOSTPROCESS-NEXT: br i1 [[ISEND_I]], label [[TMP13:%.*]], label [[TMP15:%.*]]
-; DXILCONTPOSTPROCESS: 13:
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD_ADDR1:%.*]] = getelementptr inbounds [[MYINTERSECTIONSHADERLARGEATTRS_FRAME:%.*]], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD2:%.*]] = load i64, ptr [[RETURNADDR_RELOAD_ADDR1]], align 4
+; DXILCONTPOSTPROCESS-NEXT: br i1 [[ISEND_I]], label [[TMP7:%.*]], label [[TMP9:%.*]]
+; DXILCONTPOSTPROCESS: 7:
+; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD_ADDR1:%.*]] = getelementptr inbounds [[MYINTERSECTIONSHADERLARGEATTRS_FRAME:%.*]], ptr addrspace(21) [[TMP6]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD2:%.*]] = load i64, ptr addrspace(21) [[RETURNADDR_RELOAD_ADDR1]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_INSERT28:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] poison, <3 x i32> [[DOTFCA_0_0_0_EXTRACT10]], 0, 0, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_INSERT31:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_0_0_0_INSERT28]], <2 x float> [[DOTFCA_0_1_0_EXTRACT12]], 0, 1, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_INSERT34:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_0_1_0_INSERT31]], float [[DOTFCA_1_0_EXTRACT14]], 1, 0
@@ -1571,12 +1502,12 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_INSERT43:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_2_INSERT40]], <3 x float> [[DOTFCA_3_EXTRACT20]], 3
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_4_INSERT46:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_3_INSERT43]], float [[DOTFCA_4_EXTRACT22]], 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_INSERT49:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_4_INSERT46]], i64 [[DOTFCA_5_EXTRACT24]], 5
-; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD2]], i32 [[TMP14]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT49]]), !continuation.registercount [[META32]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD2]], i32 [[TMP8]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT49]]), !continuation.registercount [[META32]]
; DXILCONTPOSTPROCESS-NEXT: unreachable
-; DXILCONTPOSTPROCESS: 15:
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[MYINTERSECTIONSHADERLARGEATTRS_FRAME]], ptr [[CONT_STATE]], i32 0, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr [[RETURNADDR_RELOAD_ADDR]], align 4
+; DXILCONTPOSTPROCESS: 9:
+; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[MYINTERSECTIONSHADERLARGEATTRS_FRAME]], ptr addrspace(21) [[TMP6]], i32 0, i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[RETURNADDR_RELOAD:%.*]] = load i64, ptr addrspace(21) [[RETURNADDR_RELOAD_ADDR]], align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_0_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] poison, <3 x i32> [[DOTFCA_0_0_0_EXTRACT10]], 0, 0, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_1_0_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_0_0_0_INSERT]], <2 x float> [[DOTFCA_0_1_0_EXTRACT12]], 0, 1, 0
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_0_1_0_INSERT]], float [[DOTFCA_1_0_EXTRACT14]], 1, 0
@@ -1585,49 +1516,45 @@ attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_3_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_2_INSERT]], <3 x float> [[DOTFCA_3_EXTRACT20]], 3
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_4_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_3_INSERT]], float [[DOTFCA_4_EXTRACT22]], 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_5_INSERT:%.*]] = insertvalue [[STRUCT_TRAVERSALDATA]] [[DOTFCA_4_INSERT]], i64 [[DOTFCA_5_EXTRACT24]], 5
-; DXILCONTPOSTPROCESS-NEXT: [[TMP16:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP16]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT]]), !continuation.registercount [[META32]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR_RELOAD]], i32 [[TMP10]], [[STRUCT_TRAVERSALDATA]] [[DOTFCA_5_INSERT]]), !continuation.registercount [[META32]]
; DXILCONTPOSTPROCESS-NEXT: unreachable
;
;
; DXILCONTPOSTPROCESS-LABEL: define void @MyMissShader(
; DXILCONTPOSTPROCESS-SAME: i32 [[CSPINIT:%.*]], i64 [[RETURNADDR:%.*]], [[STRUCT_SYSTEMDATA:%.*]] [[TMP0:%.*]]) #[[ATTR3]] !lgc.rt.shaderstage [[META44:![0-9]+]] !continuation.registercount [[META35]] !continuation [[META45:![0-9]+]] !continuation.state [[META22]] {
; DXILCONTPOSTPROCESS-NEXT: AllocaSpillBB:
-; DXILCONTPOSTPROCESS-NEXT: [[SYSTEM_DATA:%.*]] = alloca [[STRUCT_SYSTEMDATA]], align 8
-; DXILCONTPOSTPROCESS-NEXT: [[CONT_STATE:%.*]] = alloca [0 x i32], align 4
; DXILCONTPOSTPROCESS-NEXT: [[CSP:%.*]] = alloca i32, align 4
-; DXILCONTPOSTPROCESS-NEXT: store [[STRUCT_SYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA]], align 4
; DXILCONTPOSTPROCESS-NEXT: store i32 [[CSPINIT]], ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = load [[STRUCT_SYSTEMDATA]], ptr [[SYSTEM_DATA]], align 4
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP1]], 0, 0
-; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP1]], 1, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP0]], 0, 0
+; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_1_0_EXTRACT:%.*]] = extractvalue [[STRUCT_SYSTEMDATA]] [[TMP0]], 1, 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_0_VEC_INSERT:%.*]] = insertelement <4 x float> undef, float [[TMP2]], i32 0
+; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = bitcast i32 [[TMP3]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_4_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_0_VEC_INSERT]], float [[TMP4]], i32 1
+; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = bitcast i32 [[TMP5]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_8_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_4_VEC_INSERT]], float [[TMP6]], i32 2
+; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = bitcast i32 [[TMP7]] to float
+; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_12_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_8_VEC_INSERT]], float [[TMP8]], i32 3
; DXILCONTPOSTPROCESS-NEXT: call void @amd.dx.setLocalRootIndex(i32 5)
-; DXILCONTPOSTPROCESS-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(20) @REGISTERS, align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_0_VEC_INSERT:%.*]] = insertelement <4 x float> undef, float [[TMP3]], i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_4_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_0_VEC_INSERT]], float [[TMP5]], i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP7:%.*]] = bitcast i32 [[TMP6]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_8_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_4_VEC_INSERT]], float [[TMP7]], i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_4_MISS_IN]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
-; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = bitcast i32 [[TMP8]] to float
-; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_12_VEC_INSERT:%.*]] = insertelement <4 x float> [[DOTSROA_0_8_VEC_INSERT]], float [[TMP9]], i32 3
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_0_VEC_EXTRACT:%.*]] = extractelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, i32 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = bitcast float [[DOTSROA_0_0_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP10]], ptr addrspace(20) @REGISTERS, align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP9:%.*]] = bitcast float [[DOTSROA_0_0_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP9]], ptr addrspace(20) @REGISTERS, align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_4_VEC_EXTRACT:%.*]] = extractelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, i32 1
-; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = bitcast float [[DOTSROA_0_4_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP11]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP10:%.*]] = bitcast float [[DOTSROA_0_4_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP10]], ptr addrspace(20) addrspacecast (ptr getelementptr inbounds ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT:%.*]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i32 7) to ptr addrspace(20)), align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_8_VEC_EXTRACT:%.*]] = extractelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, i32 2
-; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = bitcast float [[DOTSROA_0_8_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP12]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP11:%.*]] = bitcast float [[DOTSROA_0_8_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP11]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 8) to ptr addrspace(20)), align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTSROA_0_12_VEC_EXTRACT:%.*]] = extractelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, i32 3
-; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = bitcast float [[DOTSROA_0_12_VEC_EXTRACT]] to i32
-; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP13]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
+; DXILCONTPOSTPROCESS-NEXT: [[TMP12:%.*]] = bitcast float [[DOTSROA_0_12_VEC_EXTRACT]] to i32
+; DXILCONTPOSTPROCESS-NEXT: store i32 [[TMP12]], ptr addrspace(20) addrspacecast (ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_6_MISS_OUT]], ptr addrspacecast (ptr addrspace(20) @REGISTERS to ptr), i32 0, i32 0, i64 9) to ptr addrspace(20)), align 4
; DXILCONTPOSTPROCESS-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [[STRUCT_DISPATCHSYSTEMDATA:%.*]] poison, <3 x i32> [[DOTFCA_0_0_EXTRACT]], 0
-; DXILCONTPOSTPROCESS-NEXT: [[TMP14:%.*]] = load i32, ptr [[CSP]], align 4
-; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP14]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META35]]
+; DXILCONTPOSTPROCESS-NEXT: [[TMP13:%.*]] = load i32, ptr [[CSP]], align 4
+; DXILCONTPOSTPROCESS-NEXT: call void (i64, ...) @continuation.continue(i64 [[RETURNADDR]], i32 [[TMP13]], [[STRUCT_DISPATCHSYSTEMDATA]] [[DOTFCA_0_INSERT]]), !continuation.registercount [[META35]]
; DXILCONTPOSTPROCESS-NEXT: unreachable
;
diff --git a/shared/continuations/test/dx/unnamed-type-intrinsics.ll b/shared/continuations/test/dx/unnamed-type-intrinsics.ll
index 0aab765fec..dc9d7f13b3 100644
--- a/shared/continuations/test/dx/unnamed-type-intrinsics.ll
+++ b/shared/continuations/test/dx/unnamed-type-intrinsics.ll
@@ -346,12 +346,10 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
;
;
; LOWERRAYTRACINGPIPELINE-LABEL: define void @MyRayGen(
-; LOWERRAYTRACINGPIPELINE-SAME: ) #[[ATTR2:[0-9]+]] !lgc.rt.shaderstage [[META15:![0-9]+]] !continuation.entry [[META20:![0-9]+]] !continuation.registercount [[META15]] !continuation [[META21:![0-9]+]] {
-; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[TMP0:%.*]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP1:%.*]] = call [[TMP0]] @continuations.getSystemData.s_s()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[TMP0]] [[TMP1]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
+; LOWERRAYTRACINGPIPELINE-SAME: [[TMP0:%.*]] [[TMP0]]) #[[ATTR2:[0-9]+]] !lgc.rt.shaderstage [[META15:![0-9]+]] !continuation.entry [[META20:![0-9]+]] !continuation.registercount [[META15]] !continuation [[META21:![0-9]+]] {
+; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[TMP0]], align 8
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[TMP0]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP2:%.*]] = load [[DX_TYPES_HANDLE:%.*]], ptr @"\01?Scene@@3URaytracingAccelerationStructure@@A", align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = load [[DX_TYPES_HANDLE]], ptr @"\01?RenderTarget@@3V?$RWTexture2D@V?$vector@M$03@@@@A", align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 4
@@ -364,7 +362,7 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP9:%.*]] = call i64 @amd.dx.getAccelStructAddr([[DX_TYPES_HANDLE]] [[TMP8]])
; LOWERRAYTRACINGPIPELINE-NEXT: [[DIS_DATA_I:%.*]] = load [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYS_DATA_I:%.*]] = insertvalue [[TMP2]] undef, [[TMP0]] [[DIS_DATA_I]], 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TRAV_DATA_I:%.*]] = insertvalue [[TMP1]] undef, [[TMP2]] [[SYS_DATA_I]], 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TRAV_DATA_I:%.*]] = insertvalue [[TMP1:%.*]] undef, [[TMP2]] [[SYS_DATA_I]], 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[ADDR_I:%.*]] = call i64 @_AmdGetResumePointAddr() #[[ATTR3:[0-9]+]]
; LOWERRAYTRACINGPIPELINE-NEXT: [[TRAV_DATA2_I:%.*]] = insertvalue [[TMP1]] [[TRAV_DATA_I]], i64 [[ADDR_I]], 5
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP4]], i32 0, i32 0
@@ -401,8 +399,7 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP33:%.*]] = load i32, ptr getelementptr ([[STRUCT_RAYPAYLOAD_ATTR_MAX_8_I32S_LAYOUT_5_CLOSESTHIT_OUT]], ptr @PAYLOAD, i32 0, i32 0, i64 9), align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP33]], ptr [[TMP32]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store [[TMP0]] [[TMP22]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[LOCAL_ROOT_INDEX1:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX1]])
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; LOWERRAYTRACINGPIPELINE-NEXT: br label [[DOTSPLIT:%.*]]
; LOWERRAYTRACINGPIPELINE: .split:
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP34:%.*]] = load <4 x float>, ptr [[TMP6]], align 4, !tbaa [[TBAA22]]
@@ -427,11 +424,9 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[TMP2]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP3:%.*]] = alloca [[STRUCT_RAYPAYLOAD:%.*]], align 8
; LOWERRAYTRACINGPIPELINE-NEXT: [[HITATTRS:%.*]] = alloca [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], align 8
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = call [[TMP2]] @continuations.getSystemData.s_s_0()
-; LOWERRAYTRACINGPIPELINE-NEXT: store [[TMP2]] [[TMP4]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[TMP2]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
-; LOWERRAYTRACINGPIPELINE-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP5]])
-; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
+; LOWERRAYTRACINGPIPELINE-NEXT: store [[TMP2]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[TMP2]], ptr [[SYSTEM_DATA_ALLOCA]], i32 0, i32 0
+; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP5:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[TMP4]])
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_RAYPAYLOAD]], ptr [[TMP3]], i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP6]], i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i64 0
@@ -458,6 +453,7 @@ attributes #5 = { nocallback nofree nosync nounwind willreturn memory(argmem: re
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 1
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: store i32 [[TMP23]], ptr [[TMP21]], align 4
+; LOWERRAYTRACINGPIPELINE-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[TMP5]])
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_BUILTINTRIANGLEINTERSECTIONATTRIBUTES]], ptr [[HITATTRS]], i32 0, i32 0
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP25:%.*]] = load <2 x float>, ptr [[TMP24]], align 4
; LOWERRAYTRACINGPIPELINE-NEXT: [[TMP26:%.*]] = extractelement <2 x float> [[TMP25]], i32 0
diff --git a/shared/continuations/test/intrinsics/get-func-addr.ll b/shared/continuations/test/intrinsics/get-func-addr.ll
index 496e1eaf91..b8a0cc54a5 100644
--- a/shared/continuations/test/intrinsics/get-func-addr.ll
+++ b/shared/continuations/test/intrinsics/get-func-addr.ll
@@ -12,16 +12,15 @@ declare %struct.DispatchSystemData @_cont_SetupRayGen()
declare !types !8 i32 @_cont_GetLocalRootIndex(%struct.DispatchSystemData*)
define { i64, i32 } @main() !lgc.rt.shaderstage !10 {
-; CHECK-LABEL: define void @main() !lgc.rt.shaderstage !6 !continuation.entry !12 !continuation.registercount !6 !continuation !13 {
+; CHECK-LABEL: define void @main
+; CHECK-SAME: ([[STRUCT_DISPATCHSYSTEMDATA:%.*]] [[TMP0:%.*]]) !lgc.rt.shaderstage [[META6:![0-9]+]] !continuation.entry [[META12:![0-9]+]] !continuation.registercount [[META6]] !continuation [[META13:![0-9]+]] {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA:%.*]], align 8
-; CHECK-NEXT: [[TMP0:%.*]] = call [[STRUCT_DISPATCHSYSTEMDATA]] @continuations.getSystemData.s_struct.DispatchSystemDatas()
+; CHECK-NEXT: [[SYSTEM_DATA_ALLOCA:%.*]] = alloca [[STRUCT_DISPATCHSYSTEMDATA]], align 8
; CHECK-NEXT: store [[STRUCT_DISPATCHSYSTEMDATA]] [[TMP0]], ptr [[SYSTEM_DATA_ALLOCA]], align 4
-; CHECK-NEXT: [[LOCAL_ROOT_INDEX:%.*]] = call i32 @_cont_GetLocalRootIndex(ptr [[SYSTEM_DATA_ALLOCA]])
-; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 [[LOCAL_ROOT_INDEX]])
+; CHECK-NEXT: call void @amd.dx.setLocalRootIndex(i32 0)
; CHECK-NEXT: [[V0:%.*]] = insertvalue { i64, i32 } undef, i64 ptrtoint (ptr @MyFunc to i64), 0
; CHECK-NEXT: [[V1:%.*]] = insertvalue { i64, i32 } undef, i32 ptrtoint (ptr @MyFunc2 to i32), 1
-; CHECK-NEXT: ret void, !continuation.registercount !9
+; CHECK-NEXT: ret void, !continuation.registercount [[META9:![0-9]+]]
;
entry:
%val = call i64 @_AmdGetFuncAddrMyFunc()
diff --git a/shared/continuations/test/lgccps/alloca-select.ll b/shared/continuations/test/lgccps/alloca-select.ll
index a935c900c1..6622b1c372 100644
--- a/shared/continuations/test/lgccps/alloca-select.ll
+++ b/shared/continuations/test/lgccps/alloca-select.ll
@@ -24,7 +24,7 @@ declare i32 @lgc.cps.as.continuation.reference(...) memory(none)
declare float @lgc.cps.await.f32(...)
declare void @lgc.cps.jump(...)
; CHECK-LABEL: define void @test
-; CHECK-SAME: ({} [[STATE:%.*]], i32 [[RCR:%.*]], float [[ARG:%.*]], i32 [[ARG1:%.*]]) !lgc.cps !0 !continuation !1 {
+; CHECK-SAME: ({} [[STATE:%.*]], i32 [[RCR:%.*]], float [[ARG:%.*]], i32 [[ARG1:%.*]]) !lgc.cps [[META0:![0-9]+]] !continuation [[META1:![0-9]+]] {
; CHECK-NEXT: AllocaSpillBB:
; CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(32) @lgc.cps.alloc(i32 20)
; CHECK-NEXT: [[A1:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP0]], i32 0, i32 0
@@ -47,20 +47,20 @@ declare void @lgc.cps.jump(...)
;
;
; CHECK-LABEL: define dso_local void @test.resume.0
-; CHECK-SAME: ({} [[TMP0:%.*]], i32 [[TMP1:%.*]], float [[TMP2:%.*]]) !lgc.cps !0 !continuation !1 {
+; CHECK-SAME: ({} [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]], float [[TMP3:%.*]]) !lgc.cps [[META0]] !continuation [[META1]] {
; CHECK-NEXT: entryresume.0:
-; CHECK-NEXT: [[TMP3:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 20)
-; CHECK-NEXT: [[A1:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP3]], i32 0, i32 0
-; CHECK-NEXT: [[A2:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP3]], i32 0, i32 1
-; CHECK-NEXT: [[ARG1_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP3]], i32 0, i32 4
+; CHECK-NEXT: [[TMP4:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 20)
+; CHECK-NEXT: [[A1:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP4]], i32 0, i32 0
+; CHECK-NEXT: [[A2:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP4]], i32 0, i32 1
+; CHECK-NEXT: [[ARG1_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP4]], i32 0, i32 4
; CHECK-NEXT: [[ARG1_RELOAD:%.*]] = load i32, ptr addrspace(32) [[ARG1_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP3]], i32 0, i32 3
+; CHECK-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP4]], i32 0, i32 3
; CHECK-NEXT: [[ARG_RELOAD:%.*]] = load float, ptr addrspace(32) [[ARG_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP3]], i32 0, i32 2
+; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP4]], i32 0, i32 2
; CHECK-NEXT: [[RCR_RELOAD:%.*]] = load i32, ptr addrspace(32) [[RCR_RELOAD_ADDR]], align 4
; CHECK-NEXT: [[COND2:%.*]] = icmp ult i32 [[ARG1_RELOAD]], 0
; CHECK-NEXT: [[P1:%.*]] = select i1 [[COND2]], ptr addrspace(32) [[A1]], ptr addrspace(32) [[A2]]
-; CHECK-NEXT: [[TMP:%.*]] = fmul float [[TMP2]], [[ARG_RELOAD]]
+; CHECK-NEXT: [[TMP:%.*]] = fmul float [[TMP3]], [[ARG_RELOAD]]
; CHECK-NEXT: [[V111:%.*]] = load float, ptr addrspace(32) [[P1]], align 4
; CHECK-NEXT: [[RETURNVALUE:%.*]] = fmul float [[TMP]], [[V111]]
; CHECK-NEXT: call void @lgc.cps.free(i32 20)
diff --git a/shared/continuations/test/lgccps/await-if-else.ll b/shared/continuations/test/lgccps/await-if-else.ll
index 370943b73b..d68edbb11d 100644
--- a/shared/continuations/test/lgccps/await-if-else.ll
+++ b/shared/continuations/test/lgccps/await-if-else.ll
@@ -31,7 +31,7 @@ declare i32 @lgc.cps.as.continuation.reference(...) memory(none)
declare float @lgc.cps.await.f32(...)
declare void @lgc.cps.jump(...)
; CHECK-LABEL: define void @test(
-; CHECK-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], float [[ARG:%.*]]) !lgc.cps !0 !continuation !1 {
+; CHECK-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], float [[ARG:%.*]]) !lgc.cps [[META0:![0-9]+]] !continuation [[META1:![0-9]+]] {
; CHECK-NEXT: AllocaSpillBB:
; CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(32) @lgc.cps.alloc(i32 8)
; CHECK-NEXT: [[ARG_SPILL_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP0]], i32 0, i32 1
@@ -56,28 +56,28 @@ declare void @lgc.cps.jump(...)
;
;
; CHECK-LABEL: define dso_local void @test.resume.0(
-; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], float [[TMP2:%.*]]) !lgc.cps !0 !continuation !1 {
+; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]], float [[TMP3:%.*]]) !lgc.cps [[META0]] !continuation [[META1]] {
; CHECK-NEXT: entryresume.0:
-; CHECK-NEXT: [[TMP3:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 8)
-; CHECK-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP3]], i32 0, i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 8)
+; CHECK-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP4]], i32 0, i32 1
; CHECK-NEXT: [[ARG_RELOAD:%.*]] = load float, ptr addrspace(32) [[ARG_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP3]], i32 0, i32 0
+; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP4]], i32 0, i32 0
; CHECK-NEXT: [[RCR_RELOAD:%.*]] = load i32, ptr addrspace(32) [[RCR_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[RETURNVALUE:%.*]] = fmul float [[TMP2]], [[ARG_RELOAD]]
+; CHECK-NEXT: [[RETURNVALUE:%.*]] = fmul float [[TMP3]], [[ARG_RELOAD]]
; CHECK-NEXT: call void @lgc.cps.free(i32 8)
; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[RCR_RELOAD]], i32 2, {} poison, i32 poison, float [[RETURNVALUE]])
; CHECK-NEXT: unreachable
;
;
; CHECK-LABEL: define dso_local void @test.resume.1(
-; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], float [[TMP2:%.*]]) !lgc.cps !0 !continuation !1 {
+; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]], float [[TMP3:%.*]]) !lgc.cps [[META0]] !continuation [[META1]] {
; CHECK-NEXT: entryresume.1:
-; CHECK-NEXT: [[TMP3:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 8)
-; CHECK-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP3]], i32 0, i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 8)
+; CHECK-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP4]], i32 0, i32 1
; CHECK-NEXT: [[ARG_RELOAD:%.*]] = load float, ptr addrspace(32) [[ARG_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP3]], i32 0, i32 0
+; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP4]], i32 0, i32 0
; CHECK-NEXT: [[RCR_RELOAD:%.*]] = load i32, ptr addrspace(32) [[RCR_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[RETURNVALUE:%.*]] = fmul float [[TMP2]], [[ARG_RELOAD]]
+; CHECK-NEXT: [[RETURNVALUE:%.*]] = fmul float [[TMP3]], [[ARG_RELOAD]]
; CHECK-NEXT: call void @lgc.cps.free(i32 8)
; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[RCR_RELOAD]], i32 2, {} poison, i32 poison, float [[RETURNVALUE]])
; CHECK-NEXT: unreachable
diff --git a/shared/continuations/test/lgccps/await-if.ll b/shared/continuations/test/lgccps/await-if.ll
index 1076ebe0e8..fed102292e 100644
--- a/shared/continuations/test/lgccps/await-if.ll
+++ b/shared/continuations/test/lgccps/await-if.ll
@@ -27,7 +27,7 @@ declare i32 @lgc.cps.as.continuation.reference(...) memory(none)
declare float @lgc.cps.await.f32(...)
declare void @lgc.cps.jump(...)
; CHECK-LABEL: define void @test(
-; CHECK-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], float [[ARG:%.*]]) !lgc.cps !0 !continuation !1 {
+; CHECK-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], float [[ARG:%.*]]) !lgc.cps [[META0:![0-9]+]] !continuation [[META1:![0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(32) @lgc.cps.alloc(i32 8)
; CHECK-NEXT: [[ARG_SPILL_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP0]], i32 0, i32 1
@@ -45,25 +45,21 @@ declare void @lgc.cps.jump(...)
; CHECK-NEXT: unreachable
; CHECK: bb2:
; CHECK-NEXT: [[T0_BB2:%.*]] = phi float [ [[T0]], [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP0]], i32 0, i32 1
-; CHECK-NEXT: [[ARG_RELOAD:%.*]] = load float, ptr addrspace(32) [[ARG_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP0]], i32 0, i32 0
-; CHECK-NEXT: [[RCR_RELOAD:%.*]] = load i32, ptr addrspace(32) [[RCR_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[RETURNVALUE:%.*]] = fmul float [[T0_BB2]], [[ARG_RELOAD]]
+; CHECK-NEXT: [[RETURNVALUE:%.*]] = fmul float [[T0_BB2]], [[ARG]]
; CHECK-NEXT: call void @lgc.cps.free(i32 8)
-; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[RCR_RELOAD]], i32 2, {} poison, i32 poison, float [[RETURNVALUE]])
+; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[RCR]], i32 2, {} poison, i32 poison, float [[RETURNVALUE]])
; CHECK-NEXT: unreachable
;
;
; CHECK-LABEL: define dso_local void @test.resume.0(
-; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], float [[TMP2:%.*]]) !lgc.cps !0 !continuation !1 {
+; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]], float [[TMP3:%.*]]) !lgc.cps [[META0]] !continuation [[META1]] {
; CHECK-NEXT: entryresume.0:
-; CHECK-NEXT: [[TMP3:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 8)
-; CHECK-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP3]], i32 0, i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 8)
+; CHECK-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP4]], i32 0, i32 1
; CHECK-NEXT: [[ARG_RELOAD:%.*]] = load float, ptr addrspace(32) [[ARG_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP3]], i32 0, i32 0
+; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP4]], i32 0, i32 0
; CHECK-NEXT: [[RCR_RELOAD:%.*]] = load i32, ptr addrspace(32) [[RCR_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[RETURNVALUE:%.*]] = fmul float [[TMP2]], [[ARG_RELOAD]]
+; CHECK-NEXT: [[RETURNVALUE:%.*]] = fmul float [[TMP3]], [[ARG_RELOAD]]
; CHECK-NEXT: call void @lgc.cps.free(i32 8)
; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[RCR_RELOAD]], i32 2, {} poison, i32 poison, float [[RETURNVALUE]])
; CHECK-NEXT: unreachable
diff --git a/shared/continuations/test/lgccps/await-in-loop.ll b/shared/continuations/test/lgccps/await-in-loop.ll
index ead48b312d..0a7612aa41 100644
--- a/shared/continuations/test/lgccps/await-in-loop.ll
+++ b/shared/continuations/test/lgccps/await-in-loop.ll
@@ -29,7 +29,7 @@ declare i32 @lgc.cps.as.continuation.reference(...) memory(none)
declare float @lgc.cps.await.f32(...)
declare void @lgc.cps.jump(...)
; CHECK-LABEL: define void @test(
-; CHECK-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], float [[ARG:%.*]], float [[ARG2:%.*]]) !lgc.cps !0 !continuation !1 {
+; CHECK-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], float [[ARG:%.*]], float [[ARG2:%.*]]) !lgc.cps [[META0:![0-9]+]] !continuation [[META1:![0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(32) @lgc.cps.alloc(i32 20)
; CHECK-NEXT: [[ARG2_SPILL_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP0]], i32 0, i32 2
@@ -44,41 +44,39 @@ declare void @lgc.cps.jump(...)
; CHECK-NEXT: store i32 [[CR]], ptr addrspace(32) [[CR_SPILL_ADDR]], align 4
; CHECK-NEXT: [[IND_SPILL_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP0]], i32 0, i32 4
; CHECK-NEXT: store i32 0, ptr addrspace(32) [[IND_SPILL_ADDR]], align 4
-; CHECK-NEXT: [[CR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP0]], i32 0, i32 3
-; CHECK-NEXT: [[CR_RELOAD:%.*]] = load i32, ptr addrspace(32) [[CR_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = inttoptr i32 [[CR_RELOAD]] to ptr
+; CHECK-NEXT: [[TMP1:%.*]] = inttoptr i32 [[CR]] to ptr
; CHECK-NEXT: [[TMP2:%.*]] = call i32 (...) @lgc.cps.as.continuation.reference(ptr @test.resume.0)
-; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[CR_RELOAD]], i32 2, {} poison, i32 [[TMP2]], i32 0)
+; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[CR]], i32 2, {} poison, i32 [[TMP2]], i32 0)
; CHECK-NEXT: unreachable
;
;
; CHECK-LABEL: define dso_local void @test.resume.0(
-; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], float [[TMP2:%.*]]) !lgc.cps !0 !continuation !1 {
+; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]], float [[TMP3:%.*]]) !lgc.cps [[META0]] !continuation [[META1]] {
; CHECK-NEXT: entryresume.0:
-; CHECK-NEXT: [[TMP3:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 20)
-; CHECK-NEXT: [[IND_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP3]], i32 0, i32 4
+; CHECK-NEXT: [[TMP4:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 20)
+; CHECK-NEXT: [[IND_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP4]], i32 0, i32 4
; CHECK-NEXT: [[IND_RELOAD:%.*]] = load i32, ptr addrspace(32) [[IND_RELOAD_ADDR]], align 4
; CHECK-NEXT: [[INC:%.*]] = add i32 [[IND_RELOAD]], 1
-; CHECK-NEXT: [[COND:%.*]] = fcmp olt float [[TMP2]], 5.000000e+00
+; CHECK-NEXT: [[COND:%.*]] = fcmp olt float [[TMP3]], 5.000000e+00
; CHECK-NEXT: br i1 [[COND]], label [[LOOP_FROM_AFTERCOROSUSPEND:%.*]], label [[END:%.*]]
; CHECK: loop.from.AfterCoroSuspend:
; CHECK-NEXT: [[INC_LOOP:%.*]] = phi i32 [ [[INC]], [[ENTRYRESUME_0:%.*]] ]
-; CHECK-NEXT: [[IND_SPILL_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP3]], i32 0, i32 4
+; CHECK-NEXT: [[IND_SPILL_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP4]], i32 0, i32 4
; CHECK-NEXT: store i32 [[INC_LOOP]], ptr addrspace(32) [[IND_SPILL_ADDR]], align 4
-; CHECK-NEXT: [[CR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP3]], i32 0, i32 3
+; CHECK-NEXT: [[CR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP4]], i32 0, i32 3
; CHECK-NEXT: [[CR_RELOAD:%.*]] = load i32, ptr addrspace(32) [[CR_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i32 [[CR_RELOAD]] to ptr
-; CHECK-NEXT: [[TMP5:%.*]] = call i32 (...) @lgc.cps.as.continuation.reference(ptr @test.resume.0)
-; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[CR_RELOAD]], i32 2, {} poison, i32 [[TMP5]], i32 [[INC_LOOP]])
+; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i32 [[CR_RELOAD]] to ptr
+; CHECK-NEXT: [[TMP6:%.*]] = call i32 (...) @lgc.cps.as.continuation.reference(ptr @test.resume.0)
+; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[CR_RELOAD]], i32 2, {} poison, i32 [[TMP6]], i32 [[INC_LOOP]])
; CHECK-NEXT: unreachable
; CHECK: end:
-; CHECK-NEXT: [[ARG2_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP3]], i32 0, i32 2
+; CHECK-NEXT: [[ARG2_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP4]], i32 0, i32 2
; CHECK-NEXT: [[ARG2_RELOAD:%.*]] = load float, ptr addrspace(32) [[ARG2_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP3]], i32 0, i32 1
+; CHECK-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP4]], i32 0, i32 1
; CHECK-NEXT: [[ARG_RELOAD:%.*]] = load float, ptr addrspace(32) [[ARG_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP3]], i32 0, i32 0
+; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP4]], i32 0, i32 0
; CHECK-NEXT: [[RCR_RELOAD:%.*]] = load i32, ptr addrspace(32) [[RCR_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[T2:%.*]] = fmul float [[TMP2]], [[ARG_RELOAD]]
+; CHECK-NEXT: [[T2:%.*]] = fmul float [[TMP3]], [[ARG_RELOAD]]
; CHECK-NEXT: [[RETURNVALUE:%.*]] = fadd float [[T2]], [[ARG2_RELOAD]]
; CHECK-NEXT: call void @lgc.cps.free(i32 20)
; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[RCR_RELOAD]], i32 2, {} poison, i32 poison, float [[RETURNVALUE]])
diff --git a/shared/continuations/test/lgccps/cleanup-store-loads.ll b/shared/continuations/test/lgccps/cleanup-store-loads.ll
new file mode 100644
index 0000000000..6355707977
--- /dev/null
+++ b/shared/continuations/test/lgccps/cleanup-store-loads.ll
@@ -0,0 +1,365 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --include-generated-funcs --version 3
+; RUN: opt --verify-each -S -o - -passes='cgscc(inline),cleanup-continuations' %s | FileCheck --check-prefixes=CHECK %s
+
+declare !lgc.cps !0 void @callee({}, i32, float)
+
+declare i64 @getVal64()
+declare void @useVal64(i64)
+declare i32 @getVal32()
+declare void @useVal32(i32)
+declare void @useValF32(float)
+declare i8 @getVal8()
+declare void @useVal8(i8)
+
+; Calls getVal32() to obtain a value, and writes it
+; to the given offset in data.
+define void @storeToOffsetI32(ptr %data, i32 %offset) #4 {
+ %val = call i32 @getVal32()
+ %addr = getelementptr i8, ptr %data, i32 %offset
+ store i32 %val, ptr %addr, align 2
+ ret void
+}
+
+; I8 version store
+define void @storeToOffsetI8(ptr %data, i32 %offset) #4 {
+ %val = call i8 @getVal8()
+ %addr = getelementptr i8, ptr %data, i32 %offset
+ store i8 %val, ptr %addr
+ ret void
+}
+
+; I64 version store
+define void @storeToOffsetI64(ptr %data, i32 %offset) #4 {
+ %val = call i64 @getVal64()
+ %addr = getelementptr i8, ptr %data, i32 %offset
+ store i64 %val, ptr %addr
+ ret void
+}
+
+; Loads the value in data at the given offset, and
+; feeds it into useVal32().
+define void @loadAtOffsetI32(ptr %data, i32 %offset) #4 {
+ %addr = getelementptr i8, ptr %data, i32 %offset
+ %val.reload = load i32, ptr %addr
+ call void @useVal32(i32 %val.reload)
+ ret void
+}
+
+; I64 version load
+define void @loadAtOffsetI64(ptr %data, i32 %offset) #4 {
+ %addr = getelementptr i8, ptr %data, i32 %offset
+ %val.reload = load i32, ptr %addr
+ call void @useVal32(i32 %val.reload)
+ ret void
+}
+
+; F32 version load
+define void @loadAtOffsetF32(ptr %data, i32 %offset) #4 {
+ %addr = getelementptr i8, ptr %data, i32 %offset
+ %val.reload = load float, ptr %addr
+ call void @useValF32(float %val.reload)
+ ret void
+}
+
+%test.Frame = type { i32, float, [100 x i32] }
+
+define { ptr, ptr } @test({} %state, i32 %rcr, float %arg, ptr %0) !lgc.cps !0 !continuation !1 {
+entry:
+ %1 = call ptr @continuation.malloc(i32 408)
+ store ptr %1, ptr %0, align 8
+
+ %arg.spill.addr = getelementptr inbounds %test.Frame, ptr %1, i32 0, i32 1
+ store float %arg, ptr %arg.spill.addr, align 4
+ %rcr.spill.addr = getelementptr inbounds %test.Frame, ptr %1, i32 0, i32 0
+ store i32 %rcr, ptr %rcr.spill.addr, align 4
+
+ %t0 = fadd float %arg, 1.000000e+00
+ %cr = call i32 @lgc.cps.as.continuation.reference(ptr @callee)
+ %cond = fcmp olt float %t0, 1.000000e+00
+ %data = getelementptr inbounds %test.Frame, ptr %1, i32 0, i32 2
+
+ ; Matching load/store pair at offset 0 in data. range: [0, 4)
+ call void @storeToOffsetI32(ptr %data, i32 0)
+
+ ; Double store, no forwarding (even though we could, the second dominates the load)
+ call void @storeToOffsetI32(ptr %data, i32 4)
+ call void @storeToOffsetI32(ptr %data, i32 4)
+
+ ; Store with conflicting store at the start point
+ call void @storeToOffsetI32(ptr %data, i32 10)
+ call void @storeToOffsetI32(ptr %data, i32 12)
+
+ ; Store with conflicting store at the end point
+ call void @storeToOffsetI32(ptr %data, i32 16)
+ call void @storeToOffsetI32(ptr %data, i32 18)
+
+ ; Store with conflicting store strictly inside its range
+ call void @storeToOffsetI32(ptr %data, i32 24)
+ call void @storeToOffsetI8(ptr %data, i32 25)
+
+ ; Load from part of the store range
+ call void @storeToOffsetI64(ptr %data, i32 28)
+
+ ; Type mismatch
+ call void @storeToOffsetI32(ptr %data, i32 36)
+
+ ; Store does not dominate load
+ call void @loadAtOffsetI32(ptr %data, i32 40)
+
+ ; Check tightly packed loads/stores can be optimized correctly
+ call void @storeToOffsetI32(ptr %data, i32 44)
+ call void @storeToOffsetI32(ptr %data, i32 48)
+ br i1 %cond, label %bb1, label %bb2
+
+bb1: ; preds = %entry
+ %2 = inttoptr i32 %cr to ptr
+ %3 = call ptr %2(i32 %cr, i32 2, float %arg)
+ %4 = insertvalue { ptr, ptr } undef, ptr @test.resume.0, 0
+ %5 = insertvalue { ptr, ptr } %4, ptr %3, 1
+ ret { ptr, ptr } %5
+
+bb2: ; preds = %entry
+ %t0.bb2 = phi float [ %t0, %entry ]
+ %arg.reload.addr = getelementptr inbounds %test.Frame, ptr %1, i32 0, i32 1
+ %arg.reload = load float, ptr %arg.reload.addr, align 4
+ %rcr.reload.addr = getelementptr inbounds %test.Frame, ptr %1, i32 0, i32 0
+ %rcr.reload = load i32, ptr %rcr.reload.addr, align 4
+ %returnvalue = fmul float %t0.bb2, %arg.reload
+
+ ; Perfect eliminated case
+ call void @loadAtOffsetI32(ptr %data, i32 0)
+
+ ; Double store, no forwarding (even though we could, the second dominates the load)
+ call void @loadAtOffsetI32(ptr %data, i32 4)
+
+ ; Store with conflicting store at the start point
+ call void @loadAtOffsetI32(ptr %data, i32 12)
+
+ ; Store with conflicting store at the end point
+ call void @loadAtOffsetI32(ptr %data, i32 16)
+
+ ; Store with conflicting store strictly inside its range
+ call void @loadAtOffsetI32(ptr %data, i32 24)
+
+ ; Load from part of the store range
+ call void @loadAtOffsetI32(ptr %data, i32 32)
+
+ ; Type mismatch
+ call void @loadAtOffsetF32(ptr %data, i32 36)
+
+ ; Store does not dominate load
+ call void @storeToOffsetI32(ptr %data, i32 40)
+
+ ; Check tightly packed loads/stores can be optimized correctly
+ call void @loadAtOffsetI32(ptr %data, i32 44)
+ call void @loadAtOffsetI32(ptr %data, i32 48)
+
+ ; Multiple loads can be optimized away
+ call void @loadAtOffsetI32(ptr %data, i32 48)
+
+ call void (...) @lgc.cps.jump(i32 %rcr.reload, i32 2, {} poison, i32 poison, float %returnvalue)
+ unreachable
+}
+
+define internal { ptr, ptr } @test.resume.0(ptr noalias noundef nonnull align 4 dereferenceable(8) %0, i1 %1) !lgc.cps !0 !continuation !1 {
+entryresume.0:
+ %2 = load ptr, ptr %0, align 8
+ %3 = call float @continuations.getReturnValue.f32()
+ %arg.reload.addr = getelementptr inbounds %test.Frame, ptr %2, i32 0, i32 1
+ %arg.reload = load float, ptr %arg.reload.addr, align 4
+ %rcr.reload.addr = getelementptr inbounds %test.Frame, ptr %2, i32 0, i32 0
+ %rcr.reload = load i32, ptr %rcr.reload.addr, align 4
+ %returnvalue = fmul float %3, %arg.reload
+ call void (...) @lgc.cps.jump(i32 %rcr.reload, i32 2, {} poison, i32 poison, float %returnvalue)
+ unreachable
+}
+
+; Function Attrs: memory(none)
+declare i32 @lgc.cps.as.continuation.reference(...) #0
+
+declare float @lgc.cps.await.f32(...)
+
+declare void @lgc.cps.jump(...)
+
+declare !continuation !1 { ptr, ptr } @continuation.prototype.test(ptr, i1)
+
+declare ptr @continuation.malloc(i32)
+
+declare void @continuation.free(ptr)
+
+; Function Attrs: nounwind
+declare token @llvm.coro.id.retcon(i32, i32, ptr, ptr, ptr, ptr) #1
+
+; Function Attrs: nounwind
+declare ptr @llvm.coro.begin(token, ptr writeonly) #1
+
+; Function Attrs: nounwind
+declare i1 @llvm.coro.suspend.retcon.i1(...) #1
+
+; Function Attrs: nounwind willreturn
+declare float @continuations.getReturnValue.f32() #2
+
+; Function Attrs: noreturn
+declare void @continuation.return(...) #3
+
+attributes #0 = { memory(none) }
+attributes #1 = { nounwind }
+attributes #2 = { nounwind willreturn }
+attributes #3 = { noreturn }
+attributes #4 = { alwaysinline }
+
+!0 = !{i32 1}
+!1 = !{ptr @test}
+; CHECK-LABEL: define void @storeToOffsetI32(
+; CHECK-SAME: ptr [[DATA:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[VAL:%.*]] = call i32 @getVal32()
+; CHECK-NEXT: [[ADDR:%.*]] = getelementptr i8, ptr [[DATA]], i32 [[OFFSET]]
+; CHECK-NEXT: store i32 [[VAL]], ptr [[ADDR]], align 2
+; CHECK-NEXT: ret void
+;
+;
+; CHECK-LABEL: define void @storeToOffsetI8(
+; CHECK-SAME: ptr [[DATA:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[VAL:%.*]] = call i8 @getVal8()
+; CHECK-NEXT: [[ADDR:%.*]] = getelementptr i8, ptr [[DATA]], i32 [[OFFSET]]
+; CHECK-NEXT: store i8 [[VAL]], ptr [[ADDR]], align 1
+; CHECK-NEXT: ret void
+;
+;
+; CHECK-LABEL: define void @storeToOffsetI64(
+; CHECK-SAME: ptr [[DATA:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[VAL:%.*]] = call i64 @getVal64()
+; CHECK-NEXT: [[ADDR:%.*]] = getelementptr i8, ptr [[DATA]], i32 [[OFFSET]]
+; CHECK-NEXT: store i64 [[VAL]], ptr [[ADDR]], align 4
+; CHECK-NEXT: ret void
+;
+;
+; CHECK-LABEL: define void @loadAtOffsetI32(
+; CHECK-SAME: ptr [[DATA:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ADDR:%.*]] = getelementptr i8, ptr [[DATA]], i32 [[OFFSET]]
+; CHECK-NEXT: [[VAL_RELOAD:%.*]] = load i32, ptr [[ADDR]], align 4
+; CHECK-NEXT: call void @useVal32(i32 [[VAL_RELOAD]])
+; CHECK-NEXT: ret void
+;
+;
+; CHECK-LABEL: define void @loadAtOffsetI64(
+; CHECK-SAME: ptr [[DATA:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ADDR:%.*]] = getelementptr i8, ptr [[DATA]], i32 [[OFFSET]]
+; CHECK-NEXT: [[VAL_RELOAD:%.*]] = load i32, ptr [[ADDR]], align 4
+; CHECK-NEXT: call void @useVal32(i32 [[VAL_RELOAD]])
+; CHECK-NEXT: ret void
+;
+;
+; CHECK-LABEL: define void @loadAtOffsetF32(
+; CHECK-SAME: ptr [[DATA:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ADDR:%.*]] = getelementptr i8, ptr [[DATA]], i32 [[OFFSET]]
+; CHECK-NEXT: [[VAL_RELOAD:%.*]] = load float, ptr [[ADDR]], align 4
+; CHECK-NEXT: call void @useValF32(float [[VAL_RELOAD]])
+; CHECK-NEXT: ret void
+;
+;
+; CHECK-LABEL: define void @test(
+; CHECK-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], float [[ARG:%.*]]) !lgc.cps [[META0:![0-9]+]] !continuation [[META1:![0-9]+]] {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(32) @lgc.cps.alloc(i32 408)
+; CHECK-NEXT: [[ARG_SPILL_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP0]], i32 0, i32 1
+; CHECK-NEXT: store float [[ARG]], ptr addrspace(32) [[ARG_SPILL_ADDR]], align 4
+; CHECK-NEXT: [[RCR_SPILL_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP0]], i32 0, i32 0
+; CHECK-NEXT: store i32 [[RCR]], ptr addrspace(32) [[RCR_SPILL_ADDR]], align 4
+; CHECK-NEXT: [[T0:%.*]] = fadd float [[ARG]], 1.000000e+00
+; CHECK-NEXT: [[CR:%.*]] = call i32 @lgc.cps.as.continuation.reference(ptr @callee)
+; CHECK-NEXT: [[COND:%.*]] = fcmp olt float [[T0]], 1.000000e+00
+; CHECK-NEXT: [[DATA:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP0]], i32 0, i32 2
+; CHECK-NEXT: [[VAL_I:%.*]] = call i32 @getVal32()
+; CHECK-NEXT: store i32 [[VAL_I]], ptr addrspace(32) [[DATA]], align 2
+; CHECK-NEXT: [[VAL_I1:%.*]] = call i32 @getVal32()
+; CHECK-NEXT: [[ADDR_I:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 4
+; CHECK-NEXT: store i32 [[VAL_I1]], ptr addrspace(32) [[ADDR_I]], align 2
+; CHECK-NEXT: [[VAL_I2:%.*]] = call i32 @getVal32()
+; CHECK-NEXT: [[ADDR_I3:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 4
+; CHECK-NEXT: store i32 [[VAL_I2]], ptr addrspace(32) [[ADDR_I3]], align 2
+; CHECK-NEXT: [[VAL_I4:%.*]] = call i32 @getVal32()
+; CHECK-NEXT: [[ADDR_I5:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 10
+; CHECK-NEXT: store i32 [[VAL_I4]], ptr addrspace(32) [[ADDR_I5]], align 2
+; CHECK-NEXT: [[VAL_I6:%.*]] = call i32 @getVal32()
+; CHECK-NEXT: [[ADDR_I7:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 12
+; CHECK-NEXT: store i32 [[VAL_I6]], ptr addrspace(32) [[ADDR_I7]], align 2
+; CHECK-NEXT: [[VAL_I8:%.*]] = call i32 @getVal32()
+; CHECK-NEXT: [[ADDR_I9:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 16
+; CHECK-NEXT: store i32 [[VAL_I8]], ptr addrspace(32) [[ADDR_I9]], align 2
+; CHECK-NEXT: [[VAL_I10:%.*]] = call i32 @getVal32()
+; CHECK-NEXT: [[ADDR_I11:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 18
+; CHECK-NEXT: store i32 [[VAL_I10]], ptr addrspace(32) [[ADDR_I11]], align 2
+; CHECK-NEXT: [[VAL_I12:%.*]] = call i32 @getVal32()
+; CHECK-NEXT: [[ADDR_I13:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 24
+; CHECK-NEXT: store i32 [[VAL_I12]], ptr addrspace(32) [[ADDR_I13]], align 2
+; CHECK-NEXT: [[VAL_I14:%.*]] = call i8 @getVal8()
+; CHECK-NEXT: [[ADDR_I15:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 25
+; CHECK-NEXT: store i8 [[VAL_I14]], ptr addrspace(32) [[ADDR_I15]], align 1
+; CHECK-NEXT: [[VAL_I16:%.*]] = call i64 @getVal64()
+; CHECK-NEXT: [[ADDR_I17:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 28
+; CHECK-NEXT: store i64 [[VAL_I16]], ptr addrspace(32) [[ADDR_I17]], align 4
+; CHECK-NEXT: [[VAL_I18:%.*]] = call i32 @getVal32()
+; CHECK-NEXT: [[ADDR_I19:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 36
+; CHECK-NEXT: store i32 [[VAL_I18]], ptr addrspace(32) [[ADDR_I19]], align 2
+; CHECK-NEXT: [[ADDR_I20:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 40
+; CHECK-NEXT: [[VAL_RELOAD_I:%.*]] = load i32, ptr addrspace(32) [[ADDR_I20]], align 4
+; CHECK-NEXT: call void @useVal32(i32 [[VAL_RELOAD_I]])
+; CHECK-NEXT: [[VAL_I21:%.*]] = call i32 @getVal32()
+; CHECK-NEXT: [[ADDR_I22:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 44
+; CHECK-NEXT: store i32 [[VAL_I21]], ptr addrspace(32) [[ADDR_I22]], align 2
+; CHECK-NEXT: [[VAL_I23:%.*]] = call i32 @getVal32()
+; CHECK-NEXT: [[ADDR_I24:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 48
+; CHECK-NEXT: store i32 [[VAL_I23]], ptr addrspace(32) [[ADDR_I24]], align 2
+; CHECK-NEXT: br i1 [[COND]], label [[BB1:%.*]], label [[BB2:%.*]]
+; CHECK: bb1:
+; CHECK-NEXT: [[TMP1:%.*]] = inttoptr i32 [[CR]] to ptr
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 (...) @lgc.cps.as.continuation.reference(ptr @test.resume.0)
+; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[CR]], i32 2, {} poison, i32 [[TMP2]], float [[ARG]])
+; CHECK-NEXT: unreachable
+; CHECK: bb2:
+; CHECK-NEXT: [[T0_BB2:%.*]] = phi float [ [[T0]], [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[RETURNVALUE:%.*]] = fmul float [[T0_BB2]], [[ARG]]
+; CHECK-NEXT: call void @useVal32(i32 [[VAL_I]])
+; CHECK-NEXT: [[ADDR_I26:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 4
+; CHECK-NEXT: [[VAL_RELOAD_I27:%.*]] = load i32, ptr addrspace(32) [[ADDR_I26]], align 4
+; CHECK-NEXT: call void @useVal32(i32 [[VAL_RELOAD_I27]])
+; CHECK-NEXT: [[ADDR_I28:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 12
+; CHECK-NEXT: [[VAL_RELOAD_I29:%.*]] = load i32, ptr addrspace(32) [[ADDR_I28]], align 4
+; CHECK-NEXT: call void @useVal32(i32 [[VAL_RELOAD_I29]])
+; CHECK-NEXT: [[ADDR_I30:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 16
+; CHECK-NEXT: [[VAL_RELOAD_I31:%.*]] = load i32, ptr addrspace(32) [[ADDR_I30]], align 4
+; CHECK-NEXT: call void @useVal32(i32 [[VAL_RELOAD_I31]])
+; CHECK-NEXT: [[ADDR_I32:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 24
+; CHECK-NEXT: [[VAL_RELOAD_I33:%.*]] = load i32, ptr addrspace(32) [[ADDR_I32]], align 4
+; CHECK-NEXT: call void @useVal32(i32 [[VAL_RELOAD_I33]])
+; CHECK-NEXT: [[ADDR_I34:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 32
+; CHECK-NEXT: [[VAL_RELOAD_I35:%.*]] = load i32, ptr addrspace(32) [[ADDR_I34]], align 4
+; CHECK-NEXT: call void @useVal32(i32 [[VAL_RELOAD_I35]])
+; CHECK-NEXT: [[ADDR_I36:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 36
+; CHECK-NEXT: [[VAL_RELOAD_I37:%.*]] = load float, ptr addrspace(32) [[ADDR_I36]], align 4
+; CHECK-NEXT: call void @useValF32(float [[VAL_RELOAD_I37]])
+; CHECK-NEXT: [[VAL_I38:%.*]] = call i32 @getVal32()
+; CHECK-NEXT: [[ADDR_I39:%.*]] = getelementptr i8, ptr addrspace(32) [[DATA]], i32 40
+; CHECK-NEXT: store i32 [[VAL_I38]], ptr addrspace(32) [[ADDR_I39]], align 2
+; CHECK-NEXT: call void @useVal32(i32 [[VAL_I21]])
+; CHECK-NEXT: call void @useVal32(i32 [[VAL_I23]])
+; CHECK-NEXT: call void @useVal32(i32 [[VAL_I23]])
+; CHECK-NEXT: call void @lgc.cps.free(i32 408)
+; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[RCR]], i32 2, {} poison, i32 poison, float [[RETURNVALUE]])
+; CHECK-NEXT: unreachable
+;
+;
+; CHECK-LABEL: define dso_local void @test.resume.0(
+; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]], float [[TMP3:%.*]]) !lgc.cps [[META0]] !continuation [[META1]] {
+; CHECK-NEXT: entryresume.0:
+; CHECK-NEXT: [[TMP4:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 408)
+; CHECK-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP4]], i32 0, i32 1
+; CHECK-NEXT: [[ARG_RELOAD:%.*]] = load float, ptr addrspace(32) [[ARG_RELOAD_ADDR]], align 4
+; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP4]], i32 0, i32 0
+; CHECK-NEXT: [[RCR_RELOAD:%.*]] = load i32, ptr addrspace(32) [[RCR_RELOAD_ADDR]], align 4
+; CHECK-NEXT: [[RETURNVALUE:%.*]] = fmul float [[TMP3]], [[ARG_RELOAD]]
+; CHECK-NEXT: call void @lgc.cps.free(i32 408)
+; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[RCR_RELOAD]], i32 2, {} poison, i32 poison, float [[RETURNVALUE]])
+; CHECK-NEXT: unreachable
+;
diff --git a/shared/continuations/test/lgccps/entry-point-with-cps.ll b/shared/continuations/test/lgccps/entry-point-with-cps.ll
index a9b678ebb1..afe4541051 100644
--- a/shared/continuations/test/lgccps/entry-point-with-cps.ll
+++ b/shared/continuations/test/lgccps/entry-point-with-cps.ll
@@ -64,7 +64,7 @@ declare i32 @lgc.cps.await.i32(...)
declare [2 x i32] @lgc.cps.await.a2i32(...)
declare void @lgc.cps.jump(...)
; CHECK-LABEL: define spir_func void @raygen(
-; CHECK-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]]) !lgc.shaderstage !0 !lgc.cps !1 !continuation !2 {
+; CHECK-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]]) !lgc.shaderstage [[META0:![0-9]+]] !lgc.cps [[META1:![0-9]+]] !continuation [[META2:![0-9]+]] {
; CHECK-NEXT: AllocaSpillBB:
; CHECK-NEXT: [[PUSHCONST:%.*]] = call ptr addrspace(4) @lgc.user.data(i32 0)
; CHECK-NEXT: [[FN:%.*]] = load ptr, ptr addrspace(4) [[PUSHCONST]], align 8
@@ -81,17 +81,17 @@ declare void @lgc.cps.jump(...)
;
;
; CHECK-LABEL: define dso_local void @raygen.resume.0(
-; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], [2 x i32] [[TMP2:%.*]]) !lgc.shaderstage !0 !lgc.cps !1 !continuation !2 {
+; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]], [2 x i32] [[TMP3:%.*]]) !lgc.shaderstage [[META0]] !lgc.cps [[META1]] !continuation [[META2]] {
; CHECK-NEXT: entryresume.0:
; CHECK-NEXT: [[PUSHCONST3:%.*]] = call ptr addrspace(4) @lgc.user.data(i32 0)
; CHECK-NEXT: [[P162:%.*]] = getelementptr i8, ptr addrspace(4) [[PUSHCONST3]], i32 16
; CHECK-NEXT: [[DST1:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[P162]], align 8
-; CHECK-NEXT: store [2 x i32] [[TMP2]], ptr addrspace(1) [[DST1]], align 4
+; CHECK-NEXT: store [2 x i32] [[TMP3]], ptr addrspace(1) [[DST1]], align 4
; CHECK-NEXT: ret void
;
;
; CHECK-LABEL: define spir_func void @chs(
-; CHECK-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], i32 [[X:%.*]]) !lgc.shaderstage !0 !lgc.cps !3 !continuation !4 {
+; CHECK-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], i32 [[X:%.*]]) !lgc.shaderstage [[META0]] !lgc.cps [[META3:![0-9]+]] !continuation [[META4:![0-9]+]] {
; CHECK-NEXT: AllocaSpillBB:
; CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(32) @lgc.cps.alloc(i32 8)
; CHECK-NEXT: [[RCR_SPILL_ADDR:%.*]] = getelementptr inbounds [[CHS_FRAME:%.*]], ptr addrspace(32) [[TMP0]], i32 0, i32 0
@@ -107,17 +107,18 @@ declare void @lgc.cps.jump(...)
;
;
; CHECK-LABEL: define dso_local void @chs.resume.0(
-; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]]) !lgc.shaderstage !0 !lgc.cps !3 !continuation !4 {
+; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]], i32 [[TMP3:%.*]]) !lgc.shaderstage [[META0]] !lgc.cps [[META3]] !continuation [[META4]] {
; CHECK-NEXT: entryresume.0:
-; CHECK-NEXT: [[TMP3:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 8)
-; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[CHS_FRAME:%.*]], ptr addrspace(32) [[TMP3]], i32 0, i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 8)
+; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[CHS_FRAME:%.*]], ptr addrspace(32) [[TMP4]], i32 0, i32 0
; CHECK-NEXT: [[RCR_RELOAD:%.*]] = load i32, ptr addrspace(32) [[RCR_RELOAD_ADDR]], align 4
; CHECK-NEXT: call void @lgc.cps.free(i32 8)
-; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[RCR_RELOAD]], i32 5, i32 [[TMP2]])
+; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[RCR_RELOAD]], i32 5, i32 [[TMP3]])
; CHECK-NEXT: unreachable
;
;
-; CHECK-LABEL: define dllexport void @lgc.shader.CS.main() !lgc.shaderstage !0 !continuation !5 {
+; CHECK-LABEL: define dllexport void @lgc.shader.CS.main(
+; CHECK-SAME: ) !lgc.shaderstage [[META0]] !continuation [[META5:![0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ID:%.*]] = call <3 x i32> @lgc.shader.input.LocalInvocationId(i32 0)
; CHECK-NEXT: [[ID0:%.*]] = extractelement <3 x i32> [[ID]], i32 0
@@ -135,7 +136,7 @@ declare void @lgc.cps.jump(...)
;
;
; LOWER-AWAIT-LABEL: define spir_func { ptr, ptr } @raygen(
-; LOWER-AWAIT-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], ptr [[TMP0:%.*]]) !lgc.shaderstage !0 !lgc.cps !1 !continuation !2 {
+; LOWER-AWAIT-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], ptr [[TMP0:%.*]]) !lgc.shaderstage [[META0:![0-9]+]] !lgc.cps [[META1:![0-9]+]] !continuation [[META2:![0-9]+]] {
; LOWER-AWAIT-NEXT: [[TMP2:%.*]] = call token @llvm.coro.id.retcon(i32 8, i32 4, ptr [[TMP0]], ptr @continuation.prototype.raygen, ptr @continuation.malloc, ptr @continuation.free)
; LOWER-AWAIT-NEXT: [[TMP3:%.*]] = call ptr @llvm.coro.begin(token [[TMP2]], ptr null)
; LOWER-AWAIT-NEXT: [[PUSHCONST:%.*]] = call ptr addrspace(4) @lgc.user.data(i32 0)
@@ -156,7 +157,7 @@ declare void @lgc.cps.jump(...)
;
;
; LOWER-AWAIT-LABEL: define spir_func { ptr, ptr } @chs(
-; LOWER-AWAIT-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], i32 [[X:%.*]], ptr [[TMP0:%.*]]) !lgc.shaderstage !0 !lgc.cps !3 !continuation !4 {
+; LOWER-AWAIT-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], i32 [[X:%.*]], ptr [[TMP0:%.*]]) !lgc.shaderstage [[META0]] !lgc.cps [[META3:![0-9]+]] !continuation [[META4:![0-9]+]] {
; LOWER-AWAIT-NEXT: [[TMP2:%.*]] = call token @llvm.coro.id.retcon(i32 8, i32 4, ptr [[TMP0]], ptr @continuation.prototype.chs, ptr @continuation.malloc, ptr @continuation.free)
; LOWER-AWAIT-NEXT: [[TMP3:%.*]] = call ptr @llvm.coro.begin(token [[TMP2]], ptr null)
; LOWER-AWAIT-NEXT: [[PUSHCONST:%.*]] = call ptr addrspace(4) @lgc.user.data(i32 24)
@@ -172,7 +173,7 @@ declare void @lgc.cps.jump(...)
;
;
; LOWER-AWAIT-LABEL: define dllexport { ptr, ptr } @lgc.shader.CS.main(
-; LOWER-AWAIT-SAME: ptr [[TMP0:%.*]]) !lgc.shaderstage !0 !continuation !5 {
+; LOWER-AWAIT-SAME: ptr [[TMP0:%.*]]) !lgc.shaderstage [[META0]] !continuation [[META5:![0-9]+]] {
; LOWER-AWAIT-NEXT: entry:
; LOWER-AWAIT-NEXT: [[TMP1:%.*]] = call token @llvm.coro.id.retcon(i32 8, i32 4, ptr [[TMP0]], ptr @continuation.prototype.lgc.shader.CS.main, ptr @continuation.malloc, ptr @continuation.free)
; LOWER-AWAIT-NEXT: [[TMP2:%.*]] = call ptr @llvm.coro.begin(token [[TMP1]], ptr null)
diff --git a/shared/continuations/test/lgccps/multiple-await.ll b/shared/continuations/test/lgccps/multiple-await.ll
index 8e51ba6344..2667866e01 100644
--- a/shared/continuations/test/lgccps/multiple-await.ll
+++ b/shared/continuations/test/lgccps/multiple-await.ll
@@ -22,7 +22,7 @@ declare i32 @lgc.cps.as.continuation.reference(...) memory(none)
declare float @lgc.cps.await.f32(...)
declare void @lgc.cps.jump(...)
; CHECK-LABEL: define void @test(
-; CHECK-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], float [[ARG:%.*]], float [[ARG2:%.*]]) !lgc.cps !0 !continuation !1 {
+; CHECK-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], float [[ARG:%.*]], float [[ARG2:%.*]]) !lgc.cps [[META0:![0-9]+]] !continuation [[META1:![0-9]+]] {
; CHECK-NEXT: AllocaSpillBB:
; CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(32) @lgc.cps.alloc(i32 12)
; CHECK-NEXT: [[ARG2_SPILL_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP0]], i32 0, i32 2
@@ -40,28 +40,28 @@ declare void @lgc.cps.jump(...)
;
;
; CHECK-LABEL: define dso_local void @test.resume.0(
-; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], float [[TMP2:%.*]]) !lgc.cps !0 !continuation !1 {
+; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]], float [[TMP3:%.*]]) !lgc.cps [[META0]] !continuation [[META1]] {
; CHECK-NEXT: entryresume.0:
-; CHECK-NEXT: [[TMP3:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 12)
-; CHECK-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP3]], i32 0, i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 12)
+; CHECK-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP4]], i32 0, i32 1
; CHECK-NEXT: [[ARG_RELOAD:%.*]] = load float, ptr addrspace(32) [[ARG_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[T2:%.*]] = fmul float [[TMP2]], [[ARG_RELOAD]]
+; CHECK-NEXT: [[T2:%.*]] = fmul float [[TMP3]], [[ARG_RELOAD]]
; CHECK-NEXT: [[CR2:%.*]] = call i32 @lgc.cps.as.continuation.reference(ptr @callee2)
-; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i32 [[CR2]] to ptr
-; CHECK-NEXT: [[TMP5:%.*]] = call i32 (...) @lgc.cps.as.continuation.reference(ptr @test.resume.1)
-; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[CR2]], i32 2, {} poison, i32 [[TMP5]], float [[T2]])
+; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i32 [[CR2]] to ptr
+; CHECK-NEXT: [[TMP6:%.*]] = call i32 (...) @lgc.cps.as.continuation.reference(ptr @test.resume.1)
+; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[CR2]], i32 2, {} poison, i32 [[TMP6]], float [[T2]])
; CHECK-NEXT: unreachable
;
;
; CHECK-LABEL: define dso_local void @test.resume.1(
-; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], float [[TMP2:%.*]]) !lgc.cps !0 !continuation !1 {
+; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]], float [[TMP3:%.*]]) !lgc.cps [[META0]] !continuation [[META1]] {
; CHECK-NEXT: entryresume.1:
-; CHECK-NEXT: [[TMP3:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 12)
-; CHECK-NEXT: [[ARG2_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP3]], i32 0, i32 2
+; CHECK-NEXT: [[TMP4:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 12)
+; CHECK-NEXT: [[ARG2_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP4]], i32 0, i32 2
; CHECK-NEXT: [[ARG2_RELOAD:%.*]] = load float, ptr addrspace(32) [[ARG2_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP3]], i32 0, i32 0
+; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP4]], i32 0, i32 0
; CHECK-NEXT: [[RCR_RELOAD:%.*]] = load i32, ptr addrspace(32) [[RCR_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[RETURNVALUE:%.*]] = fadd float [[TMP2]], [[ARG2_RELOAD]]
+; CHECK-NEXT: [[RETURNVALUE:%.*]] = fadd float [[TMP3]], [[ARG2_RELOAD]]
; CHECK-NEXT: call void @lgc.cps.free(i32 12)
; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[RCR_RELOAD]], i32 2, {} poison, i32 poison, float [[RETURNVALUE]])
; CHECK-NEXT: unreachable
diff --git a/shared/continuations/test/lgccps/simple-await-more-state.ll b/shared/continuations/test/lgccps/simple-await-more-state.ll
index a5a11a395c..112f7637e1 100644
--- a/shared/continuations/test/lgccps/simple-await-more-state.ll
+++ b/shared/continuations/test/lgccps/simple-await-more-state.ll
@@ -19,7 +19,7 @@ declare i32 @lgc.cps.as.continuation.reference(...) memory(none)
declare float @lgc.cps.await.f32(...)
declare void @lgc.cps.jump(...)
; CHECK-LABEL: define void @test(
-; CHECK-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], float [[ARG:%.*]], float [[ARG2:%.*]]) !lgc.cps !0 !continuation !1 {
+; CHECK-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], float [[ARG:%.*]], float [[ARG2:%.*]]) !lgc.cps [[META0:![0-9]+]] !continuation [[META1:![0-9]+]] {
; CHECK-NEXT: AllocaSpillBB:
; CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(32) @lgc.cps.alloc(i32 12)
; CHECK-NEXT: [[ARG2_SPILL_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP0]], i32 0, i32 2
@@ -37,16 +37,16 @@ declare void @lgc.cps.jump(...)
;
;
; CHECK-LABEL: define dso_local void @test.resume.0(
-; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], float [[TMP2:%.*]]) !lgc.cps !0 !continuation !1 {
+; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]], float [[TMP3:%.*]]) !lgc.cps [[META0]] !continuation [[META1]] {
; CHECK-NEXT: entryresume.0:
-; CHECK-NEXT: [[TMP3:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 12)
-; CHECK-NEXT: [[ARG2_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP3]], i32 0, i32 2
+; CHECK-NEXT: [[TMP4:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 12)
+; CHECK-NEXT: [[ARG2_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP4]], i32 0, i32 2
; CHECK-NEXT: [[ARG2_RELOAD:%.*]] = load float, ptr addrspace(32) [[ARG2_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP3]], i32 0, i32 1
+; CHECK-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP4]], i32 0, i32 1
; CHECK-NEXT: [[ARG_RELOAD:%.*]] = load float, ptr addrspace(32) [[ARG_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP3]], i32 0, i32 0
+; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP4]], i32 0, i32 0
; CHECK-NEXT: [[RCR_RELOAD:%.*]] = load i32, ptr addrspace(32) [[RCR_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[T2:%.*]] = fmul float [[TMP2]], [[ARG_RELOAD]]
+; CHECK-NEXT: [[T2:%.*]] = fmul float [[TMP3]], [[ARG_RELOAD]]
; CHECK-NEXT: [[RETURNVALUE:%.*]] = fadd float [[T2]], [[ARG2_RELOAD]]
; CHECK-NEXT: call void @lgc.cps.free(i32 12)
; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[RCR_RELOAD]], i32 2, {} poison, i32 poison, float [[RETURNVALUE]])
diff --git a/shared/continuations/test/lgccps/simple-await.ll b/shared/continuations/test/lgccps/simple-await.ll
index c6022cf9a3..5ab088a2ac 100644
--- a/shared/continuations/test/lgccps/simple-await.ll
+++ b/shared/continuations/test/lgccps/simple-await.ll
@@ -18,7 +18,7 @@ declare i32 @lgc.cps.as.continuation.reference(...) memory(none)
declare float @lgc.cps.await.f32(...)
declare void @lgc.cps.jump(...)
; CHECK-LABEL: define void @test(
-; CHECK-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], float [[ARG:%.*]]) !lgc.cps !0 !continuation !1 {
+; CHECK-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], float [[ARG:%.*]]) !lgc.cps [[META0:![0-9]+]] !continuation [[META1:![0-9]+]] {
; CHECK-NEXT: AllocaSpillBB:
; CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(32) @lgc.cps.alloc(i32 8)
; CHECK-NEXT: [[ARG_SPILL_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP0]], i32 0, i32 1
@@ -34,21 +34,21 @@ declare void @lgc.cps.jump(...)
;
;
; CHECK-LABEL: define dso_local void @test.resume.0(
-; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], float [[TMP2:%.*]]) !lgc.cps !0 !continuation !1 {
+; CHECK-SAME: {} [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]], float [[TMP3:%.*]]) !lgc.cps [[META0]] !continuation [[META1]] {
; CHECK-NEXT: entryresume.0:
-; CHECK-NEXT: [[TMP3:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 8)
-; CHECK-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP3]], i32 0, i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = call ptr addrspace(32) @lgc.cps.peek(i32 8)
+; CHECK-NEXT: [[ARG_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME:%.*]], ptr addrspace(32) [[TMP4]], i32 0, i32 1
; CHECK-NEXT: [[ARG_RELOAD:%.*]] = load float, ptr addrspace(32) [[ARG_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP3]], i32 0, i32 0
+; CHECK-NEXT: [[RCR_RELOAD_ADDR:%.*]] = getelementptr inbounds [[TEST_FRAME]], ptr addrspace(32) [[TMP4]], i32 0, i32 0
; CHECK-NEXT: [[RCR_RELOAD:%.*]] = load i32, ptr addrspace(32) [[RCR_RELOAD_ADDR]], align 4
-; CHECK-NEXT: [[RETURNVALUE:%.*]] = fmul float [[TMP2]], [[ARG_RELOAD]]
+; CHECK-NEXT: [[RETURNVALUE:%.*]] = fmul float [[TMP3]], [[ARG_RELOAD]]
; CHECK-NEXT: call void @lgc.cps.free(i32 8)
; CHECK-NEXT: call void (...) @lgc.cps.jump(i32 [[RCR_RELOAD]], i32 2, {} poison, i32 poison, float [[RETURNVALUE]])
; CHECK-NEXT: unreachable
;
;
; LOWER-AWAIT-LABEL: define { ptr, ptr } @test(
-; LOWER-AWAIT-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], float [[ARG:%.*]], ptr [[TMP0:%.*]]) !lgc.cps !0 !continuation !1 {
+; LOWER-AWAIT-SAME: {} [[STATE:%.*]], i32 [[RCR:%.*]], float [[ARG:%.*]], ptr [[TMP0:%.*]]) !lgc.cps [[META0:![0-9]+]] !continuation [[META1:![0-9]+]] {
; LOWER-AWAIT-NEXT: [[TMP2:%.*]] = call token @llvm.coro.id.retcon(i32 8, i32 4, ptr [[TMP0]], ptr @continuation.prototype.test, ptr @continuation.malloc, ptr @continuation.free)
; LOWER-AWAIT-NEXT: [[TMP3:%.*]] = call ptr @llvm.coro.begin(token [[TMP2]], ptr null)
; LOWER-AWAIT-NEXT: [[T0:%.*]] = fadd float [[ARG]], 1.000000e+00
diff --git a/shared/continuations/unittests/RemainingArgumentDwordTests.cpp b/shared/continuations/unittests/RemainingArgumentDwordTests.cpp
index 6d88da0838..0368540d21 100644
--- a/shared/continuations/unittests/RemainingArgumentDwordTests.cpp
+++ b/shared/continuations/unittests/RemainingArgumentDwordTests.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
- *deal in the Software without restriction, including without limitation the
- *rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- *sell copies of the Software, and to permit persons to whom the Software is
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
@@ -18,8 +18,8 @@
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- *IN THE SOFTWARE.
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt
index 991aea1fb0..aff47981ef 100644
--- a/test/CMakeLists.txt
+++ b/test/CMakeLists.txt
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/test/run_amber_test.py b/test/run_amber_test.py
index e99536991c..4fb1dabbd5 100755
--- a/test/run_amber_test.py
+++ b/test/run_amber_test.py
@@ -2,13 +2,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -18,9 +18,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/tool/dumper/CMakeLists.txt b/tool/dumper/CMakeLists.txt
index 364a2fa18d..5cd8b18acf 100644
--- a/tool/dumper/CMakeLists.txt
+++ b/tool/dumper/CMakeLists.txt
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/tool/dumper/vkgcPipelineDumper.cpp b/tool/dumper/vkgcPipelineDumper.cpp
index bb928c58c5..32d7c8ea18 100644
--- a/tool/dumper/vkgcPipelineDumper.cpp
+++ b/tool/dumper/vkgcPipelineDumper.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -31,6 +31,7 @@
#include "vkgcPipelineDumper.h"
#include "vkgcElfReader.h"
#include "vkgcUtil.h"
+#include "llvm/BinaryFormat/MsgPackDocument.h"
#include "llvm/Support/Mutex.h"
#include "llvm/Support/raw_ostream.h"
#include <fstream>
@@ -332,6 +333,15 @@ void VKAPI_CALL IPipelineDumper::DumpRayTracingPipelineMetadata(void *dumpFile,
PipelineDumper::dumpRayTracingPipelineMetadata(reinterpret_cast<PipelineDumpFile *>(dumpFile), pipelineMeta);
}
+// =====================================================================================================================
+/// Dumps ray tracing library summary.
+///
+/// @param [in] dumpFile The handle of pipeline dump file
+/// @param [in] librarySummary Ray tracing library summary binary
+void VKAPI_CALL IPipelineDumper::DumpRayTracingLibrarySummary(void *dumpFile, BinaryData *librarySummary) {
+ PipelineDumper::dumpRayTracingLibrarySummary(reinterpret_cast<PipelineDumpFile *>(dumpFile), librarySummary);
+}
+
// =====================================================================================================================
// Gets the file name of SPIR-V binary according the specified shader hash.
//
@@ -371,8 +381,10 @@ std::string PipelineDumper::getPipelineInfoFileName(PipelineBuildInfo pipelineIn
fileNamePrefix = "PipelineLibGs";
else if (pipelineInfo.pGraphicsInfo->mesh.pModuleData)
fileNamePrefix = "PipelineLibMesh";
- else
+ else if (pipelineInfo.pGraphicsInfo->fs.pModuleData)
fileNamePrefix = "PipelineLibFs";
+ else
+ fileNamePrefix = "PipelineLibCes";
} else if (pipelineInfo.pGraphicsInfo->tes.pModuleData && pipelineInfo.pGraphicsInfo->gs.pModuleData)
fileNamePrefix = "PipelineGsTess";
else if (pipelineInfo.pGraphicsInfo->gs.pModuleData)
@@ -644,6 +656,7 @@ void PipelineDumper::dumpPipelineShaderInfo(const PipelineShaderInfo *shaderInfo
dumpFile << "options.disableLicmThreshold = " << shaderInfo->options.disableLicmThreshold << "\n";
dumpFile << "options.unrollHintThreshold = " << shaderInfo->options.unrollHintThreshold << "\n";
dumpFile << "options.dontUnrollHintThreshold = " << shaderInfo->options.dontUnrollHintThreshold << "\n";
+ dumpFile << "options.noContractOpDot = " << shaderInfo->options.noContractOpDot << "\n";
dumpFile << "options.fastMathFlags = " << shaderInfo->options.fastMathFlags << "\n";
dumpFile << "options.disableFastMathFlags = " << shaderInfo->options.disableFastMathFlags << "\n";
dumpFile << "options.ldsSpillLimitDwords = " << shaderInfo->options.ldsSpillLimitDwords << "\n";
@@ -656,6 +669,7 @@ void PipelineDumper::dumpPipelineShaderInfo(const PipelineShaderInfo *shaderInfo
dumpFile << "options.workaroundStorageImageFormats = " << shaderInfo->options.workaroundStorageImageFormats << "\n";
dumpFile << "options.workaroundInitializeOutputsToZero = " << shaderInfo->options.workaroundInitializeOutputsToZero << "\n";
dumpFile << "options.disableFMA = " << shaderInfo->options.disableFMA << "\n";
+ dumpFile << "options.constantBufferBindingOffset = " << shaderInfo->options.constantBufferBindingOffset << "\n";
dumpFile << "options.backwardPropagateNoContract = " << shaderInfo->options.backwardPropagateNoContract << "\n";
dumpFile << "options.forwardPropagateNoContract = " << shaderInfo->options.forwardPropagateNoContract << "\n";
dumpFile << "\n";
@@ -860,9 +874,12 @@ void PipelineDumper::dumpPipelineOptions(const PipelineOptions *options, std::os
dumpFile << "options.disableSampleMask = " << options->disableSampleMask << "\n";
dumpFile << "options.buildResourcesDataForShaderModule = " << options->buildResourcesDataForShaderModule << "\n";
dumpFile << "options.disableTruncCoordForGather = " << options->disableTruncCoordForGather << "\n";
+ dumpFile << "options.enableCombinedTexture = " << options->enableCombinedTexture << "\n";
dumpFile << "options.vertex64BitsAttribSingleLoc = " << options->vertex64BitsAttribSingleLoc << "\n";
- dumpFile << "options.enablePrimGeneratedQuery = " << options->enablePrimGeneratedQuery << "\n";
dumpFile << "options.enableFragColor = " << options->enableFragColor << "\n";
+ dumpFile << "options.disableBaseVertex = " << options->disableBaseVertex << "\n";
+ dumpFile << "options.enablePrimGeneratedQuery = " << options->enablePrimGeneratedQuery << "\n";
+ dumpFile << "options.disablePerCompFetch = " << options->disablePerCompFetch << "\n";
}
// =====================================================================================================================
@@ -954,6 +971,7 @@ void PipelineDumper::dumpGraphicsStateInfo(const GraphicsPipelineBuildInfo *pipe
dumpFile << "enableEarlyCompile = " << pipelineInfo->enableEarlyCompile << "\n";
dumpFile << "enableColorExportShader = " << pipelineInfo->enableColorExportShader << "\n";
dumpFile << "useSoftwareVertexBufferDescriptors = " << pipelineInfo->useSoftwareVertexBufferDescriptors << "\n";
+ dumpFile << "vbAddressLowBitsKnown = " << pipelineInfo->vbAddressLowBitsKnown << "\n";
dumpPipelineOptions(&pipelineInfo->options, dumpFile);
#if LLPC_CLIENT_INTERFACE_MAJOR_VERSION < 62
@@ -988,6 +1006,9 @@ void PipelineDumper::dumpGraphicsStateInfo(const GraphicsPipelineBuildInfo *pipe
dumpFile << "attribute[" << i << "].binding = " << attrib->binding << "\n";
dumpFile << "attribute[" << i << "].format = " << attrib->format << "\n";
dumpFile << "attribute[" << i << "].offset = " << attrib->offset << "\n";
+ dumpFile << "attribute[" << i
+ << "].vbAddressLowBits = " << static_cast<unsigned>((pipelineInfo->vbAddressLowBits[attrib->binding]))
+ << "\n";
}
auto divisorState = findVkStructInChain<VkPipelineVertexInputDivisorStateCreateInfoEXT>(
@@ -1086,6 +1107,20 @@ void PipelineDumper::dumpRayTracingPipelineInfo(std::ostream *dumpFile, const ch
dumpPipelineShaderInfo(shaderInfo, *dumpFile);
}
+ for (unsigned i = 0; i < pipelineInfo->libraryCount; ++i) {
+ *dumpFile << "[RayTracingLibrarySummary]\n";
+
+ const BinaryData &summary = pipelineInfo->pLibrarySummaries[i];
+ msgpack::Document doc;
+ doc.readFromBlob(StringRef(static_cast<const char *>(summary.pCode), summary.codeSize), false);
+
+ std::string yaml;
+ raw_string_ostream outs(yaml);
+ doc.toYAML(outs);
+ *dumpFile << yaml;
+ *dumpFile << "\n\n";
+ }
+
dumpResourceMappingInfo(&pipelineInfo->resourceMapping, *dumpFile);
dumpRayTracingStateInfo(pipelineInfo, dumpDir, *dumpFile);
@@ -1131,6 +1166,7 @@ void PipelineDumper::dumpRayTracingStateInfo(const RayTracingPipelineBuildInfo *
dumpFile << "maxRecursionDepth = " << pipelineInfo->maxRecursionDepth << "\n";
dumpFile << "indirectStageMask = " << pipelineInfo->indirectStageMask << "\n";
+ dumpFile << "libraryMode = " << static_cast<unsigned>(pipelineInfo->libraryMode) << "\n";
dumpFile << "mode = " << static_cast<unsigned>(pipelineInfo->mode) << "\n";
dumpRayTracingRtState(&pipelineInfo->rtState, dumpDir, dumpFile);
dumpFile << "payloadSizeMaxInLib = " << pipelineInfo->payloadSizeMaxInLib << "\n";
@@ -1245,6 +1281,33 @@ void PipelineDumper::dumpRayTracingPipelineMetadata(PipelineDumpFile *dumpFile,
}
}
+// =====================================================================================================================
+/// Dumps ray tracing library summary.
+///
+/// @param [in] dumpFile The pointer of pipeline dump file
+/// @param [in] librarySummary Ray tracing library summary
+void PipelineDumper::dumpRayTracingLibrarySummary(PipelineDumpFile *dumpFile, const BinaryData *librarySummary) {
+ if (!dumpFile)
+ return;
+
+ if (!librarySummary->pCode || librarySummary->codeSize == 0)
+ return;
+
+ // Replace the suffix (which in practice is always going to be .pipe) by .summary
+ auto extPos = dumpFile->binaryFileName.rfind('.');
+ assert(extPos != std::string::npos);
+ std::string metaFileName = dumpFile->binaryFileName.substr(0, extPos) + ".summary";
+
+ // Write the summary as human-readable YAML if possible, using the YAML support in LLVM.
+ std::error_code ec;
+ raw_fd_ostream outfile(metaFileName, ec);
+ if (!ec) {
+ msgpack::Document doc;
+ doc.readFromBlob(StringRef(static_cast<const char *>(librarySummary->pCode), librarySummary->codeSize), false);
+ doc.toYAML(outfile);
+ }
+}
+
// =====================================================================================================================
// Update hash code for the pipeline rtstate
//
@@ -1364,13 +1427,16 @@ MetroHash::Hash PipelineDumper::generateHashForGraphicsPipeline(const GraphicsPi
// Relocatable shaders force an unlinked compilation.
hasher.Update(pipeline->unlinked);
hasher.Update(pipeline->enableEarlyCompile);
- if (unlinkedShaderType == UnlinkedStageFragment)
+ if (unlinkedShaderType == UnlinkedStageFragment && isCacheHash)
hasher.Update(pipeline->enableColorExportShader);
updateHashForPipelineOptions(&pipeline->options, &hasher, isCacheHash, unlinkedShaderType);
if (unlinkedShaderType != UnlinkedStageFragment) {
- if (!pipeline->enableUberFetchShader)
+ if (!pipeline->enableUberFetchShader) {
updateHashForVertexInputState(pipeline->pVertexInput, pipeline->dynamicVertexStride, &hasher);
+ hasher.Update(pipeline->vbAddressLowBits);
+ }
+ hasher.Update(pipeline->vbAddressLowBitsKnown);
updateHashForNonFragmentState(pipeline, isCacheHash, &hasher);
}
@@ -1452,6 +1518,14 @@ MetroHash::Hash PipelineDumper::generateHashForRayTracingPipeline(const RayTraci
hasher.Update(pipeline->mode);
updateHashForRtState(&pipeline->rtState, &hasher, isCacheHash);
+ hasher.Update(pipeline->libraryMode);
+ hasher.Update(pipeline->libraryCount);
+ for (unsigned i = 0; i < pipeline->libraryCount; ++i) {
+ hasher.Update(pipeline->pLibrarySummaries->codeSize);
+ hasher.Update(static_cast<const uint8_t *>(pipeline->pLibrarySummaries->pCode),
+ pipeline->pLibrarySummaries->codeSize);
+ }
+
hasher.Update(pipeline->payloadSizeMaxInLib);
hasher.Update(pipeline->attributeSizeMaxInLib);
@@ -1538,6 +1612,9 @@ void PipelineDumper::updateHashForNonFragmentState(const GraphicsPipelineBuildIn
hasher->Update(pipeline->dynamicVertexStride);
hasher->Update(pipeline->enableUberFetchShader);
+ if (pipeline->enableUberFetchShader) {
+ hasher->Update(pipeline->options.disablePerCompFetch);
+ }
bool passthroughMode = !nggState->enableBackfaceCulling && !nggState->enableFrustumCulling &&
!nggState->enableBoxFilterCulling && !nggState->enableSphereCulling &&
@@ -1575,6 +1652,7 @@ void PipelineDumper::updateHashForNonFragmentState(const GraphicsPipelineBuildIn
hasher->Update(pipeline->apiXfbOutData.forceEnablePrimStats);
#endif
hasher->Update(pipeline->useSoftwareVertexBufferDescriptors);
+ hasher->Update(pipeline->vbAddressLowBitsKnown);
}
// =====================================================================================================================
@@ -1659,9 +1737,13 @@ void PipelineDumper::updateHashForPipelineOptions(const PipelineOptions *options
hasher->Update(options->internalRtShaders);
hasher->Update(options->forceNonUniformResourceIndexStageMask);
hasher->Update(options->replaceSetWithResourceType);
+ hasher->Update(options->buildResourcesDataForShaderModule);
hasher->Update(options->disableTruncCoordForGather);
- hasher->Update(options->enablePrimGeneratedQuery);
+ hasher->Update(options->enableCombinedTexture);
+ hasher->Update(options->vertex64BitsAttribSingleLoc);
hasher->Update(options->enableFragColor);
+ hasher->Update(options->disableBaseVertex);
+ hasher->Update(options->enablePrimGeneratedQuery);
}
// =====================================================================================================================
@@ -1730,6 +1812,7 @@ void PipelineDumper::updateHashForPipelineShaderInfo(ShaderStage stage, const Pi
hasher->Update(options.disableLicmThreshold);
hasher->Update(options.unrollHintThreshold);
hasher->Update(options.dontUnrollHintThreshold);
+ hasher->Update(options.noContractOpDot);
hasher->Update(options.fastMathFlags);
hasher->Update(options.disableFastMathFlags);
hasher->Update(options.ldsSpillLimitDwords);
@@ -1742,6 +1825,7 @@ void PipelineDumper::updateHashForPipelineShaderInfo(ShaderStage stage, const Pi
hasher->Update(options.workaroundStorageImageFormats);
hasher->Update(options.workaroundInitializeOutputsToZero);
hasher->Update(options.disableFMA);
+ hasher->Update(options.constantBufferBindingOffset);
hasher->Update(options.backwardPropagateNoContract);
hasher->Update(options.forwardPropagateNoContract);
}
@@ -2584,6 +2668,26 @@ std::ostream &operator<<(std::ostream &out, VkFormat format) {
CASE_ENUM_TO_STRING(VK_FORMAT_A4B4G4R4_UNORM_PACK16_EXT)
CASE_ENUM_TO_STRING(VK_FORMAT_A1B5G5R5_UNORM_PACK16)
CASE_ENUM_TO_STRING(VK_FORMAT_A8_UNORM_KHR)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32_UNORM)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32_SNORM)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32G32_UNORM)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32G32_SNORM)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32G32B32_UNORM)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32G32B32_SNORM)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32G32B32A32_UNORM)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32G32B32A32_SNORM)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32_FIXED)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32G32_FIXED)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32G32B32_FIXED)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32G32B32A32_FIXED)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32_USCALED)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32_SSCALED)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32G32_USCALED)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32G32_SSCALED)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32G32B32_USCALED)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32G32B32_SSCALED)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32G32B32A32_USCALED)
+ CASE_ENUM_TO_STRING(VK_FORMAT_EXT_R32G32B32A32_SSCALED)
break;
default:
diff --git a/tool/dumper/vkgcPipelineDumper.h b/tool/dumper/vkgcPipelineDumper.h
index 9bc3f0ef1f..ee69c485e9 100644
--- a/tool/dumper/vkgcPipelineDumper.h
+++ b/tool/dumper/vkgcPipelineDumper.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -74,6 +74,7 @@ class PipelineDumper {
bool isCacheHash);
static void dumpRayTracingRtState(const RtState *rtState, const char *dumpDir, std::ostream &dumpFile);
static void dumpRayTracingPipelineMetadata(PipelineDumpFile *binaryFile, const BinaryData *pipelineBin);
+ static void dumpRayTracingLibrarySummary(PipelineDumpFile *binaryFile, const BinaryData *librarySummary);
static std::string getPipelineInfoFileName(PipelineBuildInfo pipelineInfo, const uint64_t hashCode64);
diff --git a/tool/dumper/vkgcPipelineDumperRegs.cpp b/tool/dumper/vkgcPipelineDumperRegs.cpp
index 2ca94f0bb7..96416d38b9 100644
--- a/tool/dumper/vkgcPipelineDumperRegs.cpp
+++ b/tool/dumper/vkgcPipelineDumperRegs.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/tool/vfx/CMakeLists.txt b/tool/vfx/CMakeLists.txt
index be89a976d1..66b73686e5 100644
--- a/tool/vfx/CMakeLists.txt
+++ b/tool/vfx/CMakeLists.txt
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
@@ -47,5 +47,12 @@ target_include_directories(vfx PUBLIC ${PROJECT_SOURCE_DIR})
target_link_libraries(vfx PRIVATE spvgen_static vkgc_headers khronos_vulkan_interface khronos_spirv_interface)
+if(ICD_BUILD_LLPC)
+ target_compile_definitions(vfx PRIVATE ICD_BUILD_LLPC)
+ llvm_map_components_to_libnames(vfx_llvm_libs BinaryFormat Support)
+ target_link_libraries(vfx PRIVATE ${vfx_llvm_libs})
+ target_include_directories(vfx PRIVATE ${LLVM_INCLUDE_DIRS})
+endif()
+
include(../../cmake/CompilerFlags.cmake)
set_compiler_options(vfx ${VFX_ENABLE_WERROR})
diff --git a/tool/vfx/vfx.h b/tool/vfx/vfx.h
index bcdfbe3030..c83c9dff6f 100644
--- a/tool/vfx/vfx.h
+++ b/tool/vfx/vfx.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -536,6 +536,7 @@ struct GraphicsPipelineState {
bool enableEarlyCompile; // Enable early compile
bool enableColorExportShader; // Enable color export shader
bool useSoftwareVertexBufferDescriptors; // Use software vertex buffer descriptors
+ bool vbAddressLowBitsKnown; // Vertex buffer address low bits is known
float tessLevelInner[2];
float tessLevelOuter[4];
diff --git a/tool/vfx/vfxEnumsConverter.cpp b/tool/vfx/vfxEnumsConverter.cpp
index 314f0c6dec..9343c352aa 100644
--- a/tool/vfx/vfxEnumsConverter.cpp
+++ b/tool/vfx/vfxEnumsConverter.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/tool/vfx/vfxEnumsConverter.h b/tool/vfx/vfxEnumsConverter.h
index f67eaf050f..a91a5323b9 100644
--- a/tool/vfx/vfxEnumsConverter.h
+++ b/tool/vfx/vfxEnumsConverter.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/tool/vfx/vfxError.h b/tool/vfx/vfxError.h
index 3db684aa71..7a8c89bcda 100644
--- a/tool/vfx/vfxError.h
+++ b/tool/vfx/vfxError.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/tool/vfx/vfxParser.cpp b/tool/vfx/vfxParser.cpp
index ae2173fd81..06c3a51609 100644
--- a/tool/vfx/vfxParser.cpp
+++ b/tool/vfx/vfxParser.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -270,7 +270,8 @@ bool Document::endSection() {
if (!m_currentSection) {
// Do nothing
- } else if (m_currentSection->isShaderSourceSection() || m_currentSection->getSectionType() == SectionTypeCompileLog) {
+ } else if (m_currentSection->isShaderSourceSection() || m_currentSection->getSectionType() == SectionTypeCompileLog ||
+ m_currentSection->getSectionType() == SectionTypeRayTracingLibrarySummary) {
// Process shader source sections.
parseSectionShaderSource();
} else {
diff --git a/tool/vfx/vfxParser.h b/tool/vfx/vfxParser.h
index bafc55d6b3..a632fa8e6d 100644
--- a/tool/vfx/vfxParser.h
+++ b/tool/vfx/vfxParser.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/tool/vfx/vfxPipelineDoc.cpp b/tool/vfx/vfxPipelineDoc.cpp
index b5cabed674..6a91c7d584 100644
--- a/tool/vfx/vfxPipelineDoc.cpp
+++ b/tool/vfx/vfxPipelineDoc.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -61,6 +61,9 @@ unsigned PipelineDocument::getMaxSectionCount(SectionType type) {
case SectionTypeRayTracingState:
maxSectionCount = 1;
break;
+ case SectionTypeRayTracingLibrarySummary:
+ maxSectionCount = UINT32_MAX;
+ break;
case SectionTypeVertexInputState:
maxSectionCount = 1;
break;
@@ -156,6 +159,7 @@ VfxPipelineStatePtr PipelineDocument::getDocument() {
gfxPipelineInfo->enableEarlyCompile = graphicState.enableEarlyCompile;
gfxPipelineInfo->enableColorExportShader = graphicState.enableColorExportShader;
gfxPipelineInfo->useSoftwareVertexBufferDescriptors = graphicState.useSoftwareVertexBufferDescriptors;
+ gfxPipelineInfo->vbAddressLowBitsKnown = graphicState.vbAddressLowBitsKnown;
#if LLPC_CLIENT_INTERFACE_MAJOR_VERSION < 62
gfxPipelineInfo->shaderLibrary = graphicState.shaderLibrary;
#endif
@@ -225,6 +229,8 @@ VfxPipelineStatePtr PipelineDocument::getDocument() {
if (m_sections[SectionTypeVertexInputState].size() > 0) {
reinterpret_cast<SectionVertexInput *>(m_sections[SectionTypeVertexInputState][0])->getSubState(m_vertexInputState);
m_pipelineState.gfxPipelineInfo.pVertexInput = &m_vertexInputState;
+ reinterpret_cast<SectionVertexInput *>(m_sections[SectionTypeVertexInputState][0])
+ ->getvbAddressLowBits(m_pipelineState.gfxPipelineInfo.vbAddressLowBits);
}
if (m_pipelineState.pipelineType == VfxPipelineTypeGraphics ||
@@ -288,6 +294,14 @@ VfxPipelineStatePtr PipelineDocument::getDocument() {
mapIt.second.second->getSubState(m_descriptorRangeValues);
stageIndex++;
}
+
+ for (Section *section : m_sections[SectionTypeRayTracingLibrarySummary]) {
+ auto *summarySection = static_cast<SectionRayTracingLibrarySummary *>(section);
+ m_librarySummaries.push_back(summarySection->getSubState());
+ }
+
+ m_pipelineState.rayPipelineInfo.libraryCount = m_librarySummaries.size();
+ m_pipelineState.rayPipelineInfo.pLibrarySummaries = m_librarySummaries.data();
} else {
VFX_NEVER_CALLED();
}
@@ -427,6 +441,9 @@ Section *PipelineDocument::createSection(const char *sectionName) {
case SectionTypeRtState:
section = new SectionRtState();
break;
+ case SectionTypeRayTracingLibrarySummary:
+ section = new SectionRayTracingLibrarySummary;
+ break;
case SectionTypeVertexInputState:
section = new SectionVertexInput();
break;
diff --git a/tool/vfx/vfxPipelineDoc.h b/tool/vfx/vfxPipelineDoc.h
index b06bc20d51..22c931fad1 100644
--- a/tool/vfx/vfxPipelineDoc.h
+++ b/tool/vfx/vfxPipelineDoc.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -47,6 +47,8 @@ class PipelineDocument : public Document {
m_pipelineState.gfxPipelineInfo.options.optimizationLevel = 2;
m_pipelineState.compPipelineInfo.options.optimizationLevel = 2;
+ memset(&m_pipelineState.gfxPipelineInfo.vbAddressLowBits, 0,
+ sizeof(m_pipelineState.gfxPipelineInfo.vbAddressLowBits));
memset(&m_vertexInputState, 0, sizeof(m_vertexInputState));
};
@@ -69,6 +71,7 @@ class PipelineDocument : public Document {
VkPipelineVertexInputStateCreateInfo m_vertexInputState;
std::vector<Vfx::ShaderSource> m_shaderSources;
std::vector<Vkgc::PipelineShaderInfo> m_shaderInfos;
+ std::vector<Vkgc::BinaryData> m_librarySummaries;
// Used for backward compatibility with Version 1 .pipe files
std::vector<Vkgc::ResourceMappingRootNode> m_resourceMappingNodes;
diff --git a/tool/vfx/vfxSection.cpp b/tool/vfx/vfxSection.cpp
index a77cca8366..fb44ad54cd 100644
--- a/tool/vfx/vfxSection.cpp
+++ b/tool/vfx/vfxSection.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/tool/vfx/vfxSection.h b/tool/vfx/vfxSection.h
index 2f5c1d6cac..3792ada3e7 100644
--- a/tool/vfx/vfxSection.h
+++ b/tool/vfx/vfxSection.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -57,10 +57,11 @@ enum SectionType : unsigned {
SectionTypeImageView, // Image view section
SectionTypeSampler, // Sampler section
// VKGC pipeline
- SectionTypeGraphicsState, // Graphics state section
- SectionTypeComputeState, // Compute state section
- SectionTypeRayTracingState, // Ray tracing state section
- SectionTypeRtState, // Ray tracing rtState section
+ SectionTypeGraphicsState, // Graphics state section
+ SectionTypeComputeState, // Compute state section
+ SectionTypeRayTracingState, // Ray tracing state section
+ SectionTypeRtState, // Ray tracing rtState section
+ SectionTypeRayTracingLibrarySummary,
SectionTypeVertexInputState, // Vertex input state section
SectionTypeShaderInfo, // Shader info section
SectionTypeResourceMapping, // Resource mapping section
@@ -687,6 +688,7 @@ class SectionVertexInputAttribute : public Section {
}
void getSubState(SubState &state) { state = m_state; };
+ void getVbAddressLowBits(uint8_t &lowBits) { lowBits = m_vbAddressLowBits; };
SubState &getSubStateRef() { return m_state; };
private:
@@ -697,12 +699,14 @@ class SectionVertexInputAttribute : public Section {
INIT_STATE_MEMBER_NAME_TO_ADDR(SectionVertexInputAttribute, binding, MemberTypeInt, false);
INIT_STATE_MEMBER_NAME_TO_ADDR(SectionVertexInputAttribute, format, MemberTypeEnum, false);
INIT_STATE_MEMBER_NAME_TO_ADDR(SectionVertexInputAttribute, offset, MemberTypeInt, false);
+ INIT_MEMBER_NAME_TO_ADDR(SectionVertexInputAttribute, m_vbAddressLowBits, MemberTypeInt, false);
return addrTableInitializer;
}();
return {addrTable.data(), addrTable.size()};
}
SubState m_state;
+ uint8_t m_vbAddressLowBits;
};
// =====================================================================================================================
@@ -742,14 +746,17 @@ class SectionVertexInput : public Section {
memset(&m_vkDivisorState, 0, sizeof(m_vkDivisorState));
m_vkDivisorState.sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT;
}
-
+ void getvbAddressLowBits(uint8_t *vbAddrLowBits) { memcpy(vbAddrLowBits, &m_vbAddressLowBits[0], 64); }
void getSubState(SubState &state) {
m_vkBindings.resize(m_binding.size());
m_vkAttributes.resize(m_attribute.size());
m_vkDivisors.resize(m_divisor.size());
+ m_vbAddressLowBits.resize(64);
- for (unsigned i = 0; i < m_attribute.size(); ++i)
+ for (unsigned i = 0; i < m_attribute.size(); ++i) {
m_attribute[i].getSubState(m_vkAttributes[i]);
+ m_attribute[i].getVbAddressLowBits(m_vbAddressLowBits[m_vkAttributes[i].binding]);
+ }
for (unsigned i = 0; i < m_binding.size(); ++i)
m_binding[i].getSubState(m_vkBindings[i]);
@@ -787,6 +794,7 @@ class SectionVertexInput : public Section {
std::vector<VkVertexInputAttributeDescription> m_vkAttributes; // Vulkan vertex input attribute
std::vector<VkVertexInputBindingDivisorDescriptionEXT> m_vkDivisors; // Vulkan vertex input divisor
VkPipelineVertexInputDivisorStateCreateInfoEXT m_vkDivisorState; // Vulkan vertex input divisor state
+ std::vector<uint8_t> m_vbAddressLowBits; // Lowest two bits of vertex inputs offsets.
};
// =====================================================================================================================
diff --git a/tool/vfx/vfxVkSection.cpp b/tool/vfx/vfxVkSection.cpp
index 340f181406..76154ca8ac 100644
--- a/tool/vfx/vfxVkSection.cpp
+++ b/tool/vfx/vfxVkSection.cpp
@@ -1,8 +1,10 @@
#include "vfxEnumsConverter.h"
+#include "vfxError.h"
#include "vfxSection.h"
#if VFX_SUPPORT_VK_PIPELINE
#include "vfxVkSection.h"
+#include "llvm/BinaryFormat/MsgPackDocument.h"
using namespace Vkgc;
@@ -20,6 +22,7 @@ class VkSectionParserInit {
INIT_SECTION_INFO("ComputePipelineState", SectionTypeComputeState, 0)
INIT_SECTION_INFO("RayTracingPipelineState", SectionTypeRayTracingState, 0)
INIT_SECTION_INFO("RtState", SectionTypeRtState, 0)
+ INIT_SECTION_INFO("RayTracingLibrarySummary", SectionTypeRayTracingLibrarySummary, 0)
INIT_SECTION_INFO("VertexInputState", SectionTypeVertexInputState, 0)
INIT_SECTION_INFO("TaskInfo", SectionTypeShaderInfo, ShaderStage::ShaderStageTask)
INIT_SECTION_INFO("VsInfo", SectionTypeShaderInfo, ShaderStage::ShaderStageVertex)
@@ -105,6 +108,21 @@ void initVkSections() {
static VkSectionParserInit init;
}
+// =====================================================================================================================
+// Convert the raytracing library summary from YAML to msgpack
+Vkgc::BinaryData SectionRayTracingLibrarySummary::getSubState() {
+ std::string errorMsgTmp;
+ llvm::msgpack::Document doc;
+ if (!doc.fromYAML(m_yaml))
+ PARSE_ERROR(errorMsgTmp, getLineNum(), "Failed to parse YAML for raytracing library summary");
+ doc.writeToBlob(m_msgpack);
+
+ Vkgc::BinaryData data;
+ data.pCode = m_msgpack.data();
+ data.codeSize = m_msgpack.size();
+ return data;
+}
+
// =====================================================================================================================
// Parse the RT IP version
bool SectionRtState::parseRtIpVersion(RtIpVersion *rtIpVersion) {
diff --git a/tool/vfx/vfxVkSection.h b/tool/vfx/vfxVkSection.h
index 92fd19ae64..4cca957f46 100644
--- a/tool/vfx/vfxVkSection.h
+++ b/tool/vfx/vfxVkSection.h
@@ -271,6 +271,7 @@ class SectionShaderOption : public Section {
INIT_STATE_MEMBER_NAME_TO_ADDR(SectionShaderOption, disableLicmThreshold, MemberTypeInt, false);
INIT_STATE_MEMBER_NAME_TO_ADDR(SectionShaderOption, unrollHintThreshold, MemberTypeInt, false);
INIT_STATE_MEMBER_NAME_TO_ADDR(SectionShaderOption, dontUnrollHintThreshold, MemberTypeInt, false);
+ INIT_STATE_MEMBER_NAME_TO_ADDR(SectionShaderOption, noContractOpDot, MemberTypeBool, false);
INIT_STATE_MEMBER_NAME_TO_ADDR(SectionShaderOption, fastMathFlags, MemberTypeInt, false);
INIT_STATE_MEMBER_NAME_TO_ADDR(SectionShaderOption, disableFastMathFlags, MemberTypeInt, false);
INIT_STATE_MEMBER_NAME_TO_ADDR(SectionShaderOption, ldsSpillLimitDwords, MemberTypeInt, false);
@@ -283,6 +284,7 @@ class SectionShaderOption : public Section {
INIT_STATE_MEMBER_NAME_TO_ADDR(SectionShaderOption, workaroundStorageImageFormats, MemberTypeBool, false);
INIT_STATE_MEMBER_NAME_TO_ADDR(SectionShaderOption, workaroundInitializeOutputsToZero, MemberTypeBool, false);
INIT_STATE_MEMBER_NAME_TO_ADDR(SectionShaderOption, disableFMA, MemberTypeBool, false);
+ INIT_STATE_MEMBER_NAME_TO_ADDR(SectionShaderOption, constantBufferBindingOffset, MemberTypeInt, false);
return addrTableInitializer;
}();
return {addrTable.data(), addrTable.size()};
@@ -500,7 +502,9 @@ class SectionPipelineOption : public Section {
INIT_STATE_MEMBER_NAME_TO_ADDR(SectionPipelineOption, disableTruncCoordForGather, MemberTypeBool, false);
INIT_STATE_MEMBER_NAME_TO_ADDR(SectionPipelineOption, vertex64BitsAttribSingleLoc, MemberTypeBool, false);
INIT_STATE_MEMBER_NAME_TO_ADDR(SectionPipelineOption, enableFragColor, MemberTypeBool, false);
+ INIT_STATE_MEMBER_NAME_TO_ADDR(SectionPipelineOption, disableBaseVertex, MemberTypeBool, false);
INIT_STATE_MEMBER_NAME_TO_ADDR(SectionPipelineOption, enablePrimGeneratedQuery, MemberTypeBool, false);
+ INIT_STATE_MEMBER_NAME_TO_ADDR(SectionPipelineOption, disablePerCompFetch, MemberTypeBool, false);
return addrTableInitializer;
}();
return {addrTable.data(), addrTable.size()};
@@ -679,6 +683,21 @@ class SectionGpurtFuncTable : public Section {
std::string m_pFunc[Vkgc::RT_ENTRY_FUNC_COUNT];
};
+// =====================================================================================================================
+// Represents a raytracing library summary
+class SectionRayTracingLibrarySummary : public Section {
+public:
+ SectionRayTracingLibrarySummary() : Section({}, SectionTypeRayTracingLibrarySummary, "RayTracingLibrarySummary") {}
+
+ virtual void addLine(const char *line) { m_yaml += line; }
+
+ Vkgc::BinaryData getSubState();
+
+private:
+ std::string m_yaml;
+ std::string m_msgpack;
+};
+
// =====================================================================================================================
// Represents the sub section RtState state
class SectionRtState : public Section {
@@ -812,6 +831,7 @@ class SectionGraphicsState : public Section {
INIT_STATE_MEMBER_NAME_TO_ADDR(SectionGraphicsState, enableEarlyCompile, MemberTypeBool, false);
INIT_STATE_MEMBER_NAME_TO_ADDR(SectionGraphicsState, enableColorExportShader, MemberTypeBool, false);
INIT_STATE_MEMBER_NAME_TO_ADDR(SectionGraphicsState, useSoftwareVertexBufferDescriptors, MemberTypeBool, false);
+ INIT_STATE_MEMBER_NAME_TO_ADDR(SectionGraphicsState, vbAddressLowBitsKnown, MemberTypeBool, false);
INIT_MEMBER_NAME_TO_ADDR(SectionGraphicsState, m_shaderLibrary, MemberTypeString, false);
INIT_MEMBER_NAME_TO_ADDR(SectionGraphicsState, m_rtState, MemberTypeRtState, true);
INIT_MEMBER_ARRAY_NAME_TO_ADDR(SectionGraphicsState, tessLevelInner, MemberTypeFloat, 2, false);
diff --git a/util/CMakeLists.txt b/util/CMakeLists.txt
index a0ce352593..96fe215338 100644
--- a/util/CMakeLists.txt
+++ b/util/CMakeLists.txt
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/util/generate_strings.py b/util/generate_strings.py
index ba3a3e35aa..df1a6d5be6 100644
--- a/util/generate_strings.py
+++ b/util/generate_strings.py
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/util/gpurtshim/CMakeLists.txt b/util/gpurtshim/CMakeLists.txt
index 3db46c5f6a..05c0db7e01 100644
--- a/util/gpurtshim/CMakeLists.txt
+++ b/util/gpurtshim/CMakeLists.txt
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
diff --git a/util/gpurtshim/GpurtShim.cpp b/util/gpurtshim/GpurtShim.cpp
index 9cf72e519c..30964e08d7 100644
--- a/util/gpurtshim/GpurtShim.cpp
+++ b/util/gpurtshim/GpurtShim.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -93,11 +93,7 @@ void gpurt::getFuncTable(RtIpVersion rtIpVersion, GpurtFuncTable &table) {
Pal::RayTracingIpLevel rtIpLevel = getRtIpLevel(rtIpVersion);
GpuRt::EntryFunctionTable gpurtTable;
-#if GPURT_BUILD_RTIP3
- GpuRt::QueryRayTracingEntryFunctionTable(rtIpLevel, true, &gpurtTable);
-#else
GpuRt::QueryRayTracingEntryFunctionTable(rtIpLevel, &gpurtTable);
-#endif
unmangleDxilName(table.pFunc[RT_ENTRY_TRACE_RAY], gpurtTable.traceRay.pTraceRay);
unmangleDxilName(table.pFunc[RT_ENTRY_TRACE_RAY_INLINE], gpurtTable.rayQuery.pTraceRayInline);
diff --git a/util/vkgcCapability.h b/util/vkgcCapability.h
index 01604ce415..4a35f27642 100644
--- a/util/vkgcCapability.h
+++ b/util/vkgcCapability.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/util/vkgcElfReader.cpp b/util/vkgcElfReader.cpp
index 12f5975e08..f948731361 100644
--- a/util/vkgcElfReader.cpp
+++ b/util/vkgcElfReader.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/util/vkgcElfReader.h b/util/vkgcElfReader.h
index 6d0b7dafa4..2686ec915e 100644
--- a/util/vkgcElfReader.h
+++ b/util/vkgcElfReader.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/util/vkgcExtension.cpp b/util/vkgcExtension.cpp
index ce4790b8df..acfe1af16f 100644
--- a/util/vkgcExtension.cpp
+++ b/util/vkgcExtension.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2018-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2018-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/util/vkgcExtension.h b/util/vkgcExtension.h
index a79b06398d..0da87c3e0b 100644
--- a/util/vkgcExtension.h
+++ b/util/vkgcExtension.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/util/vkgcMetroHash.h b/util/vkgcMetroHash.h
index 5bd429ad66..1ff211de93 100644
--- a/util/vkgcMetroHash.h
+++ b/util/vkgcMetroHash.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2019-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/util/vkgcUtil.cpp b/util/vkgcUtil.cpp
index a73e58589f..da52ff8df4 100644
--- a/util/vkgcUtil.cpp
+++ b/util/vkgcUtil.cpp
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/util/vkgcUtil.h b/util/vkgcUtil.h
index 5813ad4343..b50616f886 100644
--- a/util/vkgcUtil.h
+++ b/util/vkgcUtil.h
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
diff --git a/version/CMakeLists.txt b/version/CMakeLists.txt
index 6d73ed02a5..f29c12e7cf 100644
--- a/version/CMakeLists.txt
+++ b/version/CMakeLists.txt
@@ -1,13 +1,13 @@
##
#######################################################################################################################
#
- # Copyright (c) 2017-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ # Copyright (c) 2017-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
- # of this software and associated documentation files (the "Software"), to deal
- # in the Software without restriction, including without limitation the rights
- # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- # copies of the Software, and to permit persons to whom the Software is
+ # of this software and associated documentation files (the "Software"), to
+ # deal in the Software without restriction, including without limitation the
+ # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ # sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
@@ -17,17 +17,20 @@
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- # SOFTWARE.
+ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ # IN THE SOFTWARE.
#
#######################################################################################################################
+include(GNUInstallDirs)
+
### llpc_version library ###############################################################################################
add_library(llpc_version INTERFACE)
target_include_directories(llpc_version INTERFACE
- $<BUILD_INTERFACE:${CMAKE_CURRENT_BINARY_DIR}/include>)
+ $<BUILD_INTERFACE:${CMAKE_CURRENT_BINARY_DIR}/include>
+ $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/include>)
configure_file(include/llpcVersion.h.in include/llpcVersion.h)
@@ -66,9 +69,11 @@ target_compile_definitions(llpc_version INTERFACE
# but then that would create a footgun if any of the version definitions are
# used in header files. Better to have this weird hack and have everybody link
# against llpc_version PUBLICly.
-install(TARGETS llpc_version EXPORT llpc_version-targets)
-install(EXPORT llpc_version-targets DESTINATION ${CMAKE_INSTALL_LIBDIR}/cmake) # installed version
-export(TARGETS llpc_version FILE llpc_version.cmake) # build-tree version
+if (NOT DISABLE_LLPC_VERSION_USES_LLVM)
+ install(TARGETS llpc_version EXPORT llpc_version-targets)
+ install(EXPORT llpc_version-targets DESTINATION ${CMAKE_INSTALL_LIBDIR}/cmake) # installed version
+ export(TARGETS llpc_version FILE llpc_version.cmake) # build-tree version
+endif()
### Cached Config-related Options ######################################################################################
option(LLPC_BUILD_NAVI12 "LLPC support for NAVI12?" ON)
diff --git a/version/include/llpc/GpurtEnums.h b/version/include/llpc/GpurtEnums.h
new file mode 100644
index 0000000000..c8e4f61940
--- /dev/null
+++ b/version/include/llpc/GpurtEnums.h
@@ -0,0 +1,66 @@
+/*
+ ***********************************************************************************************************************
+ *
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ **********************************************************************************************************************/
+/**
+ ***********************************************************************************************************************
+ * @file GpurtEnums.h
+ * @brief Declare enums that are shared between gpurt shader code and the compiler.
+ ***********************************************************************************************************************
+ */
+#pragma once
+
+#ifdef __cplusplus
+#include <cstdint>
+#endif
+
+/// Shader types.
+/// The values of this enum must match DXIL::ShaderKind from DxilConstants.h.
+enum class DXILShaderKind : uint32_t {
+ Pixel = 0,
+ Vertex,
+ Geometry,
+ Hull,
+ Domain,
+ Compute,
+ Library,
+ RayGeneration,
+ Intersection,
+ AnyHit,
+ ClosestHit,
+ Miss,
+ Callable,
+ Mesh,
+ Amplification,
+ Node,
+ Invalid
+};
+
+// clang-format off
+/// Decimal encoding of rtip levels.
+// clang-format on
+enum class RayTracingIpLevel : uint32_t {
+ _None = 0,
+ RtIp1_1 = 11,
+ RtIp2_0 = 20,
+};
diff --git a/version/include/llpc/GpurtIntrinsics.h b/version/include/llpc/GpurtIntrinsics.h
new file mode 100644
index 0000000000..16b05c7334
--- /dev/null
+++ b/version/include/llpc/GpurtIntrinsics.h
@@ -0,0 +1,241 @@
+/*
+ ***********************************************************************************************************************
+ *
+ * Copyright (c) 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ **********************************************************************************************************************/
+/**
+ ***********************************************************************************************************************
+ * @file GpurtIntrinsics.h
+ * @brief Declare intrinsics that are called from gpurt shader code and implemented in the compiler.
+ ***********************************************************************************************************************
+ */
+#pragma once
+
+#include "llpc/GpurtEnums.h"
+
+// clang-format off
+
+#ifndef DUMMY_VOID_FUNC
+#ifdef AMD_VULKAN
+#define DUMMY_VOID_FUNC {}
+#else // AMD_VULKAN
+#define DUMMY_VOID_FUNC ;
+#endif
+#endif
+
+#ifndef DUMMY_GENERIC_FUNC
+#ifdef AMD_VULKAN
+#define DUMMY_GENERIC_FUNC(value) { return value; }
+#else // AMD_VULKAN
+#define DUMMY_GENERIC_FUNC(value) ;
+#endif
+#endif
+
+#ifdef __cplusplus
+#define GPURT_INOUT
+#define GPURT_DECL extern
+#else // __cplusplus
+#define GPURT_INOUT inout
+#ifdef AMD_VULKAN
+#define GPURT_DECL [noinline]
+#else // AMD_VULKAN
+#define GPURT_DECL
+#endif
+#endif
+
+//=====================================================================================================================
+// Continuation intrinsics
+//
+//=====================================================================================================================
+// Control flow intrinsics: Enqueue, WaitEnqueue and Await
+// -------------------------------------------------------
+// In general, these intrinsics provide the continuation equivalent of indirect tail calls, by jumping to a passed
+// address and passing arbitrary arguments to the function at that address.
+//
+// Special arguments, and variants for different arguments and return types
+// ------------------------------------------------------------------------
+// Each such intrinsic has an addr argument of the referenced function.
+// WaitEnqueue has an additional waitMask argument.
+// All other arguments are generic function arguments passed to the referenced function.
+// For Await, the return type of the intrinsic is the return type of the referenced function.
+// Thus, arguments and return type of the HLSL intrinsic depend on the referenced function, which is why we need
+// multiple variants of each intrinsic.
+// There is no special handling for those variants, the compiler just knows the baseline intrinsics
+// _AmdEnqueue, _AmdWaitEnqueue and _AmdAwait and allows arbitrary suffixes.
+//
+// Function arguments and transformations
+// --------------------------------------
+// Referenced functions are in fact pointers to compiled HLSL-defined shaders (e.g. CHS) obtained e.g. from shader ids,
+// or resume functions created by Await calls.
+// These functions are heavily transformed in DXIL by the continuations compiler, also changing their arguments.
+// Continuation intrinsics refer to functions after these transformations, and pass arguments accordingly.
+// For example, a CHS shader in HLSL receives a payload and hit attributes. However, after continuation transforms,
+// the DXIL representation of a CHS receives a CSP (continuation stack pointer), a return address
+// (typically RGS.resume), and system data. The payload is implicitly passed via a global variable.
+// Thus, usage of these intrinsics is tightly coupled to function argument conventions of the continuations compiler.
+//
+// Return address handling
+// -----------------------
+// Some functions determine the next function to continue to on their own (Traversal, RayGen), all others are passed
+// a return address as follows. In these cases, the return address is always explicitly passed to these intrinsics,
+// even if the return address is a resume function or the current function, which are obtained via intrinsics.
+// Explicitly passing the return address allows to set metadata (e.g. scheduling priority) from HLSL.
+//
+// Enqueue
+// -------
+// Enqueue just jumps to the function at the given address. Enqueue is noreturn, and following code is unreachable.
+// _AmdEnqueue*(uint64_t addr, uint32_t csp, ...)
+#define DECLARE_ENQUEUE(Suffix, ...) GPURT_DECL \
+ void _AmdEnqueue##Suffix(uint64_t addr, uint32_t csp, __VA_ARGS__) DUMMY_VOID_FUNC
+//
+// WaitEnqueue
+// -----------
+// WaitEnqueue waits until all lanes in the mask also have enqueued the same wait mask before performing the Enqueue.
+// Generic function arguments start with the third argument.
+// _AmdWaitEnqueue*(uint64_t addr, uint64_t waitMask, uint32_t csp, ...)
+#define DECLARE_WAIT_ENQUEUE(Suffix, ...) GPURT_DECL \
+ void _AmdWaitEnqueue##Suffix(uint64_t addr, uint64_t waitMask, uint32_t csp, __VA_ARGS__) DUMMY_VOID_FUNC
+//
+// Complete
+// --------
+// Complete ends the program.
+GPURT_DECL void _AmdComplete() DUMMY_VOID_FUNC
+//
+// Await
+// -----
+// Await adds a resume point in the containing function (after inlining), creating a *resume function*,
+// and jumps to the referenced function.
+// The CSP is prepended to the generic arguments as new first argument for the referenced function.
+// The return address is passed explicitly to the intrinsic if needed by the referenced function, and is expected to
+// be the address of the resume function obtained via GetResumePointAddr.
+// It is passed explicitly because some uses do not need it (Traversal), and allowing to control metadata from HLSL,
+// such as the scheduling priority.
+// Thus, in contrast to Enqueue which renders all following code in the containing function unreachable, Await is more
+// similar to an ordinary indirect function call.
+// Any state in the containing function that is still needed in the resume function is stored in the continuation state
+// managed by the compiler.
+// Just like with enqueue, there is a waiting variant _AmdWaitAwait that waits on running the passed function.
+// ReturnTy _AmdAwait*(uint64_t addr, ...)
+
+#define DECLARE_AWAIT(Suffix, ReturnTy, ...) GPURT_DECL \
+ ReturnTy _AmdAwait##Suffix(uint64_t addr, __VA_ARGS__) DUMMY_GENERIC_FUNC((ReturnTy)0)
+
+// ReturnTy _AmdWaitAwait*(uint64_t addr, uint64_t waitMask, ...)
+#define DECLARE_WAIT_AWAIT(Suffix, ReturnTy, ...) GPURT_DECL \
+ ReturnTy _AmdWaitAwait##Suffix(uint64_t addr, uint64_t waitMask, __VA_ARGS__) DUMMY_GENERIC_FUNC((ReturnTy)0)
+//
+// GetResumePointAddr
+// ------------------
+// Returns the address of the resume function of the next resume point, i.e. at the next Await intrinsic.
+// Forbidden if the call site does not dominate a unique suspend point.
+// If this intrinsic is used, the implicit return address argument is removed from the next Await call.
+GPURT_DECL uint64_t _AmdGetResumePointAddr() DUMMY_GENERIC_FUNC(0)
+//
+// GetCurrentFuncAddr
+// ------------------
+// Returns the address of the caller function making this intrinsic call, after inlining and continuation function splitting.
+GPURT_DECL uint64_t _AmdGetCurrentFuncAddr() DUMMY_GENERIC_FUNC(0)
+//
+//=====================================================================================================================
+// GetShaderKind
+// Returns the kind of the shader this intrinsic is used in.
+// This is lowered after inlining GPURT functions (e.g. TraceRay) into app shaders.
+GPURT_DECL DXILShaderKind _AmdGetShaderKind() DUMMY_GENERIC_FUNC(DXILShaderKind::Invalid)
+//
+//=====================================================================================================================
+// ContStackAlloc
+// Allocate space on the continuation stack.
+// Arguments are the current stack pointer and the size of the allocation.
+// Returns the address of the allocation.
+//
+// This is equivalent to
+// return_value = csp
+// csp += byteSize
+//
+// In addition, it tells the compiler and driver about this allocation, so they can reserve enough memory for the
+// stack.
+GPURT_DECL uint32_t _AmdContStackAlloc(GPURT_INOUT uint32_t csp, uint32_t byteSize) DUMMY_GENERIC_FUNC(0)
+
+//=====================================================================================================================
+// Free the current continuation stack
+GPURT_DECL void _AmdContStackFree(uint32_t stackSize) DUMMY_VOID_FUNC
+
+//=====================================================================================================================
+// Set the current continuation stack pointer
+GPURT_DECL void _AmdContStackSetPtr(uint32_t csp) DUMMY_VOID_FUNC
+
+//=====================================================================================================================
+// Get the current continuation stack pointer
+GPURT_DECL uint32_t _AmdContStackGetPtr() DUMMY_GENERIC_FUNC(0)
+
+//=====================================================================================================================
+// Load data from a given continuation stack address
+#define DECLARE_CONT_STACK_LOAD(Suffix, ReturnTy) GPURT_DECL \
+ ReturnTy _AmdContStackLoad##Suffix(uint32_t addr) DUMMY_GENERIC_FUNC((ReturnTy)0)
+
+//=====================================================================================================================
+// Store data to a given continuation stack address
+#define DECLARE_CONT_STACK_STORE(Suffix, ...) GPURT_DECL \
+ void _AmdContStackStore##Suffix(uint32_t addr, __VA_ARGS__) DUMMY_VOID_FUNC
+
+//
+//=====================================================================================================================
+// State (system data / hit attributes) modifier intrinsics
+// void _AmdRestoreSystemData*(in SystemData data)
+#define DECLARE_RESTORE_SYSTEM_DATA(Suffix, ...) GPURT_DECL \
+ void _AmdRestoreSystemData##Suffix(__VA_ARGS__) DUMMY_VOID_FUNC
+// void _AmdAcceptHitAttributes*(inout SystemData data)
+#define DECLARE_ACCEPT_HIT_ATTRIBUTES(Suffix, ...) GPURT_DECL \
+ void _AmdAcceptHitAttributes##Suffix(__VA_ARGS__) DUMMY_VOID_FUNC
+//
+//=====================================================================================================================
+// Intrinsics to access arbitrary structs as i32 arrays
+// uint32_t _AmdValueI32Count*(Struct data)
+#define DECLARE_VALUE_I32_COUNT(Suffix, ...) GPURT_DECL \
+ uint32_t _AmdValueI32Count##Suffix(__VA_ARGS__) DUMMY_GENERIC_FUNC(0)
+// uint32_t _AmdValueGetI32*(Struct data, uint32_t i)
+#define DECLARE_VALUE_GET_I32(Suffix, ...) GPURT_DECL \
+ uint32_t _AmdValueGetI32##Suffix(__VA_ARGS__, uint32_t i) DUMMY_GENERIC_FUNC(0)
+// void _AmdValueSetI32*(inout Struct data, uint32_t i, uint32_t value)
+#define DECLARE_VALUE_SET_I32(Suffix, ...) GPURT_DECL \
+ void _AmdValueSetI32##Suffix(__VA_ARGS__, uint32_t value, uint32_t i) DUMMY_VOID_FUNC
+//
+//=====================================================================================================================
+// Intrinsics to access payload as i32 arrays
+GPURT_DECL uint32_t _AmdContPayloadRegistersI32Count() DUMMY_GENERIC_FUNC(0)
+GPURT_DECL uint32_t _AmdContPayloadRegistersGetI32(uint32_t i) DUMMY_GENERIC_FUNC(0)
+GPURT_DECL void _AmdContPayloadRegistersSetI32(uint32_t i, uint32_t value) DUMMY_VOID_FUNC
+//
+//=====================================================================================================================
+// Intrinsics returning uninitialized values (poison in LLVM IR),
+// used to hint the compiler to not keep certain values alive.
+// ReturnTy _AmdGetUninitialized*()
+#define DECLARE_GET_UNINITIALIZED(Suffix, ReturnTy) GPURT_DECL \
+ ReturnTy _AmdGetUninitialized##Suffix() DUMMY_GENERIC_FUNC((ReturnTy)0)
+
+//=====================================================================================================================
+// Intrinsics to access properties of the current configuration
+GPURT_DECL bool _AmdContinuationStackIsGlobal() DUMMY_GENERIC_FUNC(0)
+//=====================================================================================================================
+// Intrinsic to get the current rtip version.
+// The version is encoded as <major><minor> in decimal digits, so 11 is rtip 1.1, 20 is rtip 2.0
+GPURT_DECL RayTracingIpLevel _AmdGetRtip() DUMMY_GENERIC_FUNC(RayTracingIpLevel::_None)
diff --git a/version/include/llpcVersion.h.in b/version/include/llpcVersion.h.in
index 80a289b916..6a027da047 100644
--- a/version/include/llpcVersion.h.in
+++ b/version/include/llpcVersion.h.in
@@ -1,13 +1,13 @@
/*
***********************************************************************************************************************
*
- * Copyright (c) 2020-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (c) 2020-2024 Advanced Micro Devices, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
@@ -17,9 +17,9 @@
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
*
**********************************************************************************************************************/
/**
@@ -37,6 +37,11 @@
// %Version History
// | %Version | Change Description |
// | -------- | ----------------------------------------------------------------------------------------------------- |
+// | 70.5 | Add vbAddressLowBitsKnown to Options. Add vbAddrLowBits to VertexInputDescription. |
+// | Add vbAddressLowBitsKnown and vbAddressLowBits to GraphicsPipelineBuildInfo. |
+// | Add columnCount to ResourceNodeData. |
+// | Support vertex fetch in Byte, refine vertex fetch to always fetch in Component. |
+// | 70.4 | Add LibraryMode and pLibrarySummaries to RayTracingPipelineBuildInfo |
// | 70.2 | Add useSoftwareVertexBufferDescriptors to GraphicsPipelineBuildInfo |
// | 70.1 | Add cpsFlags to RayTracingPipelineBuildInfo |
// | 70.0 | Add enablePrimGeneratedQuery to PipelineOptions |
@@ -168,7 +173,7 @@
#define LLPC_INTERFACE_MAJOR_VERSION 70
/// LLPC minor interface version.
-#define LLPC_INTERFACE_MINOR_VERSION 2
+#define LLPC_INTERFACE_MINOR_VERSION 5
/// The client's LLPC major interface version
#ifndef LLPC_CLIENT_INTERFACE_MAJOR_VERSION