diff --git a/lgc/patch/MeshTaskShader.cpp b/lgc/patch/MeshTaskShader.cpp
index 3a7219bf27..5572680750 100644
--- a/lgc/patch/MeshTaskShader.cpp
+++ b/lgc/patch/MeshTaskShader.cpp
@@ -479,7 +479,7 @@ void MeshTaskShader::processMeshShader(Function *entryPoint) {
   const unsigned flatWorkgroupSize =
       alignTo(m_pipelineState->enableMeshRowExport() ? numMeshThreads : primAmpFactor, waveSize);
   entryPoint->addFnAttr("amdgpu-flat-work-group-size",
-                        std::to_string(primAmpFactor) + std::string(",") + std::to_string(flatWorkgroupSize));
+                        std::to_string(flatWorkgroupSize) + std::string(",") + std::to_string(flatWorkgroupSize));
 
   const unsigned numWaves = flatWorkgroupSize / waveSize;
   const unsigned numMeshWaves = alignTo(numMeshThreads, waveSize) / waveSize;
@@ -555,6 +555,9 @@ void MeshTaskShader::processMeshShader(Function *entryPoint) {
       m_builder.CreateStore(m_builder.getFalse(), m_barrierToggle);
     }
 
+    if (m_gfxIp.major >= 11)
+      prepareAttribRingAccess();
+
     m_builder.CreateBr(initPrimitiveIndicesHeaderBlock);
   }
 
@@ -573,9 +576,6 @@ void MeshTaskShader::processMeshShader(Function *entryPoint) {
                               m_builder.CreateMul(loopIndexPhi, m_builder.getInt32(waveSize)), "primitiveIndex");
     }
 
-    if (m_gfxIp.major >= 11)
-      prepareAttribRingAccess();
-
     auto validPrimitive =
         m_builder.CreateICmpULT(m_waveThreadInfo.primOrVertexIndex, m_builder.getInt32(meshMode.outputPrimitives));
     m_builder.CreateCondBr(validPrimitive, initPrimitiveIndicesBodyBlock, endInitPrimitiveIndicesBlock);
@@ -2234,7 +2234,7 @@ void MeshTaskShader::doExport(ExportKind kind, ArrayRef<ExportInfo> exports) {
         }
 
         m_builder.CreateIntrinsic(Intrinsic::amdgcn_struct_buffer_store, valueToStore->getType(),
-                                  {valueToStore, m_attribRingBufDesc, m_waveThreadInfo.threadIdInSubgroup,
+                                  {valueToStore, m_attribRingBufDesc, m_waveThreadInfo.primOrVertexIndex,
                                    locationOffset, m_attribRingBaseOffset, m_builder.getInt32(coherent.u32All)});
       }
     } else {
diff --git a/lgc/state/PipelineState.cpp b/lgc/state/PipelineState.cpp
index 6833b027fa..03dad2cd21 100644
--- a/lgc/state/PipelineState.cpp
+++ b/lgc/state/PipelineState.cpp
@@ -52,7 +52,7 @@ static cl::opt<bool> EnableTessOffChip("enable-tess-offchip", cl::desc("Enable t
 
 // -enable-row-export: enable row export for mesh shader
 static cl::opt<bool> EnableRowExport("enable-row-export", cl::desc("Enable row export for mesh shader"),
-                                     cl::init(false));
+                                     cl::init(true));
 
 cl::opt<bool> UseRegisterFieldFormat("use-register-field-format", cl::desc("Use register field format in pipeline ELF"),
                                      cl::init(true));