From ebb7137839035ca8d3a9ae6cce163411ccd93c09 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Mon, 24 Jun 2024 16:58:02 +0200 Subject: [PATCH] IRDumper: Allow const RA data --- FEXCore/Source/Interface/IR/IR.h | 2 +- FEXCore/Source/Interface/IR/IRDumper.cpp | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/FEXCore/Source/Interface/IR/IR.h b/FEXCore/Source/Interface/IR/IR.h index 3e73f838ed..5de4b2346b 100644 --- a/FEXCore/Source/Interface/IR/IR.h +++ b/FEXCore/Source/Interface/IR/IR.h @@ -724,7 +724,7 @@ inline NodeID NodeWrapperBase::ID() const { bool IsFragmentExit(FEXCore::IR::IROps Op); bool IsBlockExit(FEXCore::IR::IROps Op); -void Dump(fextl::stringstream* out, const IRListView* IR, IR::RegisterAllocationData* RAData); +void Dump(fextl::stringstream* out, const IRListView* IR, const IR::RegisterAllocationData* RAData); } // namespace FEXCore::IR template<> diff --git a/FEXCore/Source/Interface/IR/IRDumper.cpp b/FEXCore/Source/Interface/IR/IRDumper.cpp index fab30b4074..79ed952cdf 100644 --- a/FEXCore/Source/Interface/IR/IRDumper.cpp +++ b/FEXCore/Source/Interface/IR/IRDumper.cpp @@ -82,7 +82,7 @@ static void PrintArg(fextl::stringstream* out, [[maybe_unused]] const IRListView } } -static void PrintArg(fextl::stringstream* out, const IRListView* IR, OrderedNodeWrapper Arg, IR::RegisterAllocationData* RAData) { +static void PrintArg(fextl::stringstream* out, const IRListView* IR, OrderedNodeWrapper Arg, const IR::RegisterAllocationData* RAData) { auto [CodeNode, IROp] = IR->at(Arg)(); const auto ArgID = Arg.ID(); @@ -271,7 +271,7 @@ static void PrintArg(fextl::stringstream* out, [[maybe_unused]] const IRListView } } -void Dump(fextl::stringstream* out, const IRListView* IR, IR::RegisterAllocationData* RAData) { +void Dump(fextl::stringstream* out, const IRListView* IR, const IR::RegisterAllocationData* RAData) { auto HeaderOp = IR->GetHeader(); int8_t CurrentIndent = 0;