diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index 0ac40e2f7d..9f4db12396 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -3571,7 +3571,9 @@ void OpDispatchBuilder::DECOp(OpcodeArgs) {
     HandledLock = true;
     auto DestAddress = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, {.LoadData = false});
     DestAddress = AppendSegmentOffset(DestAddress, Op->Flags);
-    Dest = _AtomicFetchSub(OpSizeFromSrc(Op), OneConst, DestAddress);
+
+    // Use Add instead of Sub to avoid a NEG
+    Dest = _AtomicFetchAdd(OpSizeFromSrc(Op), _Constant(Size, -1), DestAddress);
   } else {
     Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, {.AllowUpperGarbage = Size >= 32});
   }
diff --git a/unittests/InstructionCountCI/Atomics.json b/unittests/InstructionCountCI/Atomics.json
index 2c6886ddd9..699ffedd61 100644
--- a/unittests/InstructionCountCI/Atomics.json
+++ b/unittests/InstructionCountCI/Atomics.json
@@ -1431,8 +1431,8 @@
       "Comment": "GROUP3 0xfe /1",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "neg w1, w20",
-        "ldaddalb w1, w27, [x4]",
+        "mov w21, #0xff",
+        "ldaddalb w21, w27, [x4]",
         "cset w21, hs",
         "lsl w0, w27, #24",
         "cmp w0, w20, lsl #24",
@@ -1541,8 +1541,8 @@
       "Comment": "GROUP4 0xfe /1",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "neg w1, w20",
-        "ldaddalh w1, w27, [x4]",
+        "mov w21, #0xffff",
+        "ldaddalh w21, w27, [x4]",
         "cset w21, hs",
         "lsl w0, w27, #16",
         "cmp w0, w20, lsl #16",
@@ -1553,12 +1553,11 @@
       ]
     },
     "lock dec dword [rax]": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 9,
       "Comment": "GROUP4 0xfe /1",
       "ExpectedArm64ASM": [
-        "mov w20, #0x1",
-        "neg w1, w20",
-        "ldaddal w1, w27, [x4]",
+        "mov w20, #0xffffffff",
+        "ldaddal w20, w27, [x4]",
         "cset w20, hs",
         "subs w26, w27, #0x1 (1)",
         "mrs x21, nzcv",
@@ -1569,12 +1568,11 @@
       ]
     },
     "lock dec qword [rax]": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 9,
       "Comment": "GROUP4 0xfe /1",
       "ExpectedArm64ASM": [
-        "mov w20, #0x1",
-        "neg x1, x20",
-        "ldaddal x1, x27, [x4]",
+        "mov x20, #0xffffffffffffffff",
+        "ldaddal x20, x27, [x4]",
         "cset w20, hs",
         "subs x26, x27, #0x1 (1)",
         "mrs x21, nzcv",
diff --git a/unittests/InstructionCountCI/FlagM/Atomics.json b/unittests/InstructionCountCI/FlagM/Atomics.json
index c1e63ff0c6..a69290907c 100644
--- a/unittests/InstructionCountCI/FlagM/Atomics.json
+++ b/unittests/InstructionCountCI/FlagM/Atomics.json
@@ -1300,8 +1300,8 @@
       "Comment": "GROUP3 0xfe /1",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "neg w1, w20",
-        "ldaddalb w1, w27, [x4]",
+        "mov w21, #0xff",
+        "ldaddalb w21, w27, [x4]",
         "cset w21, hs",
         "lsl w0, w27, #24",
         "cmp w0, w20, lsl #24",
@@ -1400,8 +1400,8 @@
       "Comment": "GROUP4 0xfe /1",
       "ExpectedArm64ASM": [
         "mov w20, #0x1",
-        "neg w1, w20",
-        "ldaddalh w1, w27, [x4]",
+        "mov w21, #0xffff",
+        "ldaddalh w21, w27, [x4]",
         "cset w21, hs",
         "lsl w0, w27, #16",
         "cmp w0, w20, lsl #16",
@@ -1410,24 +1410,22 @@
       ]
     },
     "lock dec dword [rax]": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 5,
       "Comment": "GROUP4 0xfe /1",
       "ExpectedArm64ASM": [
-        "mov w20, #0x1",
-        "neg w1, w20",
-        "ldaddal w1, w27, [x4]",
+        "mov w20, #0xffffffff",
+        "ldaddal w20, w27, [x4]",
         "cset w20, hs",
         "subs w26, w27, #0x1 (1)",
         "rmif x20, #63, #nzCv"
       ]
     },
     "lock dec qword [rax]": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 5,
       "Comment": "GROUP4 0xfe /1",
       "ExpectedArm64ASM": [
-        "mov w20, #0x1",
-        "neg x1, x20",
-        "ldaddal x1, x27, [x4]",
+        "mov x20, #0xffffffffffffffff",
+        "ldaddal x20, x27, [x4]",
         "cset w20, hs",
         "subs x26, x27, #0x1 (1)",
         "rmif x20, #63, #nzCv"