From 8548e1b66b3dd46ca8577e7514c66af81aa9810b Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Sun, 31 Mar 2024 17:51:47 -0400 Subject: [PATCH] InstCountCI: Update Signed-off-by: Alyssa Rosenzweig --- .../InstructionCountCI/FlagM/Primary.json | 176 ++++++++------- unittests/InstructionCountCI/Primary.json | 208 ++++++++++-------- 2 files changed, 208 insertions(+), 176 deletions(-) diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json index 743376c771..aedf1e479a 100644 --- a/unittests/InstructionCountCI/FlagM/Primary.json +++ b/unittests/InstructionCountCI/FlagM/Primary.json @@ -1950,153 +1950,169 @@ ] }, "repz cmpsb": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 15, "Comment": "0xa6", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", - "cbz x5, #+0x30", - "ldrb w21, [x11]", - "ldrb w22, [x10]", - "eor w27, w22, w21", - "lsl w0, w22, #24", - "cmp w0, w21, lsl #24", - "sub w26, w22, w21", - "cfinv", - "sub x5, x5, #0x1 (1)", + "cbz x5, #+0x38", + "ldrb w26, [x11]", + "ldrb w27, [x10]", + "subs x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", - "b.eq #-0x2c" + "ccmp x27, x26, #nzcv, ne", + "b.eq #-0x1c", + "mov x20, x27", + "eor w27, w20, w26", + "lsl w0, w20, #24", + "cmp w0, w26, lsl #24", + "sub w26, w20, w26", + "cfinv" ] }, "repz cmpsw": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 16, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", "lsl x20, x20, #1", - "cbz x5, #+0x30", - "ldrh w21, [x11]", - "ldrh w22, [x10]", - "eor w27, w22, w21", - "lsl w0, w22, #16", - "cmp w0, w21, lsl #16", - "sub w26, w22, w21", - "cfinv", - "sub x5, x5, #0x1 (1)", + "cbz x5, #+0x38", + "ldrh w26, [x11]", + "ldrh w27, [x10]", + "subs x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", - "b.eq #-0x2c" + "ccmp x27, x26, #nzcv, ne", + "b.eq #-0x1c", + "mov x20, x27", + "eor w27, w20, w26", + "lsl w0, w20, #16", + "cmp w0, w26, lsl #16", + "sub w26, w20, w26", + "cfinv" ] }, "repz cmpsd": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 14, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", "lsl x20, x20, #2", - "cbz x5, #+0x28", - "ldr w21, [x11]", - "ldr w22, [x10]", - "eor w27, w22, w21", - "subs w26, w22, w21", - "cfinv", - "sub x5, x5, #0x1 (1)", + "cbz x5, #+0x30", + "ldr w26, [x11]", + "ldr w27, [x10]", + "subs x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", - "b.eq #-0x24" + "ccmp x27, x26, #nzcv, ne", + "b.eq #-0x1c", + "mov x20, x27", + "eor w27, w20, w26", + "subs w26, w20, w26", + "cfinv" ] }, "repz cmpsq": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 14, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", "lsl x20, x20, #3", - "cbz x5, #+0x28", - "ldr x21, [x11]", - "ldr x22, [x10]", - "eor w27, w22, w21", - "subs x26, x22, x21", - "cfinv", - "sub x5, x5, #0x1 (1)", + "cbz x5, #+0x30", + "ldr x26, [x11]", + "ldr x27, [x10]", + "subs x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", - "b.eq #-0x24" + "ccmp x27, x26, #nzcv, ne", + "b.eq #-0x1c", + "mov x20, x27", + "eor w27, w20, w26", + "subs x26, x20, x26", + "cfinv" ] }, "repnz cmpsb": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 15, "Comment": "0xa6", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", - "cbz x5, #+0x30", - "ldrb w21, [x11]", - "ldrb w22, [x10]", - "eor w27, w22, w21", - "lsl w0, w22, #24", - "cmp w0, w21, lsl #24", - "sub w26, w22, w21", - "cfinv", - "sub x5, x5, #0x1 (1)", + "cbz x5, #+0x38", + "ldrb w26, [x11]", + "ldrb w27, [x10]", + "subs x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", - "b.ne #-0x2c" + "ccmp x27, x26, #nZcv, ne", + "b.ne #-0x1c", + "mov x20, x27", + "eor w27, w20, w26", + "lsl w0, w20, #24", + "cmp w0, w26, lsl #24", + "sub w26, w20, w26", + "cfinv" ] }, "repnz cmpsw": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 16, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", "lsl x20, x20, #1", - "cbz x5, #+0x30", - "ldrh w21, [x11]", - "ldrh w22, [x10]", - "eor w27, w22, w21", - "lsl w0, w22, #16", - "cmp w0, w21, lsl #16", - "sub w26, w22, w21", - "cfinv", - "sub x5, x5, #0x1 (1)", + "cbz x5, #+0x38", + "ldrh w26, [x11]", + "ldrh w27, [x10]", + "subs x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", - "b.ne #-0x2c" + "ccmp x27, x26, #nZcv, ne", + "b.ne #-0x1c", + "mov x20, x27", + "eor w27, w20, w26", + "lsl w0, w20, #16", + "cmp w0, w26, lsl #16", + "sub w26, w20, w26", + "cfinv" ] }, "repnz cmpsd": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 14, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", "lsl x20, x20, #2", - "cbz x5, #+0x28", - "ldr w21, [x11]", - "ldr w22, [x10]", - "eor w27, w22, w21", - "subs w26, w22, w21", - "cfinv", - "sub x5, x5, #0x1 (1)", + "cbz x5, #+0x30", + "ldr w26, [x11]", + "ldr w27, [x10]", + "subs x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", - "b.ne #-0x24" + "ccmp x27, x26, #nZcv, ne", + "b.ne #-0x1c", + "mov x20, x27", + "eor w27, w20, w26", + "subs w26, w20, w26", + "cfinv" ] }, "repnz cmpsq": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 14, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", "lsl x20, x20, #3", - "cbz x5, #+0x28", - "ldr x21, [x11]", - "ldr x22, [x10]", - "eor w27, w22, w21", - "subs x26, x22, x21", - "cfinv", - "sub x5, x5, #0x1 (1)", + "cbz x5, #+0x30", + "ldr x26, [x11]", + "ldr x27, [x10]", + "subs x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", - "b.ne #-0x24" + "ccmp x27, x26, #nZcv, ne", + "b.ne #-0x1c", + "mov x20, x27", + "eor w27, w20, w26", + "subs x26, x20, x26", + "cfinv" ] }, "test al, 1": { diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index 5ee00256f5..e38172bcb6 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -3295,169 +3295,185 @@ ] }, "repz cmpsb": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 17, "Comment": "0xa6", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", - "cbz x5, #+0x38", - "ldrb w21, [x11]", - "ldrb w22, [x10]", - "eor w27, w22, w21", - "lsl w0, w22, #24", - "cmp w0, w21, lsl #24", - "sub w26, w22, w21", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", - "sub x5, x5, #0x1 (1)", + "cbz x5, #+0x40", + "ldrb w26, [x11]", + "ldrb w27, [x10]", + "subs x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", - "b.eq #-0x34" + "ccmp x27, x26, #nzcv, ne", + "b.eq #-0x1c", + "mov x20, x27", + "eor w27, w20, w26", + "lsl w0, w20, #24", + "cmp w0, w26, lsl #24", + "sub w26, w20, w26", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "repz cmpsw": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 18, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", "lsl x20, x20, #1", - "cbz x5, #+0x38", - "ldrh w21, [x11]", - "ldrh w22, [x10]", - "eor w27, w22, w21", - "lsl w0, w22, #16", - "cmp w0, w21, lsl #16", - "sub w26, w22, w21", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", - "sub x5, x5, #0x1 (1)", + "cbz x5, #+0x40", + "ldrh w26, [x11]", + "ldrh w27, [x10]", + "subs x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", - "b.eq #-0x34" + "ccmp x27, x26, #nzcv, ne", + "b.eq #-0x1c", + "mov x20, x27", + "eor w27, w20, w26", + "lsl w0, w20, #16", + "cmp w0, w26, lsl #16", + "sub w26, w20, w26", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "repz cmpsd": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 16, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", "lsl x20, x20, #2", - "cbz x5, #+0x30", - "ldr w21, [x11]", - "ldr w22, [x10]", - "eor w27, w22, w21", - "subs w26, w22, w21", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", - "sub x5, x5, #0x1 (1)", + "cbz x5, #+0x38", + "ldr w26, [x11]", + "ldr w27, [x10]", + "subs x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", - "b.eq #-0x2c" + "ccmp x27, x26, #nzcv, ne", + "b.eq #-0x1c", + "mov x20, x27", + "eor w27, w20, w26", + "subs w26, w20, w26", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "repz cmpsq": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 16, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", "lsl x20, x20, #3", - "cbz x5, #+0x30", - "ldr x21, [x11]", - "ldr x22, [x10]", - "eor w27, w22, w21", - "subs x26, x22, x21", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", - "sub x5, x5, #0x1 (1)", + "cbz x5, #+0x38", + "ldr x26, [x11]", + "ldr x27, [x10]", + "subs x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", - "b.eq #-0x2c" + "ccmp x27, x26, #nzcv, ne", + "b.eq #-0x1c", + "mov x20, x27", + "eor w27, w20, w26", + "subs x26, x20, x26", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "repnz cmpsb": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 17, "Comment": "0xa6", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", - "cbz x5, #+0x38", - "ldrb w21, [x11]", - "ldrb w22, [x10]", - "eor w27, w22, w21", - "lsl w0, w22, #24", - "cmp w0, w21, lsl #24", - "sub w26, w22, w21", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", - "sub x5, x5, #0x1 (1)", + "cbz x5, #+0x40", + "ldrb w26, [x11]", + "ldrb w27, [x10]", + "subs x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", - "b.ne #-0x34" + "ccmp x27, x26, #nZcv, ne", + "b.ne #-0x1c", + "mov x20, x27", + "eor w27, w20, w26", + "lsl w0, w20, #24", + "cmp w0, w26, lsl #24", + "sub w26, w20, w26", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "repnz cmpsw": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 18, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", "lsl x20, x20, #1", - "cbz x5, #+0x38", - "ldrh w21, [x11]", - "ldrh w22, [x10]", - "eor w27, w22, w21", - "lsl w0, w22, #16", - "cmp w0, w21, lsl #16", - "sub w26, w22, w21", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", - "sub x5, x5, #0x1 (1)", + "cbz x5, #+0x40", + "ldrh w26, [x11]", + "ldrh w27, [x10]", + "subs x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", - "b.ne #-0x34" + "ccmp x27, x26, #nZcv, ne", + "b.ne #-0x1c", + "mov x20, x27", + "eor w27, w20, w26", + "lsl w0, w20, #16", + "cmp w0, w26, lsl #16", + "sub w26, w20, w26", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "repnz cmpsd": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 16, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", "lsl x20, x20, #2", - "cbz x5, #+0x30", - "ldr w21, [x11]", - "ldr w22, [x10]", - "eor w27, w22, w21", - "subs w26, w22, w21", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", - "sub x5, x5, #0x1 (1)", + "cbz x5, #+0x38", + "ldr w26, [x11]", + "ldr w27, [x10]", + "subs x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", - "b.ne #-0x2c" + "ccmp x27, x26, #nZcv, ne", + "b.ne #-0x1c", + "mov x20, x27", + "eor w27, w20, w26", + "subs w26, w20, w26", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "repnz cmpsq": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 16, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #714]", "lsl x20, x20, #3", - "cbz x5, #+0x30", - "ldr x21, [x11]", - "ldr x22, [x10]", - "eor w27, w22, w21", - "subs x26, x22, x21", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", - "sub x5, x5, #0x1 (1)", + "cbz x5, #+0x38", + "ldr x26, [x11]", + "ldr x27, [x10]", + "subs x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", - "b.ne #-0x2c" + "ccmp x27, x26, #nZcv, ne", + "b.ne #-0x1c", + "mov x20, x27", + "eor w27, w20, w26", + "subs x26, x20, x26", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test al, 1": {