diff --git a/unittests/InstructionCountCI/X87ldst-SVE.json b/unittests/InstructionCountCI/X87ldst-SVE.json
index d82b68d9b1..27804513f6 100644
--- a/unittests/InstructionCountCI/X87ldst-SVE.json
+++ b/unittests/InstructionCountCI/X87ldst-SVE.json
@@ -17,10 +17,10 @@
       "ExpectedInstructionCount": 13,
       "Comment": "Single 80-bit store.",
       "ExpectedArm64ASM": [
+        "ptrue p2.h, vl5",
         "ldrb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "ptrue p2.h, vl5",
         "st1h {z2.h}, p2, [x4]",
         "ldrb w21, [x28, #1298]",
         "mov w22, #0x1",
@@ -40,10 +40,10 @@
         "fstp tword [rax+10]"
       ],
       "ExpectedArm64ASM": [
+        "ptrue p2.h, vl5",
         "ldrb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "ptrue p2.h, vl5",
         "st1h {z2.h}, p2, [x4]",
         "ldrb w21, [x28, #1298]",
         "mov w22, #0x1",
@@ -81,10 +81,10 @@
         "fstp tword [rax+70]"
       ],
       "ExpectedArm64ASM": [
+        "ptrue p2.h, vl5",
         "ldrb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "ptrue p2.h, vl5",
         "st1h {z2.h}, p2, [x4]",
         "ldrb w21, [x28, #1298]",
         "mov w22, #0x1",