From 0e93fd0f3e5e7e5f8764eb7059034f63a7884b05 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Mon, 8 Apr 2024 11:32:01 -0700 Subject: [PATCH] OpcodeDispatcher: Fixes disabling TSO access on RSP SIB stores GPR Direct/Indirect already had this and SIB version also already supported on the load side. Fixes this missed behaviour. --- .../Interface/Core/OpcodeDispatcher.cpp | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 9282b91444..d717f2063c 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -4475,9 +4475,6 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, X auto Constant = _Constant(GPRSize * 8, Operand.Data.SIB.Scale); Tmp = _Mul(IR::SizeToOpSize(GPRSize), Tmp, Constant); } - if (Operand.Data.SIB.Index == FEXCore::X86State::REG_RSP && AccessType == MemoryAccessType::DEFAULT) { - AccessType = MemoryAccessType::NONTSO; - } } if (Operand.Data.SIB.Base != FEXCore::X86State::REG_INVALID) { @@ -4489,10 +4486,6 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, X else { Tmp = GPR; } - - if (Operand.Data.SIB.Base == FEXCore::X86State::REG_RSP && AccessType == MemoryAccessType::DEFAULT) { - AccessType = MemoryAccessType::NONTSO; - } } } @@ -4513,6 +4506,12 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, X } } + if ((Operand.Data.SIB.Base == FEXCore::X86State::REG_RSP || + Operand.Data.SIB.Index == FEXCore::X86State::REG_RSP) + && AccessType == MemoryAccessType::DEFAULT) { + AccessType = MemoryAccessType::NONTSO; + } + LoadableType = true; } else { @@ -4762,6 +4761,12 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl MemStoreDst = _Bfe(IR::SizeToOpSize(std::max(4u, AddrSize)), AddrSize * 8, 0, MemStoreDst); } + if ((Operand.Data.SIB.Base == FEXCore::X86State::REG_RSP || + Operand.Data.SIB.Index == FEXCore::X86State::REG_RSP) + && AccessType == MemoryAccessType::DEFAULT) { + AccessType = MemoryAccessType::NONTSO; + } + MemStore = true; }