Where to work on the gateware (HDL design)

[sly547]

Hello! I have a ZynqSDR, I'm starting to work with it, and this seems to be a place to discuss firmware/gateware (yeah I'm referring to the programmable logic (PL) of the Zynq and people now seem to use the word "gateware".. 🤷 ).

At the moment it is being built from Analog's repo (https://github.com/analogdevicesinc/hdl). The other project at https://github.com/hz12opensource/libresdr is patching it by adding a customized project called "project/libre", based on "project/pluto".

I want to make some changes to the design, for the ZynqSDR in particular, based on hz12opensource's work:

• route the two LEDs at the 10MHz and PPS inputs to the PS, so that Linux can set them (I think the EMIO interface can be used)
• add a second AXI IIC to the block design and connect both to the two I2C interfaces correctly
• maybe route something to the unpopulated CN1 "EXT_GPIO" header

I guess I could fork the "hdl" repo, or maybe better create a separate repo with only my version of "project/libre". It would somehow have to refer to the libraries in the original "hdl" repo. I think I will try this. Any thoughts on this?

[F5OEO]

Yes, tezuka_fw aims to be a place to help in helping building firmware included hdl. At this time, it is done with package and compiled bitstream.
Example : https://github.com/F5OEO/tezuka_fw/tree/main/package/libre_fpga which refere to https://github.com/F5OEO/tezuka_fw/tree/main/board/libre/bitstream

You can also use example of a bitstream package which run vivado to build the bitstream :
https://github.com/F5OEO/tezuka_fw/tree/main/package/pluto-fpga

Libresdr hdl included in tezuka is at : https://github.com/F5OEO/maia-sdr/tree/sweep/maia-hdl

Le me know if you have any question.

[sly547]

Ah, I had overlooked most of this. This helps. I will dig deeper. Thanks!