diff --git a/src/Core/Generator/VerilogCodeTemplateGenerator.h b/src/Core/Generator/VerilogCodeTemplateGenerator.h
index 0aa487be..33d9d276 100644
--- a/src/Core/Generator/VerilogCodeTemplateGenerator.h
+++ b/src/Core/Generator/VerilogCodeTemplateGenerator.h
@@ -56,7 +56,7 @@ namespace degate
         virtual std::string generate_port_definition() const;
 
         virtual std::string generate_module(std::string const& entity_name,
-                                            std::string const& port_description = "") const;
+                                            std::string const& port_description) const;
 
 
         virtual std::string generate_impl(std::string const& logic_class = "") const;
diff --git a/src/Core/Image/TileCache.h b/src/Core/Image/TileCache.h
index a1f3be37..0c9f3408 100644
--- a/src/Core/Image/TileCache.h
+++ b/src/Core/Image/TileCache.h
@@ -324,7 +324,9 @@ namespace degate
                   unsigned int min_cache_tiles = 4) :
             directory(directory),
             tile_width_exp(tile_width_exp),
-            persistent(persistent)
+            persistent(persistent),
+            curr_tile_num_x(0),
+            curr_tile_num_y(0)
         {
         }