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Fire_Mux_syn.v
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// megafunction wizard: %LPM_MUX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mux
// ============================================================
// File Name: Fire_Mux.v
// Megafunction Name(s):
// lpm_mux
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//lpm_mux DEVICE_FAMILY="Cyclone III" LPM_SIZE=4 LPM_WIDTH=8 LPM_WIDTHS=2 data result sel
//VERSION_BEGIN 9.1SP2 cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = lut 16
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module Fire_Mux_mux
(
data,
result,
sel) /* synthesis synthesis_clearbox=1 */;
input [31:0] data;
output [7:0] result;
input [1:0] sel;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [31:0] data;
tri0 [1:0] sel;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] result_node;
wire [1:0] sel_node;
wire [3:0] w_data109w;
wire [3:0] w_data134w;
wire [3:0] w_data159w;
wire [3:0] w_data184w;
wire [3:0] w_data34w;
wire [3:0] w_data4w;
wire [3:0] w_data59w;
wire [3:0] w_data84w;
assign
result = result_node,
result_node = {(((w_data184w[1] & sel_node[0]) & (~ (((w_data184w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data184w[2]))))) | ((((w_data184w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data184w[2]))) & (w_data184w[3] | (~ sel_node[0])))), (((w_data159w[1] & sel_node[0]) & (~ (((w_data159w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data159w[2]))))) | ((((w_data159w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data159w[2]))) & (w_data159w[3] | (~ sel_node[0])))), (((w_data134w[1] & sel_node[0]) & (~ (((w_data134w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data134w[2]))))) | ((((w_data134w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data134w[2]))) & (w_data134w[3] | (~ sel_node[0])))), (((w_data109w[1] & sel_node[0]) & (~ (((w_data109w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data109w[2]))))) | ((((w_data109w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data109w[2]))) & (w_data109w[3] | (~ sel_node[0])))), (((w_data84w[1] & sel_node[0]) & (~ (((w_data84w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data84w[2]))))) | ((((w_data84w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data84w[2]))) & (w_data84w[3] | (~ sel_node[0])))), (((w_data59w[1] & sel_node[0]) & (~ (((w_data59w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data59w[2]))))) | ((((w_data59w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data59w[2]))) & (w_data59w[3] | (~ sel_node[0])))), (((w_data34w[1] & sel_node[0]) & (~ (((w_data34w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data34w[2]))))) | ((((w_data34w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data34w[2]))) & (w_data34w[3] | (~ sel_node[0])))), (((w_data4w[1] & sel_node[0]
) & (~ (((w_data4w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data4w[2]))))) | ((((w_data4w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data4w[2]))) & (w_data4w[3] | (~ sel_node[0]))))},
sel_node = {sel[1:0]},
w_data109w = {data[28], data[20], data[12], data[4]},
w_data134w = {data[29], data[21], data[13], data[5]},
w_data159w = {data[30], data[22], data[14], data[6]},
w_data184w = {data[31], data[23], data[15], data[7]},
w_data34w = {data[25], data[17], data[9], data[1]},
w_data4w = {data[24], data[16], data[8], data[0]},
w_data59w = {data[26], data[18], data[10], data[2]},
w_data84w = {data[27], data[19], data[11], data[3]};
endmodule //Fire_Mux_mux
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Fire_Mux (
data0x,
data1x,
data2x,
data3x,
sel,
result)/* synthesis synthesis_clearbox = 1 */;
input [7:0] data0x;
input [7:0] data1x;
input [7:0] data2x;
input [7:0] data3x;
input [1:0] sel;
output [7:0] result;
wire [7:0] sub_wire0;
wire [7:0] sub_wire5 = data3x[7:0];
wire [7:0] sub_wire4 = data1x[7:0];
wire [7:0] sub_wire3 = data0x[7:0];
wire [7:0] result = sub_wire0[7:0];
wire [7:0] sub_wire1 = data2x[7:0];
wire [31:0] sub_wire2 = {sub_wire5, sub_wire1, sub_wire4, sub_wire3};
Fire_Mux_mux Fire_Mux_mux_component (
.sel (sel),
.data (sub_wire2),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
// Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL data0x[7..0]
// Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL data1x[7..0]
// Retrieval info: USED_PORT: data2x 0 0 8 0 INPUT NODEFVAL data2x[7..0]
// Retrieval info: USED_PORT: data3x 0 0 8 0 INPUT NODEFVAL data3x[7..0]
// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
// Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0]
// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
// Retrieval info: CONNECT: @data 0 0 8 24 data3x 0 0 8 0
// Retrieval info: CONNECT: @data 0 0 8 16 data2x 0 0 8 0
// Retrieval info: CONNECT: @data 0 0 8 8 data1x 0 0 8 0
// Retrieval info: CONNECT: @data 0 0 8 0 data0x 0 0 8 0
// Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Fire_Mux.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Fire_Mux.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Fire_Mux.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Fire_Mux.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Fire_Mux_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Fire_Mux_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Fire_Mux_syn.v TRUE
// Retrieval info: LIB_FILE: lpm