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Is the CSYNC signal correct? #8

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baicker opened this issue Feb 18, 2022 · 0 comments
Open

Is the CSYNC signal correct? #8

baicker opened this issue Feb 18, 2022 · 0 comments

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@baicker
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baicker commented Feb 18, 2022 •
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1FCBCD7397907B6CFA4809B436D9214A

my timings file:
320 1 24 32 48 240 1 3 3 14 0 0 0 60 0 6639840 1 # 320x240@60p Default mode
640 1 20 60 82 480 1 22 5 24 0 0 0 60 1 12800000 1 # 640x480@60i ES 480i
1920 1 78 192 210 240 1 3 3 16 0 0 0 60 0 37730000 1 # 1920x240@60p ES 240p

dmesg shows:
[ 65.538030] [RPI-DPIDAC]: "320x240": 60 6639 320 344 376 424 240 243 246 260 0x48 0xa
[ 65.538080] [RPI-DPIDAC]: "640x480i": 60 12800 640 660 720 802 480 502 507 531 0x40 0x1a
[ 65.538108] [RPI-DPIDAC]: "1920x240": 60 37730 1920 1998 2190 2400 240 243 246 262 0x40 0xa
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@baicker