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- diff --git a/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.runs/synth_1/gen_run.xml b/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.runs/synth_1/gen_run.xml deleted file mode 100644 index 6aec613..0000000 --- a/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.runs/synth_1/gen_run.xml +++ /dev/null @@ -1,115 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml b/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml deleted file mode 100644 index 2b05476..0000000 --- a/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml +++ /dev/null @@ -1,5366 +0,0 @@ - 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- - - ASSOCIATED_BUSIF - s_axi_lite - - - ASSOCIATED_RESET - s_axi_aresetn - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - ref_clk - ref_clk - - - - - - - CLK - - - ref_clk - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_resetn - S_AXI_RESETN - - - - - - - RST - - - s_axi_aresetn - - - - - - ASSOCIATED_RESET - aresetn - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - intr - Intr - - - - - - - INTERRUPT - - - ip2intc_irpt - - - - - - SENSITIVITY - LEVEL_HIGH - - - none - - - - - PortWidth - 1 - - - none - - - - - - - - false - - - - - - CLK_IN1_D - CLK_IN1_D - Differential Clock input - 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FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - reset - reset - - - - - - - RST - - - reset - - - - - - POLARITY - ACTIVE_HIGH - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - resetn - resetn - - - - - - - RST - - - resetn - - - - - - POLARITY - ACTIVE_LOW - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - clock_CLK_IN1 - - - - - - - CLK_IN1 - - - clk_in1 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN1_BOARD_INTERFACE - - - - - clock_CLK_OUT1 - - - - - - - CLK_OUT1 - - - clk_out1 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - 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INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT5 - - - - - - - CLK_OUT5 - - - clk_out5 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT6 - - - - - - - CLK_OUT6 - - - clk_out6 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - xilinx_elaborateports - Elaborate Ports - :vivado.xilinx.com:elaborate.ports - - - outputProductCRC - 9:645f10ac - - - - - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog - clk_wiz_v6_0_3 - - xilinx_veriloginstantiationtemplate_view_fileset - - - - GENtimestamp - Sat Sep 14 03:25:51 UTC 2019 - - - outputProductCRC - 9:8f74fa14 - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - clk_wiz_v6_0_3 - - xilinx_anylanguagesynthesis_view_fileset - - - - GENtimestamp - Sat Sep 14 03:25:52 UTC 2019 - - - outputProductCRC - 9:8f74fa14 - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - - outputProductCRC - 9:8f74fa14 - - - - - xilinx_anylanguagesynthesiswrapper - Synthesis Wrapper - :vivado.xilinx.com:synthesis.wrapper - clk_wiz_0 - - xilinx_anylanguagesynthesiswrapper_view_fileset - - - - GENtimestamp - Sat Sep 14 03:25:52 UTC 2019 - - - outputProductCRC - 9:8f74fa14 - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - clk_wiz_v6_0_3 - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - GENtimestamp - Sat Sep 14 03:25:52 UTC 2019 - - - outputProductCRC - 9:9032b1ca - - - - - xilinx_anylanguagesimulationwrapper - Simulation Wrapper - :vivado.xilinx.com:simulation.wrapper - clk_wiz_0 - - xilinx_anylanguagesimulationwrapper_view_fileset - - - - GENtimestamp - Sat Sep 14 03:25:52 UTC 2019 - - - outputProductCRC - 9:9032b1ca - - - - - xilinx_implementation - Implementation - :vivado.xilinx.com:implementation - - xilinx_implementation_view_fileset - - - - GENtimestamp - Sat Sep 14 03:25:53 UTC 2019 - - - outputProductCRC - 9:8f74fa14 - - - - - xilinx_versioninformation - Version Information - :vivado.xilinx.com:docs.versioninfo - - xilinx_versioninformation_view_fileset - - - - GENtimestamp - Sat Sep 14 03:25:53 UTC 2019 - - - outputProductCRC - 9:8f74fa14 - - - - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Sat Sep 14 03:26:32 UTC 2019 - - - outputProductCRC - 9:8f74fa14 - - - - - - - s_axi_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_aresetn - 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xilinx_anylanguagebehavioralsimulation - - - - - - clk_out6 - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - locked - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - C_CLKOUT2_USED - 1 - - - C_USER_CLK_FREQ0 - 100.0 - - - C_AUTO_PRIMITIVE - MMCM - - - C_USER_CLK_FREQ1 - 100.0 - - - C_USER_CLK_FREQ2 - 100.0 - - - C_USER_CLK_FREQ3 - 100.0 - - - C_ENABLE_CLOCK_MONITOR - 0 - - - C_ENABLE_USER_CLOCK0 - 0 - - - C_ENABLE_USER_CLOCK1 - 0 - - - C_ENABLE_USER_CLOCK2 - 0 - - - C_ENABLE_USER_CLOCK3 - 0 - - - C_Enable_PLL0 - 0 - - - C_Enable_PLL1 - 0 - - - C_REF_CLK_FREQ - 100.0 - - - C_PRECISION - 1 - - - C_CLKOUT3_USED - 1 - - - C_CLKOUT4_USED - 1 - - - C_CLKOUT5_USED - 1 - - - C_CLKOUT6_USED - 1 - - - C_CLKOUT7_USED - 0 - - - C_USE_CLKOUT1_BAR - 0 - - - C_USE_CLKOUT2_BAR - 0 - - - C_USE_CLKOUT3_BAR - 0 - - - C_USE_CLKOUT4_BAR - 0 - - - c_component_name - clk_wiz_0 - - - C_PLATFORM - UNKNOWN - - - C_USE_FREQ_SYNTH - 0 - - - C_USE_PHASE_ALIGNMENT - 0 - - - C_PRIM_IN_JITTER - 0.010 - - - C_SECONDARY_IN_JITTER - 0.010 - - - C_JITTER_SEL - No_Jitter - - - C_USE_MIN_POWER - 0 - - - C_USE_MIN_O_JITTER - 0 - - - C_USE_MAX_I_JITTER - 0 - - - C_USE_DYN_PHASE_SHIFT - 0 - - - C_USE_INCLK_SWITCHOVER - 0 - - - C_USE_DYN_RECONFIG - 0 - - - C_USE_SPREAD_SPECTRUM - 0 - - - C_USE_FAST_SIMULATION - 0 - - - C_PRIMTYPE_SEL - AUTO - - - C_USE_CLK_VALID - 0 - - - C_PRIM_IN_FREQ - 100.000 - - - C_PRIM_IN_TIMEPERIOD - 10.000 - - - C_IN_FREQ_UNITS - Units_MHz - - - C_SECONDARY_IN_FREQ - 100.000 - - - C_SECONDARY_IN_TIMEPERIOD - 10.000 - - - C_FEEDBACK_SOURCE - FDBK_AUTO - - - C_PRIM_SOURCE - Single_ended_clock_capable_pin - - - C_PHASESHIFT_MODE - WAVEFORM - - - C_SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - C_CLKFB_IN_SIGNALING - SINGLE - - - C_USE_RESET - 1 - - - C_RESET_LOW - 0 - - - C_USE_LOCKED - 1 - - - C_USE_INCLK_STOPPED - 0 - - - C_USE_CLKFB_STOPPED - 0 - - - C_USE_POWER_DOWN - 0 - - - C_USE_STATUS - 0 - - - C_USE_FREEZE - 0 - - - C_NUM_OUT_CLKS - 6 - - - C_CLKOUT1_DRIVES - BUFG - - - C_CLKOUT2_DRIVES - BUFG - - - C_CLKOUT3_DRIVES - BUFG - - - C_CLKOUT4_DRIVES - BUFG - - - C_CLKOUT5_DRIVES - BUFG - - - C_CLKOUT6_DRIVES - BUFG - - - C_CLKOUT7_DRIVES - BUFG - - - C_INCLK_SUM_ROW0 - Input Clock Freq (MHz) Input Jitter (UI) - - - C_INCLK_SUM_ROW1 - __primary_________100.000____________0.010 - - - C_INCLK_SUM_ROW2 - no_secondary_input_clock - - - C_OUTCLK_SUM_ROW0A - C Outclk Sum Row0a - Output Output Phase Duty Cycle Pk-to-Pk Phase - - - C_OUTCLK_SUM_ROW0B - Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - - - C_OUTCLK_SUM_ROW1 - clk_out1_____6.250______0.000______50.0______251.196____114.212 - - - C_OUTCLK_SUM_ROW2 - clk_out2____15.094______0.000______50.0______211.677____114.212 - - - C_OUTCLK_SUM_ROW3 - clk_out3____50.000______0.000______50.0______167.017____114.212 - - - C_OUTCLK_SUM_ROW4 - clk_out4___160.000______0.000______50.0______131.841____114.212 - - - C_OUTCLK_SUM_ROW5 - clk_out5___266.667______0.000______50.0______119.853____114.212 - - - C_OUTCLK_SUM_ROW6 - clk_out6___400.000______0.000______50.0______111.164____114.212 - - - C_OUTCLK_SUM_ROW7 - no_CLK_OUT7_output - - - C_CLKOUT1_REQUESTED_OUT_FREQ - 6.25 - - - C_CLKOUT2_REQUESTED_OUT_FREQ - 15 - - - C_CLKOUT3_REQUESTED_OUT_FREQ - 50 - - - C_CLKOUT4_REQUESTED_OUT_FREQ - 150 - - - C_CLKOUT5_REQUESTED_OUT_FREQ - 300 - - - C_CLKOUT6_REQUESTED_OUT_FREQ - 450 - - - C_CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT1_REQUESTED_PHASE - 0.000 - - - C_CLKOUT2_REQUESTED_PHASE - 0.000 - - - C_CLKOUT3_REQUESTED_PHASE - 0.000 - - - C_CLKOUT4_REQUESTED_PHASE - 0.000 - - - C_CLKOUT5_REQUESTED_PHASE - 0.000 - - - C_CLKOUT6_REQUESTED_PHASE - 0.000 - - - C_CLKOUT7_REQUESTED_PHASE - 0.000 - - - C_CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT1_OUT_FREQ - 6.250 - - - C_CLKOUT2_OUT_FREQ - 15.094 - - - C_CLKOUT3_OUT_FREQ - 50.000 - - - C_CLKOUT4_OUT_FREQ - 160.000 - - - C_CLKOUT5_OUT_FREQ - 266.667 - - - C_CLKOUT6_OUT_FREQ - 400.000 - - - C_CLKOUT7_OUT_FREQ - 100.000 - - - C_CLKOUT1_PHASE - 0.000 - - - C_CLKOUT2_PHASE - 0.000 - - - C_CLKOUT3_PHASE - 0.000 - - - C_CLKOUT4_PHASE - 0.000 - - - C_CLKOUT5_PHASE - 0.000 - - - C_CLKOUT6_PHASE - 0.000 - - - C_CLKOUT7_PHASE - 0.000 - - - C_CLKOUT1_DUTY_CYCLE - 50.0 - - - C_CLKOUT2_DUTY_CYCLE - 50.0 - - - C_CLKOUT3_DUTY_CYCLE - 50.0 - - - C_CLKOUT4_DUTY_CYCLE - 50.0 - - - C_CLKOUT5_DUTY_CYCLE - 50.0 - - - C_CLKOUT6_DUTY_CYCLE - 50.0 - - - C_CLKOUT7_DUTY_CYCLE - 50.000 - - - C_USE_SAFE_CLOCK_STARTUP - 0 - - - C_USE_CLOCK_SEQUENCING - 0 - - - C_CLKOUT1_SEQUENCE_NUMBER - 1 - - - C_CLKOUT2_SEQUENCE_NUMBER - 1 - - - C_CLKOUT3_SEQUENCE_NUMBER - 1 - - - C_CLKOUT4_SEQUENCE_NUMBER - 1 - - - C_CLKOUT5_SEQUENCE_NUMBER - 1 - - - C_CLKOUT6_SEQUENCE_NUMBER - 1 - - - C_CLKOUT7_SEQUENCE_NUMBER - 1 - - - C_MMCM_NOTES - None - - - C_MMCM_BANDWIDTH - OPTIMIZED - - - C_MMCM_CLKFBOUT_MULT_F - 8.000 - - - C_MMCM_CLKIN1_PERIOD - 10.0 - - - C_MMCM_CLKIN2_PERIOD - 10.0 - - - C_MMCM_CLKOUT4_CASCADE - FALSE - - - C_MMCM_CLOCK_HOLD - FALSE - - - C_MMCM_COMPENSATION - ZHOLD - - - C_MMCM_DIVCLK_DIVIDE - 1 - - - C_MMCM_REF_JITTER1 - 0.010 - - - C_MMCM_REF_JITTER2 - 0.010 - - - C_MMCM_STARTUP_WAIT - FALSE - - - C_MMCM_CLKOUT0_DIVIDE_F - 128.000 - - - C_MMCM_CLKOUT1_DIVIDE - 53 - - - C_MMCM_CLKOUT2_DIVIDE - 16 - - - C_MMCM_CLKOUT3_DIVIDE - 5 - - - C_MMCM_CLKOUT4_DIVIDE - 3 - - - C_MMCM_CLKOUT5_DIVIDE - 2 - - - C_MMCM_CLKOUT6_DIVIDE - 1 - - - C_MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKFBOUT_PHASE - 0.000 - - - C_MMCM_CLKOUT0_PHASE - 0.000 - - - C_MMCM_CLKOUT1_PHASE - 0.000 - - - C_MMCM_CLKOUT2_PHASE - 0.000 - - - C_MMCM_CLKOUT3_PHASE - 0.000 - - - C_MMCM_CLKOUT4_PHASE - 0.000 - - - C_MMCM_CLKOUT5_PHASE - 0.000 - - - C_MMCM_CLKOUT6_PHASE - 0.000 - - - C_MMCM_CLKFBOUT_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT0_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT1_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT2_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT3_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT4_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT5_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT6_USE_FINE_PS - FALSE - - - C_PLL_NOTES - No notes - - - C_PLL_BANDWIDTH - OPTIMIZED - - - C_PLL_CLK_FEEDBACK - CLKFBOUT - - - C_PLL_CLKFBOUT_MULT - 1 - - - C_PLL_CLKIN_PERIOD - 1.000 - - - C_PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - C_PLL_DIVCLK_DIVIDE - 1 - - - C_PLL_REF_JITTER - 0.010 - - - C_PLL_CLKOUT0_DIVIDE - 1 - - - C_PLL_CLKOUT1_DIVIDE - 1 - - - C_PLL_CLKOUT2_DIVIDE - 1 - - - C_PLL_CLKOUT3_DIVIDE - 1 - - - C_PLL_CLKOUT4_DIVIDE - 1 - - - C_PLL_CLKOUT5_DIVIDE - 1 - - - C_PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_PLL_CLKFBOUT_PHASE - 0.000 - - - C_PLL_CLKOUT0_PHASE - 0.000 - - - C_PLL_CLKOUT1_PHASE - 0.000 - - - C_PLL_CLKOUT2_PHASE - 0.000 - - - C_PLL_CLKOUT3_PHASE - 0.000 - - - C_PLL_CLKOUT4_PHASE - 0.000 - - - C_PLL_CLKOUT5_PHASE - 0.000 - - - C_CLOCK_MGR_TYPE - NA - - - C_OVERRIDE_MMCM - 0 - - - C_OVERRIDE_PLL - 0 - - - C_PRIMARY_PORT - clk_in1 - - - C_SECONDARY_PORT - clk_in2 - - - C_CLK_OUT1_PORT - clk_out1 - - - C_CLK_OUT2_PORT - clk_out2 - - - C_CLK_OUT3_PORT - clk_out3 - - - C_CLK_OUT4_PORT - clk_out4 - - - C_CLK_OUT5_PORT - clk_out5 - - - C_CLK_OUT6_PORT - clk_out6 - - - C_CLK_OUT7_PORT - clk_out7 - - - C_RESET_PORT - reset - - - C_LOCKED_PORT - locked - - - C_CLKFB_IN_PORT - clkfb_in - - - C_CLKFB_IN_P_PORT - clkfb_in_p - - - C_CLKFB_IN_N_PORT - clkfb_in_n - - - C_CLKFB_OUT_PORT - clkfb_out - - - C_CLKFB_OUT_P_PORT - clkfb_out_p - - - C_CLKFB_OUT_N_PORT - clkfb_out_n - - - C_POWER_DOWN_PORT - power_down - - - C_DADDR_PORT - daddr - - - C_DCLK_PORT - dclk - - - C_DRDY_PORT - drdy - - - C_DWE_PORT - dwe - - - C_DIN_PORT - din - - - C_DOUT_PORT - dout - - - C_DEN_PORT - den - - - C_PSCLK_PORT - psclk - - - C_PSEN_PORT - psen - - - C_PSINCDEC_PORT - psincdec - - - C_PSDONE_PORT - psdone - - - C_CLK_VALID_PORT - CLK_VALID - - - C_STATUS_PORT - STATUS - - - C_CLK_IN_SEL_PORT - clk_in_sel - - - C_INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - C_CLKFB_STOPPED_PORT - clkfb_stopped - - - C_CLKIN1_JITTER_PS - 100.0 - - - C_CLKIN2_JITTER_PS - 100.0 - - - C_PRIMITIVE - PLL - - - C_SS_MODE - CENTER_HIGH - - - C_SS_MOD_PERIOD - 4000 - - - C_SS_MOD_TIME - 0.004 - - - C_HAS_CDDC - 0 - - - C_CDDCDONE_PORT - cddcdone - - - C_CDDCREQ_PORT - cddcreq - - - C_CLKOUTPHY_MODE - VCO - - - C_ENABLE_CLKOUTPHY - 0 - - - C_INTERFACE_SELECTION - 0 - - - C_S_AXI_ADDR_WIDTH - C S Axi Addr Width - 11 - - - C_S_AXI_DATA_WIDTH - C S Axi Data Width - 32 - - - C_POWER_REG - 0000 - - - C_CLKOUT0_1 - 0000 - - - C_CLKOUT0_2 - 0000 - - - C_CLKOUT1_1 - 0000 - - - C_CLKOUT1_2 - 0000 - - - C_CLKOUT2_1 - 0000 - - - C_CLKOUT2_2 - 0000 - - - C_CLKOUT3_1 - 0000 - - - C_CLKOUT3_2 - 0000 - - - C_CLKOUT4_1 - 0000 - - - C_CLKOUT4_2 - 0000 - - - C_CLKOUT5_1 - 0000 - - - C_CLKOUT5_2 - 0000 - - - C_CLKOUT6_1 - 0000 - - - C_CLKOUT6_2 - 0000 - - - C_CLKFBOUT_1 - 0000 - - - C_CLKFBOUT_2 - 0000 - - - C_DIVCLK - 0000 - - - C_LOCK_1 - 0000 - - - C_LOCK_2 - 0000 - - - C_LOCK_3 - 0000 - - - C_FILTER_1 - 0000 - - - C_FILTER_2 - 0000 - - - C_DIVIDE1_AUTO - 1 - - - C_DIVIDE2_AUTO - 0.4166666666666667 - - - C_DIVIDE3_AUTO - 0.125 - - - C_DIVIDE4_AUTO - 0.041666666666666664 - - - C_DIVIDE5_AUTO - 0.020833333333333332 - - - C_DIVIDE6_AUTO - 0.013888888888888888 - - - C_DIVIDE7_AUTO - 0.0625 - - - C_PLLBUFGCEDIV - false - - - C_MMCMBUFGCEDIV - false - - - C_PLLBUFGCEDIV1 - false - - - C_PLLBUFGCEDIV2 - false - - - C_PLLBUFGCEDIV3 - false - - - C_PLLBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV1 - false - - - C_MMCMBUFGCEDIV2 - false - - - C_MMCMBUFGCEDIV3 - false - - - C_MMCMBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV5 - false - - - C_MMCMBUFGCEDIV6 - false - - - C_MMCMBUFGCEDIV7 - false - - - C_CLKOUT1_MATCHED_ROUTING - false - - - C_CLKOUT2_MATCHED_ROUTING - false - - - C_CLKOUT3_MATCHED_ROUTING - false - - - C_CLKOUT4_MATCHED_ROUTING - false - - - C_CLKOUT5_MATCHED_ROUTING - false - - - C_CLKOUT6_MATCHED_ROUTING - false - - - C_CLKOUT7_MATCHED_ROUTING - false - - - C_CLKOUT0_ACTUAL_FREQ - 6.250 - - - C_CLKOUT1_ACTUAL_FREQ - 15.094 - - - C_CLKOUT2_ACTUAL_FREQ - 50.000 - - - C_CLKOUT3_ACTUAL_FREQ - 160.000 - - - C_CLKOUT4_ACTUAL_FREQ - 266.667 - - - C_CLKOUT5_ACTUAL_FREQ - 400.000 - - - C_CLKOUT6_ACTUAL_FREQ - 100.000 - - - - - - choice_list_1d3de01d - WAVEFORM - LATENCY - - - choice_list_876bfc32 - UI - PS - - - choice_list_a9bdfce0 - LOW - HIGH - OPTIMIZED - - - choice_list_ac75ef1e - Custom - - - choice_list_b9d38208 - CLKFBOUT - CLKOUT0 - - - choice_list_e099fe6c - MMCM - PLL - - - choice_pairs_035ca1c3 - SYSTEM_SYNCHRONOUS - SOURCE_SYNCHRONOUS - INTERNAL - EXTERNAL - - - choice_pairs_0920eb1b - Custom - sys_diff_clock - - - choice_pairs_11d71346 - Single_ended_clock_capable_pin - Differential_clock_capable_pin - Global_buffer - No_buffer - - - choice_pairs_15c806d5 - FDBK_AUTO - FDBK_AUTO_OFFCHIP - FDBK_ONCHIP - FDBK_OFFCHIP - - - choice_pairs_340369e0 - Custom - sys_clock - sys_diff_clock - - - choice_pairs_3c2d3ec7 - SINGLE - DIFF - - - choice_pairs_502d9f23 - ZHOLD - EXTERNAL - INTERNAL - BUF_IN - - - choice_pairs_66e4c81f - BUFG - BUFH - BUFGCE - BUFHCE - No_buffer - - - choice_pairs_77d3d587 - MMCM - PLL - BUFGCE_DIV - - - choice_pairs_8b28f1f7 - Enable_AXI - Enable_DRP - - - choice_pairs_8eea9b32 - Units_MHz - Units_ns - - - choice_pairs_a4fbc00c - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_a8642b4c - No_Jitter - Min_O_Jitter - Max_I_Jitter - - - choice_pairs_c5ef7212 - Units_UI - Units_ps - - - choice_pairs_e1c87518 - REL_PRIMARY - REL_SECONDARY - - - choice_pairs_f4e10086 - CENTER_HIGH - CENTER_LOW - DOWN_HIGH - DOWN_LOW - - - choice_pairs_f669c2f5 - frequency - Time - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - clk_wiz_0.veo - verilogTemplate - - - - xilinx_anylanguagesynthesis_view_fileset - - clk_wiz_0.xdc - xdc - - processing_order - early - - - - clk_wiz_0_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - mmcm_pll_drp_func_7s_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_7s_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - clk_wiz_0_clk_wiz.v - verilogSource - - - - xilinx_anylanguagesynthesiswrapper_view_fileset - - clk_wiz_0.v - verilogSource - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - mmcm_pll_drp_func_7s_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_7s_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - clk_wiz_0_clk_wiz.v - verilogSource - - - - xilinx_anylanguagesimulationwrapper_view_fileset - - clk_wiz_0.v - verilogSource - - - - xilinx_implementation_view_fileset - - clk_wiz_0_board.xdc - xdc - USED_IN_board - USED_IN_implementation - USED_IN_synthesis - - - - xilinx_versioninformation_view_fileset - - doc/clk_wiz_v6_0_changelog.txt - text - - - - xilinx_externalfiles_view_fileset - - clk_wiz_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - clk_wiz_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - clk_wiz_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - clk_wiz_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - clk_wiz_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. - - - Component_Name - clk_wiz_0 - - - USER_CLK_FREQ0 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ1 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ2 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ3 - User Frequency(MHz) - 100.0 - - - ENABLE_CLOCK_MONITOR - Enable Clock Monitoring - false - - - ENABLE_USER_CLOCK0 - User Clock - false - - - ENABLE_USER_CLOCK1 - User Clock - false - - - ENABLE_USER_CLOCK2 - User Clock - false - - - ENABLE_USER_CLOCK3 - User Clock - false - - - Enable_PLL0 - User Clock - false - - - Enable_PLL1 - User Clock - false - - - REF_CLK_FREQ - Reference Frequency(MHz) - 100.0 - - - PRECISION - Tolerance(MHz) - 1 - - - PRIMITIVE - Primitive - PLL - - - PRIMTYPE_SEL - Primtype Sel - mmcm_adv - - - CLOCK_MGR_TYPE - Clock Mgr Type - auto - - - USE_FREQ_SYNTH - false - - - USE_SPREAD_SPECTRUM - false - - - USE_PHASE_ALIGNMENT - false - - - USE_MIN_POWER - false - - - USE_DYN_PHASE_SHIFT - false - - - USE_DYN_RECONFIG - false - - - JITTER_SEL - No_Jitter - - - PRIM_IN_FREQ - 100.000 - - - PRIM_IN_TIMEPERIOD - 10.000 - - - IN_FREQ_UNITS - Units_MHz - - - PHASESHIFT_MODE - WAVEFORM - - - IN_JITTER_UNITS - Units_UI - - - RELATIVE_INCLK - REL_PRIMARY - - - USE_INCLK_SWITCHOVER - false - - - SECONDARY_IN_FREQ - 100.000 - - - SECONDARY_IN_TIMEPERIOD - 10.000 - - - SECONDARY_PORT - clk_in2 - - - SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - JITTER_OPTIONS - UI - - - CLKIN1_UI_JITTER - 0.010 - - - CLKIN2_UI_JITTER - 0.010 - - - PRIM_IN_JITTER - 0.010 - - - SECONDARY_IN_JITTER - 0.010 - - - CLKIN1_JITTER_PS - 100.0 - - - CLKIN2_JITTER_PS - 100.0 - - - CLKOUT1_USED - true - - - CLKOUT2_USED - true - - - CLKOUT3_USED - true - - - CLKOUT4_USED - true - - - CLKOUT5_USED - true - - - CLKOUT6_USED - true - - - CLKOUT7_USED - false - - - NUM_OUT_CLKS - 6 - - - CLK_OUT1_USE_FINE_PS_GUI - false - - - CLK_OUT2_USE_FINE_PS_GUI - false - - - CLK_OUT3_USE_FINE_PS_GUI - false - - - CLK_OUT4_USE_FINE_PS_GUI - false - - - CLK_OUT5_USE_FINE_PS_GUI - false - - - CLK_OUT6_USE_FINE_PS_GUI - false - - - CLK_OUT7_USE_FINE_PS_GUI - false - - - PRIMARY_PORT - clk_in1 - - - CLK_OUT1_PORT - clk_out1 - - - CLK_OUT2_PORT - clk_out2 - - - CLK_OUT3_PORT - clk_out3 - - - CLK_OUT4_PORT - clk_out4 - - - CLK_OUT5_PORT - clk_out5 - - - CLK_OUT6_PORT - clk_out6 - - - CLK_OUT7_PORT - clk_out7 - - - DADDR_PORT - daddr - - - DCLK_PORT - dclk - - - DRDY_PORT - drdy - - - DWE_PORT - dwe - - - DIN_PORT - din - - - DOUT_PORT - dout - - - DEN_PORT - den - - - PSCLK_PORT - psclk - - - PSEN_PORT - psen - - - PSINCDEC_PORT - psincdec - - - PSDONE_PORT - psdone - - - CLKOUT1_REQUESTED_OUT_FREQ - 6.25 - - - CLKOUT1_REQUESTED_PHASE - 0.000 - - - CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT2_REQUESTED_OUT_FREQ - 15 - - - CLKOUT2_REQUESTED_PHASE - 0.000 - - - CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT3_REQUESTED_OUT_FREQ - 50 - - - CLKOUT3_REQUESTED_PHASE - 0.000 - - - CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT4_REQUESTED_OUT_FREQ - 150 - - - CLKOUT4_REQUESTED_PHASE - 0.000 - - - CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT5_REQUESTED_OUT_FREQ - 300 - - - CLKOUT5_REQUESTED_PHASE - 0.000 - - - CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT6_REQUESTED_OUT_FREQ - 450 - - - CLKOUT6_REQUESTED_PHASE - 0.000 - - - CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT7_REQUESTED_PHASE - 0.000 - - - CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - USE_MAX_I_JITTER - false - - - USE_MIN_O_JITTER - false - - - CLKOUT1_MATCHED_ROUTING - false - - - CLKOUT2_MATCHED_ROUTING - false - - - CLKOUT3_MATCHED_ROUTING - false - - - CLKOUT4_MATCHED_ROUTING - false - - - CLKOUT5_MATCHED_ROUTING - false - - - CLKOUT6_MATCHED_ROUTING - false - - - CLKOUT7_MATCHED_ROUTING - false - - - PRIM_SOURCE - Single_ended_clock_capable_pin - - - CLKOUT1_DRIVES - BUFG - - - CLKOUT2_DRIVES - BUFG - - - CLKOUT3_DRIVES - BUFG - - - CLKOUT4_DRIVES - BUFG - - - CLKOUT5_DRIVES - BUFG - - - CLKOUT6_DRIVES - BUFG - - - CLKOUT7_DRIVES - BUFG - - - FEEDBACK_SOURCE - FDBK_AUTO - - - CLKFB_IN_SIGNALING - SINGLE - - - CLKFB_IN_PORT - clkfb_in - - - CLKFB_IN_P_PORT - clkfb_in_p - - - CLKFB_IN_N_PORT - clkfb_in_n - - - CLKFB_OUT_PORT - clkfb_out - - - CLKFB_OUT_P_PORT - clkfb_out_p - - - CLKFB_OUT_N_PORT - clkfb_out_n - - - PLATFORM - UNKNOWN - - - SUMMARY_STRINGS - empty - - - USE_LOCKED - true - - - CALC_DONE - empty - - - USE_RESET - true - - - USE_POWER_DOWN - false - - - USE_STATUS - false - - - USE_FREEZE - false - - - USE_CLK_VALID - false - - - USE_INCLK_STOPPED - false - - - USE_CLKFB_STOPPED - false - - - RESET_PORT - reset - - - LOCKED_PORT - locked - - - POWER_DOWN_PORT - power_down - - - CLK_VALID_PORT - CLK_VALID - - - STATUS_PORT - STATUS - - - CLK_IN_SEL_PORT - clk_in_sel - - - INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - CLKFB_STOPPED_PORT - clkfb_stopped - - - SS_MODE - CENTER_HIGH - - - SS_MOD_FREQ - 250 - - - SS_MOD_TIME - 0.004 - - - OVERRIDE_MMCM - false - - - MMCM_NOTES - None - - - MMCM_DIVCLK_DIVIDE - 1 - - - MMCM_BANDWIDTH - OPTIMIZED - - - MMCM_CLKFBOUT_MULT_F - 8 - - - MMCM_CLKFBOUT_PHASE - 0.000 - - - MMCM_CLKFBOUT_USE_FINE_PS - false - - - MMCM_CLKIN1_PERIOD - 10.0 - - - MMCM_CLKIN2_PERIOD - 10.0 - - - MMCM_CLKOUT4_CASCADE - false - - - MMCM_CLOCK_HOLD - false - - - MMCM_COMPENSATION - ZHOLD - - - MMCM_REF_JITTER1 - 0.010 - - - MMCM_REF_JITTER2 - 0.010 - - - MMCM_STARTUP_WAIT - false - - - MMCM_CLKOUT0_DIVIDE_F - 128 - - - MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT0_PHASE - 0.000 - - - MMCM_CLKOUT0_USE_FINE_PS - false - - - MMCM_CLKOUT1_DIVIDE - 53 - - - MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT1_PHASE - 0.000 - - - MMCM_CLKOUT1_USE_FINE_PS - false - - - MMCM_CLKOUT2_DIVIDE - 16 - - - MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT2_PHASE - 0.000 - - - MMCM_CLKOUT2_USE_FINE_PS - false - - - MMCM_CLKOUT3_DIVIDE - 5 - - - MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT3_PHASE - 0.000 - - - MMCM_CLKOUT3_USE_FINE_PS - false - - - MMCM_CLKOUT4_DIVIDE - 3 - - - MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT4_PHASE - 0.000 - - - MMCM_CLKOUT4_USE_FINE_PS - false - - - MMCM_CLKOUT5_DIVIDE - 2 - - - MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT5_PHASE - 0.000 - - - MMCM_CLKOUT5_USE_FINE_PS - false - - - MMCM_CLKOUT6_DIVIDE - 1 - - - MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT6_PHASE - 0.000 - - - MMCM_CLKOUT6_USE_FINE_PS - false - - - OVERRIDE_PLL - false - - - PLL_NOTES - None - - - PLL_BANDWIDTH - OPTIMIZED - - - PLL_CLKFBOUT_MULT - 4 - - - PLL_CLKFBOUT_PHASE - 0.000 - - - PLL_CLK_FEEDBACK - CLKFBOUT - - - PLL_DIVCLK_DIVIDE - 1 - - - PLL_CLKIN_PERIOD - 10.000 - - - PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - PLL_REF_JITTER - 0.010 - - - PLL_CLKOUT0_DIVIDE - 1 - - - PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT0_PHASE - 0.000 - - - PLL_CLKOUT1_DIVIDE - 1 - - - PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT1_PHASE - 0.000 - - - PLL_CLKOUT2_DIVIDE - 1 - - - PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT2_PHASE - 0.000 - - - PLL_CLKOUT3_DIVIDE - 1 - - - PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT3_PHASE - 0.000 - - - PLL_CLKOUT4_DIVIDE - 1 - - - PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT4_PHASE - 0.000 - - - PLL_CLKOUT5_DIVIDE - 1 - - - PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT5_PHASE - 0.000 - - - RESET_TYPE - Reset Type - ACTIVE_HIGH - - - USE_SAFE_CLOCK_STARTUP - false - - - USE_CLOCK_SEQUENCING - false - - - CLKOUT1_SEQUENCE_NUMBER - 1 - - - CLKOUT2_SEQUENCE_NUMBER - 1 - - - CLKOUT3_SEQUENCE_NUMBER - 1 - - - CLKOUT4_SEQUENCE_NUMBER - 1 - - - CLKOUT5_SEQUENCE_NUMBER - 1 - - - CLKOUT6_SEQUENCE_NUMBER - 1 - - - CLKOUT7_SEQUENCE_NUMBER - 1 - - - USE_BOARD_FLOW - Generate Board based IO Constraints - false - - - CLK_IN1_BOARD_INTERFACE - Custom - - - CLK_IN2_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN1_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN2_BOARD_INTERFACE - Custom - - - AUTO_PRIMITIVE - MMCM - - - RESET_BOARD_INTERFACE - Custom - - - ENABLE_CDDC - false - - - CDDCDONE_PORT - cddcdone - - - CDDCREQ_PORT - cddcreq - - - ENABLE_CLKOUTPHY - false - - - CLKOUTPHY_REQUESTED_FREQ - 600.000 - - - CLKOUT1_JITTER - Clkout1 Jitter - 251.196 - - - CLKOUT1_PHASE_ERROR - Clkout1 Phase - 114.212 - - - CLKOUT2_JITTER - Clkout2 Jitter - 211.677 - - - CLKOUT2_PHASE_ERROR - Clkout2 Phase - 114.212 - - - CLKOUT3_JITTER - Clkout3 Jitter - 167.017 - - - CLKOUT3_PHASE_ERROR - Clkout3 Phase - 114.212 - - - CLKOUT4_JITTER - Clkout4 Jitter - 131.841 - - - CLKOUT4_PHASE_ERROR - Clkout4 Phase - 114.212 - - - CLKOUT5_JITTER - Clkout5 Jitter - 119.853 - - - CLKOUT5_PHASE_ERROR - Clkout5 Phase - 114.212 - - - CLKOUT6_JITTER - Clkout6 Jitter - 111.164 - - - CLKOUT6_PHASE_ERROR - Clkout6 Phase - 114.212 - - - CLKOUT7_JITTER - Clkout7 Jitter - 0.0 - - - CLKOUT7_PHASE_ERROR - Clkout7 Phase - 0.0 - - - INPUT_MODE - frequency - - - INTERFACE_SELECTION - Enable_AXI - - - AXI_DRP - Write DRP registers - false - - - PHASE_DUTY_CONFIG - Phase Duty Cycle Config - false - - - - - Clocking Wizard - - XPM_CDC - - 3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.1.1 - - - - - - - - diff --git a/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1.xml b/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1.xml deleted file mode 100644 index 2639485..0000000 --- a/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1.xml +++ /dev/null @@ -1,5360 +0,0 @@ - - - xilinx.com - customized_ip - clk_wiz_1 - 1.0 - - - s_axi_lite - S_AXI_LITE - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARREADY - - - s_axi_arready - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWREADY - - - s_axi_awready - - - - - AWVALID - - - s_axi_awvalid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 1 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 1 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 0 - - - none - - - - - HAS_BRESP - 0 - - - none - - - - - HAS_RRESP - 0 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_aclk - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi_lite - - - ASSOCIATED_RESET - s_axi_aresetn - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - ref_clk - ref_clk - - - - - - - CLK - - - ref_clk - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_resetn - S_AXI_RESETN - - - - - - - RST - - - s_axi_aresetn - - - - - - ASSOCIATED_RESET - aresetn - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - intr - Intr - - - - - - - INTERRUPT - - - ip2intc_irpt - - - - - - SENSITIVITY - LEVEL_HIGH - - - none - - - - - PortWidth - 1 - - - none - - - - - - - - false - - - - - - CLK_IN1_D - CLK_IN1_D - Differential Clock input - - - - - - - CLK_N - - - clk_in1_n - - - - - CLK_P - - - clk_in1_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN1_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLK_IN2_D - CLK_IN2_D - Differential Clock input - - - - - - - CLK_N - - - clk_in2_n - - - - - CLK_P - - - clk_in2_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN2_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_IN_D - CLKFB_IN_D - Differential Feedback Clock input - - - - - - - CLK_N - - - clkfb_in_n - - - - - CLK_P - - - clkfb_in_p - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_OUT_D - CLKFB_OUT_D - Differential Feeback Clock Output - - - - - - - CLK_N - - - clkfb_out_n - - - - - CLK_P - - - clkfb_out_p - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - reset - reset - - - - - - - RST - - - reset - - - - - - POLARITY - ACTIVE_HIGH - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - resetn - resetn - - - - - - - RST - - - resetn - - - - - - POLARITY - ACTIVE_LOW - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - clock_CLK_IN1 - - - - - - - CLK_IN1 - - - clk_in1 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN1_BOARD_INTERFACE - - - - - clock_CLK_OUT1 - - - - - - - CLK_OUT1 - - - clk_out1 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT2 - - - - - - - CLK_OUT2 - - - clk_out2 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT3 - - - - - - - CLK_OUT3 - - - clk_out3 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT4 - - - - - - - CLK_OUT4 - - - clk_out4 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT5 - - - - - - - CLK_OUT5 - - - clk_out5 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT6 - - - - - - - CLK_OUT6 - - - clk_out6 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - xilinx_elaborateports - Elaborate Ports - :vivado.xilinx.com:elaborate.ports - - - outputProductCRC - 9:1abd837a - - - - - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog - clk_wiz_v6_0_3 - - xilinx_veriloginstantiationtemplate_view_fileset - - - - GENtimestamp - Sat Sep 14 02:43:34 UTC 2019 - - - outputProductCRC - 9:636d2344 - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - clk_wiz_v6_0_3 - - xilinx_anylanguagesynthesis_view_fileset - - - - GENtimestamp - Sat Sep 14 02:43:34 UTC 2019 - - - outputProductCRC - 9:636d2344 - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - - outputProductCRC - 9:636d2344 - - - - - xilinx_anylanguagesynthesiswrapper - Synthesis Wrapper - :vivado.xilinx.com:synthesis.wrapper - clk_wiz_1 - - xilinx_anylanguagesynthesiswrapper_view_fileset - - - - GENtimestamp - Sat Sep 14 02:43:35 UTC 2019 - - - outputProductCRC - 9:636d2344 - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - clk_wiz_v6_0_3 - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - GENtimestamp - Sat Sep 14 02:43:34 UTC 2019 - - - outputProductCRC - 9:6d930546 - - - - - xilinx_anylanguagesimulationwrapper - Simulation Wrapper - :vivado.xilinx.com:simulation.wrapper - clk_wiz_1 - - xilinx_anylanguagesimulationwrapper_view_fileset - - - - GENtimestamp - Sat Sep 14 02:43:35 UTC 2019 - - - outputProductCRC - 9:6d930546 - - - - - xilinx_implementation - Implementation - :vivado.xilinx.com:implementation - - xilinx_implementation_view_fileset - - - - GENtimestamp - Sat Sep 14 02:43:35 UTC 2019 - - - outputProductCRC - 9:636d2344 - - - - - xilinx_versioninformation - Version Information - :vivado.xilinx.com:docs.versioninfo - - xilinx_versioninformation_view_fileset - - - - GENtimestamp - Sat Sep 14 02:43:35 UTC 2019 - - - outputProductCRC - 9:636d2344 - - - - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Sat Sep 14 02:44:46 UTC 2019 - - - outputProductCRC - 9:636d2344 - - - - - - - s_axi_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awaddr - - in - - 10 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_bvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_bready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_araddr - - in - - 10 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_rvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_rready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in1_p - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in1_n - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in2_p - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in2_n - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clkfb_in_p - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clkfb_in_n - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clkfb_out_p - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - clkfb_out_n - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - reset - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - resetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - ref_clk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_stop - - out - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_glitch - - out - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - interrupt - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_oor - - out - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - user_clk0 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - user_clk1 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - user_clk2 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - user_clk3 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in1 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - clk_out1 - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - clk_out2 - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - clk_out3 - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - clk_out4 - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - clk_out5 - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - clk_out6 - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - locked - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - C_CLKOUT2_USED - 1 - - - C_USER_CLK_FREQ0 - 100.0 - - - C_AUTO_PRIMITIVE - MMCM - - - C_USER_CLK_FREQ1 - 100.0 - - - C_USER_CLK_FREQ2 - 100.0 - - - C_USER_CLK_FREQ3 - 100.0 - - - C_ENABLE_CLOCK_MONITOR - 0 - - - C_ENABLE_USER_CLOCK0 - 0 - - - C_ENABLE_USER_CLOCK1 - 0 - - - C_ENABLE_USER_CLOCK2 - 0 - - - C_ENABLE_USER_CLOCK3 - 0 - - - C_Enable_PLL0 - 0 - - - C_Enable_PLL1 - 0 - - - C_REF_CLK_FREQ - 100.0 - - - C_PRECISION - 1 - - - C_CLKOUT3_USED - 1 - - - C_CLKOUT4_USED - 1 - - - C_CLKOUT5_USED - 1 - - - C_CLKOUT6_USED - 1 - - - C_CLKOUT7_USED - 0 - - - C_USE_CLKOUT1_BAR - 0 - - - C_USE_CLKOUT2_BAR - 0 - - - C_USE_CLKOUT3_BAR - 0 - - - C_USE_CLKOUT4_BAR - 0 - - - c_component_name - clk_wiz_1 - - - C_PLATFORM - UNKNOWN - - - C_USE_FREQ_SYNTH - 1 - - - C_USE_PHASE_ALIGNMENT - 1 - - - C_PRIM_IN_JITTER - 0.010 - - - C_SECONDARY_IN_JITTER - 0.010 - - - C_JITTER_SEL - No_Jitter - - - C_USE_MIN_POWER - 0 - - - C_USE_MIN_O_JITTER - 0 - - - C_USE_MAX_I_JITTER - 0 - - - C_USE_DYN_PHASE_SHIFT - 0 - - - C_USE_INCLK_SWITCHOVER - 0 - - - C_USE_DYN_RECONFIG - 0 - - - C_USE_SPREAD_SPECTRUM - 0 - - - C_USE_FAST_SIMULATION - 0 - - - C_PRIMTYPE_SEL - AUTO - - - C_USE_CLK_VALID - 0 - - - C_PRIM_IN_FREQ - 100.000 - - - C_PRIM_IN_TIMEPERIOD - 10.000 - - - C_IN_FREQ_UNITS - Units_MHz - - - C_SECONDARY_IN_FREQ - 100.000 - - - C_SECONDARY_IN_TIMEPERIOD - 10.000 - - - C_FEEDBACK_SOURCE - FDBK_AUTO - - - C_PRIM_SOURCE - Single_ended_clock_capable_pin - - - C_PHASESHIFT_MODE - WAVEFORM - - - C_SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - C_CLKFB_IN_SIGNALING - SINGLE - - - C_USE_RESET - 1 - - - C_RESET_LOW - 0 - - - C_USE_LOCKED - 1 - - - C_USE_INCLK_STOPPED - 0 - - - C_USE_CLKFB_STOPPED - 0 - - - C_USE_POWER_DOWN - 0 - - - C_USE_STATUS - 0 - - - C_USE_FREEZE - 0 - - - C_NUM_OUT_CLKS - 6 - - - C_CLKOUT1_DRIVES - BUFH - - - C_CLKOUT2_DRIVES - BUFH - - - C_CLKOUT3_DRIVES - BUFH - - - C_CLKOUT4_DRIVES - BUFH - - - C_CLKOUT5_DRIVES - BUFH - - - C_CLKOUT6_DRIVES - BUFH - - - C_CLKOUT7_DRIVES - BUFG - - - C_INCLK_SUM_ROW0 - Input Clock Freq (MHz) Input Jitter (UI) - - - C_INCLK_SUM_ROW1 - __primary_________100.000____________0.010 - - - C_INCLK_SUM_ROW2 - no_secondary_input_clock - - - C_OUTCLK_SUM_ROW0A - C Outclk Sum Row0a - Output Output Phase Duty Cycle Pk-to-Pk Phase - - - C_OUTCLK_SUM_ROW0B - Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - - - C_OUTCLK_SUM_ROW1 - clk_out1____10.000______0.000______50.0______188.586_____87.180 - - - C_OUTCLK_SUM_ROW2 - clk_out2____50.000______0.000______50.0______132.683_____87.180 - - - C_OUTCLK_SUM_ROW3 - clk_out3___100.000______0.000______50.0______115.831_____87.180 - - - C_OUTCLK_SUM_ROW4 - clk_out4___150.000______0.000______50.0______107.567_____87.180 - - - C_OUTCLK_SUM_ROW5 - clk_out5___200.000______0.000______50.0______102.086_____87.180 - - - C_OUTCLK_SUM_ROW6 - clk_out6___240.000______0.000______50.0_______98.767_____87.180 - - - C_OUTCLK_SUM_ROW7 - no_CLK_OUT7_output - - - C_CLKOUT1_REQUESTED_OUT_FREQ - 10 - - - C_CLKOUT2_REQUESTED_OUT_FREQ - 50 - - - C_CLKOUT3_REQUESTED_OUT_FREQ - 100 - - - C_CLKOUT4_REQUESTED_OUT_FREQ - 150 - - - C_CLKOUT5_REQUESTED_OUT_FREQ - 200 - - - C_CLKOUT6_REQUESTED_OUT_FREQ - 250 - - - C_CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT1_REQUESTED_PHASE - 0.000 - - - C_CLKOUT2_REQUESTED_PHASE - 0.000 - - - C_CLKOUT3_REQUESTED_PHASE - 0.000 - - - C_CLKOUT4_REQUESTED_PHASE - 0.000 - - - C_CLKOUT5_REQUESTED_PHASE - 0.000 - - - C_CLKOUT6_REQUESTED_PHASE - 0.000 - - - C_CLKOUT7_REQUESTED_PHASE - 0.000 - - - C_CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT1_OUT_FREQ - 10.000 - - - C_CLKOUT2_OUT_FREQ - 50.000 - - - C_CLKOUT3_OUT_FREQ - 100.000 - - - C_CLKOUT4_OUT_FREQ - 150.000 - - - C_CLKOUT5_OUT_FREQ - 200.000 - - - C_CLKOUT6_OUT_FREQ - 240.000 - - - C_CLKOUT7_OUT_FREQ - 100.000 - - - C_CLKOUT1_PHASE - 0.000 - - - C_CLKOUT2_PHASE - 0.000 - - - C_CLKOUT3_PHASE - 0.000 - - - C_CLKOUT4_PHASE - 0.000 - - - C_CLKOUT5_PHASE - 0.000 - - - C_CLKOUT6_PHASE - 0.000 - - - C_CLKOUT7_PHASE - 0.000 - - - C_CLKOUT1_DUTY_CYCLE - 50.0 - - - C_CLKOUT2_DUTY_CYCLE - 50.0 - - - C_CLKOUT3_DUTY_CYCLE - 50.0 - - - C_CLKOUT4_DUTY_CYCLE - 50.0 - - - C_CLKOUT5_DUTY_CYCLE - 50.0 - - - C_CLKOUT6_DUTY_CYCLE - 50.0 - - - C_CLKOUT7_DUTY_CYCLE - 50.000 - - - C_USE_SAFE_CLOCK_STARTUP - 0 - - - C_USE_CLOCK_SEQUENCING - 0 - - - C_CLKOUT1_SEQUENCE_NUMBER - 1 - - - C_CLKOUT2_SEQUENCE_NUMBER - 1 - - - C_CLKOUT3_SEQUENCE_NUMBER - 1 - - - C_CLKOUT4_SEQUENCE_NUMBER - 1 - - - C_CLKOUT5_SEQUENCE_NUMBER - 1 - - - C_CLKOUT6_SEQUENCE_NUMBER - 1 - - - C_CLKOUT7_SEQUENCE_NUMBER - 1 - - - C_MMCM_NOTES - None - - - C_MMCM_BANDWIDTH - OPTIMIZED - - - C_MMCM_CLKFBOUT_MULT_F - 12.000 - - - C_MMCM_CLKIN1_PERIOD - 10.000 - - - C_MMCM_CLKIN2_PERIOD - 10.000 - - - C_MMCM_CLKOUT4_CASCADE - FALSE - - - C_MMCM_CLOCK_HOLD - FALSE - - - C_MMCM_COMPENSATION - ZHOLD - - - C_MMCM_DIVCLK_DIVIDE - 1 - - - C_MMCM_REF_JITTER1 - 0.010 - - - C_MMCM_REF_JITTER2 - 0.010 - - - C_MMCM_STARTUP_WAIT - FALSE - - - C_MMCM_CLKOUT0_DIVIDE_F - 120.000 - - - C_MMCM_CLKOUT1_DIVIDE - 24 - - - C_MMCM_CLKOUT2_DIVIDE - 12 - - - C_MMCM_CLKOUT3_DIVIDE - 8 - - - C_MMCM_CLKOUT4_DIVIDE - 6 - - - C_MMCM_CLKOUT5_DIVIDE - 5 - - - C_MMCM_CLKOUT6_DIVIDE - 1 - - - C_MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKFBOUT_PHASE - 0.000 - - - C_MMCM_CLKOUT0_PHASE - 0.000 - - - C_MMCM_CLKOUT1_PHASE - 0.000 - - - C_MMCM_CLKOUT2_PHASE - 0.000 - - - C_MMCM_CLKOUT3_PHASE - 0.000 - - - C_MMCM_CLKOUT4_PHASE - 0.000 - - - C_MMCM_CLKOUT5_PHASE - 0.000 - - - C_MMCM_CLKOUT6_PHASE - 0.000 - - - C_MMCM_CLKFBOUT_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT0_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT1_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT2_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT3_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT4_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT5_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT6_USE_FINE_PS - FALSE - - - C_PLL_NOTES - No notes - - - C_PLL_BANDWIDTH - OPTIMIZED - - - C_PLL_CLK_FEEDBACK - CLKFBOUT - - - C_PLL_CLKFBOUT_MULT - 1 - - - C_PLL_CLKIN_PERIOD - 1.000 - - - C_PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - C_PLL_DIVCLK_DIVIDE - 1 - - - C_PLL_REF_JITTER - 0.010 - - - C_PLL_CLKOUT0_DIVIDE - 1 - - - C_PLL_CLKOUT1_DIVIDE - 1 - - - C_PLL_CLKOUT2_DIVIDE - 1 - - - C_PLL_CLKOUT3_DIVIDE - 1 - - - C_PLL_CLKOUT4_DIVIDE - 1 - - - C_PLL_CLKOUT5_DIVIDE - 1 - - - C_PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_PLL_CLKFBOUT_PHASE - 0.000 - - - C_PLL_CLKOUT0_PHASE - 0.000 - - - C_PLL_CLKOUT1_PHASE - 0.000 - - - C_PLL_CLKOUT2_PHASE - 0.000 - - - C_PLL_CLKOUT3_PHASE - 0.000 - - - C_PLL_CLKOUT4_PHASE - 0.000 - - - C_PLL_CLKOUT5_PHASE - 0.000 - - - C_CLOCK_MGR_TYPE - NA - - - C_OVERRIDE_MMCM - 0 - - - C_OVERRIDE_PLL - 0 - - - C_PRIMARY_PORT - clk_in1 - - - C_SECONDARY_PORT - clk_in2 - - - C_CLK_OUT1_PORT - clk_out1 - - - C_CLK_OUT2_PORT - clk_out2 - - - C_CLK_OUT3_PORT - clk_out3 - - - C_CLK_OUT4_PORT - clk_out4 - - - C_CLK_OUT5_PORT - clk_out5 - - - C_CLK_OUT6_PORT - clk_out6 - - - C_CLK_OUT7_PORT - clk_out7 - - - C_RESET_PORT - reset - - - C_LOCKED_PORT - locked - - - C_CLKFB_IN_PORT - clkfb_in - - - C_CLKFB_IN_P_PORT - clkfb_in_p - - - C_CLKFB_IN_N_PORT - clkfb_in_n - - - C_CLKFB_OUT_PORT - clkfb_out - - - C_CLKFB_OUT_P_PORT - clkfb_out_p - - - C_CLKFB_OUT_N_PORT - clkfb_out_n - - - C_POWER_DOWN_PORT - power_down - - - C_DADDR_PORT - daddr - - - C_DCLK_PORT - dclk - - - C_DRDY_PORT - drdy - - - C_DWE_PORT - dwe - - - C_DIN_PORT - din - - - C_DOUT_PORT - dout - - - C_DEN_PORT - den - - - C_PSCLK_PORT - psclk - - - C_PSEN_PORT - psen - - - C_PSINCDEC_PORT - psincdec - - - C_PSDONE_PORT - psdone - - - C_CLK_VALID_PORT - CLK_VALID - - - C_STATUS_PORT - STATUS - - - C_CLK_IN_SEL_PORT - clk_in_sel - - - C_INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - C_CLKFB_STOPPED_PORT - clkfb_stopped - - - C_CLKIN1_JITTER_PS - 100.0 - - - C_CLKIN2_JITTER_PS - 100.0 - - - C_PRIMITIVE - PLL - - - C_SS_MODE - CENTER_HIGH - - - C_SS_MOD_PERIOD - 4000 - - - C_SS_MOD_TIME - 0.004 - - - C_HAS_CDDC - 0 - - - C_CDDCDONE_PORT - cddcdone - - - C_CDDCREQ_PORT - cddcreq - - - C_CLKOUTPHY_MODE - VCO - - - C_ENABLE_CLKOUTPHY - 0 - - - C_INTERFACE_SELECTION - 0 - - - C_S_AXI_ADDR_WIDTH - C S Axi Addr Width - 11 - - - C_S_AXI_DATA_WIDTH - C S Axi Data Width - 32 - - - C_POWER_REG - 0000 - - - C_CLKOUT0_1 - 0000 - - - C_CLKOUT0_2 - 0000 - - - C_CLKOUT1_1 - 0000 - - - C_CLKOUT1_2 - 0000 - - - C_CLKOUT2_1 - 0000 - - - C_CLKOUT2_2 - 0000 - - - C_CLKOUT3_1 - 0000 - - - C_CLKOUT3_2 - 0000 - - - C_CLKOUT4_1 - 0000 - - - C_CLKOUT4_2 - 0000 - - - C_CLKOUT5_1 - 0000 - - - C_CLKOUT5_2 - 0000 - - - C_CLKOUT6_1 - 0000 - - - C_CLKOUT6_2 - 0000 - - - C_CLKFBOUT_1 - 0000 - - - C_CLKFBOUT_2 - 0000 - - - C_DIVCLK - 0000 - - - C_LOCK_1 - 0000 - - - C_LOCK_2 - 0000 - - - C_LOCK_3 - 0000 - - - C_FILTER_1 - 0000 - - - C_FILTER_2 - 0000 - - - C_DIVIDE1_AUTO - 1 - - - C_DIVIDE2_AUTO - 0.2 - - - C_DIVIDE3_AUTO - 0.1 - - - C_DIVIDE4_AUTO - 0.06666666666666667 - - - C_DIVIDE5_AUTO - 0.05 - - - C_DIVIDE6_AUTO - 0.04 - - - C_DIVIDE7_AUTO - 0.1 - - - C_PLLBUFGCEDIV - false - - - C_MMCMBUFGCEDIV - false - - - C_PLLBUFGCEDIV1 - false - - - C_PLLBUFGCEDIV2 - false - - - C_PLLBUFGCEDIV3 - false - - - C_PLLBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV1 - false - - - C_MMCMBUFGCEDIV2 - false - - - C_MMCMBUFGCEDIV3 - false - - - C_MMCMBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV5 - false - - - C_MMCMBUFGCEDIV6 - false - - - C_MMCMBUFGCEDIV7 - false - - - C_CLKOUT1_MATCHED_ROUTING - false - - - C_CLKOUT2_MATCHED_ROUTING - false - - - C_CLKOUT3_MATCHED_ROUTING - false - - - C_CLKOUT4_MATCHED_ROUTING - false - - - C_CLKOUT5_MATCHED_ROUTING - false - - - C_CLKOUT6_MATCHED_ROUTING - false - - - C_CLKOUT7_MATCHED_ROUTING - false - - - C_CLKOUT0_ACTUAL_FREQ - 10.000 - - - C_CLKOUT1_ACTUAL_FREQ - 50.000 - - - C_CLKOUT2_ACTUAL_FREQ - 100.000 - - - C_CLKOUT3_ACTUAL_FREQ - 150.000 - - - C_CLKOUT4_ACTUAL_FREQ - 200.000 - - - C_CLKOUT5_ACTUAL_FREQ - 240.000 - - - C_CLKOUT6_ACTUAL_FREQ - 100.000 - - - - - - choice_list_1d3de01d - WAVEFORM - LATENCY - - - choice_list_876bfc32 - UI - PS - - - choice_list_a9bdfce0 - LOW - HIGH - OPTIMIZED - - - choice_list_ac75ef1e - Custom - - - choice_list_b9d38208 - CLKFBOUT - CLKOUT0 - - - choice_list_e099fe6c - MMCM - PLL - - - choice_pairs_035ca1c3 - SYSTEM_SYNCHRONOUS - SOURCE_SYNCHRONOUS - INTERNAL - EXTERNAL - - - choice_pairs_0920eb1b - Custom - sys_diff_clock - - - choice_pairs_11d71346 - Single_ended_clock_capable_pin - Differential_clock_capable_pin - Global_buffer - No_buffer - - - choice_pairs_15c806d5 - FDBK_AUTO - FDBK_AUTO_OFFCHIP - FDBK_ONCHIP - FDBK_OFFCHIP - - - choice_pairs_340369e0 - Custom - sys_clock - sys_diff_clock - - - choice_pairs_3c2d3ec7 - SINGLE - DIFF - - - choice_pairs_502d9f23 - ZHOLD - EXTERNAL - INTERNAL - BUF_IN - - - choice_pairs_66e4c81f - BUFG - BUFH - BUFGCE - BUFHCE - No_buffer - - - choice_pairs_77d3d587 - MMCM - PLL - BUFGCE_DIV - - - choice_pairs_8b28f1f7 - Enable_AXI - Enable_DRP - - - choice_pairs_8eea9b32 - Units_MHz - Units_ns - - - choice_pairs_a4fbc00c - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_a8642b4c - No_Jitter - Min_O_Jitter - Max_I_Jitter - - - choice_pairs_c5ef7212 - Units_UI - Units_ps - - - choice_pairs_e1c87518 - REL_PRIMARY - REL_SECONDARY - - - choice_pairs_f4e10086 - CENTER_HIGH - CENTER_LOW - DOWN_HIGH - DOWN_LOW - - - choice_pairs_f669c2f5 - frequency - Time - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - clk_wiz_1.veo - verilogTemplate - - - - xilinx_anylanguagesynthesis_view_fileset - - clk_wiz_1.xdc - xdc - - processing_order - early - - - - clk_wiz_1_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - mmcm_pll_drp_func_7s_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_7s_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - clk_wiz_1_clk_wiz.v - verilogSource - - - - xilinx_anylanguagesynthesiswrapper_view_fileset - - clk_wiz_1.v - verilogSource - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - mmcm_pll_drp_func_7s_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_7s_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - clk_wiz_1_clk_wiz.v - verilogSource - - - - xilinx_anylanguagesimulationwrapper_view_fileset - - clk_wiz_1.v - verilogSource - - - - xilinx_implementation_view_fileset - - clk_wiz_1_board.xdc - xdc - USED_IN_board - USED_IN_implementation - USED_IN_synthesis - - - - xilinx_versioninformation_view_fileset - - doc/clk_wiz_v6_0_changelog.txt - text - - - - xilinx_externalfiles_view_fileset - - clk_wiz_1.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - clk_wiz_1_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - clk_wiz_1_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - clk_wiz_1_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - clk_wiz_1_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. - - - Component_Name - clk_wiz_1 - - - USER_CLK_FREQ0 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ1 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ2 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ3 - User Frequency(MHz) - 100.0 - - - ENABLE_CLOCK_MONITOR - Enable Clock Monitoring - false - - - ENABLE_USER_CLOCK0 - User Clock - false - - - ENABLE_USER_CLOCK1 - User Clock - false - - - ENABLE_USER_CLOCK2 - User Clock - false - - - ENABLE_USER_CLOCK3 - User Clock - false - - - Enable_PLL0 - User Clock - false - - - Enable_PLL1 - User Clock - false - - - REF_CLK_FREQ - Reference Frequency(MHz) - 100.0 - - - PRECISION - Tolerance(MHz) - 1 - - - PRIMITIVE - Primitive - PLL - - - PRIMTYPE_SEL - Primtype Sel - mmcm_adv - - - CLOCK_MGR_TYPE - Clock Mgr Type - auto - - - USE_FREQ_SYNTH - true - - - USE_SPREAD_SPECTRUM - false - - - USE_PHASE_ALIGNMENT - true - - - USE_MIN_POWER - false - - - USE_DYN_PHASE_SHIFT - false - - - USE_DYN_RECONFIG - false - - - JITTER_SEL - No_Jitter - - - PRIM_IN_FREQ - 100.000 - - - PRIM_IN_TIMEPERIOD - 10.000 - - - IN_FREQ_UNITS - Units_MHz - - - PHASESHIFT_MODE - WAVEFORM - - - IN_JITTER_UNITS - Units_UI - - - RELATIVE_INCLK - REL_PRIMARY - - - USE_INCLK_SWITCHOVER - false - - - SECONDARY_IN_FREQ - 100.000 - - - SECONDARY_IN_TIMEPERIOD - 10.000 - - - SECONDARY_PORT - clk_in2 - - - SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - JITTER_OPTIONS - UI - - - CLKIN1_UI_JITTER - 0.010 - - - CLKIN2_UI_JITTER - 0.010 - - - PRIM_IN_JITTER - 0.010 - - - SECONDARY_IN_JITTER - 0.010 - - - CLKIN1_JITTER_PS - 100.0 - - - CLKIN2_JITTER_PS - 100.0 - - - CLKOUT1_USED - true - - - CLKOUT2_USED - true - - - CLKOUT3_USED - true - - - CLKOUT4_USED - true - - - CLKOUT5_USED - true - - - CLKOUT6_USED - true - - - CLKOUT7_USED - false - - - NUM_OUT_CLKS - 6 - - - CLK_OUT1_USE_FINE_PS_GUI - false - - - CLK_OUT2_USE_FINE_PS_GUI - false - - - CLK_OUT3_USE_FINE_PS_GUI - false - - - CLK_OUT4_USE_FINE_PS_GUI - false - - - CLK_OUT5_USE_FINE_PS_GUI - false - - - CLK_OUT6_USE_FINE_PS_GUI - false - - - CLK_OUT7_USE_FINE_PS_GUI - false - - - PRIMARY_PORT - clk_in1 - - - CLK_OUT1_PORT - clk_out1 - - - CLK_OUT2_PORT - clk_out2 - - - CLK_OUT3_PORT - clk_out3 - - - CLK_OUT4_PORT - clk_out4 - - - CLK_OUT5_PORT - clk_out5 - - - CLK_OUT6_PORT - clk_out6 - - - CLK_OUT7_PORT - clk_out7 - - - DADDR_PORT - daddr - - - DCLK_PORT - dclk - - - DRDY_PORT - drdy - - - DWE_PORT - dwe - - - DIN_PORT - din - - - DOUT_PORT - dout - - - DEN_PORT - den - - - PSCLK_PORT - psclk - - - PSEN_PORT - psen - - - PSINCDEC_PORT - psincdec - - - PSDONE_PORT - psdone - - - CLKOUT1_REQUESTED_OUT_FREQ - 10 - - - CLKOUT1_REQUESTED_PHASE - 0.000 - - - CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT2_REQUESTED_OUT_FREQ - 50 - - - CLKOUT2_REQUESTED_PHASE - 0.000 - - - CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT3_REQUESTED_OUT_FREQ - 100 - - - CLKOUT3_REQUESTED_PHASE - 0.000 - - - CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT4_REQUESTED_OUT_FREQ - 150 - - - CLKOUT4_REQUESTED_PHASE - 0.000 - - - CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT5_REQUESTED_OUT_FREQ - 200 - - - CLKOUT5_REQUESTED_PHASE - 0.000 - - - CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT6_REQUESTED_OUT_FREQ - 250 - - - CLKOUT6_REQUESTED_PHASE - 0.000 - - - CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT7_REQUESTED_PHASE - 0.000 - - - CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - USE_MAX_I_JITTER - false - - - USE_MIN_O_JITTER - false - - - CLKOUT1_MATCHED_ROUTING - false - - - CLKOUT2_MATCHED_ROUTING - false - - - CLKOUT3_MATCHED_ROUTING - false - - - CLKOUT4_MATCHED_ROUTING - false - - - CLKOUT5_MATCHED_ROUTING - false - - - CLKOUT6_MATCHED_ROUTING - false - - - CLKOUT7_MATCHED_ROUTING - false - - - PRIM_SOURCE - Single_ended_clock_capable_pin - - - CLKOUT1_DRIVES - BUFH - - - CLKOUT2_DRIVES - BUFH - - - CLKOUT3_DRIVES - BUFH - - - CLKOUT4_DRIVES - BUFH - - - CLKOUT5_DRIVES - BUFH - - - CLKOUT6_DRIVES - BUFH - - - CLKOUT7_DRIVES - BUFG - - - FEEDBACK_SOURCE - FDBK_AUTO - - - CLKFB_IN_SIGNALING - SINGLE - - - CLKFB_IN_PORT - clkfb_in - - - CLKFB_IN_P_PORT - clkfb_in_p - - - CLKFB_IN_N_PORT - clkfb_in_n - - - CLKFB_OUT_PORT - clkfb_out - - - CLKFB_OUT_P_PORT - clkfb_out_p - - - CLKFB_OUT_N_PORT - clkfb_out_n - - - PLATFORM - UNKNOWN - - - SUMMARY_STRINGS - empty - - - USE_LOCKED - true - - - CALC_DONE - empty - - - USE_RESET - true - - - USE_POWER_DOWN - false - - - USE_STATUS - false - - - USE_FREEZE - false - - - USE_CLK_VALID - false - - - USE_INCLK_STOPPED - false - - - USE_CLKFB_STOPPED - false - - - RESET_PORT - reset - - - LOCKED_PORT - locked - - - POWER_DOWN_PORT - power_down - - - CLK_VALID_PORT - CLK_VALID - - - STATUS_PORT - STATUS - - - CLK_IN_SEL_PORT - clk_in_sel - - - INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - CLKFB_STOPPED_PORT - clkfb_stopped - - - SS_MODE - CENTER_HIGH - - - SS_MOD_FREQ - 250 - - - SS_MOD_TIME - 0.004 - - - OVERRIDE_MMCM - false - - - MMCM_NOTES - None - - - MMCM_DIVCLK_DIVIDE - 1 - - - MMCM_BANDWIDTH - OPTIMIZED - - - MMCM_CLKFBOUT_MULT_F - 12 - - - MMCM_CLKFBOUT_PHASE - 0.000 - - - MMCM_CLKFBOUT_USE_FINE_PS - false - - - MMCM_CLKIN1_PERIOD - 10.000 - - - MMCM_CLKIN2_PERIOD - 10.000 - - - MMCM_CLKOUT4_CASCADE - false - - - MMCM_CLOCK_HOLD - false - - - MMCM_COMPENSATION - ZHOLD - - - MMCM_REF_JITTER1 - 0.010 - - - MMCM_REF_JITTER2 - 0.010 - - - MMCM_STARTUP_WAIT - false - - - MMCM_CLKOUT0_DIVIDE_F - 120 - - - MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT0_PHASE - 0.000 - - - MMCM_CLKOUT0_USE_FINE_PS - false - - - MMCM_CLKOUT1_DIVIDE - 24 - - - MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT1_PHASE - 0.000 - - - MMCM_CLKOUT1_USE_FINE_PS - false - - - MMCM_CLKOUT2_DIVIDE - 12 - - - MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT2_PHASE - 0.000 - - - MMCM_CLKOUT2_USE_FINE_PS - false - - - MMCM_CLKOUT3_DIVIDE - 8 - - - MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT3_PHASE - 0.000 - - - MMCM_CLKOUT3_USE_FINE_PS - false - - - MMCM_CLKOUT4_DIVIDE - 6 - - - MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT4_PHASE - 0.000 - - - MMCM_CLKOUT4_USE_FINE_PS - false - - - MMCM_CLKOUT5_DIVIDE - 5 - - - MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT5_PHASE - 0.000 - - - MMCM_CLKOUT5_USE_FINE_PS - false - - - MMCM_CLKOUT6_DIVIDE - 1 - - - MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT6_PHASE - 0.000 - - - MMCM_CLKOUT6_USE_FINE_PS - false - - - OVERRIDE_PLL - false - - - PLL_NOTES - None - - - PLL_BANDWIDTH - OPTIMIZED - - - PLL_CLKFBOUT_MULT - 4 - - - PLL_CLKFBOUT_PHASE - 0.000 - - - PLL_CLK_FEEDBACK - CLKFBOUT - - - PLL_DIVCLK_DIVIDE - 1 - - - PLL_CLKIN_PERIOD - 10.000 - - - PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - PLL_REF_JITTER - 0.010 - - - PLL_CLKOUT0_DIVIDE - 1 - - - PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT0_PHASE - 0.000 - - - PLL_CLKOUT1_DIVIDE - 1 - - - PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT1_PHASE - 0.000 - - - PLL_CLKOUT2_DIVIDE - 1 - - - PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT2_PHASE - 0.000 - - - PLL_CLKOUT3_DIVIDE - 1 - - - PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT3_PHASE - 0.000 - - - PLL_CLKOUT4_DIVIDE - 1 - - - PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT4_PHASE - 0.000 - - - PLL_CLKOUT5_DIVIDE - 1 - - - PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT5_PHASE - 0.000 - - - RESET_TYPE - Reset Type - ACTIVE_HIGH - - - USE_SAFE_CLOCK_STARTUP - false - - - USE_CLOCK_SEQUENCING - false - - - CLKOUT1_SEQUENCE_NUMBER - 1 - - - CLKOUT2_SEQUENCE_NUMBER - 1 - - - CLKOUT3_SEQUENCE_NUMBER - 1 - - - CLKOUT4_SEQUENCE_NUMBER - 1 - - - CLKOUT5_SEQUENCE_NUMBER - 1 - - - CLKOUT6_SEQUENCE_NUMBER - 1 - - - CLKOUT7_SEQUENCE_NUMBER - 1 - - - USE_BOARD_FLOW - Generate Board based IO Constraints - false - - - CLK_IN1_BOARD_INTERFACE - Custom - - - CLK_IN2_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN1_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN2_BOARD_INTERFACE - Custom - - - AUTO_PRIMITIVE - MMCM - - - RESET_BOARD_INTERFACE - Custom - - - ENABLE_CDDC - false - - - CDDCDONE_PORT - cddcdone - - - CDDCREQ_PORT - cddcreq - - - ENABLE_CLKOUTPHY - false - - - CLKOUTPHY_REQUESTED_FREQ - 600.000 - - - CLKOUT1_JITTER - Clkout1 Jitter - 188.586 - - - CLKOUT1_PHASE_ERROR - Clkout1 Phase - 87.180 - - - CLKOUT2_JITTER - Clkout2 Jitter - 132.683 - - - CLKOUT2_PHASE_ERROR - Clkout2 Phase - 87.180 - - - CLKOUT3_JITTER - Clkout3 Jitter - 115.831 - - - CLKOUT3_PHASE_ERROR - Clkout3 Phase - 87.180 - - - CLKOUT4_JITTER - Clkout4 Jitter - 107.567 - - - CLKOUT4_PHASE_ERROR - Clkout4 Phase - 87.180 - - - CLKOUT5_JITTER - Clkout5 Jitter - 102.086 - - - CLKOUT5_PHASE_ERROR - Clkout5 Phase - 87.180 - - - CLKOUT6_JITTER - Clkout6 Jitter - 98.767 - - - CLKOUT6_PHASE_ERROR - Clkout6 Phase - 87.180 - - - CLKOUT7_JITTER - Clkout7 Jitter - 0.0 - - - CLKOUT7_PHASE_ERROR - Clkout7 Phase - 0.0 - - - INPUT_MODE - frequency - - - INTERFACE_SELECTION - Enable_AXI - - - AXI_DRP - Write DRP registers - false - - - PHASE_DUTY_CONFIG - Phase Duty Cycle Config - false - - - - - Clocking Wizard - - XPM_CDC - - 3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.1.1 - - - - - - - - diff --git a/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_2/clk_wiz_2.xml b/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_2/clk_wiz_2.xml deleted file mode 100644 index 216efe5..0000000 --- a/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_2/clk_wiz_2.xml +++ /dev/null @@ -1,5358 +0,0 @@ - - - xilinx.com - customized_ip - clk_wiz_2 - 1.0 - - - s_axi_lite - S_AXI_LITE - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARREADY - - - s_axi_arready - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWREADY - - - s_axi_awready - - - - - AWVALID - - - s_axi_awvalid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 1 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 1 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 0 - - - none - - - - - HAS_BRESP - 0 - - - none - - - - - HAS_RRESP - 0 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_aclk - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi_lite - - - ASSOCIATED_RESET - s_axi_aresetn - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - ref_clk - ref_clk - - - - - - - CLK - - - ref_clk - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_resetn - S_AXI_RESETN - - - - - - - RST - - - s_axi_aresetn - - - - - - ASSOCIATED_RESET - aresetn - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - intr - Intr - - - - - - - INTERRUPT - - - ip2intc_irpt - - - - - - SENSITIVITY - LEVEL_HIGH - - - none - - - - - PortWidth - 1 - - - none - - - - - - - - false - - - - - - CLK_IN1_D - CLK_IN1_D - Differential Clock input - - - - - - - CLK_N - - - clk_in1_n - - - - - CLK_P - - - clk_in1_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN1_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLK_IN2_D - CLK_IN2_D - Differential Clock input - - - - - - - CLK_N - - - clk_in2_n - - - - - CLK_P - - - clk_in2_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN2_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_IN_D - CLKFB_IN_D - Differential Feedback Clock input - - - - - - - CLK_N - - - clkfb_in_n - - - - - CLK_P - - - clkfb_in_p - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_OUT_D - CLKFB_OUT_D - Differential Feeback Clock Output - - - - - - - CLK_N - - - clkfb_out_n - - - - - CLK_P - - - clkfb_out_p - - - - - - CAN_DEBUG - false - - - none - - - - - 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INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT5 - - - - - - - CLK_OUT5 - - - clk_out5 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT6 - - - - - - - CLK_OUT6 - - - clk_out6 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - xilinx_elaborateports - Elaborate Ports - :vivado.xilinx.com:elaborate.ports - - - outputProductCRC - 9:e84b5057 - - - - - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog - clk_wiz_v6_0_3 - - xilinx_veriloginstantiationtemplate_view_fileset - - - - GENtimestamp - Sat Sep 14 01:08:19 UTC 2019 - - - outputProductCRC - 9:00356406 - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - clk_wiz_v6_0_3 - - xilinx_anylanguagesynthesis_view_fileset - - - - GENtimestamp - Sat Sep 14 01:08:20 UTC 2019 - - - outputProductCRC - 9:00356406 - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - - outputProductCRC - 9:00356406 - - - - - xilinx_anylanguagesynthesiswrapper - Synthesis Wrapper - :vivado.xilinx.com:synthesis.wrapper - clk_wiz_2 - - xilinx_anylanguagesynthesiswrapper_view_fileset - - - - GENtimestamp - Sat Sep 14 01:08:20 UTC 2019 - - - outputProductCRC - 9:00356406 - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - clk_wiz_v6_0_3 - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - GENtimestamp - Sat Sep 14 01:08:20 UTC 2019 - - - outputProductCRC - 9:1b819738 - - - - - xilinx_anylanguagesimulationwrapper - Simulation Wrapper - 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UNKNOWN - - - C_USE_FREQ_SYNTH - 1 - - - C_USE_PHASE_ALIGNMENT - 1 - - - C_PRIM_IN_JITTER - 0.010 - - - C_SECONDARY_IN_JITTER - 0.010 - - - C_JITTER_SEL - No_Jitter - - - C_USE_MIN_POWER - 0 - - - C_USE_MIN_O_JITTER - 0 - - - C_USE_MAX_I_JITTER - 0 - - - C_USE_DYN_PHASE_SHIFT - 0 - - - C_USE_INCLK_SWITCHOVER - 0 - - - C_USE_DYN_RECONFIG - 0 - - - C_USE_SPREAD_SPECTRUM - 0 - - - C_USE_FAST_SIMULATION - 0 - - - C_PRIMTYPE_SEL - AUTO - - - C_USE_CLK_VALID - 0 - - - C_PRIM_IN_FREQ - 100.000 - - - C_PRIM_IN_TIMEPERIOD - 10.000 - - - C_IN_FREQ_UNITS - Units_MHz - - - C_SECONDARY_IN_FREQ - 100.000 - - - C_SECONDARY_IN_TIMEPERIOD - 10.000 - - - C_FEEDBACK_SOURCE - FDBK_AUTO - - - C_PRIM_SOURCE - Single_ended_clock_capable_pin - - - C_PHASESHIFT_MODE - WAVEFORM - - - C_SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - C_CLKFB_IN_SIGNALING - SINGLE - - - C_USE_RESET - 1 - - - C_RESET_LOW - 0 - - - C_USE_LOCKED - 1 - - - C_USE_INCLK_STOPPED - 0 - - - C_USE_CLKFB_STOPPED - 0 - - - C_USE_POWER_DOWN - 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50.000 - - - C_CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT1_OUT_FREQ - 19.907 - - - C_CLKOUT2_OUT_FREQ - 59.722 - - - C_CLKOUT3_OUT_FREQ - 110.256 - - - C_CLKOUT4_OUT_FREQ - 204.762 - - - C_CLKOUT5_OUT_FREQ - 238.889 - - - C_CLKOUT6_OUT_FREQ - 286.667 - - - C_CLKOUT7_OUT_FREQ - 100.000 - - - C_CLKOUT1_PHASE - 0.000 - - - C_CLKOUT2_PHASE - 0.000 - - - C_CLKOUT3_PHASE - 0.000 - - - C_CLKOUT4_PHASE - 0.000 - - - C_CLKOUT5_PHASE - 0.000 - - - C_CLKOUT6_PHASE - 0.000 - - - C_CLKOUT7_PHASE - 0.000 - - - C_CLKOUT1_DUTY_CYCLE - 50.0 - - - C_CLKOUT2_DUTY_CYCLE - 50.0 - - - C_CLKOUT3_DUTY_CYCLE - 50.0 - - - C_CLKOUT4_DUTY_CYCLE - 50.0 - - - C_CLKOUT5_DUTY_CYCLE - 50.0 - - - C_CLKOUT6_DUTY_CYCLE - 50.0 - - - C_CLKOUT7_DUTY_CYCLE - 50.000 - - - C_USE_SAFE_CLOCK_STARTUP - 0 - - - C_USE_CLOCK_SEQUENCING - 0 - - - C_CLKOUT1_SEQUENCE_NUMBER - 1 - - - C_CLKOUT2_SEQUENCE_NUMBER - 1 - - - C_CLKOUT3_SEQUENCE_NUMBER - 1 - - - C_CLKOUT4_SEQUENCE_NUMBER - 1 - - - C_CLKOUT5_SEQUENCE_NUMBER - 1 - - - C_CLKOUT6_SEQUENCE_NUMBER - 1 - - - C_CLKOUT7_SEQUENCE_NUMBER - 1 - - - C_MMCM_NOTES - None - - - C_MMCM_BANDWIDTH - OPTIMIZED - - - C_MMCM_CLKFBOUT_MULT_F - 43.000 - - - C_MMCM_CLKIN1_PERIOD - 10.000 - - - C_MMCM_CLKIN2_PERIOD - 10.000 - - - C_MMCM_CLKOUT4_CASCADE - FALSE - - - C_MMCM_CLOCK_HOLD - FALSE - - - C_MMCM_COMPENSATION - ZHOLD - - - C_MMCM_DIVCLK_DIVIDE - 3 - - - C_MMCM_REF_JITTER1 - 0.010 - - - C_MMCM_REF_JITTER2 - 0.010 - - - C_MMCM_STARTUP_WAIT - FALSE - - - C_MMCM_CLKOUT0_DIVIDE_F - 72.000 - - - C_MMCM_CLKOUT1_DIVIDE - 24 - - - C_MMCM_CLKOUT2_DIVIDE - 13 - - - C_MMCM_CLKOUT3_DIVIDE - 7 - - - C_MMCM_CLKOUT4_DIVIDE - 6 - - - C_MMCM_CLKOUT5_DIVIDE - 5 - - - C_MMCM_CLKOUT6_DIVIDE - 1 - - - C_MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKFBOUT_PHASE - 0.000 - - - C_MMCM_CLKOUT0_PHASE - 0.000 - - - C_MMCM_CLKOUT1_PHASE - 0.000 - - - C_MMCM_CLKOUT2_PHASE - 0.000 - - - C_MMCM_CLKOUT3_PHASE - 0.000 - - - C_MMCM_CLKOUT4_PHASE - 0.000 - - - C_MMCM_CLKOUT5_PHASE - 0.000 - - - C_MMCM_CLKOUT6_PHASE - 0.000 - - - C_MMCM_CLKFBOUT_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT0_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT1_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT2_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT3_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT4_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT5_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT6_USE_FINE_PS - FALSE - - - C_PLL_NOTES - No notes - - - C_PLL_BANDWIDTH - OPTIMIZED - - - C_PLL_CLK_FEEDBACK - CLKFBOUT - - - C_PLL_CLKFBOUT_MULT - 1 - - - C_PLL_CLKIN_PERIOD - 1.000 - - - C_PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - C_PLL_DIVCLK_DIVIDE - 1 - - - C_PLL_REF_JITTER - 0.010 - - - C_PLL_CLKOUT0_DIVIDE - 1 - - - C_PLL_CLKOUT1_DIVIDE - 1 - - - C_PLL_CLKOUT2_DIVIDE - 1 - - - C_PLL_CLKOUT3_DIVIDE - 1 - - - C_PLL_CLKOUT4_DIVIDE - 1 - - - C_PLL_CLKOUT5_DIVIDE - 1 - - - C_PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_PLL_CLKFBOUT_PHASE - 0.000 - - - C_PLL_CLKOUT0_PHASE - 0.000 - - - C_PLL_CLKOUT1_PHASE - 0.000 - - - C_PLL_CLKOUT2_PHASE - 0.000 - - - C_PLL_CLKOUT3_PHASE - 0.000 - - - C_PLL_CLKOUT4_PHASE - 0.000 - - - C_PLL_CLKOUT5_PHASE - 0.000 - - - C_CLOCK_MGR_TYPE - NA - - - C_OVERRIDE_MMCM - 0 - - - C_OVERRIDE_PLL - 0 - - - C_PRIMARY_PORT - clk_in1 - - - C_SECONDARY_PORT - clk_in2 - - - C_CLK_OUT1_PORT - clk_out1 - - - C_CLK_OUT2_PORT - clk_out2 - - - C_CLK_OUT3_PORT - clk_out3 - - - C_CLK_OUT4_PORT - clk_out4 - - - C_CLK_OUT5_PORT - clk_out5 - - - C_CLK_OUT6_PORT - clk_out6 - - - C_CLK_OUT7_PORT - clk_out7 - - - C_RESET_PORT - reset - - - C_LOCKED_PORT - locked - - - C_CLKFB_IN_PORT - clkfb_in - - - C_CLKFB_IN_P_PORT - clkfb_in_p - - - C_CLKFB_IN_N_PORT - clkfb_in_n - - - C_CLKFB_OUT_PORT - clkfb_out - - - C_CLKFB_OUT_P_PORT - clkfb_out_p - - - C_CLKFB_OUT_N_PORT - clkfb_out_n - - - C_POWER_DOWN_PORT - power_down - - - C_DADDR_PORT - daddr - - - C_DCLK_PORT - dclk - - - C_DRDY_PORT - drdy - - - C_DWE_PORT - dwe - - - C_DIN_PORT - din - - - C_DOUT_PORT - dout - - - C_DEN_PORT - den - - - C_PSCLK_PORT - psclk - - - C_PSEN_PORT - psen - - - C_PSINCDEC_PORT - psincdec - - - C_PSDONE_PORT - psdone - - - C_CLK_VALID_PORT - CLK_VALID - - - C_STATUS_PORT - STATUS - - - C_CLK_IN_SEL_PORT - clk_in_sel - - - C_INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - C_CLKFB_STOPPED_PORT - clkfb_stopped - - - C_CLKIN1_JITTER_PS - 100.0 - - - C_CLKIN2_JITTER_PS - 100.0 - - - C_PRIMITIVE - PLL - - - C_SS_MODE - CENTER_HIGH - - - C_SS_MOD_PERIOD - 4000 - - - C_SS_MOD_TIME - 0.004 - - - C_HAS_CDDC - 0 - - - C_CDDCDONE_PORT - cddcdone - - - C_CDDCREQ_PORT - cddcreq - - - C_CLKOUTPHY_MODE - VCO - - - C_ENABLE_CLKOUTPHY - 0 - - - C_INTERFACE_SELECTION - 0 - - - C_S_AXI_ADDR_WIDTH - C S Axi Addr Width - 11 - - - C_S_AXI_DATA_WIDTH - C S Axi Data Width - 32 - - - C_POWER_REG - 0000 - - - C_CLKOUT0_1 - 0000 - - - C_CLKOUT0_2 - 0000 - - - C_CLKOUT1_1 - 0000 - - - C_CLKOUT1_2 - 0000 - - - C_CLKOUT2_1 - 0000 - - - C_CLKOUT2_2 - 0000 - - - C_CLKOUT3_1 - 0000 - - - C_CLKOUT3_2 - 0000 - - - C_CLKOUT4_1 - 0000 - - - C_CLKOUT4_2 - 0000 - - - C_CLKOUT5_1 - 0000 - - - C_CLKOUT5_2 - 0000 - - - C_CLKOUT6_1 - 0000 - - - C_CLKOUT6_2 - 0000 - - - C_CLKFBOUT_1 - 0000 - - - C_CLKFBOUT_2 - 0000 - - - C_DIVCLK - 0000 - - - C_LOCK_1 - 0000 - - - C_LOCK_2 - 0000 - - - C_LOCK_3 - 0000 - - - C_FILTER_1 - 0000 - - - C_FILTER_2 - 0000 - - - C_DIVIDE1_AUTO - 1 - - - C_DIVIDE2_AUTO - 0.3333333333333333 - - - C_DIVIDE3_AUTO - 0.18181818181818182 - - - C_DIVIDE4_AUTO - 0.09523809523809523 - - - C_DIVIDE5_AUTO - 0.07692307692307693 - - - C_DIVIDE6_AUTO - 0.06451612903225806 - - - C_DIVIDE7_AUTO - 0.2 - - - C_PLLBUFGCEDIV - false - - - C_MMCMBUFGCEDIV - false - - - C_PLLBUFGCEDIV1 - false - - - C_PLLBUFGCEDIV2 - false - - - C_PLLBUFGCEDIV3 - false - - - C_PLLBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV1 - false - - - C_MMCMBUFGCEDIV2 - false - - - C_MMCMBUFGCEDIV3 - false - - - C_MMCMBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV5 - false - - - C_MMCMBUFGCEDIV6 - false - - - C_MMCMBUFGCEDIV7 - false - - - C_CLKOUT1_MATCHED_ROUTING - false - - - C_CLKOUT2_MATCHED_ROUTING - false - - - C_CLKOUT3_MATCHED_ROUTING - false - - - C_CLKOUT4_MATCHED_ROUTING - false - - - C_CLKOUT5_MATCHED_ROUTING - false - - - C_CLKOUT6_MATCHED_ROUTING - false - - - C_CLKOUT7_MATCHED_ROUTING - false - - - C_CLKOUT0_ACTUAL_FREQ - 19.907 - - - C_CLKOUT1_ACTUAL_FREQ - 59.722 - - - C_CLKOUT2_ACTUAL_FREQ - 110.256 - - - C_CLKOUT3_ACTUAL_FREQ - 204.762 - - - C_CLKOUT4_ACTUAL_FREQ - 238.889 - - - C_CLKOUT5_ACTUAL_FREQ - 286.667 - - - C_CLKOUT6_ACTUAL_FREQ - 100.000 - - - - - - choice_list_1d3de01d - WAVEFORM - LATENCY - - - choice_list_876bfc32 - UI - PS - - - choice_list_a9bdfce0 - LOW - HIGH - OPTIMIZED - - - choice_list_ac75ef1e - Custom - - - choice_list_b9d38208 - CLKFBOUT - CLKOUT0 - - - choice_list_e099fe6c - MMCM - PLL - - - choice_pairs_035ca1c3 - SYSTEM_SYNCHRONOUS - SOURCE_SYNCHRONOUS - INTERNAL - EXTERNAL - - - choice_pairs_0920eb1b - Custom - sys_diff_clock - - - choice_pairs_11d71346 - Single_ended_clock_capable_pin - Differential_clock_capable_pin - Global_buffer - No_buffer - - - choice_pairs_15c806d5 - FDBK_AUTO - FDBK_AUTO_OFFCHIP - FDBK_ONCHIP - FDBK_OFFCHIP - - - choice_pairs_340369e0 - Custom - sys_clock - sys_diff_clock - - - choice_pairs_3c2d3ec7 - SINGLE - DIFF - - - choice_pairs_502d9f23 - ZHOLD - EXTERNAL - INTERNAL - BUF_IN - - - choice_pairs_66e4c81f - BUFG - BUFH - BUFGCE - BUFHCE - No_buffer - - - choice_pairs_77d3d587 - MMCM - PLL - BUFGCE_DIV - - - choice_pairs_8b28f1f7 - Enable_AXI - Enable_DRP - - - choice_pairs_8eea9b32 - Units_MHz - Units_ns - - - choice_pairs_a4fbc00c - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_a8642b4c - No_Jitter - Min_O_Jitter - Max_I_Jitter - - - choice_pairs_c5ef7212 - Units_UI - Units_ps - - - choice_pairs_e1c87518 - REL_PRIMARY - REL_SECONDARY - - - choice_pairs_f4e10086 - CENTER_HIGH - CENTER_LOW - DOWN_HIGH - DOWN_LOW - - - choice_pairs_f669c2f5 - frequency - Time - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - clk_wiz_2.veo - verilogTemplate - - - - xilinx_anylanguagesynthesis_view_fileset - - clk_wiz_2.xdc - xdc - - processing_order - early - - - - clk_wiz_2_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - mmcm_pll_drp_func_7s_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_7s_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - clk_wiz_2_clk_wiz.v - verilogSource - - - - xilinx_anylanguagesynthesiswrapper_view_fileset - - clk_wiz_2.v - verilogSource - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - mmcm_pll_drp_func_7s_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_7s_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - clk_wiz_2_clk_wiz.v - verilogSource - - - - xilinx_anylanguagesimulationwrapper_view_fileset - - clk_wiz_2.v - verilogSource - - - - xilinx_implementation_view_fileset - - clk_wiz_2_board.xdc - xdc - USED_IN_board - USED_IN_implementation - USED_IN_synthesis - - - - xilinx_versioninformation_view_fileset - - doc/clk_wiz_v6_0_changelog.txt - text - - - - xilinx_externalfiles_view_fileset - - clk_wiz_2.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - clk_wiz_2_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - clk_wiz_2_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - clk_wiz_2_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - clk_wiz_2_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. - - - Component_Name - clk_wiz_2 - - - USER_CLK_FREQ0 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ1 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ2 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ3 - User Frequency(MHz) - 100.0 - - - ENABLE_CLOCK_MONITOR - Enable Clock Monitoring - false - - - ENABLE_USER_CLOCK0 - User Clock - false - - - ENABLE_USER_CLOCK1 - User Clock - false - - - ENABLE_USER_CLOCK2 - User Clock - false - - - ENABLE_USER_CLOCK3 - User Clock - false - - - Enable_PLL0 - User Clock - false - - - Enable_PLL1 - User Clock - false - - - REF_CLK_FREQ - Reference Frequency(MHz) - 100.0 - - - PRECISION - Tolerance(MHz) - 1 - - - PRIMITIVE - Primitive - PLL - - - PRIMTYPE_SEL - Primtype Sel - mmcm_adv - - - CLOCK_MGR_TYPE - Clock Mgr Type - auto - - - USE_FREQ_SYNTH - true - - - USE_SPREAD_SPECTRUM - false - - - USE_PHASE_ALIGNMENT - true - - - USE_MIN_POWER - false - - - USE_DYN_PHASE_SHIFT - false - - - USE_DYN_RECONFIG - false - - - JITTER_SEL - No_Jitter - - - PRIM_IN_FREQ - 100.000 - - - PRIM_IN_TIMEPERIOD - 10.000 - - - IN_FREQ_UNITS - Units_MHz - - - PHASESHIFT_MODE - WAVEFORM - - - IN_JITTER_UNITS - Units_UI - - - RELATIVE_INCLK - REL_PRIMARY - - - USE_INCLK_SWITCHOVER - false - - - SECONDARY_IN_FREQ - 100.000 - - - SECONDARY_IN_TIMEPERIOD - 10.000 - - - SECONDARY_PORT - clk_in2 - - - SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - JITTER_OPTIONS - UI - - - CLKIN1_UI_JITTER - 0.010 - - - CLKIN2_UI_JITTER - 0.010 - - - PRIM_IN_JITTER - 0.010 - - - SECONDARY_IN_JITTER - 0.010 - - - CLKIN1_JITTER_PS - 100.0 - - - CLKIN2_JITTER_PS - 100.0 - - - CLKOUT1_USED - true - - - CLKOUT2_USED - true - - - CLKOUT3_USED - true - - - CLKOUT4_USED - true - - - CLKOUT5_USED - true - - - CLKOUT6_USED - true - - - CLKOUT7_USED - false - - - NUM_OUT_CLKS - 6 - - - CLK_OUT1_USE_FINE_PS_GUI - false - - - CLK_OUT2_USE_FINE_PS_GUI - false - - - CLK_OUT3_USE_FINE_PS_GUI - false - - - CLK_OUT4_USE_FINE_PS_GUI - false - - - CLK_OUT5_USE_FINE_PS_GUI - false - - - CLK_OUT6_USE_FINE_PS_GUI - false - - - CLK_OUT7_USE_FINE_PS_GUI - false - - - PRIMARY_PORT - clk_in1 - - - CLK_OUT1_PORT - clk_out1 - - - CLK_OUT2_PORT - clk_out2 - - - CLK_OUT3_PORT - clk_out3 - - - CLK_OUT4_PORT - clk_out4 - - - CLK_OUT5_PORT - clk_out5 - - - CLK_OUT6_PORT - clk_out6 - - - CLK_OUT7_PORT - clk_out7 - - - DADDR_PORT - daddr - - - DCLK_PORT - dclk - - - DRDY_PORT - drdy - - - DWE_PORT - dwe - - - DIN_PORT - din - - - DOUT_PORT - dout - - - DEN_PORT - den - - - PSCLK_PORT - psclk - - - PSEN_PORT - psen - - - PSINCDEC_PORT - psincdec - - - PSDONE_PORT - psdone - - - CLKOUT1_REQUESTED_OUT_FREQ - 20 - - - CLKOUT1_REQUESTED_PHASE - 0.000 - - - CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT2_REQUESTED_OUT_FREQ - 60 - - - CLKOUT2_REQUESTED_PHASE - 0.000 - - - CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT3_REQUESTED_OUT_FREQ - 110 - - - CLKOUT3_REQUESTED_PHASE - 0.000 - - - CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT4_REQUESTED_OUT_FREQ - 210 - - - CLKOUT4_REQUESTED_PHASE - 0.000 - - - CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT5_REQUESTED_OUT_FREQ - 260 - - - CLKOUT5_REQUESTED_PHASE - 0.000 - - - CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT6_REQUESTED_OUT_FREQ - 310 - - - CLKOUT6_REQUESTED_PHASE - 0.000 - - - CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT7_REQUESTED_PHASE - 0.000 - - - CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - USE_MAX_I_JITTER - false - - - USE_MIN_O_JITTER - false - - - CLKOUT1_MATCHED_ROUTING - false - - - CLKOUT2_MATCHED_ROUTING - false - - - CLKOUT3_MATCHED_ROUTING - false - - - CLKOUT4_MATCHED_ROUTING - false - - - CLKOUT5_MATCHED_ROUTING - false - - - CLKOUT6_MATCHED_ROUTING - false - - - CLKOUT7_MATCHED_ROUTING - false - - - PRIM_SOURCE - Single_ended_clock_capable_pin - - - CLKOUT1_DRIVES - BUFG - - - CLKOUT2_DRIVES - BUFG - - - CLKOUT3_DRIVES - BUFG - - - CLKOUT4_DRIVES - BUFG - - - CLKOUT5_DRIVES - BUFG - - - CLKOUT6_DRIVES - BUFG - - - CLKOUT7_DRIVES - BUFG - - - FEEDBACK_SOURCE - FDBK_AUTO - - - CLKFB_IN_SIGNALING - SINGLE - - - CLKFB_IN_PORT - clkfb_in - - - CLKFB_IN_P_PORT - clkfb_in_p - - - CLKFB_IN_N_PORT - clkfb_in_n - - - CLKFB_OUT_PORT - clkfb_out - - - CLKFB_OUT_P_PORT - clkfb_out_p - - - CLKFB_OUT_N_PORT - clkfb_out_n - - - PLATFORM - UNKNOWN - - - SUMMARY_STRINGS - empty - - - USE_LOCKED - true - - - CALC_DONE - empty - - - USE_RESET - true - - - USE_POWER_DOWN - false - - - USE_STATUS - false - - - USE_FREEZE - false - - - USE_CLK_VALID - false - - - USE_INCLK_STOPPED - false - - - USE_CLKFB_STOPPED - false - - - RESET_PORT - reset - - - LOCKED_PORT - locked - - - POWER_DOWN_PORT - power_down - - - CLK_VALID_PORT - CLK_VALID - - - STATUS_PORT - STATUS - - - CLK_IN_SEL_PORT - clk_in_sel - - - INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - CLKFB_STOPPED_PORT - clkfb_stopped - - - SS_MODE - CENTER_HIGH - - - SS_MOD_FREQ - 250 - - - SS_MOD_TIME - 0.004 - - - OVERRIDE_MMCM - false - - - MMCM_NOTES - None - - - MMCM_DIVCLK_DIVIDE - 3 - - - MMCM_BANDWIDTH - OPTIMIZED - - - MMCM_CLKFBOUT_MULT_F - 43 - - - MMCM_CLKFBOUT_PHASE - 0.000 - - - MMCM_CLKFBOUT_USE_FINE_PS - false - - - MMCM_CLKIN1_PERIOD - 10.000 - - - MMCM_CLKIN2_PERIOD - 10.000 - - - MMCM_CLKOUT4_CASCADE - false - - - MMCM_CLOCK_HOLD - false - - - MMCM_COMPENSATION - ZHOLD - - - MMCM_REF_JITTER1 - 0.010 - - - MMCM_REF_JITTER2 - 0.010 - - - MMCM_STARTUP_WAIT - false - - - MMCM_CLKOUT0_DIVIDE_F - 72 - - - MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT0_PHASE - 0.000 - - - MMCM_CLKOUT0_USE_FINE_PS - false - - - MMCM_CLKOUT1_DIVIDE - 24 - - - MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT1_PHASE - 0.000 - - - MMCM_CLKOUT1_USE_FINE_PS - false - - - MMCM_CLKOUT2_DIVIDE - 13 - - - MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT2_PHASE - 0.000 - - - MMCM_CLKOUT2_USE_FINE_PS - false - - - MMCM_CLKOUT3_DIVIDE - 7 - - - MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT3_PHASE - 0.000 - - - MMCM_CLKOUT3_USE_FINE_PS - false - - - MMCM_CLKOUT4_DIVIDE - 6 - - - MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT4_PHASE - 0.000 - - - MMCM_CLKOUT4_USE_FINE_PS - false - - - MMCM_CLKOUT5_DIVIDE - 5 - - - MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT5_PHASE - 0.000 - - - MMCM_CLKOUT5_USE_FINE_PS - false - - - MMCM_CLKOUT6_DIVIDE - 1 - - - MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT6_PHASE - 0.000 - - - MMCM_CLKOUT6_USE_FINE_PS - false - - - OVERRIDE_PLL - false - - - PLL_NOTES - None - - - PLL_BANDWIDTH - OPTIMIZED - - - PLL_CLKFBOUT_MULT - 4 - - - PLL_CLKFBOUT_PHASE - 0.000 - - - PLL_CLK_FEEDBACK - CLKFBOUT - - - PLL_DIVCLK_DIVIDE - 1 - - - PLL_CLKIN_PERIOD - 10.000 - - - PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - PLL_REF_JITTER - 0.010 - - - PLL_CLKOUT0_DIVIDE - 1 - - - PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT0_PHASE - 0.000 - - - PLL_CLKOUT1_DIVIDE - 1 - - - PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT1_PHASE - 0.000 - - - PLL_CLKOUT2_DIVIDE - 1 - - - PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT2_PHASE - 0.000 - - - PLL_CLKOUT3_DIVIDE - 1 - - - PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT3_PHASE - 0.000 - - - PLL_CLKOUT4_DIVIDE - 1 - - - PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT4_PHASE - 0.000 - - - PLL_CLKOUT5_DIVIDE - 1 - - - PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT5_PHASE - 0.000 - - - RESET_TYPE - Reset Type - ACTIVE_HIGH - - - USE_SAFE_CLOCK_STARTUP - false - - - USE_CLOCK_SEQUENCING - false - - - CLKOUT1_SEQUENCE_NUMBER - 1 - - - CLKOUT2_SEQUENCE_NUMBER - 1 - - - CLKOUT3_SEQUENCE_NUMBER - 1 - - - CLKOUT4_SEQUENCE_NUMBER - 1 - - - CLKOUT5_SEQUENCE_NUMBER - 1 - - - CLKOUT6_SEQUENCE_NUMBER - 1 - - - CLKOUT7_SEQUENCE_NUMBER - 1 - - - USE_BOARD_FLOW - Generate Board based IO Constraints - false - - - CLK_IN1_BOARD_INTERFACE - Custom - - - CLK_IN2_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN1_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN2_BOARD_INTERFACE - Custom - - - AUTO_PRIMITIVE - MMCM - - - RESET_BOARD_INTERFACE - Custom - - - ENABLE_CDDC - false - - - CDDCDONE_PORT - cddcdone - - - CDDCREQ_PORT - cddcreq - - - ENABLE_CLKOUTPHY - false - - - CLKOUTPHY_REQUESTED_FREQ - 600.000 - - - CLKOUT1_JITTER - Clkout1 Jitter - 166.316 - - - CLKOUT1_PHASE_ERROR - Clkout1 Phase - 159.126 - - - CLKOUT2_JITTER - Clkout2 Jitter - 141.586 - - - CLKOUT2_PHASE_ERROR - Clkout2 Phase - 159.126 - - - CLKOUT3_JITTER - Clkout3 Jitter - 129.564 - - - CLKOUT3_PHASE_ERROR - Clkout3 Phase - 159.126 - - - CLKOUT4_JITTER - Clkout4 Jitter - 118.579 - - - CLKOUT4_PHASE_ERROR - Clkout4 Phase - 159.126 - - - CLKOUT5_JITTER - Clkout5 Jitter - 116.012 - - - CLKOUT5_PHASE_ERROR - Clkout5 Phase - 159.126 - - - CLKOUT6_JITTER - Clkout6 Jitter - 113.058 - - - CLKOUT6_PHASE_ERROR - Clkout6 Phase - 159.126 - - - CLKOUT7_JITTER - Clkout7 Jitter - 0.0 - - - CLKOUT7_PHASE_ERROR - Clkout7 Phase - 0.0 - - - INPUT_MODE - frequency - - - INTERFACE_SELECTION - Enable_AXI - - - AXI_DRP - Write DRP registers - false - - - PHASE_DUTY_CONFIG - Phase Duty Cycle Config - false - - - - - Clocking Wizard - - XPM_CDC - - 3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.1.1 - - - - - - - - diff --git a/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_3/clk_wiz_3.xml b/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_3/clk_wiz_3.xml deleted file mode 100644 index 5a41192..0000000 --- a/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_3/clk_wiz_3.xml +++ /dev/null @@ -1,5358 +0,0 @@ - - - xilinx.com - customized_ip - clk_wiz_3 - 1.0 - - - s_axi_lite - S_AXI_LITE - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARREADY - - - s_axi_arready - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWREADY - - - s_axi_awready - - - - - AWVALID - - - s_axi_awvalid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 1 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 1 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 0 - - - none - - - - - HAS_BRESP - 0 - - - none - - - - - HAS_RRESP - 0 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_aclk - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi_lite - - - ASSOCIATED_RESET - s_axi_aresetn - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - ref_clk - ref_clk - - - - - - - CLK - - - ref_clk - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_resetn - S_AXI_RESETN - - - - - - - RST - - - s_axi_aresetn - - - - - - ASSOCIATED_RESET - aresetn - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - intr - Intr - - - - - - - INTERRUPT - - - ip2intc_irpt - - - - - - SENSITIVITY - LEVEL_HIGH - - - none - - - - - PortWidth - 1 - - - none - - - - - - - - false - - - - - - CLK_IN1_D - CLK_IN1_D - Differential Clock input - - - - - - - CLK_N - - - clk_in1_n - - - - - CLK_P - - - clk_in1_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN1_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLK_IN2_D - CLK_IN2_D - Differential Clock input - - - - - - - CLK_N - - - clk_in2_n - - - - - CLK_P - - - clk_in2_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN2_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_IN_D - CLKFB_IN_D - Differential Feedback Clock input - - - - - - - CLK_N - - - clkfb_in_n - - - - - CLK_P - - - clkfb_in_p - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_OUT_D - CLKFB_OUT_D - Differential Feeback Clock Output - - - - - - - CLK_N - - - clkfb_out_n - - - - - CLK_P - - - clkfb_out_p - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - reset - reset - - - - - - - RST - - - reset - - - - - - POLARITY - ACTIVE_HIGH - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - resetn - resetn - - - - - - - RST - - - resetn - - - - - - POLARITY - ACTIVE_LOW - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - clock_CLK_IN1 - - - - - - - CLK_IN1 - - - clk_in1 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN1_BOARD_INTERFACE - - - - - clock_CLK_OUT1 - - - - - - - CLK_OUT1 - - - clk_out1 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT2 - - - - - - - CLK_OUT2 - - - clk_out2 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT3 - - - - - - - CLK_OUT3 - - - clk_out3 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT4 - - - - - - - CLK_OUT4 - - - clk_out4 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT5 - - - - - - - CLK_OUT5 - - - clk_out5 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT6 - - - - - - - CLK_OUT6 - - - clk_out6 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - xilinx_elaborateports - Elaborate Ports - :vivado.xilinx.com:elaborate.ports - - - outputProductCRC - 9:ed16cf65 - - - - - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog - clk_wiz_v6_0_3 - - xilinx_veriloginstantiationtemplate_view_fileset - - - - GENtimestamp - Sat Sep 14 01:10:10 UTC 2019 - - - outputProductCRC - 9:8f999f2a - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - clk_wiz_v6_0_3 - - xilinx_anylanguagesynthesis_view_fileset - - - - GENtimestamp - Sat Sep 14 01:10:11 UTC 2019 - - - outputProductCRC - 9:8f999f2a - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - - outputProductCRC - 9:8f999f2a - - - - - xilinx_anylanguagesynthesiswrapper - Synthesis Wrapper - :vivado.xilinx.com:synthesis.wrapper - clk_wiz_3 - - xilinx_anylanguagesynthesiswrapper_view_fileset - - - - GENtimestamp - Sat Sep 14 01:10:11 UTC 2019 - - - outputProductCRC - 9:8f999f2a - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - clk_wiz_v6_0_3 - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - GENtimestamp - Sat Sep 14 01:10:11 UTC 2019 - - - outputProductCRC - 9:26a8ab20 - - - - - xilinx_anylanguagesimulationwrapper - Simulation Wrapper - :vivado.xilinx.com:simulation.wrapper - clk_wiz_3 - - xilinx_anylanguagesimulationwrapper_view_fileset - - - - GENtimestamp - Sat Sep 14 01:10:11 UTC 2019 - - - outputProductCRC - 9:26a8ab20 - - - - - xilinx_implementation - Implementation - :vivado.xilinx.com:implementation - - xilinx_implementation_view_fileset - - - - GENtimestamp - Sat Sep 14 01:10:11 UTC 2019 - - - outputProductCRC - 9:8f999f2a - - - - - xilinx_versioninformation - Version Information - :vivado.xilinx.com:docs.versioninfo - - xilinx_versioninformation_view_fileset - - - - GENtimestamp - Sat Sep 14 01:10:11 UTC 2019 - - - outputProductCRC - 9:8f999f2a - - - - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Sat Sep 14 01:10:53 UTC 2019 - - - outputProductCRC - 9:8f999f2a - - - - - - - s_axi_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awaddr - - in - - 10 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - 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xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in2_n - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clkfb_in_p - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clkfb_in_n - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clkfb_out_p - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - clkfb_out_n - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - reset - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - resetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - ref_clk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_stop - - out - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_glitch - - out - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - interrupt - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_oor - - out - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - user_clk0 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - user_clk1 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - user_clk2 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - user_clk3 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in1 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - clk_out1 - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - clk_out2 - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - clk_out3 - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - clk_out4 - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - clk_out5 - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - clk_out6 - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - locked - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - C_CLKOUT2_USED - 1 - - - C_USER_CLK_FREQ0 - 100.0 - - - C_AUTO_PRIMITIVE - MMCM - - - C_USER_CLK_FREQ1 - 100.0 - - - C_USER_CLK_FREQ2 - 100.0 - - - C_USER_CLK_FREQ3 - 100.0 - - - C_ENABLE_CLOCK_MONITOR - 0 - - - C_ENABLE_USER_CLOCK0 - 0 - - - C_ENABLE_USER_CLOCK1 - 0 - - - C_ENABLE_USER_CLOCK2 - 0 - - - C_ENABLE_USER_CLOCK3 - 0 - - - C_Enable_PLL0 - 0 - - - C_Enable_PLL1 - 0 - - - C_REF_CLK_FREQ - 100.0 - - - C_PRECISION - 1 - - - C_CLKOUT3_USED - 1 - - - C_CLKOUT4_USED - 1 - - - C_CLKOUT5_USED - 1 - - - C_CLKOUT6_USED - 1 - - - C_CLKOUT7_USED - 0 - - - C_USE_CLKOUT1_BAR - 0 - - - C_USE_CLKOUT2_BAR - 0 - - - C_USE_CLKOUT3_BAR - 0 - - - C_USE_CLKOUT4_BAR - 0 - - - c_component_name - clk_wiz_3 - - - C_PLATFORM - UNKNOWN - - - C_USE_FREQ_SYNTH - 1 - - - C_USE_PHASE_ALIGNMENT - 1 - - - C_PRIM_IN_JITTER - 0.010 - - - C_SECONDARY_IN_JITTER - 0.010 - - - C_JITTER_SEL - No_Jitter - - - C_USE_MIN_POWER - 0 - - - C_USE_MIN_O_JITTER - 0 - - - C_USE_MAX_I_JITTER - 0 - - - C_USE_DYN_PHASE_SHIFT - 0 - - - C_USE_INCLK_SWITCHOVER - 0 - - - C_USE_DYN_RECONFIG - 0 - - - C_USE_SPREAD_SPECTRUM - 0 - - - C_USE_FAST_SIMULATION - 0 - - - C_PRIMTYPE_SEL - AUTO - - - C_USE_CLK_VALID - 0 - - - C_PRIM_IN_FREQ - 100.000 - - - C_PRIM_IN_TIMEPERIOD - 10.000 - - - C_IN_FREQ_UNITS - Units_MHz - - - C_SECONDARY_IN_FREQ - 100.000 - - - C_SECONDARY_IN_TIMEPERIOD - 10.000 - - - C_FEEDBACK_SOURCE - FDBK_AUTO - - - C_PRIM_SOURCE - Single_ended_clock_capable_pin - - - C_PHASESHIFT_MODE - WAVEFORM - - - C_SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - C_CLKFB_IN_SIGNALING - SINGLE - - - C_USE_RESET - 1 - - - C_RESET_LOW - 0 - - - C_USE_LOCKED - 1 - - - C_USE_INCLK_STOPPED - 0 - - - C_USE_CLKFB_STOPPED - 0 - - - C_USE_POWER_DOWN - 0 - - - C_USE_STATUS - 0 - - - C_USE_FREEZE - 0 - - - C_NUM_OUT_CLKS - 6 - - - C_CLKOUT1_DRIVES - BUFG - - - C_CLKOUT2_DRIVES - BUFG - - - C_CLKOUT3_DRIVES - BUFG - - - C_CLKOUT4_DRIVES - BUFG - - - C_CLKOUT5_DRIVES - BUFG - - - C_CLKOUT6_DRIVES - BUFG - - - C_CLKOUT7_DRIVES - BUFG - - - C_INCLK_SUM_ROW0 - Input Clock Freq (MHz) Input Jitter (UI) - - - C_INCLK_SUM_ROW1 - __primary_________100.000____________0.010 - - - C_INCLK_SUM_ROW2 - no_secondary_input_clock - - - C_OUTCLK_SUM_ROW0A - C Outclk Sum Row0a - Output Output Phase Duty Cycle Pk-to-Pk Phase - - - C_OUTCLK_SUM_ROW0B - Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - - - C_OUTCLK_SUM_ROW1 - clk_out1____30.000______0.000______50.0______359.896____310.955 - - - C_OUTCLK_SUM_ROW2 - clk_out2____70.000______0.000______50.0______304.472____310.955 - - - C_OUTCLK_SUM_ROW3 - clk_out3___120.000______0.000______50.0______279.155____310.955 - - - C_OUTCLK_SUM_ROW4 - clk_out4___168.000______0.000______50.0______265.458____310.955 - - - C_OUTCLK_SUM_ROW5 - clk_out5___210.000______0.000______50.0______256.770____310.955 - - - C_OUTCLK_SUM_ROW6 - clk_out6___280.000______0.000______50.0______246.015____310.955 - - - C_OUTCLK_SUM_ROW7 - no_CLK_OUT7_output - - - C_CLKOUT1_REQUESTED_OUT_FREQ - 30 - - - C_CLKOUT2_REQUESTED_OUT_FREQ - 70 - - - C_CLKOUT3_REQUESTED_OUT_FREQ - 120 - - - C_CLKOUT4_REQUESTED_OUT_FREQ - 170 - - - C_CLKOUT5_REQUESTED_OUT_FREQ - 220 - - - C_CLKOUT6_REQUESTED_OUT_FREQ - 270 - - - C_CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT1_REQUESTED_PHASE - 0.000 - - - C_CLKOUT2_REQUESTED_PHASE - 0.000 - - - C_CLKOUT3_REQUESTED_PHASE - 0.000 - - - C_CLKOUT4_REQUESTED_PHASE - 0.000 - - - C_CLKOUT5_REQUESTED_PHASE - 0.000 - - - C_CLKOUT6_REQUESTED_PHASE - 0.000 - - - C_CLKOUT7_REQUESTED_PHASE - 0.000 - - - C_CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT1_OUT_FREQ - 30.000 - - - C_CLKOUT2_OUT_FREQ - 70.000 - - - C_CLKOUT3_OUT_FREQ - 120.000 - - - C_CLKOUT4_OUT_FREQ - 168.000 - - - C_CLKOUT5_OUT_FREQ - 210.000 - - - C_CLKOUT6_OUT_FREQ - 280.000 - - - C_CLKOUT7_OUT_FREQ - 100.000 - - - C_CLKOUT1_PHASE - 0.000 - - - C_CLKOUT2_PHASE - 0.000 - - - C_CLKOUT3_PHASE - 0.000 - - - C_CLKOUT4_PHASE - 0.000 - - - C_CLKOUT5_PHASE - 0.000 - - - C_CLKOUT6_PHASE - 0.000 - - - C_CLKOUT7_PHASE - 0.000 - - - C_CLKOUT1_DUTY_CYCLE - 50.0 - - - C_CLKOUT2_DUTY_CYCLE - 50.0 - - - C_CLKOUT3_DUTY_CYCLE - 50.0 - - - C_CLKOUT4_DUTY_CYCLE - 50.0 - - - C_CLKOUT5_DUTY_CYCLE - 50.0 - - - C_CLKOUT6_DUTY_CYCLE - 50.0 - - - C_CLKOUT7_DUTY_CYCLE - 50.000 - - - C_USE_SAFE_CLOCK_STARTUP - 0 - - - C_USE_CLOCK_SEQUENCING - 0 - - - C_CLKOUT1_SEQUENCE_NUMBER - 1 - - - C_CLKOUT2_SEQUENCE_NUMBER - 1 - - - C_CLKOUT3_SEQUENCE_NUMBER - 1 - - - C_CLKOUT4_SEQUENCE_NUMBER - 1 - - - C_CLKOUT5_SEQUENCE_NUMBER - 1 - - - C_CLKOUT6_SEQUENCE_NUMBER - 1 - - - C_CLKOUT7_SEQUENCE_NUMBER - 1 - - - C_MMCM_NOTES - None - - - C_MMCM_BANDWIDTH - OPTIMIZED - - - C_MMCM_CLKFBOUT_MULT_F - 42.000 - - - C_MMCM_CLKIN1_PERIOD - 10.000 - - - C_MMCM_CLKIN2_PERIOD - 10.000 - - - C_MMCM_CLKOUT4_CASCADE - FALSE - - - C_MMCM_CLOCK_HOLD - FALSE - - - C_MMCM_COMPENSATION - ZHOLD - - - C_MMCM_DIVCLK_DIVIDE - 5 - - - C_MMCM_REF_JITTER1 - 0.010 - - - C_MMCM_REF_JITTER2 - 0.010 - - - C_MMCM_STARTUP_WAIT - FALSE - - - C_MMCM_CLKOUT0_DIVIDE_F - 28.000 - - - C_MMCM_CLKOUT1_DIVIDE - 12 - - - C_MMCM_CLKOUT2_DIVIDE - 7 - - - C_MMCM_CLKOUT3_DIVIDE - 5 - - - C_MMCM_CLKOUT4_DIVIDE - 4 - - - C_MMCM_CLKOUT5_DIVIDE - 3 - - - C_MMCM_CLKOUT6_DIVIDE - 1 - - - C_MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKFBOUT_PHASE - 0.000 - - - C_MMCM_CLKOUT0_PHASE - 0.000 - - - C_MMCM_CLKOUT1_PHASE - 0.000 - - - C_MMCM_CLKOUT2_PHASE - 0.000 - - - C_MMCM_CLKOUT3_PHASE - 0.000 - - - C_MMCM_CLKOUT4_PHASE - 0.000 - - - C_MMCM_CLKOUT5_PHASE - 0.000 - - - C_MMCM_CLKOUT6_PHASE - 0.000 - - - C_MMCM_CLKFBOUT_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT0_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT1_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT2_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT3_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT4_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT5_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT6_USE_FINE_PS - FALSE - - - C_PLL_NOTES - No notes - - - C_PLL_BANDWIDTH - OPTIMIZED - - - C_PLL_CLK_FEEDBACK - CLKFBOUT - - - C_PLL_CLKFBOUT_MULT - 1 - - - C_PLL_CLKIN_PERIOD - 1.000 - - - C_PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - C_PLL_DIVCLK_DIVIDE - 1 - - - C_PLL_REF_JITTER - 0.010 - - - C_PLL_CLKOUT0_DIVIDE - 1 - - - C_PLL_CLKOUT1_DIVIDE - 1 - - - C_PLL_CLKOUT2_DIVIDE - 1 - - - C_PLL_CLKOUT3_DIVIDE - 1 - - - C_PLL_CLKOUT4_DIVIDE - 1 - - - C_PLL_CLKOUT5_DIVIDE - 1 - - - C_PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_PLL_CLKFBOUT_PHASE - 0.000 - - - C_PLL_CLKOUT0_PHASE - 0.000 - - - C_PLL_CLKOUT1_PHASE - 0.000 - - - C_PLL_CLKOUT2_PHASE - 0.000 - - - C_PLL_CLKOUT3_PHASE - 0.000 - - - C_PLL_CLKOUT4_PHASE - 0.000 - - - C_PLL_CLKOUT5_PHASE - 0.000 - - - C_CLOCK_MGR_TYPE - NA - - - C_OVERRIDE_MMCM - 0 - - - C_OVERRIDE_PLL - 0 - - - C_PRIMARY_PORT - clk_in1 - - - C_SECONDARY_PORT - clk_in2 - - - C_CLK_OUT1_PORT - clk_out1 - - - C_CLK_OUT2_PORT - clk_out2 - - - C_CLK_OUT3_PORT - clk_out3 - - - C_CLK_OUT4_PORT - clk_out4 - - - C_CLK_OUT5_PORT - clk_out5 - - - C_CLK_OUT6_PORT - clk_out6 - - - C_CLK_OUT7_PORT - clk_out7 - - - C_RESET_PORT - reset - - - C_LOCKED_PORT - locked - - - C_CLKFB_IN_PORT - clkfb_in - - - C_CLKFB_IN_P_PORT - clkfb_in_p - - - C_CLKFB_IN_N_PORT - clkfb_in_n - - - C_CLKFB_OUT_PORT - clkfb_out - - - C_CLKFB_OUT_P_PORT - clkfb_out_p - - - C_CLKFB_OUT_N_PORT - clkfb_out_n - - - C_POWER_DOWN_PORT - power_down - - - C_DADDR_PORT - daddr - - - C_DCLK_PORT - dclk - - - C_DRDY_PORT - drdy - - - C_DWE_PORT - dwe - - - C_DIN_PORT - din - - - C_DOUT_PORT - dout - - - C_DEN_PORT - den - - - C_PSCLK_PORT - psclk - - - C_PSEN_PORT - psen - - - C_PSINCDEC_PORT - psincdec - - - C_PSDONE_PORT - psdone - - - C_CLK_VALID_PORT - CLK_VALID - - - C_STATUS_PORT - STATUS - - - C_CLK_IN_SEL_PORT - clk_in_sel - - - C_INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - C_CLKFB_STOPPED_PORT - clkfb_stopped - - - C_CLKIN1_JITTER_PS - 100.0 - - - C_CLKIN2_JITTER_PS - 100.0 - - - C_PRIMITIVE - PLL - - - C_SS_MODE - CENTER_HIGH - - - C_SS_MOD_PERIOD - 4000 - - - C_SS_MOD_TIME - 0.004 - - - C_HAS_CDDC - 0 - - - C_CDDCDONE_PORT - cddcdone - - - C_CDDCREQ_PORT - cddcreq - - - C_CLKOUTPHY_MODE - VCO - - - C_ENABLE_CLKOUTPHY - 0 - - - C_INTERFACE_SELECTION - 0 - - - C_S_AXI_ADDR_WIDTH - C S Axi Addr Width - 11 - - - C_S_AXI_DATA_WIDTH - C S Axi Data Width - 32 - - - C_POWER_REG - 0000 - - - C_CLKOUT0_1 - 0000 - - - C_CLKOUT0_2 - 0000 - - - C_CLKOUT1_1 - 0000 - - - C_CLKOUT1_2 - 0000 - - - C_CLKOUT2_1 - 0000 - - - C_CLKOUT2_2 - 0000 - - - C_CLKOUT3_1 - 0000 - - - C_CLKOUT3_2 - 0000 - - - C_CLKOUT4_1 - 0000 - - - C_CLKOUT4_2 - 0000 - - - C_CLKOUT5_1 - 0000 - - - C_CLKOUT5_2 - 0000 - - - C_CLKOUT6_1 - 0000 - - - C_CLKOUT6_2 - 0000 - - - C_CLKFBOUT_1 - 0000 - - - C_CLKFBOUT_2 - 0000 - - - C_DIVCLK - 0000 - - - C_LOCK_1 - 0000 - - - C_LOCK_2 - 0000 - - - C_LOCK_3 - 0000 - - - C_FILTER_1 - 0000 - - - C_FILTER_2 - 0000 - - - C_DIVIDE1_AUTO - 1 - - - C_DIVIDE2_AUTO - 0.42857142857142855 - - - C_DIVIDE3_AUTO - 0.25 - - - C_DIVIDE4_AUTO - 0.17647058823529413 - - - C_DIVIDE5_AUTO - 0.13636363636363635 - - - C_DIVIDE6_AUTO - 0.1111111111111111 - - - C_DIVIDE7_AUTO - 0.3 - - - C_PLLBUFGCEDIV - false - - - C_MMCMBUFGCEDIV - false - - - C_PLLBUFGCEDIV1 - false - - - C_PLLBUFGCEDIV2 - false - - - C_PLLBUFGCEDIV3 - false - - - C_PLLBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV1 - false - - - C_MMCMBUFGCEDIV2 - false - - - C_MMCMBUFGCEDIV3 - false - - - C_MMCMBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV5 - false - - - C_MMCMBUFGCEDIV6 - false - - - C_MMCMBUFGCEDIV7 - false - - - C_CLKOUT1_MATCHED_ROUTING - false - - - C_CLKOUT2_MATCHED_ROUTING - false - - - C_CLKOUT3_MATCHED_ROUTING - false - - - C_CLKOUT4_MATCHED_ROUTING - false - - - C_CLKOUT5_MATCHED_ROUTING - false - - - C_CLKOUT6_MATCHED_ROUTING - false - - - C_CLKOUT7_MATCHED_ROUTING - false - - - C_CLKOUT0_ACTUAL_FREQ - 30.000 - - - C_CLKOUT1_ACTUAL_FREQ - 70.000 - - - C_CLKOUT2_ACTUAL_FREQ - 120.000 - - - C_CLKOUT3_ACTUAL_FREQ - 168.000 - - - C_CLKOUT4_ACTUAL_FREQ - 210.000 - - - C_CLKOUT5_ACTUAL_FREQ - 280.000 - - - C_CLKOUT6_ACTUAL_FREQ - 100.000 - - - - - - choice_list_1d3de01d - WAVEFORM - LATENCY - - - choice_list_876bfc32 - UI - PS - - - choice_list_a9bdfce0 - LOW - HIGH - OPTIMIZED - - - choice_list_ac75ef1e - Custom - - - choice_list_b9d38208 - CLKFBOUT - CLKOUT0 - - - choice_list_e099fe6c - MMCM - PLL - - - choice_pairs_035ca1c3 - SYSTEM_SYNCHRONOUS - SOURCE_SYNCHRONOUS - INTERNAL - EXTERNAL - - - choice_pairs_0920eb1b - Custom - sys_diff_clock - - - choice_pairs_11d71346 - Single_ended_clock_capable_pin - Differential_clock_capable_pin - Global_buffer - No_buffer - - - choice_pairs_15c806d5 - FDBK_AUTO - FDBK_AUTO_OFFCHIP - FDBK_ONCHIP - FDBK_OFFCHIP - - - choice_pairs_340369e0 - Custom - sys_clock - sys_diff_clock - - - choice_pairs_3c2d3ec7 - SINGLE - DIFF - - - choice_pairs_502d9f23 - ZHOLD - EXTERNAL - INTERNAL - BUF_IN - - - choice_pairs_66e4c81f - BUFG - BUFH - BUFGCE - BUFHCE - No_buffer - - - choice_pairs_77d3d587 - MMCM - PLL - BUFGCE_DIV - - - choice_pairs_8b28f1f7 - Enable_AXI - Enable_DRP - - - choice_pairs_8eea9b32 - Units_MHz - Units_ns - - - choice_pairs_a4fbc00c - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_a8642b4c - No_Jitter - Min_O_Jitter - Max_I_Jitter - - - choice_pairs_c5ef7212 - Units_UI - Units_ps - - - choice_pairs_e1c87518 - REL_PRIMARY - REL_SECONDARY - - - choice_pairs_f4e10086 - CENTER_HIGH - CENTER_LOW - DOWN_HIGH - DOWN_LOW - - - choice_pairs_f669c2f5 - frequency - Time - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - clk_wiz_3.veo - verilogTemplate - - - - xilinx_anylanguagesynthesis_view_fileset - - clk_wiz_3.xdc - xdc - - processing_order - early - - - - clk_wiz_3_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - mmcm_pll_drp_func_7s_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_7s_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - clk_wiz_3_clk_wiz.v - verilogSource - - - - xilinx_anylanguagesynthesiswrapper_view_fileset - - clk_wiz_3.v - verilogSource - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - mmcm_pll_drp_func_7s_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_7s_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - clk_wiz_3_clk_wiz.v - verilogSource - - - - xilinx_anylanguagesimulationwrapper_view_fileset - - clk_wiz_3.v - verilogSource - - - - xilinx_implementation_view_fileset - - clk_wiz_3_board.xdc - xdc - USED_IN_board - USED_IN_implementation - USED_IN_synthesis - - - - xilinx_versioninformation_view_fileset - - doc/clk_wiz_v6_0_changelog.txt - text - - - - xilinx_externalfiles_view_fileset - - clk_wiz_3.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - clk_wiz_3_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - clk_wiz_3_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - clk_wiz_3_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - clk_wiz_3_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. - - - Component_Name - clk_wiz_3 - - - USER_CLK_FREQ0 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ1 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ2 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ3 - User Frequency(MHz) - 100.0 - - - ENABLE_CLOCK_MONITOR - Enable Clock Monitoring - false - - - ENABLE_USER_CLOCK0 - User Clock - false - - - ENABLE_USER_CLOCK1 - User Clock - false - - - ENABLE_USER_CLOCK2 - User Clock - false - - - ENABLE_USER_CLOCK3 - User Clock - false - - - Enable_PLL0 - User Clock - false - - - Enable_PLL1 - User Clock - false - - - REF_CLK_FREQ - Reference Frequency(MHz) - 100.0 - - - PRECISION - Tolerance(MHz) - 1 - - - PRIMITIVE - Primitive - PLL - - - PRIMTYPE_SEL - Primtype Sel - mmcm_adv - - - CLOCK_MGR_TYPE - Clock Mgr Type - auto - - - USE_FREQ_SYNTH - true - - - USE_SPREAD_SPECTRUM - false - - - USE_PHASE_ALIGNMENT - true - - - USE_MIN_POWER - false - - - USE_DYN_PHASE_SHIFT - false - - - USE_DYN_RECONFIG - false - - - JITTER_SEL - No_Jitter - - - PRIM_IN_FREQ - 100.000 - - - PRIM_IN_TIMEPERIOD - 10.000 - - - IN_FREQ_UNITS - Units_MHz - - - PHASESHIFT_MODE - WAVEFORM - - - IN_JITTER_UNITS - Units_UI - - - RELATIVE_INCLK - REL_PRIMARY - - - USE_INCLK_SWITCHOVER - false - - - SECONDARY_IN_FREQ - 100.000 - - - SECONDARY_IN_TIMEPERIOD - 10.000 - - - SECONDARY_PORT - clk_in2 - - - SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - JITTER_OPTIONS - UI - - - CLKIN1_UI_JITTER - 0.010 - - - CLKIN2_UI_JITTER - 0.010 - - - PRIM_IN_JITTER - 0.010 - - - SECONDARY_IN_JITTER - 0.010 - - - CLKIN1_JITTER_PS - 100.0 - - - CLKIN2_JITTER_PS - 100.0 - - - CLKOUT1_USED - true - - - CLKOUT2_USED - true - - - CLKOUT3_USED - true - - - CLKOUT4_USED - true - - - CLKOUT5_USED - true - - - CLKOUT6_USED - true - - - CLKOUT7_USED - false - - - NUM_OUT_CLKS - 6 - - - CLK_OUT1_USE_FINE_PS_GUI - false - - - CLK_OUT2_USE_FINE_PS_GUI - false - - - CLK_OUT3_USE_FINE_PS_GUI - false - - - CLK_OUT4_USE_FINE_PS_GUI - false - - - CLK_OUT5_USE_FINE_PS_GUI - false - - - CLK_OUT6_USE_FINE_PS_GUI - false - - - CLK_OUT7_USE_FINE_PS_GUI - false - - - PRIMARY_PORT - clk_in1 - - - CLK_OUT1_PORT - clk_out1 - - - CLK_OUT2_PORT - clk_out2 - - - CLK_OUT3_PORT - clk_out3 - - - CLK_OUT4_PORT - clk_out4 - - - CLK_OUT5_PORT - clk_out5 - - - CLK_OUT6_PORT - clk_out6 - - - CLK_OUT7_PORT - clk_out7 - - - DADDR_PORT - daddr - - - DCLK_PORT - dclk - - - DRDY_PORT - drdy - - - DWE_PORT - dwe - - - DIN_PORT - din - - - DOUT_PORT - dout - - - DEN_PORT - den - - - PSCLK_PORT - psclk - - - PSEN_PORT - psen - - - PSINCDEC_PORT - psincdec - - - PSDONE_PORT - psdone - - - CLKOUT1_REQUESTED_OUT_FREQ - 30 - - - CLKOUT1_REQUESTED_PHASE - 0.000 - - - CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT2_REQUESTED_OUT_FREQ - 70 - - - CLKOUT2_REQUESTED_PHASE - 0.000 - - - CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT3_REQUESTED_OUT_FREQ - 120 - - - CLKOUT3_REQUESTED_PHASE - 0.000 - - - CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT4_REQUESTED_OUT_FREQ - 170 - - - CLKOUT4_REQUESTED_PHASE - 0.000 - - - CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT5_REQUESTED_OUT_FREQ - 220 - - - CLKOUT5_REQUESTED_PHASE - 0.000 - - - CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT6_REQUESTED_OUT_FREQ - 270 - - - CLKOUT6_REQUESTED_PHASE - 0.000 - - - CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT7_REQUESTED_PHASE - 0.000 - - - CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - USE_MAX_I_JITTER - false - - - USE_MIN_O_JITTER - false - - - CLKOUT1_MATCHED_ROUTING - false - - - CLKOUT2_MATCHED_ROUTING - false - - - CLKOUT3_MATCHED_ROUTING - false - - - CLKOUT4_MATCHED_ROUTING - false - - - CLKOUT5_MATCHED_ROUTING - false - - - CLKOUT6_MATCHED_ROUTING - false - - - CLKOUT7_MATCHED_ROUTING - false - - - PRIM_SOURCE - Single_ended_clock_capable_pin - - - CLKOUT1_DRIVES - BUFG - - - CLKOUT2_DRIVES - BUFG - - - CLKOUT3_DRIVES - BUFG - - - CLKOUT4_DRIVES - BUFG - - - CLKOUT5_DRIVES - BUFG - - - CLKOUT6_DRIVES - BUFG - - - CLKOUT7_DRIVES - BUFG - - - FEEDBACK_SOURCE - FDBK_AUTO - - - CLKFB_IN_SIGNALING - SINGLE - - - CLKFB_IN_PORT - clkfb_in - - - CLKFB_IN_P_PORT - clkfb_in_p - - - CLKFB_IN_N_PORT - clkfb_in_n - - - CLKFB_OUT_PORT - clkfb_out - - - CLKFB_OUT_P_PORT - clkfb_out_p - - - CLKFB_OUT_N_PORT - clkfb_out_n - - - PLATFORM - UNKNOWN - - - SUMMARY_STRINGS - empty - - - USE_LOCKED - true - - - CALC_DONE - empty - - - USE_RESET - true - - - USE_POWER_DOWN - false - - - USE_STATUS - false - - - USE_FREEZE - false - - - USE_CLK_VALID - false - - - USE_INCLK_STOPPED - false - - - USE_CLKFB_STOPPED - false - - - RESET_PORT - reset - - - LOCKED_PORT - locked - - - POWER_DOWN_PORT - power_down - - - CLK_VALID_PORT - CLK_VALID - - - STATUS_PORT - STATUS - - - CLK_IN_SEL_PORT - clk_in_sel - - - INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - CLKFB_STOPPED_PORT - clkfb_stopped - - - SS_MODE - CENTER_HIGH - - - SS_MOD_FREQ - 250 - - - SS_MOD_TIME - 0.004 - - - OVERRIDE_MMCM - false - - - MMCM_NOTES - None - - - MMCM_DIVCLK_DIVIDE - 5 - - - MMCM_BANDWIDTH - OPTIMIZED - - - MMCM_CLKFBOUT_MULT_F - 42 - - - MMCM_CLKFBOUT_PHASE - 0.000 - - - MMCM_CLKFBOUT_USE_FINE_PS - false - - - MMCM_CLKIN1_PERIOD - 10.000 - - - MMCM_CLKIN2_PERIOD - 10.000 - - - MMCM_CLKOUT4_CASCADE - false - - - MMCM_CLOCK_HOLD - false - - - MMCM_COMPENSATION - ZHOLD - - - MMCM_REF_JITTER1 - 0.010 - - - MMCM_REF_JITTER2 - 0.010 - - - MMCM_STARTUP_WAIT - false - - - MMCM_CLKOUT0_DIVIDE_F - 28 - - - MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT0_PHASE - 0.000 - - - MMCM_CLKOUT0_USE_FINE_PS - false - - - MMCM_CLKOUT1_DIVIDE - 12 - - - MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT1_PHASE - 0.000 - - - MMCM_CLKOUT1_USE_FINE_PS - false - - - MMCM_CLKOUT2_DIVIDE - 7 - - - MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT2_PHASE - 0.000 - - - MMCM_CLKOUT2_USE_FINE_PS - false - - - MMCM_CLKOUT3_DIVIDE - 5 - - - MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT3_PHASE - 0.000 - - - MMCM_CLKOUT3_USE_FINE_PS - false - - - MMCM_CLKOUT4_DIVIDE - 4 - - - MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT4_PHASE - 0.000 - - - MMCM_CLKOUT4_USE_FINE_PS - false - - - MMCM_CLKOUT5_DIVIDE - 3 - - - MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT5_PHASE - 0.000 - - - MMCM_CLKOUT5_USE_FINE_PS - false - - - MMCM_CLKOUT6_DIVIDE - 1 - - - MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT6_PHASE - 0.000 - - - MMCM_CLKOUT6_USE_FINE_PS - false - - - OVERRIDE_PLL - false - - - PLL_NOTES - None - - - PLL_BANDWIDTH - OPTIMIZED - - - PLL_CLKFBOUT_MULT - 4 - - - PLL_CLKFBOUT_PHASE - 0.000 - - - PLL_CLK_FEEDBACK - CLKFBOUT - - - PLL_DIVCLK_DIVIDE - 1 - - - PLL_CLKIN_PERIOD - 10.000 - - - PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - PLL_REF_JITTER - 0.010 - - - PLL_CLKOUT0_DIVIDE - 1 - - - PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT0_PHASE - 0.000 - - - PLL_CLKOUT1_DIVIDE - 1 - - - PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT1_PHASE - 0.000 - - - PLL_CLKOUT2_DIVIDE - 1 - - - PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT2_PHASE - 0.000 - - - PLL_CLKOUT3_DIVIDE - 1 - - - PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT3_PHASE - 0.000 - - - PLL_CLKOUT4_DIVIDE - 1 - - - PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT4_PHASE - 0.000 - - - PLL_CLKOUT5_DIVIDE - 1 - - - PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT5_PHASE - 0.000 - - - RESET_TYPE - Reset Type - ACTIVE_HIGH - - - USE_SAFE_CLOCK_STARTUP - false - - - USE_CLOCK_SEQUENCING - false - - - CLKOUT1_SEQUENCE_NUMBER - 1 - - - CLKOUT2_SEQUENCE_NUMBER - 1 - - - CLKOUT3_SEQUENCE_NUMBER - 1 - - - CLKOUT4_SEQUENCE_NUMBER - 1 - - - CLKOUT5_SEQUENCE_NUMBER - 1 - - - CLKOUT6_SEQUENCE_NUMBER - 1 - - - CLKOUT7_SEQUENCE_NUMBER - 1 - - - USE_BOARD_FLOW - Generate Board based IO Constraints - false - - - CLK_IN1_BOARD_INTERFACE - Custom - - - CLK_IN2_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN1_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN2_BOARD_INTERFACE - Custom - - - AUTO_PRIMITIVE - MMCM - - - RESET_BOARD_INTERFACE - Custom - - - ENABLE_CDDC - false - - - CDDCDONE_PORT - cddcdone - - - CDDCREQ_PORT - cddcreq - - - ENABLE_CLKOUTPHY - false - - - CLKOUTPHY_REQUESTED_FREQ - 600.000 - - - CLKOUT1_JITTER - Clkout1 Jitter - 359.896 - - - CLKOUT1_PHASE_ERROR - Clkout1 Phase - 310.955 - - - CLKOUT2_JITTER - Clkout2 Jitter - 304.472 - - - CLKOUT2_PHASE_ERROR - Clkout2 Phase - 310.955 - - - CLKOUT3_JITTER - Clkout3 Jitter - 279.155 - - - CLKOUT3_PHASE_ERROR - Clkout3 Phase - 310.955 - - - CLKOUT4_JITTER - Clkout4 Jitter - 265.458 - - - CLKOUT4_PHASE_ERROR - Clkout4 Phase - 310.955 - - - CLKOUT5_JITTER - Clkout5 Jitter - 256.770 - - - CLKOUT5_PHASE_ERROR - Clkout5 Phase - 310.955 - - - CLKOUT6_JITTER - Clkout6 Jitter - 246.015 - - - CLKOUT6_PHASE_ERROR - Clkout6 Phase - 310.955 - - - CLKOUT7_JITTER - Clkout7 Jitter - 0.0 - - - CLKOUT7_PHASE_ERROR - Clkout7 Phase - 0.0 - - - INPUT_MODE - frequency - - - INTERFACE_SELECTION - Enable_AXI - - - AXI_DRP - Write DRP registers - false - - - PHASE_DUTY_CONFIG - Phase Duty Cycle Config - false - - - - - Clocking Wizard - - XPM_CDC - - 3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.1.1 - - - - - - - - diff --git a/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_4/clk_wiz_4.xml b/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_4/clk_wiz_4.xml deleted file mode 100644 index 43c282a..0000000 --- a/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_4/clk_wiz_4.xml +++ /dev/null @@ -1,5359 +0,0 @@ - - - xilinx.com - customized_ip - clk_wiz_4 - 1.0 - - - s_axi_lite - S_AXI_LITE - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARREADY - - - s_axi_arready - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWREADY - - - s_axi_awready - - - - - AWVALID - - - s_axi_awvalid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 1 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 1 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 0 - - - none - - - - - HAS_BRESP - 0 - - - none - - - - - HAS_RRESP - 0 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_aclk - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi_lite - - - ASSOCIATED_RESET - s_axi_aresetn - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - ref_clk - ref_clk - - - - - - - CLK - - - ref_clk - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_resetn - S_AXI_RESETN - - - - - - - RST - - - s_axi_aresetn - - - - - - ASSOCIATED_RESET - aresetn - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - intr - Intr - - - - - - - INTERRUPT - - - ip2intc_irpt - - - - - - SENSITIVITY - LEVEL_HIGH - - - none - - - - - PortWidth - 1 - - - none - - - - - - - - false - - - - - - CLK_IN1_D - CLK_IN1_D - Differential Clock input - - - - - - - CLK_N - - - clk_in1_n - - - - - CLK_P - - - clk_in1_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN1_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLK_IN2_D - CLK_IN2_D - Differential Clock input - - - - - - - CLK_N - - - clk_in2_n - - - - - CLK_P - - - clk_in2_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN2_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_IN_D - CLKFB_IN_D - Differential Feedback Clock input - - - - - - - CLK_N - - - clkfb_in_n - - - - - CLK_P - - - clkfb_in_p - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_OUT_D - CLKFB_OUT_D - Differential Feeback Clock Output - - - - - - - CLK_N - - - clkfb_out_n - - - - - CLK_P - - - clkfb_out_p - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - reset - reset - - - - - - - RST - - - reset - - - - - - POLARITY - ACTIVE_HIGH - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - resetn - resetn - - - - - - - RST - - - resetn - - - - - - POLARITY - ACTIVE_LOW - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - clock_CLK_IN1 - - - - - - - CLK_IN1 - - - clk_in1 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN1_BOARD_INTERFACE - - - - - clock_CLK_OUT1 - - - - - - - CLK_OUT1 - - - clk_out1 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT2 - - - - - - - CLK_OUT2 - - - clk_out2 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT3 - - - - - - - CLK_OUT3 - - - clk_out3 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT4 - - - - - - - CLK_OUT4 - - - clk_out4 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT5 - - - - - - - CLK_OUT5 - - - clk_out5 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT6 - - - - - - - CLK_OUT6 - - - clk_out6 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - xilinx_elaborateports - Elaborate Ports - :vivado.xilinx.com:elaborate.ports - - - outputProductCRC - 9:981b1b63 - - - - - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog - clk_wiz_v6_0_3 - - xilinx_veriloginstantiationtemplate_view_fileset - - - - GENtimestamp - Sat Sep 14 01:11:28 UTC 2019 - - - outputProductCRC - 9:77d5e289 - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - clk_wiz_v6_0_3 - - xilinx_anylanguagesynthesis_view_fileset - - - - GENtimestamp - Sat Sep 14 01:11:29 UTC 2019 - - - outputProductCRC - 9:77d5e289 - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - - outputProductCRC - 9:77d5e289 - - - - - xilinx_anylanguagesynthesiswrapper - Synthesis Wrapper - :vivado.xilinx.com:synthesis.wrapper - clk_wiz_4 - - xilinx_anylanguagesynthesiswrapper_view_fileset - - - - GENtimestamp - Sat Sep 14 01:11:29 UTC 2019 - - - outputProductCRC - 9:77d5e289 - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - clk_wiz_v6_0_3 - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - GENtimestamp - Sat Sep 14 01:11:29 UTC 2019 - - - outputProductCRC - 9:29758648 - - - - - xilinx_anylanguagesimulationwrapper - Simulation Wrapper - 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UNKNOWN - - - C_USE_FREQ_SYNTH - 1 - - - C_USE_PHASE_ALIGNMENT - 1 - - - C_PRIM_IN_JITTER - 0.010 - - - C_SECONDARY_IN_JITTER - 0.010 - - - C_JITTER_SEL - No_Jitter - - - C_USE_MIN_POWER - 0 - - - C_USE_MIN_O_JITTER - 0 - - - C_USE_MAX_I_JITTER - 0 - - - C_USE_DYN_PHASE_SHIFT - 0 - - - C_USE_INCLK_SWITCHOVER - 0 - - - C_USE_DYN_RECONFIG - 0 - - - C_USE_SPREAD_SPECTRUM - 0 - - - C_USE_FAST_SIMULATION - 0 - - - C_PRIMTYPE_SEL - AUTO - - - C_USE_CLK_VALID - 0 - - - C_PRIM_IN_FREQ - 100.000 - - - C_PRIM_IN_TIMEPERIOD - 10.000 - - - C_IN_FREQ_UNITS - Units_MHz - - - C_SECONDARY_IN_FREQ - 100.000 - - - C_SECONDARY_IN_TIMEPERIOD - 10.000 - - - C_FEEDBACK_SOURCE - FDBK_AUTO - - - C_PRIM_SOURCE - Single_ended_clock_capable_pin - - - C_PHASESHIFT_MODE - WAVEFORM - - - C_SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - C_CLKFB_IN_SIGNALING - SINGLE - - - C_USE_RESET - 1 - - - C_RESET_LOW - 0 - - - C_USE_LOCKED - 1 - - - C_USE_INCLK_STOPPED - 0 - - - C_USE_CLKFB_STOPPED - 0 - - - C_USE_POWER_DOWN - 0 - - - C_USE_STATUS - 0 - - - C_USE_FREEZE - 0 - - - C_NUM_OUT_CLKS - 6 - - - C_CLKOUT1_DRIVES - BUFG - - - C_CLKOUT2_DRIVES - BUFG - - - C_CLKOUT3_DRIVES - BUFG - - - C_CLKOUT4_DRIVES - BUFG - - - C_CLKOUT5_DRIVES - BUFG - - - C_CLKOUT6_DRIVES - BUFG - - - C_CLKOUT7_DRIVES - BUFG - - - C_INCLK_SUM_ROW0 - Input Clock Freq (MHz) Input Jitter (UI) - - - C_INCLK_SUM_ROW1 - __primary_________100.000____________0.010 - - - C_INCLK_SUM_ROW2 - no_secondary_input_clock - - - C_OUTCLK_SUM_ROW0A - C Outclk Sum Row0a - Output Output Phase Duty Cycle Pk-to-Pk Phase - - - C_OUTCLK_SUM_ROW0B - Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - - - C_OUTCLK_SUM_ROW1 - clk_out1____40.000______0.000______50.0______264.672____300.278 - - - C_OUTCLK_SUM_ROW2 - clk_out2____80.000______0.000______50.0______240.422____300.278 - - - C_OUTCLK_SUM_ROW3 - clk_out3___130.000______0.000______50.0______224.856____300.278 - - - C_OUTCLK_SUM_ROW4 - clk_out4___173.333______0.000______50.0______216.148____300.278 - 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50.000 - - - C_CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT1_OUT_FREQ - 40.000 - - - C_CLKOUT2_OUT_FREQ - 80.000 - - - C_CLKOUT3_OUT_FREQ - 130.000 - - - C_CLKOUT4_OUT_FREQ - 173.333 - - - C_CLKOUT5_OUT_FREQ - 208.000 - - - C_CLKOUT6_OUT_FREQ - 260.000 - - - C_CLKOUT7_OUT_FREQ - 100.000 - - - C_CLKOUT1_PHASE - 0.000 - - - C_CLKOUT2_PHASE - 0.000 - - - C_CLKOUT3_PHASE - 0.000 - - - C_CLKOUT4_PHASE - 0.000 - - - C_CLKOUT5_PHASE - 0.000 - - - C_CLKOUT6_PHASE - 0.000 - - - C_CLKOUT7_PHASE - 0.000 - - - C_CLKOUT1_DUTY_CYCLE - 50.0 - - - C_CLKOUT2_DUTY_CYCLE - 50.0 - - - C_CLKOUT3_DUTY_CYCLE - 50.0 - - - C_CLKOUT4_DUTY_CYCLE - 50.0 - - - C_CLKOUT5_DUTY_CYCLE - 50.0 - - - C_CLKOUT6_DUTY_CYCLE - 50.0 - - - C_CLKOUT7_DUTY_CYCLE - 50.000 - - - C_USE_SAFE_CLOCK_STARTUP - 0 - - - C_USE_CLOCK_SEQUENCING - 0 - - - C_CLKOUT1_SEQUENCE_NUMBER - 1 - - - C_CLKOUT2_SEQUENCE_NUMBER - 1 - - - C_CLKOUT3_SEQUENCE_NUMBER - 1 - - - C_CLKOUT4_SEQUENCE_NUMBER - 1 - - - C_CLKOUT5_SEQUENCE_NUMBER - 1 - - - C_CLKOUT6_SEQUENCE_NUMBER - 1 - - - C_CLKOUT7_SEQUENCE_NUMBER - 1 - - - C_MMCM_NOTES - None - - - C_MMCM_BANDWIDTH - OPTIMIZED - - - C_MMCM_CLKFBOUT_MULT_F - 52.000 - - - C_MMCM_CLKIN1_PERIOD - 10.000 - - - C_MMCM_CLKIN2_PERIOD - 10.000 - - - C_MMCM_CLKOUT4_CASCADE - FALSE - - - C_MMCM_CLOCK_HOLD - FALSE - - - C_MMCM_COMPENSATION - ZHOLD - - - C_MMCM_DIVCLK_DIVIDE - 5 - - - C_MMCM_REF_JITTER1 - 0.010 - - - C_MMCM_REF_JITTER2 - 0.010 - - - C_MMCM_STARTUP_WAIT - FALSE - - - C_MMCM_CLKOUT0_DIVIDE_F - 26.000 - - - C_MMCM_CLKOUT1_DIVIDE - 13 - - - C_MMCM_CLKOUT2_DIVIDE - 8 - - - C_MMCM_CLKOUT3_DIVIDE - 6 - - - C_MMCM_CLKOUT4_DIVIDE - 5 - - - C_MMCM_CLKOUT5_DIVIDE - 4 - - - C_MMCM_CLKOUT6_DIVIDE - 1 - - - C_MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKFBOUT_PHASE - 0.000 - - - C_MMCM_CLKOUT0_PHASE - 0.000 - - - C_MMCM_CLKOUT1_PHASE - 0.000 - - - C_MMCM_CLKOUT2_PHASE - 0.000 - - - C_MMCM_CLKOUT3_PHASE - 0.000 - - - C_MMCM_CLKOUT4_PHASE - 0.000 - - - C_MMCM_CLKOUT5_PHASE - 0.000 - - - C_MMCM_CLKOUT6_PHASE - 0.000 - - - C_MMCM_CLKFBOUT_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT0_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT1_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT2_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT3_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT4_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT5_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT6_USE_FINE_PS - FALSE - - - C_PLL_NOTES - No notes - - - C_PLL_BANDWIDTH - OPTIMIZED - - - C_PLL_CLK_FEEDBACK - CLKFBOUT - - - C_PLL_CLKFBOUT_MULT - 1 - - - C_PLL_CLKIN_PERIOD - 1.000 - - - C_PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - C_PLL_DIVCLK_DIVIDE - 1 - - - C_PLL_REF_JITTER - 0.010 - - - C_PLL_CLKOUT0_DIVIDE - 1 - - - C_PLL_CLKOUT1_DIVIDE - 1 - - - C_PLL_CLKOUT2_DIVIDE - 1 - - - C_PLL_CLKOUT3_DIVIDE - 1 - - - C_PLL_CLKOUT4_DIVIDE - 1 - - - C_PLL_CLKOUT5_DIVIDE - 1 - - - C_PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_PLL_CLKFBOUT_PHASE - 0.000 - - - C_PLL_CLKOUT0_PHASE - 0.000 - - - C_PLL_CLKOUT1_PHASE - 0.000 - - - C_PLL_CLKOUT2_PHASE - 0.000 - - - C_PLL_CLKOUT3_PHASE - 0.000 - - - C_PLL_CLKOUT4_PHASE - 0.000 - - - C_PLL_CLKOUT5_PHASE - 0.000 - - - C_CLOCK_MGR_TYPE - NA - - - C_OVERRIDE_MMCM - 0 - - - C_OVERRIDE_PLL - 0 - - - C_PRIMARY_PORT - clk_in1 - - - C_SECONDARY_PORT - clk_in2 - - - C_CLK_OUT1_PORT - clk_out1 - - - C_CLK_OUT2_PORT - clk_out2 - - - C_CLK_OUT3_PORT - clk_out3 - - - C_CLK_OUT4_PORT - clk_out4 - - - C_CLK_OUT5_PORT - clk_out5 - - - C_CLK_OUT6_PORT - clk_out6 - - - C_CLK_OUT7_PORT - clk_out7 - - - C_RESET_PORT - reset - - - C_LOCKED_PORT - locked - - - C_CLKFB_IN_PORT - clkfb_in - - - C_CLKFB_IN_P_PORT - clkfb_in_p - - - C_CLKFB_IN_N_PORT - clkfb_in_n - - - C_CLKFB_OUT_PORT - clkfb_out - - - C_CLKFB_OUT_P_PORT - clkfb_out_p - - - C_CLKFB_OUT_N_PORT - clkfb_out_n - - - C_POWER_DOWN_PORT - power_down - - - C_DADDR_PORT - daddr - - - C_DCLK_PORT - dclk - - - C_DRDY_PORT - drdy - - - C_DWE_PORT - dwe - - - C_DIN_PORT - din - - - C_DOUT_PORT - dout - - - C_DEN_PORT - den - - - C_PSCLK_PORT - psclk - - - C_PSEN_PORT - psen - - - C_PSINCDEC_PORT - psincdec - - - C_PSDONE_PORT - psdone - - - C_CLK_VALID_PORT - CLK_VALID - - - C_STATUS_PORT - STATUS - - - C_CLK_IN_SEL_PORT - clk_in_sel - - - C_INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - C_CLKFB_STOPPED_PORT - clkfb_stopped - - - C_CLKIN1_JITTER_PS - 100.0 - - - C_CLKIN2_JITTER_PS - 100.0 - - - C_PRIMITIVE - PLL - - - C_SS_MODE - CENTER_HIGH - - - C_SS_MOD_PERIOD - 4000 - - - C_SS_MOD_TIME - 0.004 - - - C_HAS_CDDC - 0 - - - C_CDDCDONE_PORT - cddcdone - - - C_CDDCREQ_PORT - cddcreq - - - C_CLKOUTPHY_MODE - VCO - - - C_ENABLE_CLKOUTPHY - 0 - - - C_INTERFACE_SELECTION - 0 - - - C_S_AXI_ADDR_WIDTH - C S Axi Addr Width - 11 - - - C_S_AXI_DATA_WIDTH - C S Axi Data Width - 32 - - - C_POWER_REG - 0000 - - - C_CLKOUT0_1 - 0000 - - - C_CLKOUT0_2 - 0000 - - - C_CLKOUT1_1 - 0000 - - - C_CLKOUT1_2 - 0000 - - - C_CLKOUT2_1 - 0000 - - - C_CLKOUT2_2 - 0000 - - - C_CLKOUT3_1 - 0000 - - - C_CLKOUT3_2 - 0000 - - - C_CLKOUT4_1 - 0000 - - - C_CLKOUT4_2 - 0000 - - - C_CLKOUT5_1 - 0000 - - - C_CLKOUT5_2 - 0000 - - - C_CLKOUT6_1 - 0000 - - - C_CLKOUT6_2 - 0000 - - - C_CLKFBOUT_1 - 0000 - - - C_CLKFBOUT_2 - 0000 - - - C_DIVCLK - 0000 - - - C_LOCK_1 - 0000 - - - C_LOCK_2 - 0000 - - - C_LOCK_3 - 0000 - - - C_FILTER_1 - 0000 - - - C_FILTER_2 - 0000 - - - C_DIVIDE1_AUTO - 1 - - - C_DIVIDE2_AUTO - 0.5 - - - C_DIVIDE3_AUTO - 0.3076923076923077 - - - C_DIVIDE4_AUTO - 0.2222222222222222 - - - C_DIVIDE5_AUTO - 0.17391304347826086 - - - C_DIVIDE6_AUTO - 0.14285714285714285 - - - C_DIVIDE7_AUTO - 0.4 - - - C_PLLBUFGCEDIV - false - - - C_MMCMBUFGCEDIV - false - - - C_PLLBUFGCEDIV1 - false - - - C_PLLBUFGCEDIV2 - false - - - C_PLLBUFGCEDIV3 - false - - - C_PLLBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV1 - false - - - C_MMCMBUFGCEDIV2 - false - - - C_MMCMBUFGCEDIV3 - false - - - C_MMCMBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV5 - false - - - C_MMCMBUFGCEDIV6 - false - - - C_MMCMBUFGCEDIV7 - false - - - C_CLKOUT1_MATCHED_ROUTING - false - - - C_CLKOUT2_MATCHED_ROUTING - false - - - C_CLKOUT3_MATCHED_ROUTING - false - - - C_CLKOUT4_MATCHED_ROUTING - false - - - C_CLKOUT5_MATCHED_ROUTING - false - - - C_CLKOUT6_MATCHED_ROUTING - false - - - C_CLKOUT7_MATCHED_ROUTING - false - - - C_CLKOUT0_ACTUAL_FREQ - 40.000 - - - C_CLKOUT1_ACTUAL_FREQ - 80.000 - - - C_CLKOUT2_ACTUAL_FREQ - 130.000 - - - C_CLKOUT3_ACTUAL_FREQ - 173.333 - - - C_CLKOUT4_ACTUAL_FREQ - 208.000 - - - C_CLKOUT5_ACTUAL_FREQ - 260.000 - - - C_CLKOUT6_ACTUAL_FREQ - 100.000 - - - - - - choice_list_1d3de01d - WAVEFORM - LATENCY - - - choice_list_876bfc32 - UI - PS - - - choice_list_a9bdfce0 - LOW - HIGH - OPTIMIZED - - - choice_list_ac75ef1e - Custom - - - choice_list_b9d38208 - CLKFBOUT - CLKOUT0 - - - choice_list_e099fe6c - MMCM - PLL - - - choice_pairs_035ca1c3 - SYSTEM_SYNCHRONOUS - SOURCE_SYNCHRONOUS - INTERNAL - EXTERNAL - - - choice_pairs_0920eb1b - Custom - sys_diff_clock - - - choice_pairs_11d71346 - Single_ended_clock_capable_pin - Differential_clock_capable_pin - Global_buffer - No_buffer - - - choice_pairs_15c806d5 - FDBK_AUTO - FDBK_AUTO_OFFCHIP - FDBK_ONCHIP - FDBK_OFFCHIP - - - choice_pairs_340369e0 - Custom - sys_clock - sys_diff_clock - - - choice_pairs_3c2d3ec7 - SINGLE - DIFF - - - choice_pairs_502d9f23 - ZHOLD - EXTERNAL - INTERNAL - BUF_IN - - - choice_pairs_66e4c81f - BUFG - BUFH - BUFGCE - BUFHCE - No_buffer - - - choice_pairs_77d3d587 - MMCM - PLL - BUFGCE_DIV - - - choice_pairs_8b28f1f7 - Enable_AXI - Enable_DRP - - - choice_pairs_8eea9b32 - Units_MHz - Units_ns - - - choice_pairs_a4fbc00c - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_a8642b4c - No_Jitter - Min_O_Jitter - Max_I_Jitter - - - choice_pairs_c5ef7212 - Units_UI - Units_ps - - - choice_pairs_e1c87518 - REL_PRIMARY - REL_SECONDARY - - - choice_pairs_f4e10086 - CENTER_HIGH - CENTER_LOW - DOWN_HIGH - DOWN_LOW - - - choice_pairs_f669c2f5 - frequency - Time - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - clk_wiz_4.veo - verilogTemplate - - - - xilinx_anylanguagesynthesis_view_fileset - - clk_wiz_4.xdc - xdc - - processing_order - early - - - - clk_wiz_4_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - mmcm_pll_drp_func_7s_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_7s_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - clk_wiz_4_clk_wiz.v - verilogSource - - - - xilinx_anylanguagesynthesiswrapper_view_fileset - - clk_wiz_4.v - verilogSource - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - mmcm_pll_drp_func_7s_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_7s_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - clk_wiz_4_clk_wiz.v - verilogSource - - - - xilinx_anylanguagesimulationwrapper_view_fileset - - clk_wiz_4.v - verilogSource - - - - xilinx_implementation_view_fileset - - clk_wiz_4_board.xdc - xdc - USED_IN_board - USED_IN_implementation - USED_IN_synthesis - - - - xilinx_versioninformation_view_fileset - - doc/clk_wiz_v6_0_changelog.txt - text - - - - xilinx_externalfiles_view_fileset - - clk_wiz_4.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - clk_wiz_4_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - clk_wiz_4_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - clk_wiz_4_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - clk_wiz_4_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. - - - Component_Name - clk_wiz_4 - - - USER_CLK_FREQ0 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ1 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ2 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ3 - User Frequency(MHz) - 100.0 - - - ENABLE_CLOCK_MONITOR - Enable Clock Monitoring - false - - - ENABLE_USER_CLOCK0 - User Clock - false - - - ENABLE_USER_CLOCK1 - User Clock - false - - - ENABLE_USER_CLOCK2 - User Clock - false - - - ENABLE_USER_CLOCK3 - User Clock - false - - - Enable_PLL0 - User Clock - false - - - Enable_PLL1 - User Clock - false - - - REF_CLK_FREQ - Reference Frequency(MHz) - 100.0 - - - PRECISION - Tolerance(MHz) - 1 - - - PRIMITIVE - Primitive - PLL - - - PRIMTYPE_SEL - Primtype Sel - mmcm_adv - - - CLOCK_MGR_TYPE - Clock Mgr Type - auto - - - USE_FREQ_SYNTH - true - - - USE_SPREAD_SPECTRUM - false - - - USE_PHASE_ALIGNMENT - true - - - USE_MIN_POWER - false - - - USE_DYN_PHASE_SHIFT - false - - - USE_DYN_RECONFIG - false - - - JITTER_SEL - No_Jitter - - - PRIM_IN_FREQ - 100.000 - - - PRIM_IN_TIMEPERIOD - 10.000 - - - IN_FREQ_UNITS - Units_MHz - - - PHASESHIFT_MODE - WAVEFORM - - - IN_JITTER_UNITS - Units_UI - - - RELATIVE_INCLK - REL_PRIMARY - - - USE_INCLK_SWITCHOVER - false - - - SECONDARY_IN_FREQ - 100.000 - - - SECONDARY_IN_TIMEPERIOD - 10.000 - - - SECONDARY_PORT - clk_in2 - - - SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - JITTER_OPTIONS - UI - - - CLKIN1_UI_JITTER - 0.010 - - - CLKIN2_UI_JITTER - 0.010 - - - PRIM_IN_JITTER - 0.010 - - - SECONDARY_IN_JITTER - 0.010 - - - CLKIN1_JITTER_PS - 100.0 - - - CLKIN2_JITTER_PS - 100.0 - - - CLKOUT1_USED - true - - - CLKOUT2_USED - true - - - CLKOUT3_USED - true - - - CLKOUT4_USED - true - - - CLKOUT5_USED - true - - - CLKOUT6_USED - true - - - CLKOUT7_USED - false - - - NUM_OUT_CLKS - 6 - - - CLK_OUT1_USE_FINE_PS_GUI - false - - - CLK_OUT2_USE_FINE_PS_GUI - false - - - CLK_OUT3_USE_FINE_PS_GUI - false - - - CLK_OUT4_USE_FINE_PS_GUI - false - - - CLK_OUT5_USE_FINE_PS_GUI - false - - - CLK_OUT6_USE_FINE_PS_GUI - false - - - CLK_OUT7_USE_FINE_PS_GUI - false - - - PRIMARY_PORT - clk_in1 - - - CLK_OUT1_PORT - clk_out1 - - - CLK_OUT2_PORT - clk_out2 - - - CLK_OUT3_PORT - clk_out3 - - - CLK_OUT4_PORT - clk_out4 - - - CLK_OUT5_PORT - clk_out5 - - - CLK_OUT6_PORT - clk_out6 - - - CLK_OUT7_PORT - clk_out7 - - - DADDR_PORT - daddr - - - DCLK_PORT - dclk - - - DRDY_PORT - drdy - - - DWE_PORT - dwe - - - DIN_PORT - din - - - DOUT_PORT - dout - - - DEN_PORT - den - - - PSCLK_PORT - psclk - - - PSEN_PORT - psen - - - PSINCDEC_PORT - psincdec - - - PSDONE_PORT - psdone - - - CLKOUT1_REQUESTED_OUT_FREQ - 40 - - - CLKOUT1_REQUESTED_PHASE - 0.000 - - - CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT2_REQUESTED_OUT_FREQ - 80 - - - CLKOUT2_REQUESTED_PHASE - 0.000 - - - CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT3_REQUESTED_OUT_FREQ - 130 - - - CLKOUT3_REQUESTED_PHASE - 0.000 - - - CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT4_REQUESTED_OUT_FREQ - 180 - - - CLKOUT4_REQUESTED_PHASE - 0.000 - - - CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT5_REQUESTED_OUT_FREQ - 230 - - - CLKOUT5_REQUESTED_PHASE - 0.000 - - - CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT6_REQUESTED_OUT_FREQ - 280 - - - CLKOUT6_REQUESTED_PHASE - 0.000 - - - CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT7_REQUESTED_PHASE - 0.000 - - - CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - USE_MAX_I_JITTER - false - - - USE_MIN_O_JITTER - false - - - CLKOUT1_MATCHED_ROUTING - false - - - CLKOUT2_MATCHED_ROUTING - false - - - CLKOUT3_MATCHED_ROUTING - false - - - CLKOUT4_MATCHED_ROUTING - false - - - CLKOUT5_MATCHED_ROUTING - false - - - CLKOUT6_MATCHED_ROUTING - false - - - CLKOUT7_MATCHED_ROUTING - false - - - PRIM_SOURCE - Single_ended_clock_capable_pin - - - CLKOUT1_DRIVES - BUFG - - - CLKOUT2_DRIVES - BUFG - - - CLKOUT3_DRIVES - BUFG - - - CLKOUT4_DRIVES - BUFG - - - CLKOUT5_DRIVES - BUFG - - - CLKOUT6_DRIVES - BUFG - - - CLKOUT7_DRIVES - BUFG - - - FEEDBACK_SOURCE - FDBK_AUTO - - - CLKFB_IN_SIGNALING - SINGLE - - - CLKFB_IN_PORT - clkfb_in - - - CLKFB_IN_P_PORT - clkfb_in_p - - - CLKFB_IN_N_PORT - clkfb_in_n - - - CLKFB_OUT_PORT - clkfb_out - - - CLKFB_OUT_P_PORT - clkfb_out_p - - - CLKFB_OUT_N_PORT - clkfb_out_n - - - PLATFORM - UNKNOWN - - - SUMMARY_STRINGS - empty - - - USE_LOCKED - true - - - CALC_DONE - empty - - - USE_RESET - true - - - USE_POWER_DOWN - false - - - USE_STATUS - false - - - USE_FREEZE - false - - - USE_CLK_VALID - false - - - USE_INCLK_STOPPED - false - - - USE_CLKFB_STOPPED - false - - - RESET_PORT - reset - - - LOCKED_PORT - locked - - - POWER_DOWN_PORT - power_down - - - CLK_VALID_PORT - CLK_VALID - - - STATUS_PORT - STATUS - - - CLK_IN_SEL_PORT - clk_in_sel - - - INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - CLKFB_STOPPED_PORT - clkfb_stopped - - - SS_MODE - CENTER_HIGH - - - SS_MOD_FREQ - 250 - - - SS_MOD_TIME - 0.004 - - - OVERRIDE_MMCM - false - - - MMCM_NOTES - None - - - MMCM_DIVCLK_DIVIDE - 5 - - - MMCM_BANDWIDTH - OPTIMIZED - - - MMCM_CLKFBOUT_MULT_F - 52 - - - MMCM_CLKFBOUT_PHASE - 0.000 - - - MMCM_CLKFBOUT_USE_FINE_PS - false - - - MMCM_CLKIN1_PERIOD - 10.000 - - - MMCM_CLKIN2_PERIOD - 10.000 - - - MMCM_CLKOUT4_CASCADE - false - - - MMCM_CLOCK_HOLD - false - - - MMCM_COMPENSATION - ZHOLD - - - MMCM_REF_JITTER1 - 0.010 - - - MMCM_REF_JITTER2 - 0.010 - - - MMCM_STARTUP_WAIT - false - - - MMCM_CLKOUT0_DIVIDE_F - 26 - - - MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT0_PHASE - 0.000 - - - MMCM_CLKOUT0_USE_FINE_PS - false - - - MMCM_CLKOUT1_DIVIDE - 13 - - - MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT1_PHASE - 0.000 - - - MMCM_CLKOUT1_USE_FINE_PS - false - - - MMCM_CLKOUT2_DIVIDE - 8 - - - MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT2_PHASE - 0.000 - - - MMCM_CLKOUT2_USE_FINE_PS - false - - - MMCM_CLKOUT3_DIVIDE - 6 - - - MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT3_PHASE - 0.000 - - - MMCM_CLKOUT3_USE_FINE_PS - false - - - MMCM_CLKOUT4_DIVIDE - 5 - - - MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT4_PHASE - 0.000 - - - MMCM_CLKOUT4_USE_FINE_PS - false - - - MMCM_CLKOUT5_DIVIDE - 4 - - - MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT5_PHASE - 0.000 - - - MMCM_CLKOUT5_USE_FINE_PS - false - - - MMCM_CLKOUT6_DIVIDE - 1 - - - MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT6_PHASE - 0.000 - - - MMCM_CLKOUT6_USE_FINE_PS - false - - - OVERRIDE_PLL - false - - - PLL_NOTES - None - - - PLL_BANDWIDTH - OPTIMIZED - - - PLL_CLKFBOUT_MULT - 4 - - - PLL_CLKFBOUT_PHASE - 0.000 - - - PLL_CLK_FEEDBACK - CLKFBOUT - - - PLL_DIVCLK_DIVIDE - 1 - - - PLL_CLKIN_PERIOD - 10.000 - - - PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - PLL_REF_JITTER - 0.010 - - - PLL_CLKOUT0_DIVIDE - 1 - - - PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT0_PHASE - 0.000 - - - PLL_CLKOUT1_DIVIDE - 1 - - - PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT1_PHASE - 0.000 - - - PLL_CLKOUT2_DIVIDE - 1 - - - PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT2_PHASE - 0.000 - - - PLL_CLKOUT3_DIVIDE - 1 - - - PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT3_PHASE - 0.000 - - - PLL_CLKOUT4_DIVIDE - 1 - - - PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT4_PHASE - 0.000 - - - PLL_CLKOUT5_DIVIDE - 1 - - - PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT5_PHASE - 0.000 - - - RESET_TYPE - Reset Type - ACTIVE_HIGH - - - USE_SAFE_CLOCK_STARTUP - false - - - USE_CLOCK_SEQUENCING - false - - - CLKOUT1_SEQUENCE_NUMBER - 1 - - - CLKOUT2_SEQUENCE_NUMBER - 1 - - - CLKOUT3_SEQUENCE_NUMBER - 1 - - - CLKOUT4_SEQUENCE_NUMBER - 1 - - - CLKOUT5_SEQUENCE_NUMBER - 1 - - - CLKOUT6_SEQUENCE_NUMBER - 1 - - - CLKOUT7_SEQUENCE_NUMBER - 1 - - - USE_BOARD_FLOW - Generate Board based IO Constraints - false - - - CLK_IN1_BOARD_INTERFACE - Custom - - - CLK_IN2_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN1_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN2_BOARD_INTERFACE - Custom - - - AUTO_PRIMITIVE - MMCM - - - RESET_BOARD_INTERFACE - Custom - - - ENABLE_CDDC - false - - - CDDCDONE_PORT - cddcdone - - - CDDCREQ_PORT - cddcreq - - - ENABLE_CLKOUTPHY - false - - - CLKOUTPHY_REQUESTED_FREQ - 600.000 - - - CLKOUT1_JITTER - Clkout1 Jitter - 264.672 - - - CLKOUT1_PHASE_ERROR - Clkout1 Phase - 300.278 - - - CLKOUT2_JITTER - Clkout2 Jitter - 240.422 - - - CLKOUT2_PHASE_ERROR - Clkout2 Phase - 300.278 - - - CLKOUT3_JITTER - Clkout3 Jitter - 224.856 - - - CLKOUT3_PHASE_ERROR - Clkout3 Phase - 300.278 - - - CLKOUT4_JITTER - Clkout4 Jitter - 216.148 - - - CLKOUT4_PHASE_ERROR - Clkout4 Phase - 300.278 - - - CLKOUT5_JITTER - Clkout5 Jitter - 210.819 - - - CLKOUT5_PHASE_ERROR - Clkout5 Phase - 300.278 - - - CLKOUT6_JITTER - Clkout6 Jitter - 204.491 - - - CLKOUT6_PHASE_ERROR - Clkout6 Phase - 300.278 - - - CLKOUT7_JITTER - Clkout7 Jitter - 0.0 - - - CLKOUT7_PHASE_ERROR - Clkout7 Phase - 0.0 - - - INPUT_MODE - frequency - - - INTERFACE_SELECTION - Enable_AXI - - - AXI_DRP - Write DRP registers - false - - - PHASE_DUTY_CONFIG - Phase Duty Cycle Config - false - - - - - Clocking Wizard - - XPM_CDC - - 3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.1.1 - - - - - - - - diff --git a/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_5/clk_wiz_5.xml b/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_5/clk_wiz_5.xml deleted file mode 100644 index 937fb66..0000000 --- a/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_5/clk_wiz_5.xml +++ /dev/null @@ -1,5359 +0,0 @@ - - - xilinx.com - customized_ip - clk_wiz_5 - 1.0 - - - s_axi_lite - S_AXI_LITE - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARREADY - - - s_axi_arready - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWREADY - - - s_axi_awready - - - - - AWVALID - - - s_axi_awvalid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 1 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 1 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 0 - - - none - - - - - HAS_BRESP - 0 - - - none - - - - - HAS_RRESP - 0 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_aclk - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi_lite - - - ASSOCIATED_RESET - s_axi_aresetn - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - ref_clk - ref_clk - - - - - - - CLK - - - ref_clk - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_resetn - S_AXI_RESETN - - - - - - - RST - - - s_axi_aresetn - - - - - - ASSOCIATED_RESET - aresetn - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - intr - Intr - - - - - - - INTERRUPT - - - ip2intc_irpt - - - - - - SENSITIVITY - LEVEL_HIGH - - - none - - - - - PortWidth - 1 - - - none - - - - - - - - false - - - - - - CLK_IN1_D - CLK_IN1_D - Differential Clock input - - - - - - - CLK_N - - - clk_in1_n - - - - - CLK_P - - - clk_in1_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN1_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLK_IN2_D - CLK_IN2_D - Differential Clock input - - - - - - - CLK_N - - - clk_in2_n - - - - - CLK_P - - - clk_in2_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN2_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_IN_D - CLKFB_IN_D - Differential Feedback Clock input - - - - - - - CLK_N - - - clkfb_in_n - - - - - CLK_P - - - clkfb_in_p - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_OUT_D - CLKFB_OUT_D - Differential Feeback Clock Output - - - - - - - CLK_N - - - clkfb_out_n - - - - - CLK_P - - - clkfb_out_p - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - reset - reset - - - - - - - RST - - - reset - - - - - - POLARITY - ACTIVE_HIGH - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - resetn - resetn - - - - - - - RST - - - resetn - - - - - - POLARITY - ACTIVE_LOW - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - clock_CLK_IN1 - - - - - - - CLK_IN1 - - - clk_in1 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN1_BOARD_INTERFACE - - - - - clock_CLK_OUT1 - - - - - - - CLK_OUT1 - - - clk_out1 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT2 - - - - - - - CLK_OUT2 - - - clk_out2 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT3 - - - - - - - CLK_OUT3 - - - clk_out3 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT4 - - - - - - - CLK_OUT4 - - - clk_out4 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT5 - - - - - - - CLK_OUT5 - - - clk_out5 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT6 - - - - - - - CLK_OUT6 - - - clk_out6 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - xilinx_elaborateports - Elaborate Ports - :vivado.xilinx.com:elaborate.ports - - - outputProductCRC - 9:bad00b45 - - - - - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog - clk_wiz_v6_0_3 - - xilinx_veriloginstantiationtemplate_view_fileset - - - - GENtimestamp - Sat Sep 14 01:12:31 UTC 2019 - - - outputProductCRC - 9:e40f4ede - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - clk_wiz_v6_0_3 - - xilinx_anylanguagesynthesis_view_fileset - - - - GENtimestamp - Sat Sep 14 01:12:35 UTC 2019 - - - outputProductCRC - 9:e40f4ede - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - - outputProductCRC - 9:e40f4ede - - - - - xilinx_anylanguagesynthesiswrapper - Synthesis Wrapper - :vivado.xilinx.com:synthesis.wrapper - clk_wiz_5 - - xilinx_anylanguagesynthesiswrapper_view_fileset - - - - GENtimestamp - Sat Sep 14 01:12:35 UTC 2019 - - - outputProductCRC - 9:e40f4ede - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - clk_wiz_v6_0_3 - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - GENtimestamp - Sat Sep 14 01:12:35 UTC 2019 - - - outputProductCRC - 9:461074f0 - - - - - xilinx_anylanguagesimulationwrapper - Simulation Wrapper - :vivado.xilinx.com:simulation.wrapper - clk_wiz_5 - - xilinx_anylanguagesimulationwrapper_view_fileset - - - - GENtimestamp - Sat Sep 14 01:12:35 UTC 2019 - - - outputProductCRC - 9:461074f0 - - - - - xilinx_implementation - Implementation - :vivado.xilinx.com:implementation - - xilinx_implementation_view_fileset - - - - GENtimestamp - Sat Sep 14 01:12:35 UTC 2019 - - - outputProductCRC - 9:e40f4ede - - - - - xilinx_versioninformation - Version Information - :vivado.xilinx.com:docs.versioninfo - - xilinx_versioninformation_view_fileset - - - - GENtimestamp - Sat Sep 14 01:12:36 UTC 2019 - - - outputProductCRC - 9:e40f4ede - - - - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Sat Sep 14 01:13:16 UTC 2019 - - - outputProductCRC - 9:e40f4ede - - - - - - - s_axi_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awaddr - - in - - 10 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - 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xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_rvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_rready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in1_p - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in1_n - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in2_p - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in2_n - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clkfb_in_p - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clkfb_in_n - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clkfb_out_p - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - clkfb_out_n - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - reset - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - resetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - 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xilinx_anylanguagebehavioralsimulation - - - - - - clk_out6 - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - locked - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - C_CLKOUT2_USED - 1 - - - C_USER_CLK_FREQ0 - 100.0 - - - C_AUTO_PRIMITIVE - MMCM - - - C_USER_CLK_FREQ1 - 100.0 - - - C_USER_CLK_FREQ2 - 100.0 - - - C_USER_CLK_FREQ3 - 100.0 - - - C_ENABLE_CLOCK_MONITOR - 0 - - - C_ENABLE_USER_CLOCK0 - 0 - - - C_ENABLE_USER_CLOCK1 - 0 - - - C_ENABLE_USER_CLOCK2 - 0 - - - C_ENABLE_USER_CLOCK3 - 0 - - - C_Enable_PLL0 - 0 - - - C_Enable_PLL1 - 0 - - - C_REF_CLK_FREQ - 100.0 - - - C_PRECISION - 1 - - - C_CLKOUT3_USED - 1 - - - C_CLKOUT4_USED - 1 - - - C_CLKOUT5_USED - 1 - - - C_CLKOUT6_USED - 1 - - - C_CLKOUT7_USED - 0 - - - C_USE_CLKOUT1_BAR - 0 - - - C_USE_CLKOUT2_BAR - 0 - - - C_USE_CLKOUT3_BAR - 0 - - - C_USE_CLKOUT4_BAR - 0 - - - c_component_name - clk_wiz_5 - - - C_PLATFORM - UNKNOWN - - - C_USE_FREQ_SYNTH - 1 - - - C_USE_PHASE_ALIGNMENT - 1 - - - C_PRIM_IN_JITTER - 0.010 - - - C_SECONDARY_IN_JITTER - 0.010 - - - C_JITTER_SEL - No_Jitter - - - C_USE_MIN_POWER - 0 - - - C_USE_MIN_O_JITTER - 0 - - - C_USE_MAX_I_JITTER - 0 - - - C_USE_DYN_PHASE_SHIFT - 0 - - - C_USE_INCLK_SWITCHOVER - 0 - - - C_USE_DYN_RECONFIG - 0 - - - C_USE_SPREAD_SPECTRUM - 0 - - - C_USE_FAST_SIMULATION - 0 - - - C_PRIMTYPE_SEL - AUTO - - - C_USE_CLK_VALID - 0 - - - C_PRIM_IN_FREQ - 100.000 - - - C_PRIM_IN_TIMEPERIOD - 10.000 - - - C_IN_FREQ_UNITS - Units_MHz - - - C_SECONDARY_IN_FREQ - 100.000 - - - C_SECONDARY_IN_TIMEPERIOD - 10.000 - - - C_FEEDBACK_SOURCE - FDBK_AUTO - - - C_PRIM_SOURCE - Single_ended_clock_capable_pin - - - C_PHASESHIFT_MODE - WAVEFORM - - - C_SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - C_CLKFB_IN_SIGNALING - SINGLE - - - C_USE_RESET - 1 - - - C_RESET_LOW - 0 - - - C_USE_LOCKED - 1 - - - C_USE_INCLK_STOPPED - 0 - - - C_USE_CLKFB_STOPPED - 0 - - - C_USE_POWER_DOWN - 0 - - - C_USE_STATUS - 0 - - - C_USE_FREEZE - 0 - - - C_NUM_OUT_CLKS - 6 - - - C_CLKOUT1_DRIVES - BUFG - - - C_CLKOUT2_DRIVES - BUFG - - - C_CLKOUT3_DRIVES - BUFG - - - C_CLKOUT4_DRIVES - BUFG - - - C_CLKOUT5_DRIVES - BUFG - - - C_CLKOUT6_DRIVES - BUFG - - - C_CLKOUT7_DRIVES - BUFG - - - C_INCLK_SUM_ROW0 - Input Clock Freq (MHz) Input Jitter (UI) - - - C_INCLK_SUM_ROW1 - __primary_________100.000____________0.010 - - - C_INCLK_SUM_ROW2 - no_secondary_input_clock - - - C_OUTCLK_SUM_ROW0A - C Outclk Sum Row0a - Output Output Phase Duty Cycle Pk-to-Pk Phase - - - C_OUTCLK_SUM_ROW0B - Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - - - C_OUTCLK_SUM_ROW1 - clk_out1_____7.200______0.000______50.0______233.704____105.461 - - - C_OUTCLK_SUM_ROW2 - clk_out2____90.000______0.000______50.0______140.709____105.461 - - - C_OUTCLK_SUM_ROW3 - clk_out3___150.000______0.000______50.0______127.220____105.461 - - - C_OUTCLK_SUM_ROW4 - clk_out4___180.000______0.000______50.0______122.980____105.461 - - - C_OUTCLK_SUM_ROW5 - clk_out5___225.000______0.000______50.0______117.993____105.461 - - - C_OUTCLK_SUM_ROW6 - clk_out6___300.000______0.000______50.0______111.879____105.461 - - - C_OUTCLK_SUM_ROW7 - no_CLK_OUT7_output - - - C_CLKOUT1_REQUESTED_OUT_FREQ - 7 - - - C_CLKOUT2_REQUESTED_OUT_FREQ - 90 - - - C_CLKOUT3_REQUESTED_OUT_FREQ - 140 - - - C_CLKOUT4_REQUESTED_OUT_FREQ - 190 - - - C_CLKOUT5_REQUESTED_OUT_FREQ - 240 - - - C_CLKOUT6_REQUESTED_OUT_FREQ - 290 - - - C_CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT1_REQUESTED_PHASE - 0.000 - - - C_CLKOUT2_REQUESTED_PHASE - 0.000 - - - C_CLKOUT3_REQUESTED_PHASE - 0.000 - - - C_CLKOUT4_REQUESTED_PHASE - 0.000 - - - C_CLKOUT5_REQUESTED_PHASE - 0.000 - - - C_CLKOUT6_REQUESTED_PHASE - 0.000 - - - C_CLKOUT7_REQUESTED_PHASE - 0.000 - - - C_CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT1_OUT_FREQ - 7.200 - - - C_CLKOUT2_OUT_FREQ - 90.000 - - - C_CLKOUT3_OUT_FREQ - 150.000 - - - C_CLKOUT4_OUT_FREQ - 180.000 - - - C_CLKOUT5_OUT_FREQ - 225.000 - - - C_CLKOUT6_OUT_FREQ - 300.000 - - - C_CLKOUT7_OUT_FREQ - 100.000 - - - C_CLKOUT1_PHASE - 0.000 - - - C_CLKOUT2_PHASE - 0.000 - - - C_CLKOUT3_PHASE - 0.000 - - - C_CLKOUT4_PHASE - 0.000 - - - C_CLKOUT5_PHASE - 0.000 - - - C_CLKOUT6_PHASE - 0.000 - - - C_CLKOUT7_PHASE - 0.000 - - - C_CLKOUT1_DUTY_CYCLE - 50.0 - - - C_CLKOUT2_DUTY_CYCLE - 50.0 - - - C_CLKOUT3_DUTY_CYCLE - 50.0 - - - C_CLKOUT4_DUTY_CYCLE - 50.0 - - - C_CLKOUT5_DUTY_CYCLE - 50.0 - - - C_CLKOUT6_DUTY_CYCLE - 50.0 - - - C_CLKOUT7_DUTY_CYCLE - 50.000 - - - C_USE_SAFE_CLOCK_STARTUP - 0 - - - C_USE_CLOCK_SEQUENCING - 0 - - - C_CLKOUT1_SEQUENCE_NUMBER - 1 - - - C_CLKOUT2_SEQUENCE_NUMBER - 1 - - - C_CLKOUT3_SEQUENCE_NUMBER - 1 - - - C_CLKOUT4_SEQUENCE_NUMBER - 1 - - - C_CLKOUT5_SEQUENCE_NUMBER - 1 - - - C_CLKOUT6_SEQUENCE_NUMBER - 1 - - - C_CLKOUT7_SEQUENCE_NUMBER - 1 - - - C_MMCM_NOTES - None - - - C_MMCM_BANDWIDTH - OPTIMIZED - - - C_MMCM_CLKFBOUT_MULT_F - 9.000 - - - C_MMCM_CLKIN1_PERIOD - 10.000 - - - C_MMCM_CLKIN2_PERIOD - 10.000 - - - C_MMCM_CLKOUT4_CASCADE - FALSE - - - C_MMCM_CLOCK_HOLD - FALSE - - - C_MMCM_COMPENSATION - ZHOLD - - - C_MMCM_DIVCLK_DIVIDE - 1 - - - C_MMCM_REF_JITTER1 - 0.010 - - - C_MMCM_REF_JITTER2 - 0.010 - - - C_MMCM_STARTUP_WAIT - FALSE - - - C_MMCM_CLKOUT0_DIVIDE_F - 125.000 - - - C_MMCM_CLKOUT1_DIVIDE - 10 - - - C_MMCM_CLKOUT2_DIVIDE - 6 - - - C_MMCM_CLKOUT3_DIVIDE - 5 - - - C_MMCM_CLKOUT4_DIVIDE - 4 - - - C_MMCM_CLKOUT5_DIVIDE - 3 - - - C_MMCM_CLKOUT6_DIVIDE - 1 - - - C_MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKFBOUT_PHASE - 0.000 - - - C_MMCM_CLKOUT0_PHASE - 0.000 - - - C_MMCM_CLKOUT1_PHASE - 0.000 - - - C_MMCM_CLKOUT2_PHASE - 0.000 - - - C_MMCM_CLKOUT3_PHASE - 0.000 - - - C_MMCM_CLKOUT4_PHASE - 0.000 - - - C_MMCM_CLKOUT5_PHASE - 0.000 - - - C_MMCM_CLKOUT6_PHASE - 0.000 - - - C_MMCM_CLKFBOUT_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT0_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT1_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT2_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT3_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT4_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT5_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT6_USE_FINE_PS - FALSE - - - C_PLL_NOTES - No notes - - - C_PLL_BANDWIDTH - OPTIMIZED - - - C_PLL_CLK_FEEDBACK - CLKFBOUT - - - C_PLL_CLKFBOUT_MULT - 1 - - - C_PLL_CLKIN_PERIOD - 1.000 - - - C_PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - C_PLL_DIVCLK_DIVIDE - 1 - - - C_PLL_REF_JITTER - 0.010 - - - C_PLL_CLKOUT0_DIVIDE - 1 - - - C_PLL_CLKOUT1_DIVIDE - 1 - - - C_PLL_CLKOUT2_DIVIDE - 1 - - - C_PLL_CLKOUT3_DIVIDE - 1 - - - C_PLL_CLKOUT4_DIVIDE - 1 - - - C_PLL_CLKOUT5_DIVIDE - 1 - - - C_PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_PLL_CLKFBOUT_PHASE - 0.000 - - - C_PLL_CLKOUT0_PHASE - 0.000 - - - C_PLL_CLKOUT1_PHASE - 0.000 - - - C_PLL_CLKOUT2_PHASE - 0.000 - - - C_PLL_CLKOUT3_PHASE - 0.000 - - - C_PLL_CLKOUT4_PHASE - 0.000 - - - C_PLL_CLKOUT5_PHASE - 0.000 - - - C_CLOCK_MGR_TYPE - NA - - - C_OVERRIDE_MMCM - 0 - - - C_OVERRIDE_PLL - 0 - - - C_PRIMARY_PORT - clk_in1 - - - C_SECONDARY_PORT - clk_in2 - - - C_CLK_OUT1_PORT - clk_out1 - - - C_CLK_OUT2_PORT - clk_out2 - - - C_CLK_OUT3_PORT - clk_out3 - - - C_CLK_OUT4_PORT - clk_out4 - - - C_CLK_OUT5_PORT - clk_out5 - - - C_CLK_OUT6_PORT - clk_out6 - - - C_CLK_OUT7_PORT - clk_out7 - - - C_RESET_PORT - reset - - - C_LOCKED_PORT - locked - - - C_CLKFB_IN_PORT - clkfb_in - - - C_CLKFB_IN_P_PORT - clkfb_in_p - - - C_CLKFB_IN_N_PORT - clkfb_in_n - - - C_CLKFB_OUT_PORT - clkfb_out - - - C_CLKFB_OUT_P_PORT - clkfb_out_p - - - C_CLKFB_OUT_N_PORT - clkfb_out_n - - - C_POWER_DOWN_PORT - power_down - - - C_DADDR_PORT - daddr - - - C_DCLK_PORT - dclk - - - C_DRDY_PORT - drdy - - - C_DWE_PORT - dwe - - - C_DIN_PORT - din - - - C_DOUT_PORT - dout - - - C_DEN_PORT - den - - - C_PSCLK_PORT - psclk - - - C_PSEN_PORT - psen - - - C_PSINCDEC_PORT - psincdec - - - C_PSDONE_PORT - psdone - - - C_CLK_VALID_PORT - CLK_VALID - - - C_STATUS_PORT - STATUS - - - C_CLK_IN_SEL_PORT - clk_in_sel - - - C_INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - C_CLKFB_STOPPED_PORT - clkfb_stopped - - - C_CLKIN1_JITTER_PS - 100.0 - - - C_CLKIN2_JITTER_PS - 100.0 - - - C_PRIMITIVE - PLL - - - C_SS_MODE - CENTER_HIGH - - - C_SS_MOD_PERIOD - 4000 - - - C_SS_MOD_TIME - 0.004 - - - C_HAS_CDDC - 0 - - - C_CDDCDONE_PORT - cddcdone - - - C_CDDCREQ_PORT - cddcreq - - - C_CLKOUTPHY_MODE - VCO - - - C_ENABLE_CLKOUTPHY - 0 - - - C_INTERFACE_SELECTION - 0 - - - C_S_AXI_ADDR_WIDTH - C S Axi Addr Width - 11 - - - C_S_AXI_DATA_WIDTH - C S Axi Data Width - 32 - - - C_POWER_REG - 0000 - - - C_CLKOUT0_1 - 0000 - - - C_CLKOUT0_2 - 0000 - - - C_CLKOUT1_1 - 0000 - - - C_CLKOUT1_2 - 0000 - - - C_CLKOUT2_1 - 0000 - - - C_CLKOUT2_2 - 0000 - - - C_CLKOUT3_1 - 0000 - - - C_CLKOUT3_2 - 0000 - - - C_CLKOUT4_1 - 0000 - - - C_CLKOUT4_2 - 0000 - - - C_CLKOUT5_1 - 0000 - - - C_CLKOUT5_2 - 0000 - - - C_CLKOUT6_1 - 0000 - - - C_CLKOUT6_2 - 0000 - - - C_CLKFBOUT_1 - 0000 - - - C_CLKFBOUT_2 - 0000 - - - C_DIVCLK - 0000 - - - C_LOCK_1 - 0000 - - - C_LOCK_2 - 0000 - - - C_LOCK_3 - 0000 - - - C_FILTER_1 - 0000 - - - C_FILTER_2 - 0000 - - - C_DIVIDE1_AUTO - 1 - - - C_DIVIDE2_AUTO - 0.07777777777777778 - - - C_DIVIDE3_AUTO - 0.05 - - - C_DIVIDE4_AUTO - 0.03684210526315789 - - - C_DIVIDE5_AUTO - 0.029166666666666667 - - - C_DIVIDE6_AUTO - 0.02413793103448276 - - - C_DIVIDE7_AUTO - 0.07 - - - C_PLLBUFGCEDIV - false - - - C_MMCMBUFGCEDIV - false - - - C_PLLBUFGCEDIV1 - false - - - C_PLLBUFGCEDIV2 - false - - - C_PLLBUFGCEDIV3 - false - - - C_PLLBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV1 - false - - - C_MMCMBUFGCEDIV2 - false - - - C_MMCMBUFGCEDIV3 - false - - - C_MMCMBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV5 - false - - - C_MMCMBUFGCEDIV6 - false - - - C_MMCMBUFGCEDIV7 - false - - - C_CLKOUT1_MATCHED_ROUTING - false - - - C_CLKOUT2_MATCHED_ROUTING - false - - - C_CLKOUT3_MATCHED_ROUTING - false - - - C_CLKOUT4_MATCHED_ROUTING - false - - - C_CLKOUT5_MATCHED_ROUTING - false - - - C_CLKOUT6_MATCHED_ROUTING - false - - - C_CLKOUT7_MATCHED_ROUTING - false - - - C_CLKOUT0_ACTUAL_FREQ - 7.200 - - - C_CLKOUT1_ACTUAL_FREQ - 90.000 - - - C_CLKOUT2_ACTUAL_FREQ - 150.000 - - - C_CLKOUT3_ACTUAL_FREQ - 180.000 - - - C_CLKOUT4_ACTUAL_FREQ - 225.000 - - - C_CLKOUT5_ACTUAL_FREQ - 300.000 - - - C_CLKOUT6_ACTUAL_FREQ - 100.000 - - - - - - choice_list_1d3de01d - WAVEFORM - LATENCY - - - choice_list_876bfc32 - UI - PS - - - choice_list_a9bdfce0 - LOW - HIGH - OPTIMIZED - - - choice_list_ac75ef1e - Custom - - - choice_list_b9d38208 - CLKFBOUT - CLKOUT0 - - - choice_list_e099fe6c - MMCM - PLL - - - choice_pairs_035ca1c3 - SYSTEM_SYNCHRONOUS - SOURCE_SYNCHRONOUS - INTERNAL - EXTERNAL - - - choice_pairs_0920eb1b - Custom - sys_diff_clock - - - choice_pairs_11d71346 - Single_ended_clock_capable_pin - Differential_clock_capable_pin - Global_buffer - No_buffer - - - choice_pairs_15c806d5 - FDBK_AUTO - FDBK_AUTO_OFFCHIP - FDBK_ONCHIP - FDBK_OFFCHIP - - - choice_pairs_340369e0 - Custom - sys_clock - sys_diff_clock - - - choice_pairs_3c2d3ec7 - SINGLE - DIFF - - - choice_pairs_502d9f23 - ZHOLD - EXTERNAL - INTERNAL - BUF_IN - - - choice_pairs_66e4c81f - BUFG - BUFH - BUFGCE - BUFHCE - No_buffer - - - choice_pairs_77d3d587 - MMCM - PLL - BUFGCE_DIV - - - choice_pairs_8b28f1f7 - Enable_AXI - Enable_DRP - - - choice_pairs_8eea9b32 - Units_MHz - Units_ns - - - choice_pairs_a4fbc00c - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_a8642b4c - No_Jitter - Min_O_Jitter - Max_I_Jitter - - - choice_pairs_c5ef7212 - Units_UI - Units_ps - - - choice_pairs_e1c87518 - REL_PRIMARY - REL_SECONDARY - - - choice_pairs_f4e10086 - CENTER_HIGH - CENTER_LOW - DOWN_HIGH - DOWN_LOW - - - choice_pairs_f669c2f5 - frequency - Time - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - clk_wiz_5.veo - verilogTemplate - - - - xilinx_anylanguagesynthesis_view_fileset - - clk_wiz_5.xdc - xdc - - processing_order - early - - - - clk_wiz_5_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - mmcm_pll_drp_func_7s_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_7s_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - clk_wiz_5_clk_wiz.v - verilogSource - - - - xilinx_anylanguagesynthesiswrapper_view_fileset - - clk_wiz_5.v - verilogSource - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - mmcm_pll_drp_func_7s_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_7s_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - clk_wiz_5_clk_wiz.v - verilogSource - - - - xilinx_anylanguagesimulationwrapper_view_fileset - - clk_wiz_5.v - verilogSource - - - - xilinx_implementation_view_fileset - - clk_wiz_5_board.xdc - xdc - USED_IN_board - USED_IN_implementation - USED_IN_synthesis - - - - xilinx_versioninformation_view_fileset - - doc/clk_wiz_v6_0_changelog.txt - text - - - - xilinx_externalfiles_view_fileset - - clk_wiz_5.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - clk_wiz_5_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - clk_wiz_5_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - clk_wiz_5_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - clk_wiz_5_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. - - - Component_Name - clk_wiz_5 - - - USER_CLK_FREQ0 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ1 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ2 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ3 - User Frequency(MHz) - 100.0 - - - ENABLE_CLOCK_MONITOR - Enable Clock Monitoring - false - - - ENABLE_USER_CLOCK0 - User Clock - false - - - ENABLE_USER_CLOCK1 - User Clock - false - - - ENABLE_USER_CLOCK2 - User Clock - false - - - ENABLE_USER_CLOCK3 - User Clock - false - - - Enable_PLL0 - User Clock - false - - - Enable_PLL1 - User Clock - false - - - REF_CLK_FREQ - Reference Frequency(MHz) - 100.0 - - - PRECISION - Tolerance(MHz) - 1 - - - PRIMITIVE - Primitive - PLL - - - PRIMTYPE_SEL - Primtype Sel - mmcm_adv - - - CLOCK_MGR_TYPE - Clock Mgr Type - auto - - - USE_FREQ_SYNTH - true - - - USE_SPREAD_SPECTRUM - false - - - USE_PHASE_ALIGNMENT - true - - - USE_MIN_POWER - false - - - USE_DYN_PHASE_SHIFT - false - - - USE_DYN_RECONFIG - false - - - JITTER_SEL - No_Jitter - - - PRIM_IN_FREQ - 100.000 - - - PRIM_IN_TIMEPERIOD - 10.000 - - - IN_FREQ_UNITS - Units_MHz - - - PHASESHIFT_MODE - WAVEFORM - - - IN_JITTER_UNITS - Units_UI - - - RELATIVE_INCLK - REL_PRIMARY - - - USE_INCLK_SWITCHOVER - false - - - SECONDARY_IN_FREQ - 100.000 - - - SECONDARY_IN_TIMEPERIOD - 10.000 - - - SECONDARY_PORT - clk_in2 - - - SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - JITTER_OPTIONS - UI - - - CLKIN1_UI_JITTER - 0.010 - - - CLKIN2_UI_JITTER - 0.010 - - - PRIM_IN_JITTER - 0.010 - - - SECONDARY_IN_JITTER - 0.010 - - - CLKIN1_JITTER_PS - 100.0 - - - CLKIN2_JITTER_PS - 100.0 - - - CLKOUT1_USED - true - - - CLKOUT2_USED - true - - - CLKOUT3_USED - true - - - CLKOUT4_USED - true - - - CLKOUT5_USED - true - - - CLKOUT6_USED - true - - - CLKOUT7_USED - false - - - NUM_OUT_CLKS - 6 - - - CLK_OUT1_USE_FINE_PS_GUI - false - - - CLK_OUT2_USE_FINE_PS_GUI - false - - - CLK_OUT3_USE_FINE_PS_GUI - false - - - CLK_OUT4_USE_FINE_PS_GUI - false - - - CLK_OUT5_USE_FINE_PS_GUI - false - - - CLK_OUT6_USE_FINE_PS_GUI - false - - - CLK_OUT7_USE_FINE_PS_GUI - false - - - PRIMARY_PORT - clk_in1 - - - CLK_OUT1_PORT - clk_out1 - - - CLK_OUT2_PORT - clk_out2 - - - CLK_OUT3_PORT - clk_out3 - - - CLK_OUT4_PORT - clk_out4 - - - CLK_OUT5_PORT - clk_out5 - - - CLK_OUT6_PORT - clk_out6 - - - CLK_OUT7_PORT - clk_out7 - - - DADDR_PORT - daddr - - - DCLK_PORT - dclk - - - DRDY_PORT - drdy - - - DWE_PORT - dwe - - - DIN_PORT - din - - - DOUT_PORT - dout - - - DEN_PORT - den - - - PSCLK_PORT - psclk - - - PSEN_PORT - psen - - - PSINCDEC_PORT - psincdec - - - PSDONE_PORT - psdone - - - CLKOUT1_REQUESTED_OUT_FREQ - 7 - - - CLKOUT1_REQUESTED_PHASE - 0.000 - - - CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT2_REQUESTED_OUT_FREQ - 90 - - - CLKOUT2_REQUESTED_PHASE - 0.000 - - - CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT3_REQUESTED_OUT_FREQ - 140 - - - CLKOUT3_REQUESTED_PHASE - 0.000 - - - CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT4_REQUESTED_OUT_FREQ - 190 - - - CLKOUT4_REQUESTED_PHASE - 0.000 - - - CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT5_REQUESTED_OUT_FREQ - 240 - - - CLKOUT5_REQUESTED_PHASE - 0.000 - - - CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT6_REQUESTED_OUT_FREQ - 290 - - - CLKOUT6_REQUESTED_PHASE - 0.000 - - - CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT7_REQUESTED_PHASE - 0.000 - - - CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - USE_MAX_I_JITTER - false - - - USE_MIN_O_JITTER - false - - - CLKOUT1_MATCHED_ROUTING - false - - - CLKOUT2_MATCHED_ROUTING - false - - - CLKOUT3_MATCHED_ROUTING - false - - - CLKOUT4_MATCHED_ROUTING - false - - - CLKOUT5_MATCHED_ROUTING - false - - - CLKOUT6_MATCHED_ROUTING - false - - - CLKOUT7_MATCHED_ROUTING - false - - - PRIM_SOURCE - Single_ended_clock_capable_pin - - - CLKOUT1_DRIVES - BUFG - - - CLKOUT2_DRIVES - BUFG - - - CLKOUT3_DRIVES - BUFG - - - CLKOUT4_DRIVES - BUFG - - - CLKOUT5_DRIVES - BUFG - - - CLKOUT6_DRIVES - BUFG - - - CLKOUT7_DRIVES - BUFG - - - FEEDBACK_SOURCE - FDBK_AUTO - - - CLKFB_IN_SIGNALING - SINGLE - - - CLKFB_IN_PORT - clkfb_in - - - CLKFB_IN_P_PORT - clkfb_in_p - - - CLKFB_IN_N_PORT - clkfb_in_n - - - CLKFB_OUT_PORT - clkfb_out - - - CLKFB_OUT_P_PORT - clkfb_out_p - - - CLKFB_OUT_N_PORT - clkfb_out_n - - - PLATFORM - UNKNOWN - - - SUMMARY_STRINGS - empty - - - USE_LOCKED - true - - - CALC_DONE - empty - - - USE_RESET - true - - - USE_POWER_DOWN - false - - - USE_STATUS - false - - - USE_FREEZE - false - - - USE_CLK_VALID - false - - - USE_INCLK_STOPPED - false - - - USE_CLKFB_STOPPED - false - - - RESET_PORT - reset - - - LOCKED_PORT - locked - - - POWER_DOWN_PORT - power_down - - - CLK_VALID_PORT - CLK_VALID - - - STATUS_PORT - STATUS - - - CLK_IN_SEL_PORT - clk_in_sel - - - INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - CLKFB_STOPPED_PORT - clkfb_stopped - - - SS_MODE - CENTER_HIGH - - - SS_MOD_FREQ - 250 - - - SS_MOD_TIME - 0.004 - - - OVERRIDE_MMCM - false - - - MMCM_NOTES - None - - - MMCM_DIVCLK_DIVIDE - 1 - - - MMCM_BANDWIDTH - OPTIMIZED - - - MMCM_CLKFBOUT_MULT_F - 9 - - - MMCM_CLKFBOUT_PHASE - 0.000 - - - MMCM_CLKFBOUT_USE_FINE_PS - false - - - MMCM_CLKIN1_PERIOD - 10.000 - - - MMCM_CLKIN2_PERIOD - 10.000 - - - MMCM_CLKOUT4_CASCADE - false - - - MMCM_CLOCK_HOLD - false - - - MMCM_COMPENSATION - ZHOLD - - - MMCM_REF_JITTER1 - 0.010 - - - MMCM_REF_JITTER2 - 0.010 - - - MMCM_STARTUP_WAIT - false - - - MMCM_CLKOUT0_DIVIDE_F - 125 - - - MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT0_PHASE - 0.000 - - - MMCM_CLKOUT0_USE_FINE_PS - false - - - MMCM_CLKOUT1_DIVIDE - 10 - - - MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT1_PHASE - 0.000 - - - MMCM_CLKOUT1_USE_FINE_PS - false - - - MMCM_CLKOUT2_DIVIDE - 6 - - - MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT2_PHASE - 0.000 - - - MMCM_CLKOUT2_USE_FINE_PS - false - - - MMCM_CLKOUT3_DIVIDE - 5 - - - MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT3_PHASE - 0.000 - - - MMCM_CLKOUT3_USE_FINE_PS - false - - - MMCM_CLKOUT4_DIVIDE - 4 - - - MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT4_PHASE - 0.000 - - - MMCM_CLKOUT4_USE_FINE_PS - false - - - MMCM_CLKOUT5_DIVIDE - 3 - - - MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT5_PHASE - 0.000 - - - MMCM_CLKOUT5_USE_FINE_PS - false - - - MMCM_CLKOUT6_DIVIDE - 1 - - - MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT6_PHASE - 0.000 - - - MMCM_CLKOUT6_USE_FINE_PS - false - - - OVERRIDE_PLL - false - - - PLL_NOTES - None - - - PLL_BANDWIDTH - OPTIMIZED - - - PLL_CLKFBOUT_MULT - 4 - - - PLL_CLKFBOUT_PHASE - 0.000 - - - PLL_CLK_FEEDBACK - CLKFBOUT - - - PLL_DIVCLK_DIVIDE - 1 - - - PLL_CLKIN_PERIOD - 10.000 - - - PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - PLL_REF_JITTER - 0.010 - - - PLL_CLKOUT0_DIVIDE - 1 - - - PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT0_PHASE - 0.000 - - - PLL_CLKOUT1_DIVIDE - 1 - - - PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT1_PHASE - 0.000 - - - PLL_CLKOUT2_DIVIDE - 1 - - - PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT2_PHASE - 0.000 - - - PLL_CLKOUT3_DIVIDE - 1 - - - PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT3_PHASE - 0.000 - - - PLL_CLKOUT4_DIVIDE - 1 - - - PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT4_PHASE - 0.000 - - - PLL_CLKOUT5_DIVIDE - 1 - - - PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT5_PHASE - 0.000 - - - RESET_TYPE - Reset Type - ACTIVE_HIGH - - - USE_SAFE_CLOCK_STARTUP - false - - - USE_CLOCK_SEQUENCING - false - - - CLKOUT1_SEQUENCE_NUMBER - 1 - - - CLKOUT2_SEQUENCE_NUMBER - 1 - - - CLKOUT3_SEQUENCE_NUMBER - 1 - - - CLKOUT4_SEQUENCE_NUMBER - 1 - - - CLKOUT5_SEQUENCE_NUMBER - 1 - - - CLKOUT6_SEQUENCE_NUMBER - 1 - - - CLKOUT7_SEQUENCE_NUMBER - 1 - - - USE_BOARD_FLOW - Generate Board based IO Constraints - false - - - CLK_IN1_BOARD_INTERFACE - Custom - - - CLK_IN2_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN1_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN2_BOARD_INTERFACE - Custom - - - AUTO_PRIMITIVE - MMCM - - - RESET_BOARD_INTERFACE - Custom - - - ENABLE_CDDC - false - - - CDDCDONE_PORT - cddcdone - - - CDDCREQ_PORT - cddcreq - - - ENABLE_CLKOUTPHY - false - - - CLKOUTPHY_REQUESTED_FREQ - 600.000 - - - CLKOUT1_JITTER - Clkout1 Jitter - 233.704 - - - CLKOUT1_PHASE_ERROR - Clkout1 Phase - 105.461 - - - CLKOUT2_JITTER - Clkout2 Jitter - 140.709 - - - CLKOUT2_PHASE_ERROR - Clkout2 Phase - 105.461 - - - CLKOUT3_JITTER - Clkout3 Jitter - 127.220 - - - CLKOUT3_PHASE_ERROR - Clkout3 Phase - 105.461 - - - CLKOUT4_JITTER - Clkout4 Jitter - 122.980 - - - CLKOUT4_PHASE_ERROR - Clkout4 Phase - 105.461 - - - CLKOUT5_JITTER - Clkout5 Jitter - 117.993 - - - CLKOUT5_PHASE_ERROR - Clkout5 Phase - 105.461 - - - CLKOUT6_JITTER - Clkout6 Jitter - 111.879 - - - CLKOUT6_PHASE_ERROR - Clkout6 Phase - 105.461 - - - CLKOUT7_JITTER - Clkout7 Jitter - 0.0 - - - CLKOUT7_PHASE_ERROR - Clkout7 Phase - 0.0 - - - INPUT_MODE - frequency - - - INTERFACE_SELECTION - Enable_AXI - - - AXI_DRP - Write DRP registers - false - - - PHASE_DUTY_CONFIG - Phase Duty Cycle Config - false - - - - - Clocking Wizard - - XPM_CDC - - 3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.1.1 - - - - - - - - diff --git a/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_6/clk_wiz_6.xml b/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_6/clk_wiz_6.xml deleted file mode 100644 index 9b8b9d5..0000000 --- a/Computer_Architecture/up_down_counter_introduction/up_down_counter_introduction.srcs/sources_1/ip/clk_wiz_6/clk_wiz_6.xml +++ /dev/null @@ -1,4998 +0,0 @@ - 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- - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 0 - - - none - - - - - HAS_BRESP - 0 - - - none - - - - - HAS_RRESP - 0 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_aclk - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi_lite - - - ASSOCIATED_RESET - s_axi_aresetn - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - ref_clk - ref_clk - - - - - - - CLK - - - ref_clk - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_resetn - S_AXI_RESETN - - - - - - - RST - - - s_axi_aresetn - - - - - - ASSOCIATED_RESET - aresetn - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - intr - Intr - - - - - - - INTERRUPT - - - ip2intc_irpt - - - - - - SENSITIVITY - LEVEL_HIGH - - - none - - - - - PortWidth - 1 - - - none - - - - - - - - false - - - - - - CLK_IN1_D - CLK_IN1_D - Differential Clock input - - - - - - - CLK_N - - - clk_in1_n - - - - - CLK_P - - - clk_in1_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN1_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLK_IN2_D - CLK_IN2_D - Differential Clock input - - - - - - - CLK_N - - - clk_in2_n - - - - - CLK_P - - - clk_in2_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN2_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_IN_D - CLKFB_IN_D - Differential Feedback Clock input - - - - - - - CLK_N - - - clkfb_in_n - - - - - CLK_P - - - clkfb_in_p - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_OUT_D - CLKFB_OUT_D - Differential Feeback Clock Output - - - - - - - CLK_N - - - clkfb_out_n - - - - - CLK_P - - - clkfb_out_p - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - reset - reset - - - - - - - RST - - - reset - - - - - - POLARITY - ACTIVE_HIGH - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - resetn - resetn - - - - - - - RST - - - resetn - - - - - - POLARITY - ACTIVE_LOW - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - clock_CLK_IN1 - - - - - - - CLK_IN1 - - - clk_in1 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN1_BOARD_INTERFACE - - - - - clock_CLK_OUT1 - - - - - - - CLK_OUT1 - - - clk_out1 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - clock_CLK_OUT2 - - - - - - - CLK_OUT2 - - - clk_out2 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - xilinx_elaborateports - Elaborate Ports - :vivado.xilinx.com:elaborate.ports - - - outputProductCRC - 9:050bc3af - - - - - xilinx_veriloginstantiationtemplate - Verilog Instantiation Template - verilogSource:vivado.xilinx.com:synthesis.template - verilog - clk_wiz_v6_0_3 - - xilinx_veriloginstantiationtemplate_view_fileset - - - - GENtimestamp - Sat Sep 14 01:14:31 UTC 2019 - - - outputProductCRC - 9:ff2bdcad - - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - clk_wiz_v6_0_3 - - xilinx_anylanguagesynthesis_view_fileset - - - - GENtimestamp - Sat Sep 14 01:14:33 UTC 2019 - - - outputProductCRC - 9:ff2bdcad - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - - outputProductCRC - 9:ff2bdcad - - - - - xilinx_anylanguagesynthesiswrapper - Synthesis Wrapper - :vivado.xilinx.com:synthesis.wrapper - clk_wiz_6 - - xilinx_anylanguagesynthesiswrapper_view_fileset - - - - GENtimestamp - Sat Sep 14 01:14:33 UTC 2019 - - - outputProductCRC - 9:ff2bdcad - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - clk_wiz_v6_0_3 - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - GENtimestamp - Sat Sep 14 01:14:33 UTC 2019 - - - outputProductCRC - 9:9fb308e1 - - - - - xilinx_anylanguagesimulationwrapper - Simulation Wrapper - :vivado.xilinx.com:simulation.wrapper - clk_wiz_6 - - xilinx_anylanguagesimulationwrapper_view_fileset - - - - GENtimestamp - Sat Sep 14 01:14:33 UTC 2019 - - - outputProductCRC - 9:9fb308e1 - - - - - xilinx_implementation - Implementation - :vivado.xilinx.com:implementation - - xilinx_implementation_view_fileset - - - - GENtimestamp - Sat Sep 14 01:14:34 UTC 2019 - - - outputProductCRC - 9:ff2bdcad - - - - - xilinx_versioninformation - Version Information - :vivado.xilinx.com:docs.versioninfo - - xilinx_versioninformation_view_fileset - - - - GENtimestamp - Sat Sep 14 01:14:34 UTC 2019 - - - outputProductCRC - 9:ff2bdcad - - - - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Sat Sep 14 01:15:12 UTC 2019 - - - outputProductCRC - 9:ff2bdcad - - - - - - - s_axi_aclk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_aresetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awaddr - - in - - 10 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_awready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_wready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_bvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_bready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_araddr - - in - - 10 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arvalid - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - s_axi_arready - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_rvalid - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - s_axi_rready - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in1_p - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in1_n - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in2_p - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in2_n - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clkfb_in_p - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clkfb_in_n - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clkfb_out_p - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - clkfb_out_n - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - false - - - - - - reset - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - true - - - - - - resetn - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - ref_clk - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_stop - - out - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_glitch - - out - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - interrupt - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_oor - - out - - 3 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - user_clk0 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - user_clk1 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - user_clk2 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - user_clk3 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - 0 - - - - - - false - - - - - - clk_in1 - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - clk_out1 - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - clk_out2 - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - locked - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - C_CLKOUT2_USED - 1 - - - C_USER_CLK_FREQ0 - 100.0 - - - C_AUTO_PRIMITIVE - MMCM - - - C_USER_CLK_FREQ1 - 100.0 - - - C_USER_CLK_FREQ2 - 100.0 - - - C_USER_CLK_FREQ3 - 100.0 - - - C_ENABLE_CLOCK_MONITOR - 0 - - - C_ENABLE_USER_CLOCK0 - 0 - - - C_ENABLE_USER_CLOCK1 - 0 - - - C_ENABLE_USER_CLOCK2 - 0 - - - C_ENABLE_USER_CLOCK3 - 0 - - - C_Enable_PLL0 - 0 - - - C_Enable_PLL1 - 0 - - - C_REF_CLK_FREQ - 100.0 - - - C_PRECISION - 1 - - - C_CLKOUT3_USED - 0 - - - C_CLKOUT4_USED - 0 - - - C_CLKOUT5_USED - 0 - - - C_CLKOUT6_USED - 0 - - - C_CLKOUT7_USED - 0 - - - C_USE_CLKOUT1_BAR - 0 - - - C_USE_CLKOUT2_BAR - 0 - - - C_USE_CLKOUT3_BAR - 0 - - - C_USE_CLKOUT4_BAR - 0 - - - c_component_name - clk_wiz_6 - - - C_PLATFORM - UNKNOWN - - - C_USE_FREQ_SYNTH - 1 - - - C_USE_PHASE_ALIGNMENT - 1 - - - C_PRIM_IN_JITTER - 0.010 - - - C_SECONDARY_IN_JITTER - 0.010 - - - C_JITTER_SEL - No_Jitter - - - C_USE_MIN_POWER - 0 - - - C_USE_MIN_O_JITTER - 0 - - - C_USE_MAX_I_JITTER - 0 - - - C_USE_DYN_PHASE_SHIFT - 0 - - - C_USE_INCLK_SWITCHOVER - 0 - - - C_USE_DYN_RECONFIG - 0 - - - C_USE_SPREAD_SPECTRUM - 0 - - - C_USE_FAST_SIMULATION - 0 - - - C_PRIMTYPE_SEL - AUTO - - - C_USE_CLK_VALID - 0 - - - C_PRIM_IN_FREQ - 100.000 - - - C_PRIM_IN_TIMEPERIOD - 10.000 - - - C_IN_FREQ_UNITS - Units_MHz - - - C_SECONDARY_IN_FREQ - 100.000 - - - C_SECONDARY_IN_TIMEPERIOD - 10.000 - - - C_FEEDBACK_SOURCE - FDBK_AUTO - - - C_PRIM_SOURCE - Single_ended_clock_capable_pin - - - C_PHASESHIFT_MODE - WAVEFORM - - - C_SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - C_CLKFB_IN_SIGNALING - SINGLE - - - C_USE_RESET - 1 - - - C_RESET_LOW - 0 - - - C_USE_LOCKED - 1 - - - C_USE_INCLK_STOPPED - 0 - - - C_USE_CLKFB_STOPPED - 0 - - - C_USE_POWER_DOWN - 0 - - - C_USE_STATUS - 0 - - - C_USE_FREEZE - 0 - - - C_NUM_OUT_CLKS - 2 - - - C_CLKOUT1_DRIVES - BUFG - - - C_CLKOUT2_DRIVES - BUFG - - - C_CLKOUT3_DRIVES - BUFG - - - C_CLKOUT4_DRIVES - BUFG - - - C_CLKOUT5_DRIVES - BUFG - - - C_CLKOUT6_DRIVES - BUFG - - - C_CLKOUT7_DRIVES - BUFG - - - C_INCLK_SUM_ROW0 - Input Clock Freq (MHz) Input Jitter (UI) - - - C_INCLK_SUM_ROW1 - __primary_________100.000____________0.010 - - - C_INCLK_SUM_ROW2 - no_secondary_input_clock - - - C_OUTCLK_SUM_ROW0A - C Outclk Sum Row0a - Output Output Phase Duty Cycle Pk-to-Pk Phase - - - C_OUTCLK_SUM_ROW0B - Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - - - C_OUTCLK_SUM_ROW1 - clk_out1____15.000______0.000______50.0______325.875____240.486 - - - C_OUTCLK_SUM_ROW2 - clk_out2____65.000______0.000______50.0______238.418____240.486 - - - C_OUTCLK_SUM_ROW3 - no_CLK_OUT3_output - - - C_OUTCLK_SUM_ROW4 - no_CLK_OUT4_output - - - C_OUTCLK_SUM_ROW5 - no_CLK_OUT5_output - - - C_OUTCLK_SUM_ROW6 - no_CLK_OUT6_output - - - C_OUTCLK_SUM_ROW7 - no_CLK_OUT7_output - - - C_CLKOUT1_REQUESTED_OUT_FREQ - 15 - - - C_CLKOUT2_REQUESTED_OUT_FREQ - 65 - - - C_CLKOUT3_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT4_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT5_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT6_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT1_REQUESTED_PHASE - 0.000 - - - C_CLKOUT2_REQUESTED_PHASE - 0.000 - - - C_CLKOUT3_REQUESTED_PHASE - 0.000 - - - C_CLKOUT4_REQUESTED_PHASE - 0.000 - - - C_CLKOUT5_REQUESTED_PHASE - 0.000 - - - C_CLKOUT6_REQUESTED_PHASE - 0.000 - - - C_CLKOUT7_REQUESTED_PHASE - 0.000 - - - C_CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT1_OUT_FREQ - 15.000 - - - C_CLKOUT2_OUT_FREQ - 65.000 - - - C_CLKOUT3_OUT_FREQ - 100.000 - - - C_CLKOUT4_OUT_FREQ - 100.000 - - - C_CLKOUT5_OUT_FREQ - 100.000 - - - C_CLKOUT6_OUT_FREQ - 100.000 - - - C_CLKOUT7_OUT_FREQ - 100.000 - - - C_CLKOUT1_PHASE - 0.000 - - - C_CLKOUT2_PHASE - 0.000 - - - C_CLKOUT3_PHASE - 0.000 - - - C_CLKOUT4_PHASE - 0.000 - - - C_CLKOUT5_PHASE - 0.000 - - - C_CLKOUT6_PHASE - 0.000 - - - C_CLKOUT7_PHASE - 0.000 - - - C_CLKOUT1_DUTY_CYCLE - 50.0 - - - C_CLKOUT2_DUTY_CYCLE - 50.0 - - - C_CLKOUT3_DUTY_CYCLE - 50.000 - - - C_CLKOUT4_DUTY_CYCLE - 50.000 - - - C_CLKOUT5_DUTY_CYCLE - 50.000 - - - C_CLKOUT6_DUTY_CYCLE - 50.000 - - - C_CLKOUT7_DUTY_CYCLE - 50.000 - - - C_USE_SAFE_CLOCK_STARTUP - 0 - - - C_USE_CLOCK_SEQUENCING - 0 - - - C_CLKOUT1_SEQUENCE_NUMBER - 1 - - - C_CLKOUT2_SEQUENCE_NUMBER - 1 - - - C_CLKOUT3_SEQUENCE_NUMBER - 1 - - - C_CLKOUT4_SEQUENCE_NUMBER - 1 - - - C_CLKOUT5_SEQUENCE_NUMBER - 1 - - - C_CLKOUT6_SEQUENCE_NUMBER - 1 - - - C_CLKOUT7_SEQUENCE_NUMBER - 1 - - - C_MMCM_NOTES - None - - - C_MMCM_BANDWIDTH - OPTIMIZED - - - C_MMCM_CLKFBOUT_MULT_F - 39.000 - - - C_MMCM_CLKIN1_PERIOD - 10.000 - - - C_MMCM_CLKIN2_PERIOD - 10.000 - - - C_MMCM_CLKOUT4_CASCADE - FALSE - - - C_MMCM_CLOCK_HOLD - FALSE - - - C_MMCM_COMPENSATION - ZHOLD - - - C_MMCM_DIVCLK_DIVIDE - 4 - - - C_MMCM_REF_JITTER1 - 0.010 - - - C_MMCM_REF_JITTER2 - 0.010 - - - C_MMCM_STARTUP_WAIT - FALSE - - - C_MMCM_CLKOUT0_DIVIDE_F - 65.000 - - - C_MMCM_CLKOUT1_DIVIDE - 15 - - - C_MMCM_CLKOUT2_DIVIDE - 1 - - - C_MMCM_CLKOUT3_DIVIDE - 1 - - - C_MMCM_CLKOUT4_DIVIDE - 1 - - - C_MMCM_CLKOUT5_DIVIDE - 1 - - - C_MMCM_CLKOUT6_DIVIDE - 1 - - - C_MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKFBOUT_PHASE - 0.000 - - - C_MMCM_CLKOUT0_PHASE - 0.000 - - - C_MMCM_CLKOUT1_PHASE - 0.000 - - - C_MMCM_CLKOUT2_PHASE - 0.000 - - - C_MMCM_CLKOUT3_PHASE - 0.000 - - - C_MMCM_CLKOUT4_PHASE - 0.000 - - - C_MMCM_CLKOUT5_PHASE - 0.000 - - - C_MMCM_CLKOUT6_PHASE - 0.000 - - - C_MMCM_CLKFBOUT_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT0_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT1_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT2_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT3_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT4_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT5_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT6_USE_FINE_PS - FALSE - - - C_PLL_NOTES - No notes - - - C_PLL_BANDWIDTH - OPTIMIZED - - - C_PLL_CLK_FEEDBACK - CLKFBOUT - - - C_PLL_CLKFBOUT_MULT - 1 - - - C_PLL_CLKIN_PERIOD - 1.000 - - - C_PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - C_PLL_DIVCLK_DIVIDE - 1 - - - C_PLL_REF_JITTER - 0.010 - - - C_PLL_CLKOUT0_DIVIDE - 1 - - - C_PLL_CLKOUT1_DIVIDE - 1 - - - C_PLL_CLKOUT2_DIVIDE - 1 - - - C_PLL_CLKOUT3_DIVIDE - 1 - - - C_PLL_CLKOUT4_DIVIDE - 1 - - - C_PLL_CLKOUT5_DIVIDE - 1 - - - C_PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_PLL_CLKFBOUT_PHASE - 0.000 - - - C_PLL_CLKOUT0_PHASE - 0.000 - - - C_PLL_CLKOUT1_PHASE - 0.000 - - - C_PLL_CLKOUT2_PHASE - 0.000 - - - C_PLL_CLKOUT3_PHASE - 0.000 - - - C_PLL_CLKOUT4_PHASE - 0.000 - - - C_PLL_CLKOUT5_PHASE - 0.000 - - - C_CLOCK_MGR_TYPE - NA - - - C_OVERRIDE_MMCM - 0 - - - C_OVERRIDE_PLL - 0 - - - C_PRIMARY_PORT - clk_in1 - - - C_SECONDARY_PORT - clk_in2 - - - C_CLK_OUT1_PORT - clk_out1 - - - C_CLK_OUT2_PORT - clk_out2 - - - C_CLK_OUT3_PORT - clk_out3 - - - C_CLK_OUT4_PORT - clk_out4 - - - C_CLK_OUT5_PORT - clk_out5 - - - C_CLK_OUT6_PORT - clk_out6 - - - C_CLK_OUT7_PORT - clk_out7 - - - C_RESET_PORT - reset - - - C_LOCKED_PORT - locked - - - C_CLKFB_IN_PORT - clkfb_in - - - C_CLKFB_IN_P_PORT - clkfb_in_p - - - C_CLKFB_IN_N_PORT - clkfb_in_n - - - C_CLKFB_OUT_PORT - clkfb_out - - - C_CLKFB_OUT_P_PORT - clkfb_out_p - - - C_CLKFB_OUT_N_PORT - clkfb_out_n - - - C_POWER_DOWN_PORT - power_down - - - C_DADDR_PORT - daddr - - - C_DCLK_PORT - dclk - - - C_DRDY_PORT - drdy - - - C_DWE_PORT - dwe - - - C_DIN_PORT - din - - - C_DOUT_PORT - dout - - - C_DEN_PORT - den - - - C_PSCLK_PORT - psclk - - - C_PSEN_PORT - psen - - - C_PSINCDEC_PORT - psincdec - - - C_PSDONE_PORT - psdone - - - C_CLK_VALID_PORT - CLK_VALID - - - C_STATUS_PORT - STATUS - - - C_CLK_IN_SEL_PORT - clk_in_sel - - - C_INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - C_CLKFB_STOPPED_PORT - clkfb_stopped - - - C_CLKIN1_JITTER_PS - 100.0 - - - C_CLKIN2_JITTER_PS - 100.0 - - - C_PRIMITIVE - PLL - - - C_SS_MODE - CENTER_HIGH - - - C_SS_MOD_PERIOD - 4000 - - - C_SS_MOD_TIME - 0.004 - - - C_HAS_CDDC - 0 - - - C_CDDCDONE_PORT - cddcdone - - - C_CDDCREQ_PORT - cddcreq - - - C_CLKOUTPHY_MODE - VCO - - - C_ENABLE_CLKOUTPHY - 0 - - - C_INTERFACE_SELECTION - 0 - - - C_S_AXI_ADDR_WIDTH - C S Axi Addr Width - 11 - - - C_S_AXI_DATA_WIDTH - C S Axi Data Width - 32 - - - C_POWER_REG - 0000 - - - C_CLKOUT0_1 - 0000 - - - C_CLKOUT0_2 - 0000 - - - C_CLKOUT1_1 - 0000 - - - C_CLKOUT1_2 - 0000 - - - C_CLKOUT2_1 - 0000 - - - C_CLKOUT2_2 - 0000 - - - C_CLKOUT3_1 - 0000 - - - C_CLKOUT3_2 - 0000 - - - C_CLKOUT4_1 - 0000 - - - C_CLKOUT4_2 - 0000 - - - C_CLKOUT5_1 - 0000 - - - C_CLKOUT5_2 - 0000 - - - C_CLKOUT6_1 - 0000 - - - C_CLKOUT6_2 - 0000 - - - C_CLKFBOUT_1 - 0000 - - - C_CLKFBOUT_2 - 0000 - - - C_DIVCLK - 0000 - - - C_LOCK_1 - 0000 - - - C_LOCK_2 - 0000 - - - C_LOCK_3 - 0000 - - - C_FILTER_1 - 0000 - - - C_FILTER_2 - 0000 - - - C_DIVIDE1_AUTO - 1 - - - C_DIVIDE2_AUTO - 0.23076923076923078 - - - C_DIVIDE3_AUTO - 0.15 - - - C_DIVIDE4_AUTO - 0.15 - - - C_DIVIDE5_AUTO - 0.15 - - - C_DIVIDE6_AUTO - 0.15 - - - C_DIVIDE7_AUTO - 0.15 - - - C_PLLBUFGCEDIV - false - - - C_MMCMBUFGCEDIV - false - - - C_PLLBUFGCEDIV1 - false - - - C_PLLBUFGCEDIV2 - false - - - C_PLLBUFGCEDIV3 - false - - - C_PLLBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV1 - false - - - C_MMCMBUFGCEDIV2 - false - - - C_MMCMBUFGCEDIV3 - false - - - C_MMCMBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV5 - false - - - C_MMCMBUFGCEDIV6 - false - - - C_MMCMBUFGCEDIV7 - false - - - C_CLKOUT1_MATCHED_ROUTING - false - - - C_CLKOUT2_MATCHED_ROUTING - false - - - C_CLKOUT3_MATCHED_ROUTING - false - - - C_CLKOUT4_MATCHED_ROUTING - false - - - C_CLKOUT5_MATCHED_ROUTING - false - - - C_CLKOUT6_MATCHED_ROUTING - false - - - C_CLKOUT7_MATCHED_ROUTING - false - - - C_CLKOUT0_ACTUAL_FREQ - 15.000 - - - C_CLKOUT1_ACTUAL_FREQ - 65.000 - - - C_CLKOUT2_ACTUAL_FREQ - 100.000 - - - C_CLKOUT3_ACTUAL_FREQ - 100.000 - - - C_CLKOUT4_ACTUAL_FREQ - 100.000 - - - C_CLKOUT5_ACTUAL_FREQ - 100.000 - - - C_CLKOUT6_ACTUAL_FREQ - 100.000 - - - - - - choice_list_1d3de01d - WAVEFORM - LATENCY - - - choice_list_876bfc32 - UI - PS - - - choice_list_a9bdfce0 - LOW - HIGH - OPTIMIZED - - - choice_list_ac75ef1e - Custom - - - choice_list_b9d38208 - CLKFBOUT - CLKOUT0 - - - choice_list_e099fe6c - MMCM - PLL - - - choice_pairs_035ca1c3 - SYSTEM_SYNCHRONOUS - SOURCE_SYNCHRONOUS - INTERNAL - EXTERNAL - - - choice_pairs_0920eb1b - Custom - sys_diff_clock - - - choice_pairs_11d71346 - Single_ended_clock_capable_pin - Differential_clock_capable_pin - Global_buffer - No_buffer - - - choice_pairs_15c806d5 - FDBK_AUTO - FDBK_AUTO_OFFCHIP - FDBK_ONCHIP - FDBK_OFFCHIP - - - choice_pairs_340369e0 - Custom - sys_clock - sys_diff_clock - - - choice_pairs_3c2d3ec7 - SINGLE - DIFF - - - choice_pairs_502d9f23 - ZHOLD - EXTERNAL - INTERNAL - BUF_IN - - - choice_pairs_66e4c81f - BUFG - BUFH - BUFGCE - BUFHCE - No_buffer - - - choice_pairs_77d3d587 - MMCM - PLL - BUFGCE_DIV - - - choice_pairs_8b28f1f7 - Enable_AXI - Enable_DRP - - - choice_pairs_8eea9b32 - Units_MHz - Units_ns - - - choice_pairs_a4fbc00c - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_a8642b4c - No_Jitter - Min_O_Jitter - Max_I_Jitter - - - choice_pairs_c5ef7212 - Units_UI - Units_ps - - - choice_pairs_e1c87518 - REL_PRIMARY - REL_SECONDARY - - - choice_pairs_f4e10086 - CENTER_HIGH - CENTER_LOW - DOWN_HIGH - DOWN_LOW - - - choice_pairs_f669c2f5 - frequency - Time - - - - - xilinx_veriloginstantiationtemplate_view_fileset - - clk_wiz_6.veo - verilogTemplate - - - - xilinx_anylanguagesynthesis_view_fileset - - clk_wiz_6.xdc - xdc - - processing_order - early - - - - clk_wiz_6_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - mmcm_pll_drp_func_7s_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_7s_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_pll.vh - verilogSource - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_mmcm.vh - verilogSource - true - clk_wiz_v6_0_3 - - - clk_wiz_6_clk_wiz.v - verilogSource - - - - xilinx_anylanguagesynthesiswrapper_view_fileset - - clk_wiz_6.v - verilogSource - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - mmcm_pll_drp_func_7s_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_7s_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_pll.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - mmcm_pll_drp_func_us_plus_mmcm.vh - verilogSource - USED_IN_ipstatic - true - clk_wiz_v6_0_3 - - - clk_wiz_6_clk_wiz.v - verilogSource - - - - xilinx_anylanguagesimulationwrapper_view_fileset - - clk_wiz_6.v - verilogSource - - - - xilinx_implementation_view_fileset - - clk_wiz_6_board.xdc - xdc - USED_IN_board - USED_IN_implementation - USED_IN_synthesis - - - - xilinx_versioninformation_view_fileset - - doc/clk_wiz_v6_0_changelog.txt - text - - - - xilinx_externalfiles_view_fileset - - clk_wiz_6.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - clk_wiz_6_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - clk_wiz_6_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - clk_wiz_6_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - clk_wiz_6_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - - The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. - - - Component_Name - clk_wiz_6 - - - USER_CLK_FREQ0 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ1 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ2 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ3 - User Frequency(MHz) - 100.0 - - - ENABLE_CLOCK_MONITOR - Enable Clock Monitoring - false - - - ENABLE_USER_CLOCK0 - User Clock - false - - - ENABLE_USER_CLOCK1 - User Clock - false - - - ENABLE_USER_CLOCK2 - User Clock - false - - - ENABLE_USER_CLOCK3 - User Clock - false - - - Enable_PLL0 - User Clock - false - - - Enable_PLL1 - User Clock - false - - - REF_CLK_FREQ - Reference Frequency(MHz) - 100.0 - - - PRECISION - Tolerance(MHz) - 1 - - - PRIMITIVE - Primitive - PLL - - - PRIMTYPE_SEL - Primtype Sel - mmcm_adv - - - CLOCK_MGR_TYPE - Clock Mgr Type - auto - - - USE_FREQ_SYNTH - true - - - USE_SPREAD_SPECTRUM - false - - - USE_PHASE_ALIGNMENT - true - - - USE_MIN_POWER - false - - - USE_DYN_PHASE_SHIFT - false - - - USE_DYN_RECONFIG - false - - - JITTER_SEL - No_Jitter - - - PRIM_IN_FREQ - 100.000 - - - PRIM_IN_TIMEPERIOD - 10.000 - - - IN_FREQ_UNITS - Units_MHz - - - PHASESHIFT_MODE - WAVEFORM - - - IN_JITTER_UNITS - Units_UI - - - RELATIVE_INCLK - REL_PRIMARY - - - USE_INCLK_SWITCHOVER - false - - - SECONDARY_IN_FREQ - 100.000 - - - SECONDARY_IN_TIMEPERIOD - 10.000 - - - SECONDARY_PORT - clk_in2 - - - SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - JITTER_OPTIONS - UI - - - CLKIN1_UI_JITTER - 0.010 - - - CLKIN2_UI_JITTER - 0.010 - - - PRIM_IN_JITTER - 0.010 - - - SECONDARY_IN_JITTER - 0.010 - - - CLKIN1_JITTER_PS - 100.0 - - - CLKIN2_JITTER_PS - 100.0 - - - CLKOUT1_USED - true - - - CLKOUT2_USED - true - - - CLKOUT3_USED - false - - - CLKOUT4_USED - false - - - CLKOUT5_USED - false - - - CLKOUT6_USED - false - - - CLKOUT7_USED - false - - - NUM_OUT_CLKS - 2 - - - CLK_OUT1_USE_FINE_PS_GUI - false - - - CLK_OUT2_USE_FINE_PS_GUI - false - - - CLK_OUT3_USE_FINE_PS_GUI - false - - - CLK_OUT4_USE_FINE_PS_GUI - false - - - CLK_OUT5_USE_FINE_PS_GUI - false - - - CLK_OUT6_USE_FINE_PS_GUI - false - - - CLK_OUT7_USE_FINE_PS_GUI - false - - - PRIMARY_PORT - clk_in1 - - - CLK_OUT1_PORT - clk_out1 - - - CLK_OUT2_PORT - clk_out2 - - - CLK_OUT3_PORT - clk_out3 - - - CLK_OUT4_PORT - clk_out4 - - - CLK_OUT5_PORT - clk_out5 - - - CLK_OUT6_PORT - clk_out6 - - - CLK_OUT7_PORT - clk_out7 - - - DADDR_PORT - daddr - - - DCLK_PORT - dclk - - - DRDY_PORT - drdy - - - DWE_PORT - dwe - - - DIN_PORT - din - - - DOUT_PORT - dout - - - DEN_PORT - den - - - PSCLK_PORT - psclk - - - PSEN_PORT - psen - - - PSINCDEC_PORT - psincdec - - - PSDONE_PORT - psdone - - - CLKOUT1_REQUESTED_OUT_FREQ - 15 - - - CLKOUT1_REQUESTED_PHASE - 0.000 - - - CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT2_REQUESTED_OUT_FREQ - 65 - - - CLKOUT2_REQUESTED_PHASE - 0.000 - - - CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT3_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT3_REQUESTED_PHASE - 0.000 - - - CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT4_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT4_REQUESTED_PHASE - 0.000 - - - CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT5_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT5_REQUESTED_PHASE - 0.000 - - - CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT6_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT6_REQUESTED_PHASE - 0.000 - - - CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT7_REQUESTED_PHASE - 0.000 - - - CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - USE_MAX_I_JITTER - false - - - USE_MIN_O_JITTER - false - - - CLKOUT1_MATCHED_ROUTING - false - - - CLKOUT2_MATCHED_ROUTING - false - - - CLKOUT3_MATCHED_ROUTING - false - - - CLKOUT4_MATCHED_ROUTING - false - - - CLKOUT5_MATCHED_ROUTING - false - - - CLKOUT6_MATCHED_ROUTING - false - - - CLKOUT7_MATCHED_ROUTING - false - - - PRIM_SOURCE - Single_ended_clock_capable_pin - - - CLKOUT1_DRIVES - BUFG - - - CLKOUT2_DRIVES - BUFG - - - CLKOUT3_DRIVES - BUFG - - - CLKOUT4_DRIVES - BUFG - - - CLKOUT5_DRIVES - BUFG - - - CLKOUT6_DRIVES - BUFG - - - CLKOUT7_DRIVES - BUFG - - - FEEDBACK_SOURCE - FDBK_AUTO - - - CLKFB_IN_SIGNALING - SINGLE - - - CLKFB_IN_PORT - clkfb_in - - - CLKFB_IN_P_PORT - clkfb_in_p - - - CLKFB_IN_N_PORT - clkfb_in_n - - - CLKFB_OUT_PORT - clkfb_out - - - CLKFB_OUT_P_PORT - clkfb_out_p - - - CLKFB_OUT_N_PORT - clkfb_out_n - - - PLATFORM - UNKNOWN - - - SUMMARY_STRINGS - empty - - - USE_LOCKED - true - - - CALC_DONE - empty - - - USE_RESET - true - - - USE_POWER_DOWN - false - - - USE_STATUS - false - - - USE_FREEZE - false - - - USE_CLK_VALID - false - - - USE_INCLK_STOPPED - false - - - USE_CLKFB_STOPPED - false - - - RESET_PORT - reset - - - LOCKED_PORT - locked - - - POWER_DOWN_PORT - power_down - - - CLK_VALID_PORT - CLK_VALID - - - STATUS_PORT - STATUS - - - CLK_IN_SEL_PORT - clk_in_sel - - - INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - CLKFB_STOPPED_PORT - clkfb_stopped - - - SS_MODE - CENTER_HIGH - - - SS_MOD_FREQ - 250 - - - SS_MOD_TIME - 0.004 - - - OVERRIDE_MMCM - false - - - MMCM_NOTES - None - - - MMCM_DIVCLK_DIVIDE - 4 - - - MMCM_BANDWIDTH - OPTIMIZED - - - MMCM_CLKFBOUT_MULT_F - 39 - - - MMCM_CLKFBOUT_PHASE - 0.000 - - - MMCM_CLKFBOUT_USE_FINE_PS - false - - - MMCM_CLKIN1_PERIOD - 10.000 - - - MMCM_CLKIN2_PERIOD - 10.000 - - - MMCM_CLKOUT4_CASCADE - false - - - MMCM_CLOCK_HOLD - false - - - MMCM_COMPENSATION - ZHOLD - - - MMCM_REF_JITTER1 - 0.010 - - - MMCM_REF_JITTER2 - 0.010 - - - MMCM_STARTUP_WAIT - false - - - MMCM_CLKOUT0_DIVIDE_F - 65 - - - MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT0_PHASE - 0.000 - - - MMCM_CLKOUT0_USE_FINE_PS - false - - - MMCM_CLKOUT1_DIVIDE - 15 - - - MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT1_PHASE - 0.000 - - - MMCM_CLKOUT1_USE_FINE_PS - false - - - MMCM_CLKOUT2_DIVIDE - 1 - - - MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT2_PHASE - 0.000 - - - MMCM_CLKOUT2_USE_FINE_PS - false - - - MMCM_CLKOUT3_DIVIDE - 1 - - - MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT3_PHASE - 0.000 - - - MMCM_CLKOUT3_USE_FINE_PS - false - - - MMCM_CLKOUT4_DIVIDE - 1 - - - MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT4_PHASE - 0.000 - - - MMCM_CLKOUT4_USE_FINE_PS - false - - - MMCM_CLKOUT5_DIVIDE - 1 - - - MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT5_PHASE - 0.000 - - - MMCM_CLKOUT5_USE_FINE_PS - false - - - MMCM_CLKOUT6_DIVIDE - 1 - - - MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT6_PHASE - 0.000 - - - MMCM_CLKOUT6_USE_FINE_PS - false - - - OVERRIDE_PLL - false - - - PLL_NOTES - None - - - PLL_BANDWIDTH - OPTIMIZED - - - PLL_CLKFBOUT_MULT - 4 - - - PLL_CLKFBOUT_PHASE - 0.000 - - - PLL_CLK_FEEDBACK - CLKFBOUT - - - PLL_DIVCLK_DIVIDE - 1 - - - PLL_CLKIN_PERIOD - 10.000 - - - PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - PLL_REF_JITTER - 0.010 - - - PLL_CLKOUT0_DIVIDE - 1 - - - PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT0_PHASE - 0.000 - - - PLL_CLKOUT1_DIVIDE - 1 - - - PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT1_PHASE - 0.000 - - - PLL_CLKOUT2_DIVIDE - 1 - - - PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT2_PHASE - 0.000 - - - PLL_CLKOUT3_DIVIDE - 1 - - - PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT3_PHASE - 0.000 - - - PLL_CLKOUT4_DIVIDE - 1 - - - PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT4_PHASE - 0.000 - - - PLL_CLKOUT5_DIVIDE - 1 - - - PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT5_PHASE - 0.000 - - - RESET_TYPE - Reset Type - ACTIVE_HIGH - - - USE_SAFE_CLOCK_STARTUP - false - - - USE_CLOCK_SEQUENCING - false - - - CLKOUT1_SEQUENCE_NUMBER - 1 - - - CLKOUT2_SEQUENCE_NUMBER - 1 - - - CLKOUT3_SEQUENCE_NUMBER - 1 - - - CLKOUT4_SEQUENCE_NUMBER - 1 - - - CLKOUT5_SEQUENCE_NUMBER - 1 - - - CLKOUT6_SEQUENCE_NUMBER - 1 - - - CLKOUT7_SEQUENCE_NUMBER - 1 - - - USE_BOARD_FLOW - Generate Board based IO Constraints - false - - - CLK_IN1_BOARD_INTERFACE - Custom - - - CLK_IN2_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN1_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN2_BOARD_INTERFACE - Custom - - - AUTO_PRIMITIVE - MMCM - - - RESET_BOARD_INTERFACE - Custom - - - ENABLE_CDDC - false - - - CDDCDONE_PORT - cddcdone - - - CDDCREQ_PORT - cddcreq - - - ENABLE_CLKOUTPHY - false - - - CLKOUTPHY_REQUESTED_FREQ - 600.000 - - - CLKOUT1_JITTER - Clkout1 Jitter - 325.875 - - - CLKOUT1_PHASE_ERROR - Clkout1 Phase - 240.486 - - - CLKOUT2_JITTER - Clkout2 Jitter - 238.418 - - - CLKOUT2_PHASE_ERROR - Clkout2 Phase - 240.486 - - - CLKOUT3_JITTER - Clkout3 Jitter - 0.0 - - - CLKOUT3_PHASE_ERROR - Clkout3 Phase - 0.0 - - - CLKOUT4_JITTER - Clkout4 Jitter - 0.0 - - - CLKOUT4_PHASE_ERROR - Clkout4 Phase - 0.0 - - - CLKOUT5_JITTER - Clkout5 Jitter - 0.0 - - - CLKOUT5_PHASE_ERROR - Clkout5 Phase - 0.0 - - - CLKOUT6_JITTER - Clkout6 Jitter - 0.0 - - - CLKOUT6_PHASE_ERROR - Clkout6 Phase - 0.0 - - - CLKOUT7_JITTER - Clkout7 Jitter - 0.0 - - - CLKOUT7_PHASE_ERROR - Clkout7 Phase - 0.0 - - - INPUT_MODE - frequency - - - INTERFACE_SELECTION - Enable_AXI - - - AXI_DRP - Write DRP registers - false - - - PHASE_DUTY_CONFIG - Phase Duty Cycle Config - false - - - - - Clocking Wizard - - XPM_CDC - - 3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.1.1 - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.cache/wt/webtalk_pa.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.cache/wt/webtalk_pa.xml deleted file mode 100644 index 35e075f..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.cache/wt/webtalk_pa.xml +++ /dev/null @@ -1,137 +0,0 @@ - - - - -
- - -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.hw/hw_1/hw.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.hw/hw_1/hw.xml deleted file mode 100644 index f6cb493..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.hw/hw_1/hw.xml +++ /dev/null @@ -1,17 +0,0 @@ - - - - - - - - - - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_1.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_1.xml deleted file mode 100644 index e0a62c5..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_1.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_10.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_10.xml deleted file mode 100644 index e0a62c5..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_10.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_11.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_11.xml deleted file mode 100644 index d948cd1..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_11.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_12.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_12.xml deleted file mode 100644 index 39deff8..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_12.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_13.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_13.xml deleted file mode 100644 index e0a62c5..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_13.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_14.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_14.xml deleted file mode 100644 index 39deff8..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_14.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_15.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_15.xml deleted file mode 100644 index e0a62c5..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_15.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_16.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_16.xml deleted file mode 100644 index d948cd1..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_16.xml +++ /dev/null @@ -1,5 +0,0 @@ - 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- - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_60.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_60.xml deleted file mode 100644 index a97fa2d..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_60.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_61.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_61.xml deleted file mode 100644 index 4ff335d..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_61.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_62.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_62.xml deleted file mode 100644 index 39deff8..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_62.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_63.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_63.xml deleted file mode 100644 index 39deff8..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_63.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_64.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_64.xml deleted file mode 100644 index 39deff8..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_64.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_65.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_65.xml deleted file mode 100644 index 39deff8..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_65.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_66.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_66.xml deleted file mode 100644 index 39deff8..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_66.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_67.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_67.xml deleted file mode 100644 index 39deff8..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_67.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_68.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_68.xml deleted file mode 100644 index 39deff8..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_68.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_69.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_69.xml deleted file mode 100644 index 39deff8..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_69.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_7.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_7.xml deleted file mode 100644 index e0a62c5..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_7.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_70.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_70.xml deleted file mode 100644 index 39deff8..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_70.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_71.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_71.xml deleted file mode 100644 index 39deff8..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_71.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_72.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_72.xml deleted file mode 100644 index 39deff8..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_72.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_73.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_73.xml deleted file mode 100644 index 39deff8..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_73.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_74.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_74.xml deleted file mode 100644 index 39deff8..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_74.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_75.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_75.xml deleted file mode 100644 index 39deff8..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_75.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_76.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_76.xml deleted file mode 100644 index 39deff8..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_76.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_77.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_77.xml deleted file mode 100644 index 39deff8..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_77.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_78.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_78.xml deleted file mode 100644 index 39deff8..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_78.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_79.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_79.xml deleted file mode 100644 index 88a30d3..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/.jobs/vrs_config_79.xml +++ /dev/null @@ -1,8 +0,0 @@ - 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- - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/impl_1/gen_run.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/impl_1/gen_run.xml deleted file mode 100644 index e546676..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/impl_1/gen_run.xml +++ /dev/null @@ -1,147 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/impl_1/usage_statistics_webtalk.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/impl_1/usage_statistics_webtalk.xml deleted file mode 100644 index 6056d94..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/impl_1/usage_statistics_webtalk.xml +++ /dev/null @@ -1,659 +0,0 @@ - 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- diff --git a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/synth_1/gen_run.xml b/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/synth_1/gen_run.xml deleted file mode 100644 index cd82d1c..0000000 --- a/Digital_Circuit_Design/Final_Project_Microphone_Suite/Final_Project_Microphone_Suite.runs/synth_1/gen_run.xml +++ /dev/null @@ -1,95 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Digital_Circuit_Design/GPIO Test/Nexys-4-DDR-GPIO.board/nexys4_ddr/board.xml b/Digital_Circuit_Design/GPIO Test/Nexys-4-DDR-GPIO.board/nexys4_ddr/board.xml deleted file mode 100644 index ab788e1..0000000 --- a/Digital_Circuit_Design/GPIO Test/Nexys-4-DDR-GPIO.board/nexys4_ddr/board.xml +++ /dev/null @@ -1,1455 +0,0 @@ - - - - C.1 - -1.1 -Nexys4 DDR - - - - - Accelerometer control through SPI - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - DDR2 board interface, it can use MIG IP for connection. - - - - - - 16 DIP Switches - - - - - - - - - - - - - - - - - - - - - - - - - - - - Dual 7 Seg LED Segments - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Secondary interface to communicate with ethernet phy. - - - - - - - - - - - - - - - - - - - - - - - - - Primary interface to communicate with ethernet phy in RMII mode. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 16 LEDs - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 5 Push Buttons - - - - - - - - - - - - - - - - - Quad SPI Flash - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2 RGB LEDs - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 7 Segment Display Anodes - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Temperature Sensor connected to I2C - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - USB-to-UART Bridge, which allows a connection to a host computer with a USB port - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Accelerometer controlled through SPI - - - 256 MB Onboard DDR Memory - - - - - - - 16 Switches - - - 7 Segment Display Segment Control - - - Ethernet RMII Signals - - - Ethernet MDIO/MDC Signals - - - 16 LEDs - - - Push Buttons 5 to 0 {Down Right Left Up Center} - - - QSPI Flash - - - Onboard Reset Button - - - 2 RGB LEDs - - - 7 Segment Display Anodes - - - 100 MHz Single-Ended System Clock - - - SPI Controlled Temperature Sensor - - - USB-to-UART Bridge, which allows a connection to a host computer with a USB port - - - Pmod Connector JA - - - Pmod Connector JB - - - Pmod Connector JC - - - Pmod Connector JD - - - Pmod Connector JXADC - - - - - - - - - - - - - - - - - - - - - Onboard MicroSD Card Slot - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Digital_Circuit_Design/GPIO Test/Nexys-4-DDR-GPIO.board/nexys4_ddr/part0_pins.xml b/Digital_Circuit_Design/GPIO Test/Nexys-4-DDR-GPIO.board/nexys4_ddr/part0_pins.xml deleted file mode 100644 index 0ae3a72..0000000 --- a/Digital_Circuit_Design/GPIO Test/Nexys-4-DDR-GPIO.board/nexys4_ddr/part0_pins.xml +++ /dev/null @@ -1,139 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Digital_Circuit_Design/GPIO Test/Nexys-4-DDR-GPIO.board/nexys4_ddr/preset.xml b/Digital_Circuit_Design/GPIO Test/Nexys-4-DDR-GPIO.board/nexys4_ddr/preset.xml deleted file mode 100644 index 4496b8b..0000000 --- a/Digital_Circuit_Design/GPIO Test/Nexys-4-DDR-GPIO.board/nexys4_ddr/preset.xml +++ /dev/null @@ -1,363 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - diff --git a/Digital_Circuit_Design/GPIO Test/Nexys-4-DDR-GPIO.hw/hw_1/hw.xml b/Digital_Circuit_Design/GPIO Test/Nexys-4-DDR-GPIO.hw/hw_1/hw.xml deleted file mode 100644 index fb806c1..0000000 --- a/Digital_Circuit_Design/GPIO Test/Nexys-4-DDR-GPIO.hw/hw_1/hw.xml +++ /dev/null @@ -1,17 +0,0 @@ - - - - - - - - - - - - - - - - - diff --git a/Digital_Circuit_Design/GPIO Test/Nexys-4-DDR-GPIO.runs/impl_1/gen_run.xml b/Digital_Circuit_Design/GPIO Test/Nexys-4-DDR-GPIO.runs/impl_1/gen_run.xml deleted file mode 100644 index 445b6a9..0000000 --- a/Digital_Circuit_Design/GPIO Test/Nexys-4-DDR-GPIO.runs/impl_1/gen_run.xml +++ /dev/null @@ -1,125 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Digital_Circuit_Design/GPIO Test/Nexys-4-DDR-GPIO.runs/synth_1/gen_run.xml b/Digital_Circuit_Design/GPIO Test/Nexys-4-DDR-GPIO.runs/synth_1/gen_run.xml deleted file mode 100644 index 8812363..0000000 --- a/Digital_Circuit_Design/GPIO Test/Nexys-4-DDR-GPIO.runs/synth_1/gen_run.xml +++ /dev/null @@ -1,71 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.cache/wt/webtalk_pa.xml b/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.cache/wt/webtalk_pa.xml deleted file mode 100644 index bc95266..0000000 --- a/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.cache/wt/webtalk_pa.xml +++ /dev/null @@ -1,82 +0,0 @@ - - - - -
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- - diff --git a/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.hw/hw_1/hw.xml b/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.hw/hw_1/hw.xml deleted file mode 100644 index 7c0cadb..0000000 --- a/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.hw/hw_1/hw.xml +++ /dev/null @@ -1,17 +0,0 @@ - - - - - - - - - - - - - - - - - diff --git a/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/.jobs/vrs_config_1.xml b/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/.jobs/vrs_config_1.xml deleted file mode 100644 index 3e163b5..0000000 --- a/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/.jobs/vrs_config_1.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/.jobs/vrs_config_2.xml b/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/.jobs/vrs_config_2.xml deleted file mode 100644 index 3e163b5..0000000 --- a/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/.jobs/vrs_config_2.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/.jobs/vrs_config_3.xml b/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/.jobs/vrs_config_3.xml deleted file mode 100644 index 3e163b5..0000000 --- a/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/.jobs/vrs_config_3.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/.jobs/vrs_config_4.xml b/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/.jobs/vrs_config_4.xml deleted file mode 100644 index 47aa0e1..0000000 --- a/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/.jobs/vrs_config_4.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/impl_1/gen_run.xml b/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/impl_1/gen_run.xml deleted file mode 100644 index d87f9cb..0000000 --- a/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/impl_1/gen_run.xml +++ /dev/null @@ -1,120 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/impl_1/usage_statistics_webtalk.xml b/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/impl_1/usage_statistics_webtalk.xml deleted file mode 100644 index 31f980b..0000000 --- a/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/impl_1/usage_statistics_webtalk.xml +++ /dev/null @@ -1,605 +0,0 @@ - - -
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- diff --git a/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/synth_1/gen_run.xml b/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/synth_1/gen_run.xml deleted file mode 100644 index 0f0aaa7..0000000 --- a/Digital_Circuit_Design/Traffic_Light_Controller/Traffic_Light_Controller.runs/synth_1/gen_run.xml +++ /dev/null @@ -1,52 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Digital_Circuit_Design/adders/adders.cache/wt/webtalk_pa.xml b/Digital_Circuit_Design/adders/adders.cache/wt/webtalk_pa.xml deleted file mode 100644 index d4a2f7f..0000000 --- a/Digital_Circuit_Design/adders/adders.cache/wt/webtalk_pa.xml +++ /dev/null @@ -1,132 +0,0 @@ - - - - -
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- - diff --git a/Digital_Circuit_Design/adders/adders.hw/hw_1/hw.xml b/Digital_Circuit_Design/adders/adders.hw/hw_1/hw.xml deleted file mode 100644 index 2f9c4e1..0000000 --- a/Digital_Circuit_Design/adders/adders.hw/hw_1/hw.xml +++ /dev/null @@ -1,17 +0,0 @@ - - - - - - - - - - - - - - - - - diff --git a/Digital_Circuit_Design/adders/adders.runs/.jobs/vrs_config_1.xml b/Digital_Circuit_Design/adders/adders.runs/.jobs/vrs_config_1.xml deleted file mode 100644 index bf0fbaf..0000000 --- a/Digital_Circuit_Design/adders/adders.runs/.jobs/vrs_config_1.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/Digital_Circuit_Design/adders/adders.runs/.jobs/vrs_config_10.xml b/Digital_Circuit_Design/adders/adders.runs/.jobs/vrs_config_10.xml deleted file mode 100644 index bf0fbaf..0000000 --- a/Digital_Circuit_Design/adders/adders.runs/.jobs/vrs_config_10.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/Digital_Circuit_Design/adders/adders.runs/.jobs/vrs_config_11.xml b/Digital_Circuit_Design/adders/adders.runs/.jobs/vrs_config_11.xml deleted file mode 100644 index 67a02ff..0000000 --- a/Digital_Circuit_Design/adders/adders.runs/.jobs/vrs_config_11.xml +++ /dev/null @@ -1,8 +0,0 @@ - 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