diff --git a/drivers/gpu/drm/asahi/fw/channels.rs b/drivers/gpu/drm/asahi/fw/channels.rs index cf1f1ec4eddd77..c1a7ec82aad1e2 100644 --- a/drivers/gpu/drm/asahi/fw/channels.rs +++ b/drivers/gpu/drm/asahi/fw/channels.rs @@ -113,7 +113,7 @@ impl TxChannelState for FwCtlChannelState { } } -#[derive(Debug, Copy, Clone, Default)] +#[derive(Debug, Copy, Clone, Default, PartialEq, Eq)] #[repr(u32)] pub(crate) enum PipeType { #[default] diff --git a/drivers/gpu/drm/asahi/fw/workqueue.rs b/drivers/gpu/drm/asahi/fw/workqueue.rs index 1b55d8cb6ca273..a53312854ab356 100644 --- a/drivers/gpu/drm/asahi/fw/workqueue.rs +++ b/drivers/gpu/drm/asahi/fw/workqueue.rs @@ -98,7 +98,14 @@ pub(crate) mod raw { #[derive(Debug, Clone, Copy)] #[repr(C)] - pub(crate) struct Priority(u32, u32, U64, u32, u32, u32); + pub(crate) struct Priority( + pub(crate) u32, + pub(crate) u32, + pub(crate) U64, + pub(crate) u32, + pub(crate) u32, + pub(crate) u32, + ); pub(crate) const PRIORITY: [Priority; 4] = [ Priority(0, 0, U64(0xffff_ffff_ffff_0000), 1, 0, 1), diff --git a/drivers/gpu/drm/asahi/workqueue.rs b/drivers/gpu/drm/asahi/workqueue.rs index 46b170b1ce71d1..c91cb62c3ec834 100644 --- a/drivers/gpu/drm/asahi/workqueue.rs +++ b/drivers/gpu/drm/asahi/workqueue.rs @@ -662,6 +662,14 @@ impl WorkQueue::ver { let gpu_buf = alloc.private.array_empty_tagged(0x2c18, b"GPBF")?; let mut state = alloc.shared.new_default::()?; let ring = alloc.shared.array_empty(size as usize)?; + let mut prio = *raw::PRIORITY.get(priority as usize).ok_or(EINVAL)?; + + if pipe_type == PipeType::Compute && !debug_enabled(DebugFlags::Debug0) { + // Hack to disable compute preemption until we fix it + prio.0 = 0; + prio.5 = 1; + } + let inner = WorkQueueInner::ver { dev: dev.into(), event_manager, @@ -694,7 +702,7 @@ impl WorkQueue::ver { gpu_rptr2: Default::default(), gpu_rptr3: Default::default(), event_id: AtomicI32::new(-1), - priority: *raw::PRIORITY.get(priority as usize).ok_or(EINVAL)?, + priority: prio, unk_4c: -1, uuid: id as u32, unk_54: -1,