forked from Abdo5200/connect4-game
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathgg.c
2671 lines (2508 loc) · 103 KB
/
gg.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
//*****************************************************************************
//
// gpio.c - API for GPIO ports
//
// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup gpio_api
//! @{
//
//*****************************************************************************
#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_gpio.h"
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_sysctl.h"
#include "inc/hw_types.h"
#include "driverlib/debug.h"
#include "gg.h"
#include "driverlib/interrupt.h"
//*****************************************************************************
//
// A mapping of GPIO port address to interrupt number.
//
//*****************************************************************************
static const uint32_t g_ppui32GPIOIntMapBlizzard[][2] =
{
{ GPIO_PORTA_BASE, INT_GPIOA_TM4C123 },
{ GPIO_PORTA_AHB_BASE, INT_GPIOA_TM4C123 },
{ GPIO_PORTB_BASE, INT_GPIOB_TM4C123 },
{ GPIO_PORTB_AHB_BASE, INT_GPIOB_TM4C123 },
{ GPIO_PORTC_BASE, INT_GPIOC_TM4C123 },
{ GPIO_PORTC_AHB_BASE, INT_GPIOC_TM4C123 },
{ GPIO_PORTD_BASE, INT_GPIOD_TM4C123 },
{ GPIO_PORTD_AHB_BASE, INT_GPIOD_TM4C123 },
{ GPIO_PORTE_BASE, INT_GPIOE_TM4C123 },
{ GPIO_PORTE_AHB_BASE, INT_GPIOE_TM4C123 },
{ GPIO_PORTF_BASE, INT_GPIOF_TM4C123 },
{ GPIO_PORTF_AHB_BASE, INT_GPIOF_TM4C123 },
{ GPIO_PORTG_BASE, INT_GPIOG_TM4C123 },
{ GPIO_PORTG_AHB_BASE, INT_GPIOG_TM4C123 },
{ GPIO_PORTH_BASE, INT_GPIOH_TM4C123 },
{ GPIO_PORTH_AHB_BASE, INT_GPIOH_TM4C123 },
{ GPIO_PORTJ_BASE, INT_GPIOJ_TM4C123 },
{ GPIO_PORTJ_AHB_BASE, INT_GPIOJ_TM4C123 },
{ GPIO_PORTK_BASE, INT_GPIOK_TM4C123 },
{ GPIO_PORTL_BASE, INT_GPIOL_TM4C123 },
{ GPIO_PORTM_BASE, INT_GPIOM_TM4C123 },
{ GPIO_PORTN_BASE, INT_GPION_TM4C123 },
{ GPIO_PORTP_BASE, INT_GPIOP0_TM4C123 },
{ GPIO_PORTQ_BASE, INT_GPIOQ0_TM4C123 },
};
static const uint_fast32_t g_ui32GPIOIntMapBlizzardRows =
sizeof(g_ppui32GPIOIntMapBlizzard) / sizeof(g_ppui32GPIOIntMapBlizzard[0]);
static const uint32_t g_ppui32GPIOIntMapSnowflake[][2] =
{
{ GPIO_PORTA_BASE, INT_GPIOA_TM4C129 },
{ GPIO_PORTA_AHB_BASE, INT_GPIOA_TM4C129 },
{ GPIO_PORTB_BASE, INT_GPIOB_TM4C129 },
{ GPIO_PORTB_AHB_BASE, INT_GPIOB_TM4C129 },
{ GPIO_PORTC_BASE, INT_GPIOC_TM4C129 },
{ GPIO_PORTC_AHB_BASE, INT_GPIOC_TM4C129 },
{ GPIO_PORTD_BASE, INT_GPIOD_TM4C129 },
{ GPIO_PORTD_AHB_BASE, INT_GPIOD_TM4C129 },
{ GPIO_PORTE_BASE, INT_GPIOE_TM4C129 },
{ GPIO_PORTE_AHB_BASE, INT_GPIOE_TM4C129 },
{ GPIO_PORTF_BASE, INT_GPIOF_TM4C129 },
{ GPIO_PORTF_AHB_BASE, INT_GPIOF_TM4C129 },
{ GPIO_PORTG_BASE, INT_GPIOG_TM4C129 },
{ GPIO_PORTG_AHB_BASE, INT_GPIOG_TM4C129 },
{ GPIO_PORTH_BASE, INT_GPIOH_TM4C129 },
{ GPIO_PORTH_AHB_BASE, INT_GPIOH_TM4C129 },
{ GPIO_PORTJ_BASE, INT_GPIOJ_TM4C129 },
{ GPIO_PORTJ_AHB_BASE, INT_GPIOJ_TM4C129 },
{ GPIO_PORTK_BASE, INT_GPIOK_TM4C129 },
{ GPIO_PORTL_BASE, INT_GPIOL_TM4C129 },
{ GPIO_PORTM_BASE, INT_GPIOM_TM4C129 },
{ GPIO_PORTN_BASE, INT_GPION_TM4C129 },
{ GPIO_PORTP_BASE, INT_GPIOP0_TM4C129 },
{ GPIO_PORTQ_BASE, INT_GPIOQ0_TM4C129 },
};
static const uint_fast32_t g_ui32GPIOIntMapSnowflakeRows =
(sizeof(g_ppui32GPIOIntMapSnowflake) /
sizeof(g_ppui32GPIOIntMapSnowflake[0]));
//*****************************************************************************
//
// The base addresses of all the GPIO modules. Both the APB and AHB apertures
// are provided.
//
//*****************************************************************************
static const uint32_t g_pui32GPIOBaseAddrs[] =
{
GPIO_PORTA_BASE, GPIO_PORTA_AHB_BASE,
GPIO_PORTB_BASE, GPIO_PORTB_AHB_BASE,
GPIO_PORTC_BASE, GPIO_PORTC_AHB_BASE,
GPIO_PORTD_BASE, GPIO_PORTD_AHB_BASE,
GPIO_PORTE_BASE, GPIO_PORTE_AHB_BASE,
GPIO_PORTF_BASE, GPIO_PORTF_AHB_BASE,
GPIO_PORTG_BASE, GPIO_PORTG_AHB_BASE,
GPIO_PORTH_BASE, GPIO_PORTH_AHB_BASE,
GPIO_PORTJ_BASE, GPIO_PORTJ_AHB_BASE,
GPIO_PORTK_BASE, GPIO_PORTK_BASE,
GPIO_PORTL_BASE, GPIO_PORTL_BASE,
GPIO_PORTM_BASE, GPIO_PORTM_BASE,
GPIO_PORTN_BASE, GPIO_PORTN_BASE,
GPIO_PORTP_BASE, GPIO_PORTP_BASE,
GPIO_PORTQ_BASE, GPIO_PORTQ_BASE,
GPIO_PORTR_BASE, GPIO_PORTR_BASE,
GPIO_PORTS_BASE, GPIO_PORTS_BASE,
GPIO_PORTT_BASE, GPIO_PORTT_BASE,
};
//*****************************************************************************
//
//! \internal
//! Checks a GPIO base address.
//!
//! \param ui32Port is the base address of the GPIO port.
//!
//! This function determines if a GPIO port base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
#ifdef DEBUG
static bool
_GPIOBaseValid(uint32_t ui32Port)
{
return((ui32Port == GPIO_PORTA_BASE) ||
(ui32Port == GPIO_PORTA_AHB_BASE) ||
(ui32Port == GPIO_PORTB_BASE) ||
(ui32Port == GPIO_PORTB_AHB_BASE) ||
(ui32Port == GPIO_PORTC_BASE) ||
(ui32Port == GPIO_PORTC_AHB_BASE) ||
(ui32Port == GPIO_PORTD_BASE) ||
(ui32Port == GPIO_PORTD_AHB_BASE) ||
(ui32Port == GPIO_PORTE_BASE) ||
(ui32Port == GPIO_PORTE_AHB_BASE) ||
(ui32Port == GPIO_PORTF_BASE) ||
(ui32Port == GPIO_PORTF_AHB_BASE) ||
(ui32Port == GPIO_PORTG_BASE) ||
(ui32Port == GPIO_PORTG_AHB_BASE) ||
(ui32Port == GPIO_PORTH_BASE) ||
(ui32Port == GPIO_PORTH_AHB_BASE) ||
(ui32Port == GPIO_PORTJ_BASE) ||
(ui32Port == GPIO_PORTJ_AHB_BASE) ||
(ui32Port == GPIO_PORTK_BASE) ||
(ui32Port == GPIO_PORTL_BASE) ||
(ui32Port == GPIO_PORTM_BASE) ||
(ui32Port == GPIO_PORTN_BASE) ||
(ui32Port == GPIO_PORTP_BASE) ||
(ui32Port == GPIO_PORTQ_BASE) ||
(ui32Port == GPIO_PORTR_BASE) ||
(ui32Port == GPIO_PORTS_BASE) ||
(ui32Port == GPIO_PORTT_BASE));
}
#endif
//*****************************************************************************
//
//! Gets the GPIO interrupt number.
//!
//! \param ui32Port is the base address of the GPIO port.
//!
//! Given a GPIO base address, this function returns the corresponding
//! interrupt number.
//!
//! \return Returns a GPIO interrupt number, or 0 if \e ui32Port is invalid.
//
//*****************************************************************************
static uint32_t
_GPIOIntNumberGet(uint32_t ui32Port)
{
uint_fast32_t ui32Idx, ui32Rows;
const uint32_t (*ppui32GPIOIntMap)[2];
//
// Check the arguments.
//
ASSERT(_GPIOBaseValid(ui32Port));
ppui32GPIOIntMap = g_ppui32GPIOIntMapBlizzard;
ui32Rows = g_ui32GPIOIntMapBlizzardRows;
if(CLASS_IS_TM4C129)
{
ppui32GPIOIntMap = g_ppui32GPIOIntMapSnowflake;
ui32Rows = g_ui32GPIOIntMapSnowflakeRows;
}
//
// Loop through the table that maps I2C base addresses to interrupt
// numbers.
//
for(ui32Idx = 0; ui32Idx < ui32Rows; ui32Idx++)
{
//
// See if this base address matches.
//
if(ppui32GPIOIntMap[ui32Idx][0] == ui32Port)
{
//
// Return the corresponding interrupt number.
//
return(ppui32GPIOIntMap[ui32Idx][1]);
}
}
//
// The base address could not be found, so return an error.
//
return(0);
}
//*****************************************************************************
//
//! Sets the direction and mode of the specified pin(s).
//!
//! \param ui32Port is the base address of the GPIO port
//! \param ui8Pins is the bit-packed representation of the pin(s).
//! \param ui32PinIO is the pin direction and/or mode.
//!
//! This function configures the specified pin(s) on the selected GPIO port
//! as either input or output under software control, or it configures the
//! pin to be under hardware control.
//!
//! The parameter \e ui32PinIO is an enumerated data type that can be one of
//! the following values:
//!
//! - \b GPIO_DIR_MODE_IN
//! - \b GPIO_DIR_MODE_OUT
//! - \b GPIO_DIR_MODE_HW
//!
//! where \b GPIO_DIR_MODE_IN specifies that the pin is programmed as a
//! software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin is
//! programmed as a software controlled output, and \b GPIO_DIR_MODE_HW
//! specifies that the pin is placed under hardware control.
//!
//! The pin(s) are specified using a bit-packed byte, where each bit that is
//! set identifies the pin to be accessed, and where bit 0 of the byte
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//!
//! \note GPIOPadConfigSet() must also be used to configure the corresponding
//! pad(s) in order for them to propagate the signal to/from the GPIO.
//!
//! \note A subset of GPIO pins on Tiva devices, notably those used by the
//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
//! locked against inadvertent reconfiguration. These pins must be unlocked
//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
//! registers before this function can be called. Please see the ``gpio_jtag''
//! example application for the mechanism required and consult your part
//! datasheet for information on affected pins.
//!
//! \return None.
//
//*****************************************************************************
void
GPIODirModeSet(uint32_t ui32Port, uint8_t ui8Pins, uint32_t ui32PinIO)
{
//
// Check the arguments.
//
ASSERT(_GPIOBaseValid(ui32Port));
ASSERT((ui32PinIO == GPIO_DIR_MODE_IN) ||
(ui32PinIO == GPIO_DIR_MODE_OUT) ||
(ui32PinIO == GPIO_DIR_MODE_HW));
//
// Set the pin direction and mode.
//
HWREG(ui32Port + GPIO_O_DIR) = ((ui32PinIO & 1) ?
(HWREG(ui32Port + GPIO_O_DIR) | ui8Pins) :
(HWREG(ui32Port + GPIO_O_DIR) & ~(ui8Pins)));
HWREG(ui32Port + GPIO_O_AFSEL) = ((ui32PinIO & 2) ?
(HWREG(ui32Port + GPIO_O_AFSEL) |
ui8Pins) :
(HWREG(ui32Port + GPIO_O_AFSEL) &
~(ui8Pins)));
}
//*****************************************************************************
//
//! Gets the direction and mode of a pin.
//!
//! \param ui32Port is the base address of the GPIO port.
//! \param ui8Pin is the pin number.
//!
//! This function gets the direction and control mode for a specified pin on
//! the selected GPIO port. The pin can be configured as either an input or
//! output under software control, or it can be under hardware control. The
//! type of control and direction are returned as an enumerated data type.
//!
//! \return Returns one of the enumerated data types described for
//! GPIODirModeSet().
//
//*****************************************************************************
uint32_t
GPIODirModeGet(uint32_t ui32Port, uint8_t ui8Pin)
{
uint32_t ui32Dir, ui32AFSEL;
//
// Check the arguments.
//
ASSERT(_GPIOBaseValid(ui32Port));
ASSERT(ui8Pin < 8);
//
// Convert from a pin number to a bit position.
//
ui8Pin = 1 << ui8Pin;
//
// Return the pin direction and mode.
//
ui32Dir = HWREG(ui32Port + GPIO_O_DIR);
ui32AFSEL = HWREG(ui32Port + GPIO_O_AFSEL);
return(((ui32Dir & ui8Pin) ? 1 : 0) | ((ui32AFSEL & ui8Pin) ? 2 : 0));
}
//*****************************************************************************
//
//! Sets the interrupt type for the specified pin(s).
//!
//! \param ui32Port is the base address of the GPIO port.
//! \param ui8Pins is the bit-packed representation of the pin(s).
//! \param ui32IntType specifies the type of interrupt trigger mechanism.
//!
//! This function sets up the various interrupt trigger mechanisms for the
//! specified pin(s) on the selected GPIO port.
//!
//! One of the following flags can be used to define the \e ui32IntType
//! parameter:
//!
//! - \b GPIO_FALLING_EDGE sets detection to edge and trigger to falling
//! - \b GPIO_RISING_EDGE sets detection to edge and trigger to rising
//! - \b GPIO_BOTH_EDGES sets detection to both edges
//! - \b GPIO_LOW_LEVEL sets detection to low level
//! - \b GPIO_HIGH_LEVEL sets detection to high level
//!
//! In addition to the above flags, the following flag can be OR'd in to the
//! \e ui32IntType parameter:
//!
//! - \b GPIO_DISCRETE_INT sets discrete interrupts for each pin on a GPIO
//! port.
//!
//! The \b GPIO_DISCRETE_INT is not available on all devices or all GPIO ports,
//! consult the data sheet to ensure that the device and the GPIO port supports
//! discrete interrupts.
//!
//! The pin(s) are specified using a bit-packed byte, where each bit that is
//! set identifies the pin to be accessed, and where bit 0 of the byte
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//!
//! \note In order to avoid any spurious interrupts, the user must ensure that
//! the GPIO inputs remain stable for the duration of this function.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins,
uint32_t ui32IntType)
{
//
// Check the arguments.
//
ASSERT(_GPIOBaseValid(ui32Port));
ASSERT((ui32IntType == GPIO_FALLING_EDGE) ||
(ui32IntType == GPIO_RISING_EDGE) ||
(ui32IntType == GPIO_BOTH_EDGES) ||
(ui32IntType == GPIO_LOW_LEVEL) ||
(ui32IntType == GPIO_HIGH_LEVEL));
//
// Set the pin interrupt type.
//
HWREG(ui32Port + GPIO_O_IBE) = ((ui32IntType & 1) ?
(HWREG(ui32Port + GPIO_O_IBE) | ui8Pins) :
(HWREG(ui32Port + GPIO_O_IBE) & ~(ui8Pins)));
HWREG(ui32Port + GPIO_O_IS) = ((ui32IntType & 2) ?
(HWREG(ui32Port + GPIO_O_IS) | ui8Pins) :
(HWREG(ui32Port + GPIO_O_IS) & ~(ui8Pins)));
HWREG(ui32Port + GPIO_O_IEV) = ((ui32IntType & 4) ?
(HWREG(ui32Port + GPIO_O_IEV) | ui8Pins) :
(HWREG(ui32Port + GPIO_O_IEV) & ~(ui8Pins)));
//
// Set or clear the discrete interrupt feature. This is not available
// on all parts or ports but is safe to write in all cases.
//
HWREG(ui32Port + GPIO_O_SI) = ((ui32IntType & 0x10000) ?
(HWREG(ui32Port + GPIO_O_SI) | 0x01) :
(HWREG(ui32Port + GPIO_O_SI) & ~(0x01)));
}
//*****************************************************************************
//
//! Gets the interrupt type for a pin.
//!
//! \param ui32Port is the base address of the GPIO port.
//! \param ui8Pin is the pin number.
//!
//! This function gets the interrupt type for a specified pin on the selected
//! GPIO port. The pin can be configured as a falling-edge, rising-edge, or
//! both-edges detected interrupt, or it can be configured as a low-level or
//! high-level detected interrupt. The type of interrupt detection mechanism
//! is returned and can include the \b GPIO_DISCRETE_INT flag.
//!
//! \return Returns one of the flags described for GPIOIntTypeSet().
//
//*****************************************************************************
uint32_t
GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin)
{
uint32_t ui32IBE, ui32IS, ui32IEV, ui32SI;
//
// Check the arguments.
//
ASSERT(_GPIOBaseValid(ui32Port));
ASSERT(ui8Pin < 8);
//
// Convert from a pin number to a bit position.
//
ui8Pin = 1 << ui8Pin;
//
// Return the pin interrupt type.
//
ui32IBE = HWREG(ui32Port + GPIO_O_IBE);
ui32IS = HWREG(ui32Port + GPIO_O_IS);
ui32IEV = HWREG(ui32Port + GPIO_O_IEV);
ui32SI = HWREG(ui32Port + GPIO_O_SI);
return(((ui32IBE & ui8Pin) ? 1 : 0) | ((ui32IS & ui8Pin) ? 2 : 0) |
((ui32IEV & ui8Pin) ? 4 : 0) | (ui32SI & 0x01) ? 0x10000 : 0);
}
//*****************************************************************************
//
//! Sets the pad configuration for the specified pin(s).
//!
//! \param ui32Port is the base address of the GPIO port.
//! \param ui8Pins is the bit-packed representation of the pin(s).
//! \param ui32Strength specifies the output drive strength.
//! \param ui32PinType specifies the pin type.
//!
//! This function sets the drive strength and type for the specified pin(s)
//! on the selected GPIO port. For pin(s) configured as input ports, the
//! pad is configured as requested, but the only real effect on the input
//! is the configuration of the pull-up or pull-down termination.
//!
//! The parameter \e ui32Strength can be one of the following values:
//!
//! - \b GPIO_STRENGTH_2MA
//! - \b GPIO_STRENGTH_4MA
//! - \b GPIO_STRENGTH_8MA
//! - \b GPIO_STRENGTH_8MA_SC
//! - \b GPIO_STRENGTH_6MA
//! - \b GPIO_STRENGTH_10MA
//! - \b GPIO_STRENGTH_12MA
//!
//! where \b GPIO_STRENGTH_xMA specifies either 2, 4, or 8 mA output drive
//! strength, and \b GPIO_OUT_STRENGTH_8MA_SC specifies 8 mA output drive with
//! slew control.
//!
//! Some Tiva devices also support output drive strengths of 6, 10, and 12
//! mA.
//!
//! The parameter \e ui32PinType can be one of the following values:
//!
//! - \b GPIO_PIN_TYPE_STD
//! - \b GPIO_PIN_TYPE_STD_WPU
//! - \b GPIO_PIN_TYPE_STD_WPD
//! - \b GPIO_PIN_TYPE_OD
//! - \b GPIO_PIN_TYPE_ANALOG
//! - \b GPIO_PIN_TYPE_WAKE_HIGH
//! - \b GPIO_PIN_TYPE_WAKE_LOW
//!
//! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD*
//! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD
//! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an analog
//! input.
//!
//! The \b GPIO_PIN_TYPE_WAKE_* settings specify the pin to be used as a
//! hibernation wake source. The pin sense level can be high or low. These
//! settings are only available on some Tiva devices.
//!
//! The pin(s) are specified using a bit-packed byte, where each bit that is
//! set identifies the pin to be accessed, and where bit 0 of the byte
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//!
//! \note A subset of GPIO pins on Tiva devices, notably those used by the
//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
//! locked against inadvertent reconfiguration. These pins must be unlocked
//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
//! registers before this function can be called. Please see the ``gpio_jtag''
//! example application for the mechanism required and consult your part
//! datasheet for information on affected pins.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOPadConfigSet(uint32_t ui32Port, uint8_t ui8Pins,
uint32_t ui32Strength, uint32_t ui32PinType)
{
uint8_t ui8Bit;
//
// Check the arguments.
//
ASSERT(_GPIOBaseValid(ui32Port));
ASSERT((ui32Strength == GPIO_STRENGTH_2MA) ||
(ui32Strength == GPIO_STRENGTH_4MA) ||
(ui32Strength == GPIO_STRENGTH_6MA) ||
(ui32Strength == GPIO_STRENGTH_8MA) ||
(ui32Strength == GPIO_STRENGTH_8MA_SC) ||
(ui32Strength == GPIO_STRENGTH_10MA) ||
(ui32Strength == GPIO_STRENGTH_12MA));
ASSERT((ui32PinType == GPIO_PIN_TYPE_STD) ||
(ui32PinType == GPIO_PIN_TYPE_STD_WPU) ||
(ui32PinType == GPIO_PIN_TYPE_STD_WPD) ||
(ui32PinType == GPIO_PIN_TYPE_OD) ||
(ui32PinType == GPIO_PIN_TYPE_WAKE_LOW) ||
(ui32PinType == GPIO_PIN_TYPE_WAKE_HIGH) ||
(ui32PinType == GPIO_PIN_TYPE_ANALOG));
//
// Set the GPIO peripheral configuration register first as required. This
// register only appears in TM4E111 and later device classes, but is a
// harmless write on older devices. Walk pins 0-7 and clear or set the
// provided PC[EDMn] encoding.
//
for(ui8Bit = 0; ui8Bit < 8; ui8Bit++)
{
if(ui8Pins & (1 << ui8Bit))
{
HWREG(ui32Port + GPIO_O_PC) = (HWREG(ui32Port + GPIO_O_PC) &
~(0x3 << (2 * ui8Bit)));
HWREG(ui32Port + GPIO_O_PC) |= (((ui32Strength >> 5) & 0x3) <<
(2 * ui8Bit));
}
}
//
// Set the output drive strength.
//
HWREG(ui32Port + GPIO_O_DR2R) = ((ui32Strength & 1) ?
(HWREG(ui32Port + GPIO_O_DR2R) |
ui8Pins) :
(HWREG(ui32Port + GPIO_O_DR2R) &
~(ui8Pins)));
HWREG(ui32Port + GPIO_O_DR4R) = ((ui32Strength & 2) ?
(HWREG(ui32Port + GPIO_O_DR4R) |
ui8Pins) :
(HWREG(ui32Port + GPIO_O_DR4R) &
~(ui8Pins)));
HWREG(ui32Port + GPIO_O_DR8R) = ((ui32Strength & 4) ?
(HWREG(ui32Port + GPIO_O_DR8R) |
ui8Pins) :
(HWREG(ui32Port + GPIO_O_DR8R) &
~(ui8Pins)));
HWREG(ui32Port + GPIO_O_SLR) = ((ui32Strength & 8) ?
(HWREG(ui32Port + GPIO_O_SLR) |
ui8Pins) :
(HWREG(ui32Port + GPIO_O_SLR) &
~(ui8Pins)));
//
// Set the 12-mA drive select register. This register only appears in
// TM4E111 and later device classes, but is a harmless write on older
// devices.
//
HWREG(ui32Port + GPIO_O_DR12R) = ((ui32Strength & 0x10) ?
(HWREG(ui32Port + GPIO_O_DR12R) |
ui8Pins) :
(HWREG(ui32Port + GPIO_O_DR12R) &
~(ui8Pins)));
//
// Set the pin type.
//
HWREG(ui32Port + GPIO_O_ODR) = ((ui32PinType & 1) ?
(HWREG(ui32Port + GPIO_O_ODR) | ui8Pins) :
(HWREG(ui32Port + GPIO_O_ODR) & ~(ui8Pins)));
HWREG(ui32Port + GPIO_O_PUR) = ((ui32PinType & 2) ?
(HWREG(ui32Port + GPIO_O_PUR) | ui8Pins) :
(HWREG(ui32Port + GPIO_O_PUR) & ~(ui8Pins)));
HWREG(ui32Port + GPIO_O_PDR) = ((ui32PinType & 4) ?
(HWREG(ui32Port + GPIO_O_PDR) | ui8Pins) :
(HWREG(ui32Port + GPIO_O_PDR) & ~(ui8Pins)));
HWREG(ui32Port + GPIO_O_DEN) = ((ui32PinType & 8) ?
(HWREG(ui32Port + GPIO_O_DEN) | ui8Pins) :
(HWREG(ui32Port + GPIO_O_DEN) & ~(ui8Pins)));
//
// Set the wake pin enable register and the wake level register. These
// registers only appear in TM4E111 and later device classes, but are
// harmless writes on older devices.
//
HWREG(ui32Port + GPIO_O_WAKELVL) = ((ui32PinType & 0x200) ?
(HWREG(ui32Port + GPIO_O_WAKELVL) |
ui8Pins) :
(HWREG(ui32Port + GPIO_O_WAKELVL) &
~(ui8Pins)));
HWREG(ui32Port + GPIO_O_WAKEPEN) = ((ui32PinType & 0x300) ?
(HWREG(ui32Port + GPIO_O_WAKEPEN) |
ui8Pins) :
(HWREG(ui32Port + GPIO_O_WAKEPEN) &
~(ui8Pins)));
//
// Set the analog mode select register.
//
HWREG(ui32Port + GPIO_O_AMSEL) =
((ui32PinType == GPIO_PIN_TYPE_ANALOG) ?
(HWREG(ui32Port + GPIO_O_AMSEL) | ui8Pins) :
(HWREG(ui32Port + GPIO_O_AMSEL) & ~(ui8Pins)));
}
//*****************************************************************************
//
//! Gets the pad configuration for a pin.
//!
//! \param ui32Port is the base address of the GPIO port.
//! \param ui8Pin is the pin number.
//! \param pui32Strength is a pointer to storage for the output drive strength.
//! \param pui32PinType is a pointer to storage for the output drive type.
//!
//! This function gets the pad configuration for a specified pin on the
//! selected GPIO port. The values returned in \e pui32Strength and
//! \e pui32PinType correspond to the values used in GPIOPadConfigSet(). This
//! function also works for pin(s) configured as input pin(s); however, the
//! only meaningful data returned is whether the pin is terminated with a
//! pull-up or down resistor.
//!
//! \return None
//
//*****************************************************************************
void
GPIOPadConfigGet(uint32_t ui32Port, uint8_t ui8Pin,
uint32_t *pui32Strength, uint32_t *pui32PinType)
{
uint32_t ui32PinType, ui32Strength;
//
// Check the arguments.
//
ASSERT(_GPIOBaseValid(ui32Port));
ASSERT(ui8Pin < 8);
//
// Convert from a pin number to a bit position.
//
ui8Pin = (1 << ui8Pin);
//
// Get the drive strength for this pin.
//
ui32Strength = ((HWREG(ui32Port + GPIO_O_DR2R) & ui8Pin) ? 1 : 0);
ui32Strength |= ((HWREG(ui32Port + GPIO_O_DR4R) & ui8Pin) ? 2 : 0);
ui32Strength |= ((HWREG(ui32Port + GPIO_O_DR8R) & ui8Pin) ? 4 : 0);
ui32Strength |= ((HWREG(ui32Port + GPIO_O_SLR) & ui8Pin) ? 8 : 0);
ui32Strength |= ((HWREG(ui32Port + GPIO_O_DR12R) & ui8Pin) ? 0x10 : 0);
ui32Strength |= (((HWREG(ui32Port + GPIO_O_PC) >>
(2 * ui8Pin)) & 0x3) << 5);
*pui32Strength = ui32Strength;
//
// Get the pin type.
//
ui32PinType = ((HWREG(ui32Port + GPIO_O_ODR) & ui8Pin) ? 1 : 0);
ui32PinType |= ((HWREG(ui32Port + GPIO_O_PUR) & ui8Pin) ? 2 : 0);
ui32PinType |= ((HWREG(ui32Port + GPIO_O_PDR) & ui8Pin) ? 4 : 0);
ui32PinType |= ((HWREG(ui32Port + GPIO_O_DEN) & ui8Pin) ? 8 : 0);
if(HWREG(ui32Port + GPIO_O_WAKEPEN) & ui8Pin)
{
ui32PinType |= ((HWREG(ui32Port + GPIO_O_WAKELVL) & ui8Pin) ?
0x200 : 0x100);
}
*pui32PinType = ui32PinType;
}
//*****************************************************************************
//
//! Enables the specified GPIO interrupts.
//!
//! \param ui32Port is the base address of the GPIO port.
//! \param ui32IntFlags is the bit mask of the interrupt sources to enable.
//!
//! This function enables the indicated GPIO interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ui32IntFlags parameter is the logical OR of any of the following:
//!
//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0.
//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1.
//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2.
//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3.
//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4.
//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5.
//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6.
//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7.
//! - \b GPIO_INT_DMA - interrupt due to DMA activity on this GPIO module.
//!
//! \note If this call is being used to enable summary interrupts on GPIO port
//! P or Q (GPIOIntTypeSet() with GPIO_DISCRETE_INT not enabled), then all
//! individual interrupts for these ports must be enabled in the GPIO module
//! using GPIOIntEnable() and all but the interrupt for pin 0 must be disabled
//! in the NVIC using the IntDisable() function. The summary interrupts for
//! the ports are routed to the INT_GPIOP0 or INT_GPIOQ0 which must be enabled
//! to handle the interrupt. If this is not done then any individual GPIO pin
//! interrupts that are left enabled also trigger the individual interrupts.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntEnable(uint32_t ui32Port, uint32_t ui32IntFlags)
{
//
// Check the arguments.
//
ASSERT(_GPIOBaseValid(ui32Port));
//
// Enable the interrupts.
//
HWREG(ui32Port + GPIO_O_IM) |= ui32IntFlags;
}
//*****************************************************************************
//
//! Disables the specified GPIO interrupts.
//!
//! \param ui32Port is the base address of the GPIO port.
//! \param ui32IntFlags is the bit mask of the interrupt sources to disable.
//!
//! This function disables the indicated GPIO interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ui32IntFlags parameter is the logical OR of any of the following:
//!
//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0.
//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1.
//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2.
//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3.
//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4.
//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5.
//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6.
//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7.
//! - \b GPIO_INT_DMA - interrupt due to DMA activity on this GPIO module.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntDisable(uint32_t ui32Port, uint32_t ui32IntFlags)
{
//
// Check the arguments.
//
ASSERT(_GPIOBaseValid(ui32Port));
//
// Disable the interrupts.
//
HWREG(ui32Port + GPIO_O_IM) &= ~(ui32IntFlags);
}
//*****************************************************************************
//
//! Gets interrupt status for the specified GPIO port.
//!
//! \param ui32Port is the base address of the GPIO port.
//! \param bMasked specifies whether masked or raw interrupt status is
//! returned.
//!
//! If \e bMasked is set as \b true, then the masked interrupt status is
//! returned; otherwise, the raw interrupt status is returned.
//!
//! \return Returns the current interrupt status for the specified GPIO module.
//! The value returned is the logical OR of the \b GPIO_INT_* values that are
//! currently active.
//
//*****************************************************************************
uint32_t
GPIOIntStatus(uint32_t ui32Port, bool bMasked)
{
//
// Check the arguments.
//
ASSERT(_GPIOBaseValid(ui32Port));
//
// Return the interrupt status.
//
if(bMasked)
{
return(HWREG(ui32Port + GPIO_O_MIS));
}
else
{
return(HWREG(ui32Port + GPIO_O_RIS));
}
}
//*****************************************************************************
//
//! Clears the specified interrupt sources.
//!
//! \param ui32Port is the base address of the GPIO port.
//! \param ui32IntFlags is the bit mask of the interrupt sources to disable.
//!
//! Clears the interrupt for the specified interrupt source(s).
//!
//! The \e ui32IntFlags parameter is the logical OR of the \b GPIO_INT_*
//! values.
//!
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntClear(uint32_t ui32Port, uint32_t ui32IntFlags)
{
//
// Check the arguments.
//
ASSERT(_GPIOBaseValid(ui32Port));
//
// Clear the interrupts.
//
HWREG(ui32Port + GPIO_O_ICR) = ui32IntFlags;
}
//*****************************************************************************
//
//! Registers an interrupt handler for a GPIO port.
//!
//! \param ui32Port is the base address of the GPIO port.
//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling
//! function.
//!
//! This function ensures that the interrupt handler specified by
//! \e pfnIntHandler is called when an interrupt is detected from the selected
//! GPIO port. This function also enables the corresponding GPIO interrupt
//! in the interrupt controller; individual pin interrupts and interrupt
//! sources must be enabled with GPIOIntEnable().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler)(void))
{
uint32_t ui32Int;
//
// Check the arguments.
//
ASSERT(_GPIOBaseValid(ui32Port));
//
// Get the interrupt number associated with the specified GPIO.
//
ui32Int = _GPIOIntNumberGet(ui32Port);
ASSERT(ui32Int != 0);
//
// Register the interrupt handler.
//
IntRegister(ui32Int, pfnIntHandler);
//
// Enable the GPIO interrupt.
//
IntEnable(ui32Int);
}
//*****************************************************************************
//
//! Removes an interrupt handler for a GPIO port.
//!
//! \param ui32Port is the base address of the GPIO port.
//!
//! This function unregisters the interrupt handler for the specified
//! GPIO port. This function also disables the corresponding
//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts
//! and interrupt sources must be disabled with GPIOIntDisable().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntUnregister(uint32_t ui32Port)
{
uint32_t ui32Int;
//
// Check the arguments.
//
ASSERT(_GPIOBaseValid(ui32Port));
//
// Get the interrupt number associated with the specified GPIO.
//
ui32Int = _GPIOIntNumberGet(ui32Port);
ASSERT(ui32Int != 0);
//
// Disable the GPIO interrupt.
//
IntDisable(ui32Int);
//
// Unregister the interrupt handler.
//
IntUnregister(ui32Int);
}
//*****************************************************************************
//
//! Reads the values present of the specified pin(s).
//!
//! \param ui32Port is the base address of the GPIO port.
//! \param ui8Pins is the bit-packed representation of the pin(s).
//!
//! The values at the specified pin(s) are read, as specified by \e ui8Pins.
//! Values are returned for both input and output pin(s), and the value
//! for pin(s) that are not specified by \e ui8Pins are set to 0.
//!
//! The pin(s) are specified using a bit-packed byte, where each bit that is
//! set identifies the pin to be accessed, and where bit 0 of the byte
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//!
//! \return Returns a bit-packed byte providing the state of the specified
//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents